1 /* 2 * Copyright 2022 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_ 8 #define ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_ 9 10 /* Internal macros to pack and extract pin configuration data. */ 11 /* GPIO configuration packing macros */ 12 #define IOMUX_OFFSET_ENABLE(offset, enable, shift) \ 13 ((((offset) << 1) | (enable & 0x1)) << shift) 14 #define IOMUX_SCTIMER_OUT_CLR(offset, enable) \ 15 IOMUX_OFFSET_ENABLE(offset, enable, 0) 16 #define IOMUX_SCTIMER_IN_CLR(offset, enable) \ 17 IOMUX_OFFSET_ENABLE(offset, enable, 4) 18 #define IOMUX_CTIMER_CLR(offset, enable)\ 19 IOMUX_OFFSET_ENABLE(offset, enable, 8) 20 #define IOMUX_FSEL_CLR(mask) ((mask) << 13) 21 #define IOMUX_FLEXCOMM_CLR(idx, mask) \ 22 (((mask) << 45) | ((idx) << 56)) 23 24 /* GPIO configuration extraction macros */ 25 #define IOMUX_GET_SCTIMER_OUT_CLR_ENABLE(mux) ((mux) & 0x1) 26 #define IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(mux) (((mux) >> 1) & 0x7) 27 #define IOMUX_GET_SCTIMER_IN_CLR_ENABLE(mux) (((mux) >> 4) & 0x1) 28 #define IOMUX_GET_SCTIMER_IN_CLR_OFFSET(mux) (((mux) >> 5) & 0x7) 29 #define IOMUX_GET_CTIMER_CLR_ENABLE(mux) (((mux) >> 8) & 0x1ULL) 30 #define IOMUX_GET_CTIMER_CLR_OFFSET(mux) (((mux) >> 9) & 0xFULL) 31 #define IOMUX_GET_FSEL_CLR_MASK(mux) (((mux) >> 13) & 0xFFFFFFFFULL) 32 #define IOMUX_GET_FLEXCOMM_CLR_MASK(mux) \ 33 (((mux) >> 45) & 0x7FFULL) 34 #define IOMUX_GET_FLEXCOMM_CLR_IDX(mux) \ 35 (((mux) >> 56) & 0xF) 36 37 /* Pin mux type and gpio offset macros */ 38 #define IOMUX_GPIO_IDX(x) ((x) & 0x7F) 39 #define IOMUX_TYPE(x) (((x) & 0xF) << 7) 40 #define IOMUX_GET_GPIO_IDX(mux) ((mux) & 0x7F) 41 #define IOMUX_GET_TYPE(mux) (((mux) >> 7) & 0xF) 42 43 /* Flexcomm specific macros */ 44 #define IOMUX_FLEXCOMM_IDX(x) (((x) & 0xF) << 11) 45 #define IOMUX_FLEXCOMM_BIT(x) (((x) & 0xF) << 15) 46 #define IOMUX_GET_FLEXCOMM_IDX(mux) (((mux) >> 11) & 0xF) 47 #define IOMUX_GET_FLEXCOMM_BIT(mux) (((mux) >> 15) & 0xF) 48 49 /* Function select specific macros */ 50 #define IOMUX_FSEL_BIT(mux) (((mux) & 0x1F) << 11) 51 #define IOMUX_GET_FSEL_BIT(mux) (((mux) >> 11) & 0x1F) 52 53 /* CTimer specific macros */ 54 #define IOMUX_CTIMER_BIT(x) (((x) & 0xF) << 11) 55 #define IOMUX_GET_CTIMER_BIT(mux) (((mux) >> 11) & 0xF) 56 57 /* SCtimer specific macros */ 58 #define IOMUX_SCTIMER_BIT(x) (((x) & 0xF) << 11) 59 #define IOMUX_GET_SCTIMER_BIT(mux) (((mux) >> 11) & 0xF) 60 61 62 /* Mux Types */ 63 #define IOMUX_FLEXCOMM 0x0 64 #define IOMUX_FSEL 0x1 65 #define IOMUX_CTIMER_IN 0x2 66 #define IOMUX_CTIMER_OUT 0x3 67 #define IOMUX_SCTIMER_IN 0x4 68 #define IOMUX_SCTIMER_OUT 0x5 69 #define IOMUX_GPIO 0x6 70 #define IOMUX_SGPIO 0x7 71 #define IOMUX_AON 0x8 72 73 74 /* Pin configuration settings */ 75 #define IOMUX_PAD_PULL(x) (((x) & 0x3) << 19) 76 #define IOMUX_PAD_SLEW(x) (((x) & 0x3) << 21) 77 #define IOMUX_PAD_SLEEP_FORCE(en, val) \ 78 ((((en) & 0x1) << 24) | (((val) & 0x1) << 23)) 79 #define IOMUX_PAD_GET_PULL(mux) (((mux) >> 19) & 0x3) 80 #define IOMUX_PAD_GET_SLEW(mux) (((mux) >> 21) & 0x3) 81 #define IOMUX_PAD_GET_SLEEP_FORCE_EN(mux) (((mux) >> 24) & 0x1) 82 #define IOMUX_PAD_GET_SLEEP_FORCE_VAL(mux) (((mux) >> 23) & 0x1) 83 84 /* 85 * GPIO mux options. These options are used to clear all alternate 86 * pin functions, so the pin controller will use GPIO mode. 87 */ 88 89 #define IOMUX_GPIO_CLR_0 \ 90 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ 91 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 92 IOMUX_CTIMER_CLR(0ULL, 1ULL) | /* CTIMER offset to clear */ \ 93 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 94 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 95 96 #define IOMUX_GPIO_CLR_1 \ 97 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 98 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 99 IOMUX_CTIMER_CLR(1ULL, 1ULL) | /* CTIMER offset to clear */ \ 100 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 101 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 102 103 #define IOMUX_GPIO_CLR_2 \ 104 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x32eULL) | /* Flexcomm bits to clear */ \ 105 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 106 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 107 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 108 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 109 110 #define IOMUX_GPIO_CLR_3 \ 111 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x22eULL) | /* Flexcomm bits to clear */ \ 112 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 113 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 114 IOMUX_SCTIMER_IN_CLR(0ULL, 1ULL) | /* SCTIMER input offset to clear */ \ 115 IOMUX_SCTIMER_OUT_CLR(0ULL, 1ULL)) /* SCTIMER output offset to clear */ 116 117 #define IOMUX_GPIO_CLR_4 \ 118 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x2dULL) | /* Flexcomm bits to clear */ \ 119 IOMUX_FSEL_CLR(0x800000ULL) | /* FSEL bits to clear */ \ 120 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 121 IOMUX_SCTIMER_IN_CLR(1ULL, 1ULL) | /* SCTIMER input offset to clear */ \ 122 IOMUX_SCTIMER_OUT_CLR(1ULL, 1ULL)) /* SCTIMER output offset to clear */ 123 124 #define IOMUX_GPIO_CLR_5 \ 125 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ 126 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 127 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 128 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 129 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 130 131 #define IOMUX_GPIO_CLR_6 \ 132 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ 133 IOMUX_FSEL_CLR(0x1000000ULL) | /* FSEL bits to clear */ \ 134 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 135 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 136 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 137 138 #define IOMUX_GPIO_CLR_7 \ 139 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0xedULL) | /* Flexcomm bits to clear */ \ 140 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 141 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 142 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 143 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 144 145 #define IOMUX_GPIO_CLR_8 \ 146 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ 147 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 148 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 149 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 150 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 151 152 #define IOMUX_GPIO_CLR_9 \ 153 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ 154 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 155 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 156 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 157 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 158 159 #define IOMUX_GPIO_CLR_10 \ 160 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ 161 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 162 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 163 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 164 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 165 166 #define IOMUX_GPIO_CLR_11 \ 167 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ 168 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 169 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 170 IOMUX_SCTIMER_IN_CLR(8ULL, 1ULL) | /* SCTIMER input offset to clear */ \ 171 IOMUX_SCTIMER_OUT_CLR(8ULL, 1ULL)) /* SCTIMER output offset to clear */ 172 173 #define IOMUX_GPIO_CLR_12 \ 174 (IOMUX_FLEXCOMM_CLR(0x1ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ 175 IOMUX_FSEL_CLR(0x8020ULL) | /* FSEL bits to clear */ \ 176 IOMUX_CTIMER_CLR(2ULL, 1ULL) | /* CTIMER offset to clear */ \ 177 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 178 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 179 180 #define IOMUX_GPIO_CLR_13 \ 181 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ 182 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 183 IOMUX_CTIMER_CLR(3ULL, 1ULL) | /* CTIMER offset to clear */ \ 184 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 185 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 186 187 #define IOMUX_GPIO_CLR_14 \ 188 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ 189 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 190 IOMUX_CTIMER_CLR(4ULL, 1ULL) | /* CTIMER offset to clear */ \ 191 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 192 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 193 194 #define IOMUX_GPIO_CLR_15 \ 195 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0xedULL) | /* Flexcomm bits to clear */ \ 196 IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \ 197 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 198 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 199 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 200 201 #define IOMUX_GPIO_CLR_16 \ 202 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ 203 IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \ 204 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 205 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 206 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 207 208 #define IOMUX_GPIO_CLR_17 \ 209 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ 210 IOMUX_FSEL_CLR(0x8600ULL) | /* FSEL bits to clear */ \ 211 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 212 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 213 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 214 215 #define IOMUX_GPIO_CLR_18 \ 216 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ 217 IOMUX_FSEL_CLR(0xc600ULL) | /* FSEL bits to clear */ \ 218 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 219 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 220 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 221 222 #define IOMUX_GPIO_CLR_19 \ 223 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ 224 IOMUX_FSEL_CLR(0x8000ULL) | /* FSEL bits to clear */ \ 225 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 226 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 227 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 228 229 #define IOMUX_GPIO_CLR_20 \ 230 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ 231 IOMUX_FSEL_CLR(0x8000ULL) | /* FSEL bits to clear */ \ 232 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 233 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 234 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 235 236 #define IOMUX_GPIO_CLR_21 \ 237 (IOMUX_FLEXCOMM_CLR(0x2ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ 238 IOMUX_FSEL_CLR(0x0ULL) | /* FSEL bits to clear */ \ 239 IOMUX_CTIMER_CLR(5ULL, 1ULL) | /* CTIMER offset to clear */ \ 240 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 241 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 242 243 #define IOMUX_GPIO_CLR_22 \ 244 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ 245 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ 246 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 247 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 248 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 249 250 #define IOMUX_GPIO_CLR_23 \ 251 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ 252 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ 253 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 254 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 255 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 256 257 #define IOMUX_GPIO_CLR_24 \ 258 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ 259 IOMUX_FSEL_CLR(0x40000000ULL) | /* FSEL bits to clear */ \ 260 IOMUX_CTIMER_CLR(6ULL, 1ULL) | /* CTIMER offset to clear */ \ 261 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 262 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 263 264 #define IOMUX_GPIO_CLR_25 \ 265 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0xedULL) | /* Flexcomm bits to clear */ \ 266 IOMUX_FSEL_CLR(0x10000ULL) | /* FSEL bits to clear */ \ 267 IOMUX_CTIMER_CLR(7ULL, 1ULL) | /* CTIMER offset to clear */ \ 268 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 269 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 270 271 #define IOMUX_GPIO_CLR_26 \ 272 (IOMUX_FLEXCOMM_CLR(0x3ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ 273 IOMUX_FSEL_CLR(0x80000000ULL) | /* FSEL bits to clear */ \ 274 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 275 IOMUX_SCTIMER_IN_CLR(4ULL, 1ULL) | /* SCTIMER input offset to clear */ \ 276 IOMUX_SCTIMER_OUT_CLR(4ULL, 1ULL)) /* SCTIMER output offset to clear */ 277 278 #define IOMUX_GPIO_CLR_27 \ 279 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 280 IOMUX_FSEL_CLR(0x10000000ULL) | /* FSEL bits to clear */ \ 281 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 282 IOMUX_SCTIMER_IN_CLR(5ULL, 1ULL) | /* SCTIMER input offset to clear */ \ 283 IOMUX_SCTIMER_OUT_CLR(5ULL, 1ULL)) /* SCTIMER output offset to clear */ 284 285 #define IOMUX_GPIO_CLR_28 \ 286 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 287 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ 288 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 289 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 290 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 291 292 #define IOMUX_GPIO_CLR_29 \ 293 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 294 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ 295 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 296 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 297 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 298 299 #define IOMUX_GPIO_CLR_30 \ 300 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 301 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ 302 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 303 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 304 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 305 306 #define IOMUX_GPIO_CLR_31 \ 307 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 308 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ 309 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 310 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 311 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 312 313 #define IOMUX_GPIO_CLR_32 \ 314 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 315 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ 316 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 317 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 318 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 319 320 #define IOMUX_GPIO_CLR_33 \ 321 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 322 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ 323 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 324 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 325 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 326 327 #define IOMUX_GPIO_CLR_34 \ 328 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 329 IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \ 330 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 331 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 332 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 333 334 #define IOMUX_GPIO_CLR_35 \ 335 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 336 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ 337 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 338 IOMUX_SCTIMER_IN_CLR(6ULL, 1ULL) | /* SCTIMER input offset to clear */ \ 339 IOMUX_SCTIMER_OUT_CLR(6ULL, 1ULL)) /* SCTIMER output offset to clear */ 340 341 #define IOMUX_GPIO_CLR_36 \ 342 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 343 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ 344 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 345 IOMUX_SCTIMER_IN_CLR(7ULL, 1ULL) | /* SCTIMER input offset to clear */ \ 346 IOMUX_SCTIMER_OUT_CLR(7ULL, 1ULL)) /* SCTIMER output offset to clear */ 347 348 #define IOMUX_GPIO_CLR_37 \ 349 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 350 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ 351 IOMUX_CTIMER_CLR(8ULL, 1ULL) | /* CTIMER offset to clear */ \ 352 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 353 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 354 355 #define IOMUX_GPIO_CLR_38 \ 356 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 357 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ 358 IOMUX_CTIMER_CLR(9ULL, 1ULL) | /* CTIMER offset to clear */ \ 359 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 360 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 361 362 #define IOMUX_GPIO_CLR_39 \ 363 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 364 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ 365 IOMUX_CTIMER_CLR(10ULL, 1ULL) | /* CTIMER offset to clear */ \ 366 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 367 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 368 369 #define IOMUX_GPIO_CLR_40 \ 370 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 371 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ 372 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 373 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 374 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 375 376 #define IOMUX_GPIO_CLR_41 \ 377 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 378 IOMUX_FSEL_CLR(0x8ULL) | /* FSEL bits to clear */ \ 379 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 380 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 381 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 382 383 #define IOMUX_GPIO_CLR_42 \ 384 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 385 IOMUX_FSEL_CLR(0x800ULL) | /* FSEL bits to clear */ \ 386 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 387 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 388 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 389 390 #define IOMUX_GPIO_CLR_43 \ 391 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 392 IOMUX_FSEL_CLR(0x800ULL) | /* FSEL bits to clear */ \ 393 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 394 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 395 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 396 397 #define IOMUX_GPIO_CLR_44 \ 398 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 399 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ 400 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 401 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 402 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 403 404 #define IOMUX_GPIO_CLR_45 \ 405 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 406 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ 407 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 408 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 409 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 410 411 #define IOMUX_GPIO_CLR_46 \ 412 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 413 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ 414 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 415 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 416 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 417 418 #define IOMUX_GPIO_CLR_47 \ 419 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 420 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ 421 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 422 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 423 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 424 425 #define IOMUX_GPIO_CLR_48 \ 426 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 427 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ 428 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 429 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 430 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 431 432 #define IOMUX_GPIO_CLR_49 \ 433 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 434 IOMUX_FSEL_CLR(0x1800ULL) | /* FSEL bits to clear */ \ 435 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 436 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 437 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 438 439 #define IOMUX_GPIO_CLR_50 \ 440 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 441 IOMUX_FSEL_CLR(0x22000ULL) | /* FSEL bits to clear */ \ 442 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 443 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 444 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 445 446 #define IOMUX_GPIO_CLR_51 \ 447 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x40ULL) | /* Flexcomm bits to clear */ \ 448 IOMUX_FSEL_CLR(0x40810ULL) | /* FSEL bits to clear */ \ 449 IOMUX_CTIMER_CLR(11ULL, 1ULL) | /* CTIMER offset to clear */ \ 450 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 451 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 452 453 #define IOMUX_GPIO_CLR_52 \ 454 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x80ULL) | /* Flexcomm bits to clear */ \ 455 IOMUX_FSEL_CLR(0x80810ULL) | /* FSEL bits to clear */ \ 456 IOMUX_CTIMER_CLR(12ULL, 1ULL) | /* CTIMER offset to clear */ \ 457 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 458 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 459 460 #define IOMUX_GPIO_CLR_53 \ 461 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x418ULL) | /* Flexcomm bits to clear */ \ 462 IOMUX_FSEL_CLR(0x100810ULL) | /* FSEL bits to clear */ \ 463 IOMUX_CTIMER_CLR(13ULL, 1ULL) | /* CTIMER offset to clear */ \ 464 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 465 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 466 467 #define IOMUX_GPIO_CLR_54 \ 468 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0xedULL) | /* Flexcomm bits to clear */ \ 469 IOMUX_FSEL_CLR(0x200810ULL) | /* FSEL bits to clear */ \ 470 IOMUX_CTIMER_CLR(14ULL, 1ULL) | /* CTIMER offset to clear */ \ 471 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 472 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 473 474 #define IOMUX_GPIO_CLR_55 \ 475 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x430ULL) | /* Flexcomm bits to clear */ \ 476 IOMUX_FSEL_CLR(0x400000ULL) | /* FSEL bits to clear */ \ 477 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 478 IOMUX_SCTIMER_IN_CLR(9ULL, 1ULL) | /* SCTIMER input offset to clear */ \ 479 IOMUX_SCTIMER_OUT_CLR(9ULL, 1ULL)) /* SCTIMER output offset to clear */ 480 481 #define IOMUX_GPIO_CLR_56 \ 482 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x2eeULL) | /* Flexcomm bits to clear */ \ 483 IOMUX_FSEL_CLR(0x8000800ULL) | /* FSEL bits to clear */ \ 484 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 485 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 486 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 487 488 #define IOMUX_GPIO_CLR_57 \ 489 (IOMUX_FLEXCOMM_CLR(0x6ULL, 0x3eeULL) | /* Flexcomm bits to clear */ \ 490 IOMUX_FSEL_CLR(0x8000800ULL) | /* FSEL bits to clear */ \ 491 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 492 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 493 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 494 495 #define IOMUX_GPIO_CLR_58 \ 496 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 497 IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \ 498 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 499 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 500 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 501 502 #define IOMUX_GPIO_CLR_59 \ 503 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 504 IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \ 505 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 506 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 507 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 508 509 #define IOMUX_GPIO_CLR_60 \ 510 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 511 IOMUX_FSEL_CLR(0x2000000ULL) | /* FSEL bits to clear */ \ 512 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 513 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 514 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 515 516 #define IOMUX_GPIO_CLR_61 \ 517 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 518 IOMUX_FSEL_CLR(0x20000000ULL) | /* FSEL bits to clear */ \ 519 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 520 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 521 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 522 523 #define IOMUX_GPIO_CLR_62 \ 524 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 525 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ 526 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 527 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 528 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 529 530 #define IOMUX_GPIO_CLR_63 \ 531 (IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \ 532 IOMUX_FSEL_CLR(0x4000000ULL) | /* FSEL bits to clear */ \ 533 IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \ 534 IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \ 535 IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */ 536 537 #define IOMUX_GPIO_OPS \ 538 IOMUX_GPIO_CLR_0, IOMUX_GPIO_CLR_1, IOMUX_GPIO_CLR_2, IOMUX_GPIO_CLR_3, \ 539 IOMUX_GPIO_CLR_4, IOMUX_GPIO_CLR_5, IOMUX_GPIO_CLR_6, IOMUX_GPIO_CLR_7, \ 540 IOMUX_GPIO_CLR_8, IOMUX_GPIO_CLR_9, IOMUX_GPIO_CLR_10, IOMUX_GPIO_CLR_11, \ 541 IOMUX_GPIO_CLR_12, IOMUX_GPIO_CLR_13, IOMUX_GPIO_CLR_14, IOMUX_GPIO_CLR_15, \ 542 IOMUX_GPIO_CLR_16, IOMUX_GPIO_CLR_17, IOMUX_GPIO_CLR_18, IOMUX_GPIO_CLR_19, \ 543 IOMUX_GPIO_CLR_20, IOMUX_GPIO_CLR_21, IOMUX_GPIO_CLR_22, IOMUX_GPIO_CLR_23, \ 544 IOMUX_GPIO_CLR_24, IOMUX_GPIO_CLR_25, IOMUX_GPIO_CLR_26, IOMUX_GPIO_CLR_27, \ 545 IOMUX_GPIO_CLR_28, IOMUX_GPIO_CLR_29, IOMUX_GPIO_CLR_30, IOMUX_GPIO_CLR_31, \ 546 IOMUX_GPIO_CLR_32, IOMUX_GPIO_CLR_33, IOMUX_GPIO_CLR_34, IOMUX_GPIO_CLR_35, \ 547 IOMUX_GPIO_CLR_36, IOMUX_GPIO_CLR_37, IOMUX_GPIO_CLR_38, IOMUX_GPIO_CLR_39, \ 548 IOMUX_GPIO_CLR_40, IOMUX_GPIO_CLR_41, IOMUX_GPIO_CLR_42, IOMUX_GPIO_CLR_43, \ 549 IOMUX_GPIO_CLR_44, IOMUX_GPIO_CLR_45, IOMUX_GPIO_CLR_46, IOMUX_GPIO_CLR_47, \ 550 IOMUX_GPIO_CLR_48, IOMUX_GPIO_CLR_49, IOMUX_GPIO_CLR_50, IOMUX_GPIO_CLR_51, \ 551 IOMUX_GPIO_CLR_52, IOMUX_GPIO_CLR_53, IOMUX_GPIO_CLR_54, IOMUX_GPIO_CLR_55, \ 552 IOMUX_GPIO_CLR_56, IOMUX_GPIO_CLR_57, IOMUX_GPIO_CLR_58, IOMUX_GPIO_CLR_59, \ 553 IOMUX_GPIO_CLR_60, IOMUX_GPIO_CLR_61, IOMUX_GPIO_CLR_62, IOMUX_GPIO_CLR_63 554 555 #endif /* ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_ */ 556
