1 /* 2 * Copyright (c) 2018 TDK Invensense 3 * 4 * SPDX-License-Identifier: BSD 3-Clause 5 */ 6 7 #ifndef _INV_IMU_DEFS_H_ 8 #define _INV_IMU_DEFS_H_ 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** @file inv_imu_defs.h 15 * File exposing the device register map 16 */ 17 18 #include <stdint.h> 19 20 #define INV_IMU_REV_A 0xA 21 #define INV_IMU_REV_B 0XB 22 23 /* Include device definition */ 24 #include "imu/inv_imu.h" 25 26 #if INV_IMU_REV == INV_IMU_REV_A 27 #include "imu/inv_imu_regmap_rev_a.h" 28 #elif INV_IMU_REV == INV_IMU_REV_B 29 #include "imu/inv_imu_regmap_rev_b.h" 30 #endif 31 32 #define ACCEL_DATA_SIZE 6 33 #define GYRO_DATA_SIZE 6 34 #define TEMP_DATA_SIZE 2 35 36 #define FIFO_HEADER_SIZE 1 37 #define FIFO_ACCEL_DATA_SIZE ACCEL_DATA_SIZE 38 #define FIFO_GYRO_DATA_SIZE GYRO_DATA_SIZE 39 #define FIFO_TEMP_DATA_SIZE 1 40 #define FIFO_TS_FSYNC_SIZE 2 41 #define FIFO_TEMP_HIGH_RES_SIZE 1 42 #define FIFO_ACCEL_GYRO_HIGH_RES_SIZE 3 43 44 #define FIFO_16BYTES_PACKET_SIZE \ 45 (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + \ 46 FIFO_TS_FSYNC_SIZE) 47 #define FIFO_20BYTES_PACKET_SIZE \ 48 (FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE + FIFO_TEMP_DATA_SIZE + \ 49 FIFO_TS_FSYNC_SIZE + FIFO_TEMP_HIGH_RES_SIZE + FIFO_ACCEL_GYRO_HIGH_RES_SIZE) 50 51 #define FIFO_HEADER_ODR_ACCEL 0x01 52 #define FIFO_HEADER_ODR_GYRO 0x02 53 #define FIFO_HEADER_FSYNC 0x04 54 #define FIFO_HEADER_TMST 0x08 55 #define FIFO_HEADER_HEADER_20 0x10 56 #define FIFO_HEADER_GYRO 0x20 57 #define FIFO_HEADER_ACC 0x40 58 #define FIFO_HEADER_MSG 0x80 59 60 #define INVALID_VALUE_FIFO ((int16_t)0x8000) 61 #define INVALID_VALUE_FIFO_1B ((int8_t)0x80) 62 #define OUT_OF_BOUND_TEMPERATURE_NEG_FIFO_1B ((int8_t)0x81) 63 #define OUT_OF_BOUND_TEMPERATURE_POS_FIFO_1B ((int8_t)0x7F) 64 65 /** Describe the content of the FIFO header */ 66 typedef union { 67 unsigned char Byte; 68 struct { 69 #if INV_IMU_IS_GYRO_SUPPORTED 70 unsigned char gyro_odr_different : 1; 71 #else 72 unsigned char reserved1 : 1; 73 #endif 74 unsigned char accel_odr_different : 1; 75 #if INV_IMU_IS_GYRO_SUPPORTED 76 unsigned char fsync_bit : 1; 77 #else 78 unsigned char reserved2 : 1; 79 #endif 80 unsigned char timestamp_bit : 1; 81 unsigned char twentybits_bit : 1; 82 #if INV_IMU_IS_GYRO_SUPPORTED 83 unsigned char gyro_bit : 1; 84 #else 85 unsigned char reserved3 : 1; 86 #endif 87 unsigned char accel_bit : 1; 88 unsigned char msg_bit : 1; 89 } bits; 90 } fifo_header_t; 91 92 /* ---------------------------------------------------------------------------- 93 * Device registers description 94 * 95 * Next section defines some of the registers bitfield and declare corresponding 96 * accessors. 97 * Note that descriptors and accessors are not provided for all the registers 98 * but only for the most useful ones. 99 * For all details on registers and bitfields functionalities please refer to 100 * the device datasheet. 101 * ---------------------------------------------------------------------------- */ 102 103 /* --------------------------------------------------------------------------- 104 * register bank 0 105 * ---------------------------------------------------------------------------- */ 106 107 /* 108 * DEVICE_CONFIG 109 * Register Name : DEVICE_CONFIG 110 */ 111 112 /* SPI_MODE */ 113 typedef enum { 114 DEVICE_CONFIG_SPI_MODE_1_2 = (0x1 << DEVICE_CONFIG_SPI_MODE_POS), 115 DEVICE_CONFIG_SPI_MODE_0_3 = (0x0 << DEVICE_CONFIG_SPI_MODE_POS), 116 } DEVICE_CONFIG_SPI_MODE_t; 117 118 /* SPI_AP_4WIRE */ 119 typedef enum { 120 DEVICE_CONFIG_SPI_4WIRE = (0x1 << DEVICE_CONFIG_SPI_AP_4WIRE_POS), 121 DEVICE_CONFIG_SPI_3WIRE = (0x0 << DEVICE_CONFIG_SPI_AP_4WIRE_POS), 122 } DEVICE_CONFIG_SPI_AP_4WIRE_t; 123 124 /* 125 * SIGNAL_PATH_RESET 126 * Register Name: SIGNAL_PATH_RESET 127 */ 128 129 /* SOFT_RESET_DEVICE_CONFIG */ 130 typedef enum { 131 SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_EN = 132 (0x01 << SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_POS), 133 SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_DIS = 134 (0x00 << SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_POS), 135 } SIGNAL_PATH_RESET_SOFT_RESET_DEVICE_CONFIG_t; 136 137 /* FIFO_FLUSH */ 138 typedef enum { 139 SIGNAL_PATH_RESET_FIFO_FLUSH_EN = (0x01 << SIGNAL_PATH_RESET_FIFO_FLUSH_POS), 140 SIGNAL_PATH_RESET_FIFO_FLUSH_DIS = (0x00 << SIGNAL_PATH_RESET_FIFO_FLUSH_POS), 141 } SIGNAL_PATH_RESET_FIFO_FLUSH_t; 142 143 /* 144 * DRIVE_CONFIG3 145 * Register Name: DRIVE_CONFIG3 146 */ 147 148 /* SPI_SLEW_RATE */ 149 typedef enum { 150 DRIVE_CONFIG3_SPI_SLEW_RATE_MAX_2_NS = (0x05 << DRIVE_CONFIG3_SPI_SLEW_RATE_POS), 151 DRIVE_CONFIG3_SPI_SLEW_RATE_MAX_8_NS = (0x04 << DRIVE_CONFIG3_SPI_SLEW_RATE_POS), 152 DRIVE_CONFIG3_SPI_SLEW_RATE_MAX_14_NS = (0x03 << DRIVE_CONFIG3_SPI_SLEW_RATE_POS), 153 DRIVE_CONFIG3_SPI_SLEW_RATE_MAX_19_NS = (0x02 << DRIVE_CONFIG3_SPI_SLEW_RATE_POS), 154 DRIVE_CONFIG3_SPI_SLEW_RATE_MAX_36_NS = (0x01 << DRIVE_CONFIG3_SPI_SLEW_RATE_POS), 155 DRIVE_CONFIG3_SPI_SLEW_RATE_MAX_60_NS = (0x00 << DRIVE_CONFIG3_SPI_SLEW_RATE_POS), 156 } DRIVE_CONFIG3_SPI_SLEW_RATE_t; 157 158 /* 159 * INT_CONFIG 160 * Register Name: INT_CONFIG 161 */ 162 163 /* INT2_MODE */ 164 typedef enum { 165 INT_CONFIG_INT2_MODE_LATCHED = (0x01 << INT_CONFIG_INT2_MODE_POS), 166 INT_CONFIG_INT2_MODE_PULSED = (0x00 << INT_CONFIG_INT2_MODE_POS), 167 } INT_CONFIG_INT2_MODE_t; 168 169 /* INT2_DRIVE_CIRCUIT */ 170 typedef enum { 171 INT_CONFIG_INT2_DRIVE_CIRCUIT_PP = (0x01 << INT_CONFIG_INT2_DRIVE_CIRCUIT_POS), 172 INT_CONFIG_INT2_DRIVE_CIRCUIT_OD = (0x00 << INT_CONFIG_INT2_DRIVE_CIRCUIT_POS), 173 } INT_CONFIG_INT2_DRIVE_CIRCUIT_t; 174 175 /* INT2_POLARITY */ 176 typedef enum { 177 INT_CONFIG_INT2_POLARITY_HIGH = (0x01 << INT_CONFIG_INT2_POLARITY_POS), 178 INT_CONFIG_INT2_POLARITY_LOW = (0x00 << INT_CONFIG_INT2_POLARITY_POS), 179 } INT_CONFIG_INT2_POLARITY_t; 180 181 /* INT1_MODE */ 182 typedef enum { 183 INT_CONFIG_INT1_MODE_LATCHED = (0x01 << INT_CONFIG_INT1_MODE_POS), 184 INT_CONFIG_INT1_MODE_PULSED = (0x00 << INT_CONFIG_INT1_MODE_POS), 185 } INT_CONFIG_INT1_MODE_t; 186 187 /* INT1_DRIVE_CIRCUIT */ 188 typedef enum { 189 INT_CONFIG_INT1_DRIVE_CIRCUIT_PP = (0x01 << INT_CONFIG_INT1_DRIVE_CIRCUIT_POS), 190 INT_CONFIG_INT1_DRIVE_CIRCUIT_OD = (0x00 << INT_CONFIG_INT1_DRIVE_CIRCUIT_POS), 191 } INT_CONFIG_INT1_DRIVE_CIRCUIT_t; 192 193 /* INT1_POLARITY */ 194 typedef enum { 195 INT_CONFIG_INT1_POLARITY_HIGH = 0x01, 196 INT_CONFIG_INT1_POLARITY_LOW = 0x00, 197 } INT_CONFIG_INT1_POLARITY_t; 198 199 /* 200 * PWR_MGMT0 201 * Register Name: PWR_MGMT0 202 */ 203 204 /* ACCEL_LP_CLK_SEL */ 205 typedef enum { 206 PWR_MGMT0_ACCEL_LP_CLK_WUOSC = (0x00 << PWR_MGMT0_ACCEL_LP_CLK_SEL_POS), 207 PWR_MGMT0_ACCEL_LP_CLK_RCOSC = (0x01 << PWR_MGMT0_ACCEL_LP_CLK_SEL_POS), 208 } PWR_MGMT0_ACCEL_LP_CLK_t; 209 210 /* IDLE */ 211 typedef enum { 212 PWR_MGMT0_IDLE_DIS = (0x01 << PWR_MGMT0_IDLE_POS), 213 PWR_MGMT0_IDLE_EN = (0x00 << PWR_MGMT0_IDLE_POS), 214 } PWR_MGMT0_IDLE_t; 215 216 #if INV_IMU_IS_GYRO_SUPPORTED 217 /* GYRO_MODE */ 218 typedef enum { 219 PWR_MGMT0_GYRO_MODE_LN = (0x03 << PWR_MGMT0_GYRO_MODE_POS), 220 PWR_MGMT0_GYRO_MODE_LP = (0x02 << PWR_MGMT0_GYRO_MODE_POS), 221 PWR_MGMT0_GYRO_MODE_STANDBY = (0x01 << PWR_MGMT0_GYRO_MODE_POS), 222 PWR_MGMT0_GYRO_MODE_OFF = (0x00 << PWR_MGMT0_GYRO_MODE_POS), 223 } PWR_MGMT0_GYRO_MODE_t; 224 #endif 225 226 /* ACCEL_MODE */ 227 typedef enum { 228 PWR_MGMT0_ACCEL_MODE_LN = 0x03, 229 PWR_MGMT0_ACCEL_MODE_LP = 0x02, 230 PWR_MGMT0_ACCEL_MODE_OFF = 0x00, 231 } PWR_MGMT0_ACCEL_MODE_t; 232 233 #if INV_IMU_IS_GYRO_SUPPORTED 234 /* 235 * GYRO_CONFIG0 236 * Register Name: GYRO_CONFIG0 237 */ 238 239 /* GYRO_FS_SEL*/ 240 typedef enum { 241 #if INV_IMU_HFSR_SUPPORTED 242 GYRO_CONFIG0_FS_SEL_500dps = (3 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS), 243 GYRO_CONFIG0_FS_SEL_1000dps = (2 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS), 244 GYRO_CONFIG0_FS_SEL_2000dps = (1 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS), 245 GYRO_CONFIG0_FS_SEL_4000dps = (0 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS), 246 #else 247 GYRO_CONFIG0_FS_SEL_250dps = (3 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS), 248 GYRO_CONFIG0_FS_SEL_500dps = (2 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS), 249 GYRO_CONFIG0_FS_SEL_1000dps = (1 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS), 250 GYRO_CONFIG0_FS_SEL_2000dps = (0 << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS), 251 #endif 252 } GYRO_CONFIG0_FS_SEL_t; 253 254 /* GYRO_ODR */ 255 typedef enum { 256 GYRO_CONFIG0_ODR_1_5625_HZ = 0xF, 257 GYRO_CONFIG0_ODR_3_125_HZ = 0xE, 258 GYRO_CONFIG0_ODR_6_25_HZ = 0xD, 259 GYRO_CONFIG0_ODR_12_5_HZ = 0xC, 260 GYRO_CONFIG0_ODR_25_HZ = 0xB, 261 GYRO_CONFIG0_ODR_50_HZ = 0xA, 262 GYRO_CONFIG0_ODR_100_HZ = 0x9, 263 GYRO_CONFIG0_ODR_200_HZ = 0x8, 264 GYRO_CONFIG0_ODR_400_HZ = 0x7, 265 GYRO_CONFIG0_ODR_800_HZ = 0x6, 266 GYRO_CONFIG0_ODR_1600_HZ = 0x5, 267 } GYRO_CONFIG0_ODR_t; 268 #endif 269 270 /* 271 * ACCEL_CONFIG0 272 * Register Name: ACCEL_CONFIG0 273 */ 274 275 /* ACCEL_FS_SEL */ 276 typedef enum { 277 #if INV_IMU_HFSR_SUPPORTED 278 ACCEL_CONFIG0_FS_SEL_4g = (0x3 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS), 279 ACCEL_CONFIG0_FS_SEL_8g = (0x2 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS), 280 ACCEL_CONFIG0_FS_SEL_16g = (0x1 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS), 281 ACCEL_CONFIG0_FS_SEL_32g = (0x0 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS), 282 #else 283 ACCEL_CONFIG0_FS_SEL_2g = (0x3 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS), 284 ACCEL_CONFIG0_FS_SEL_4g = (0x2 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS), 285 ACCEL_CONFIG0_FS_SEL_8g = (0x1 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS), 286 ACCEL_CONFIG0_FS_SEL_16g = (0x0 << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS), 287 #endif 288 } ACCEL_CONFIG0_FS_SEL_t; 289 290 /* ACCEL_ODR */ 291 typedef enum { 292 ACCEL_CONFIG0_ODR_1_5625_HZ = 0xF, 293 ACCEL_CONFIG0_ODR_3_125_HZ = 0xE, 294 ACCEL_CONFIG0_ODR_6_25_HZ = 0xD, 295 ACCEL_CONFIG0_ODR_12_5_HZ = 0xC, 296 ACCEL_CONFIG0_ODR_25_HZ = 0xB, 297 ACCEL_CONFIG0_ODR_50_HZ = 0xA, 298 ACCEL_CONFIG0_ODR_100_HZ = 0x9, 299 ACCEL_CONFIG0_ODR_200_HZ = 0x8, 300 ACCEL_CONFIG0_ODR_400_HZ = 0x7, 301 ACCEL_CONFIG0_ODR_800_HZ = 0x6, 302 ACCEL_CONFIG0_ODR_1600_HZ = 0x5, 303 } ACCEL_CONFIG0_ODR_t; 304 305 #if INV_IMU_IS_GYRO_SUPPORTED 306 /* 307 * GYRO_CONFIG1 308 * Register Name: GYRO_CONFIG1 309 */ 310 311 /* GYRO_UI_FILT_BW_IND */ 312 typedef enum { 313 GYRO_CONFIG1_GYRO_FILT_BW_16 = (0x07 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS), 314 GYRO_CONFIG1_GYRO_FILT_BW_25 = (0x06 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS), 315 GYRO_CONFIG1_GYRO_FILT_BW_34 = (0x05 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS), 316 GYRO_CONFIG1_GYRO_FILT_BW_53 = (0x04 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS), 317 GYRO_CONFIG1_GYRO_FILT_BW_73 = (0x03 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS), 318 GYRO_CONFIG1_GYRO_FILT_BW_121 = (0x02 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS), 319 GYRO_CONFIG1_GYRO_FILT_BW_180 = (0x01 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS), 320 GYRO_CONFIG1_GYRO_FILT_BW_NO_FILTER = (0x00 << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS), 321 } GYRO_CONFIG1_GYRO_FILT_BW_t; 322 #endif 323 324 /* 325 * ACCEL_CONFIG1 326 * Register Name: ACCEL_CONFIG1 327 */ 328 329 /* ACCEL_UI_AVG_IND */ 330 typedef enum { 331 ACCEL_CONFIG1_ACCEL_FILT_AVG_64 = (0x5 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS), 332 ACCEL_CONFIG1_ACCEL_FILT_AVG_32 = (0x4 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS), 333 ACCEL_CONFIG1_ACCEL_FILT_AVG_16 = (0x3 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS), 334 ACCEL_CONFIG1_ACCEL_FILT_AVG_8 = (0x2 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS), 335 ACCEL_CONFIG1_ACCEL_FILT_AVG_4 = (0x1 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS), 336 ACCEL_CONFIG1_ACCEL_FILT_AVG_2 = (0x0 << ACCEL_CONFIG1_ACCEL_UI_AVG_POS), 337 } ACCEL_CONFIG1_ACCEL_FILT_AVG_t; 338 339 /* ACCEL_UI_FILT_BW_IND */ 340 typedef enum { 341 ACCEL_CONFIG1_ACCEL_FILT_BW_16 = (0x7 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS), 342 ACCEL_CONFIG1_ACCEL_FILT_BW_25 = (0x6 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS), 343 ACCEL_CONFIG1_ACCEL_FILT_BW_34 = (0x5 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS), 344 ACCEL_CONFIG1_ACCEL_FILT_BW_53 = (0x4 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS), 345 ACCEL_CONFIG1_ACCEL_FILT_BW_73 = (0x3 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS), 346 ACCEL_CONFIG1_ACCEL_FILT_BW_121 = (0x2 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS), 347 ACCEL_CONFIG1_ACCEL_FILT_BW_180 = (0x1 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS), 348 ACCEL_CONFIG1_ACCEL_FILT_BW_NO_FILTER = (0x0 << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS), 349 } ACCEL_CONFIG1_ACCEL_FILT_BW_t; 350 351 /* 352 * APEX_CONFIG0 353 * Register Name: APEX_CONFIG0 354 */ 355 356 /* DMP_POWER_SAVE_EN */ 357 typedef enum { 358 APEX_CONFIG0_DMP_POWER_SAVE_EN = (0x1 << APEX_CONFIG0_DMP_POWER_SAVE_EN_POS), 359 APEX_CONFIG0_DMP_POWER_SAVE_DIS = (0x0 << APEX_CONFIG0_DMP_POWER_SAVE_EN_POS), 360 } APEX_CONFIG0_DMP_POWER_SAVE_t; 361 362 /* DMP_INIT_EN */ 363 typedef enum { 364 APEX_CONFIG0_DMP_INIT_EN = (0x01 << APEX_CONFIG0_DMP_INIT_EN_POS), 365 APEX_CONFIG0_DMP_INIT_DIS = (0x00 << APEX_CONFIG0_DMP_INIT_EN_POS), 366 } APEX_CONFIG0_DMP_INIT_t; 367 368 /* DMP_MEM_RESET */ 369 typedef enum { 370 APEX_CONFIG0_DMP_MEM_RESET_APEX_ST_EN = (0x01 << APEX_CONFIG0_DMP_MEM_RESET_EN_POS), 371 APEX_CONFIG0_DMP_MEM_RESET_DIS = (0x00 << APEX_CONFIG0_DMP_MEM_RESET_EN_POS), 372 } APEX_CONFIG0_DMP_MEM_RESET_t; 373 374 /* 375 * APEX_CONFIG1 376 * Register Name: APEX_CONFIG1 377 */ 378 379 /* SMD_ENABLE */ 380 typedef enum { 381 APEX_CONFIG1_SMD_ENABLE_DIS = (0x00 << APEX_CONFIG1_SMD_ENABLE_POS), 382 APEX_CONFIG1_SMD_ENABLE_EN = (0x01 << APEX_CONFIG1_SMD_ENABLE_POS), 383 } APEX_CONFIG1_SMD_ENABLE_t; 384 385 /* FF_ENABLE */ 386 typedef enum { 387 APEX_CONFIG1_FF_ENABLE_DIS = (0x00 << APEX_CONFIG1_FF_ENABLE_POS), 388 APEX_CONFIG1_FF_ENABLE_EN = (0x01 << APEX_CONFIG1_FF_ENABLE_POS), 389 } APEX_CONFIG1_FF_ENABLE_t; 390 391 /* TILT_ENABLE */ 392 typedef enum { 393 APEX_CONFIG1_TILT_ENABLE_DIS = (0x0 << APEX_CONFIG1_TILT_ENABLE_POS), 394 APEX_CONFIG1_TILT_ENABLE_EN = (0x1 << APEX_CONFIG1_TILT_ENABLE_POS), 395 } APEX_CONFIG1_TILT_ENABLE_t; 396 397 /* PED_ENABLE */ 398 typedef enum { 399 APEX_CONFIG1_PED_ENABLE_DIS = (0x0 << APEX_CONFIG1_PED_ENABLE_POS), 400 APEX_CONFIG1_PED_ENABLE_EN = (0x1 << APEX_CONFIG1_PED_ENABLE_POS), 401 } APEX_CONFIG1_PED_ENABLE_t; 402 403 /* DMP_ODR */ 404 typedef enum { 405 APEX_CONFIG1_DMP_ODR_25Hz = (0x0 << APEX_CONFIG1_DMP_ODR_POS), 406 APEX_CONFIG1_DMP_ODR_50Hz = (0x2 << APEX_CONFIG1_DMP_ODR_POS), 407 APEX_CONFIG1_DMP_ODR_100Hz = (0x3 << APEX_CONFIG1_DMP_ODR_POS), 408 APEX_CONFIG1_DMP_ODR_400Hz = (0x1 << APEX_CONFIG1_DMP_ODR_POS), 409 } APEX_CONFIG1_DMP_ODR_t; 410 411 /* 412 * WOM_CONFIG 413 * Register Name: WOM_CONFIG 414 */ 415 416 /* WOM_INT_DUR */ 417 typedef enum { 418 WOM_CONFIG_WOM_INT_DUR_1_SMPL = (0x00 << WOM_CONFIG_WOM_INT_DUR_POS), 419 WOM_CONFIG_WOM_INT_DUR_2_SMPL = (0x01 << WOM_CONFIG_WOM_INT_DUR_POS), 420 WOM_CONFIG_WOM_INT_DUR_3_SMPL = (0x02 << WOM_CONFIG_WOM_INT_DUR_POS), 421 WOM_CONFIG_WOM_INT_DUR_4_SMPL = (0x03 << WOM_CONFIG_WOM_INT_DUR_POS), 422 } WOM_CONFIG_WOM_INT_DUR_t; 423 424 /* WOM_INT_MODE */ 425 typedef enum { 426 WOM_CONFIG_WOM_INT_MODE_ANDED = (0x01 << WOM_CONFIG_WOM_INT_MODE_POS), 427 WOM_CONFIG_WOM_INT_MODE_ORED = (0x00 << WOM_CONFIG_WOM_INT_MODE_POS), 428 } WOM_CONFIG_WOM_INT_MODE_t; 429 430 /* WOM_MODE */ 431 typedef enum { 432 WOM_CONFIG_WOM_MODE_CMP_PREV = (0x01 << WOM_CONFIG_WOM_MODE_POS), 433 WOM_CONFIG_WOM_MODE_CMP_INIT = (0x00 << WOM_CONFIG_WOM_MODE_POS), 434 } WOM_CONFIG_WOM_MODE_t; 435 436 /* WOM_ENABLE */ 437 typedef enum { 438 WOM_CONFIG_WOM_EN_ENABLE = (0x01 << WOM_CONFIG_WOM_EN_POS), 439 WOM_CONFIG_WOM_EN_DISABLE = (0x00 << WOM_CONFIG_WOM_EN_POS), 440 } WOM_CONFIG_WOM_EN_t; 441 442 /* 443 * FIFO_CONFIG1 444 * Register Name: FIFO_CONFIG 445 */ 446 447 /* FIFO_MODE */ 448 typedef enum { 449 FIFO_CONFIG1_FIFO_MODE_SNAPSHOT = (0x01 << FIFO_CONFIG1_FIFO_MODE_POS), 450 FIFO_CONFIG1_FIFO_MODE_STREAM = (0x00 << FIFO_CONFIG1_FIFO_MODE_POS) 451 } FIFO_CONFIG1_FIFO_MODE_t; 452 453 /* FIFO_BYPASS */ 454 typedef enum { 455 FIFO_CONFIG1_FIFO_BYPASS_ON = (0x01 << FIFO_CONFIG1_FIFO_BYPASS_POS), 456 FIFO_CONFIG1_FIFO_BYPASS_OFF = (0x00 << FIFO_CONFIG1_FIFO_BYPASS_POS), 457 } FIFO_CONFIG1_FIFO_BYPASS_t; 458 459 /* 460 * APEX_DATA3 461 * Register Name: APEX_DATA3 462 */ 463 464 /* DMP_IDLE */ 465 typedef enum { 466 APEX_DATA3_DMP_IDLE_ON = (0x01 << APEX_DATA3_DMP_IDLE_POS), 467 APEX_DATA3_DMP_IDLE_OFF = (0x00 << APEX_DATA3_DMP_IDLE_POS), 468 } APEX_DATA3_DMP_IDLE_OFF_t; 469 470 /* ACTIVITY_CLASS */ 471 typedef enum { 472 APEX_DATA3_ACTIVITY_CLASS_OTHER = 0x0, 473 APEX_DATA3_ACTIVITY_CLASS_WALK = 0x1, 474 APEX_DATA3_ACTIVITY_CLASS_RUN = 0x2, 475 } APEX_DATA3_ACTIVITY_CLASS_t; 476 477 /* 478 * INTF_CONFIG0 479 * Register Name: INTF_CONFIG0 480 */ 481 482 /* FIFO_COUNT_REC */ 483 typedef enum { 484 INTF_CONFIG0_FIFO_COUNT_REC_RECORD = (0x01 << INTF_CONFIG0_FIFO_COUNT_FORMAT_POS), 485 INTF_CONFIG0_FIFO_COUNT_REC_BYTE = (0x00 << INTF_CONFIG0_FIFO_COUNT_FORMAT_POS), 486 } INTF_CONFIG0_FIFO_COUNT_REC_t; 487 488 /* FIFO_COUNT_ENDIAN */ 489 typedef enum { 490 INTF_CONFIG0_FIFO_COUNT_BIG_ENDIAN = (0x01 << INTF_CONFIG0_FIFO_COUNT_ENDIAN_POS), 491 INTF_CONFIG0_FIFO_COUNT_LITTLE_ENDIAN = (0x00 << INTF_CONFIG0_FIFO_COUNT_ENDIAN_POS), 492 } INTF_CONFIG0_FIFO_COUNT_ENDIAN_t; 493 494 /* DATA_ENDIAN */ 495 typedef enum { 496 INTF_CONFIG0_DATA_BIG_ENDIAN = (0x01 << INTF_CONFIG0_SENSOR_DATA_ENDIAN_POS), 497 INTF_CONFIG0_DATA_LITTLE_ENDIAN = (0x00 << INTF_CONFIG0_SENSOR_DATA_ENDIAN_POS), 498 } INTF_CONFIG0_DATA_ENDIAN_t; 499 500 /* --------------------------------------------------------------------------- 501 * register bank MREG1 502 * ---------------------------------------------------------------------------- */ 503 504 /* 505 * TMST_CONFIG1_MREG1 506 * Register Name: TMST_CONFIG1 507 */ 508 509 /* TMST_RES */ 510 typedef enum { 511 TMST_CONFIG1_RESOL_16us = (0x01 << TMST_CONFIG1_TMST_RES_POS), 512 TMST_CONFIG1_RESOL_1us = (0x00 << TMST_CONFIG1_TMST_RES_POS), 513 } TMST_CONFIG1_RESOL_t; 514 515 /* TMST_FSYNC */ 516 typedef enum { 517 TMST_CONFIG1_TMST_FSYNC_EN = (0x01 << TMST_CONFIG1_TMST_FSYNC_EN_POS), 518 TMST_CONFIG1_TMST_FSYNC_DIS = (0x00 << TMST_CONFIG1_TMST_FSYNC_EN_POS), 519 } TMST_CONFIG1_TMST_FSYNC_EN_t; 520 521 /* TMST_EN */ 522 typedef enum { 523 TMST_CONFIG1_TMST_EN = 0x01, 524 TMST_CONFIG1_TMST_DIS = 0x00, 525 } TMST_CONFIG1_TMST_EN_t; 526 527 /* 528 * FIFO_CONFIG5_MREG1 529 * Register Name: FIFO_CONFIG5 530 */ 531 /* FIFO_WM_GT_TH */ 532 typedef enum { 533 FIFO_CONFIG5_WM_GT_TH_EN = (0x1 << FIFO_CONFIG5_FIFO_WM_GT_TH_POS), 534 FIFO_CONFIG5_WM_GT_TH_DIS = (0x0 << FIFO_CONFIG5_FIFO_WM_GT_TH_POS), 535 } FIFO_CONFIG5_WM_GT_t; 536 537 /* FIFO_HIRES_EN */ 538 typedef enum { 539 FIFO_CONFIG5_HIRES_EN = (0x1 << FIFO_CONFIG5_FIFO_HIRES_EN_POS), 540 FIFO_CONFIG5_HIRES_DIS = (0x0 << FIFO_CONFIG5_FIFO_HIRES_EN_POS), 541 } FIFO_CONFIG5_HIRES_t; 542 543 /* FIFO_TMST_FSYNC_EN */ 544 typedef enum { 545 FIFO_CONFIG5_TMST_FSYNC_EN = (0x1 << FIFO_CONFIG5_FIFO_TMST_FSYNC_EN_POS), 546 FIFO_CONFIG5_TMST_FSYNC_DIS = (0x0 << FIFO_CONFIG5_FIFO_TMST_FSYNC_EN_POS), 547 } FIFO_CONFIG5_TMST_FSYNC_t; 548 549 #if INV_IMU_IS_GYRO_SUPPORTED 550 /* FIFO_GYRO_EN */ 551 typedef enum { 552 FIFO_CONFIG5_GYRO_EN = (0x1 << FIFO_CONFIG5_FIFO_GYRO_EN_POS), 553 FIFO_CONFIG5_GYRO_DIS = (0x0 << FIFO_CONFIG5_FIFO_GYRO_EN_POS), 554 } FIFO_CONFIG5_GYRO_t; 555 #endif 556 557 /* FIFO_ACCEL_EN*/ 558 typedef enum { 559 FIFO_CONFIG5_ACCEL_EN = 0x01, 560 FIFO_CONFIG5_ACCEL_DIS = 0x00, 561 } FIFO_CONFIG5_ACCEL_t; 562 563 #if INV_IMU_IS_GYRO_SUPPORTED 564 /* 565 * FSYNC_CONFIG_MREG1 566 * Register Name: FSYNC_CONFIG 567 */ 568 569 /* FSYNC_UI_SEL */ 570 typedef enum { 571 FSYNC_CONFIG_UI_SEL_NO = (0x0 << FSYNC_CONFIG_FSYNC_UI_SEL_POS), 572 FSYNC_CONFIG_UI_SEL_TEMP = (0x1 << FSYNC_CONFIG_FSYNC_UI_SEL_POS), 573 FSYNC_CONFIG_UI_SEL_GYRO_X = (0x2 << FSYNC_CONFIG_FSYNC_UI_SEL_POS), 574 FSYNC_CONFIG_UI_SEL_GYRO_Y = (0x3 << FSYNC_CONFIG_FSYNC_UI_SEL_POS), 575 FSYNC_CONFIG_UI_SEL_GYRO_Z = (0x4 << FSYNC_CONFIG_FSYNC_UI_SEL_POS), 576 FSYNC_CONFIG_UI_SEL_ACCEL_X = (0x5 << FSYNC_CONFIG_FSYNC_UI_SEL_POS), 577 FSYNC_CONFIG_UI_SEL_ACCEL_Y = (0x6 << FSYNC_CONFIG_FSYNC_UI_SEL_POS), 578 FSYNC_CONFIG_UI_SEL_ACCEL_Z = (0x7 << FSYNC_CONFIG_FSYNC_UI_SEL_POS), 579 } FSYNC_CONFIG_UI_SEL_t; 580 #endif 581 582 /* 583 * ST_CONFIG_MREG1 584 * Register Name: ST_CONFIG 585 */ 586 typedef enum { 587 ST_CONFIG_16_SAMPLES = (0 << ST_CONFIG_ST_NUMBER_SAMPLE_POS), 588 ST_CONFIG_200_SAMPLES = (1 << ST_CONFIG_ST_NUMBER_SAMPLE_POS), 589 } ST_CONFIG_NUM_SAMPLES_t; 590 591 typedef enum { 592 ST_CONFIG_ACCEL_ST_LIM_50 = (7 << ST_CONFIG_ACCEL_ST_LIM_POS), 593 } ST_CONFIG_ACCEL_ST_LIM_t; 594 595 #if INV_IMU_IS_GYRO_SUPPORTED 596 typedef enum { 597 ST_CONFIG_GYRO_ST_LIM_50 = (7 << ST_CONFIG_GYRO_ST_LIM_POS), 598 } ST_CONFIG_GYRO_ST_LIM_t; 599 #endif 600 601 /* 602 * SELFTEST_MREG1 603 * Register Name: SELFTEST 604 */ 605 606 /* GYRO_ST_EN and ACCEL_ST_EN */ 607 typedef enum { 608 SELFTEST_DIS = 0, 609 SELFTEST_ACCEL_EN = SELFTEST_ACCEL_ST_EN_MASK, 610 #if INV_IMU_IS_GYRO_SUPPORTED 611 SELFTEST_GYRO_EN = SELFTEST_GYRO_ST_EN_MASK, 612 SELFTEST_EN = (SELFTEST_ACCEL_ST_EN_MASK | SELFTEST_GYRO_ST_EN_MASK) 613 #endif 614 } SELFTEST_ACCEL_GYRO_ST_EN_t; 615 616 /* 617 * OTP_CONFIG_MREG1 618 * Register Name: OTP_CONFIG 619 */ 620 621 /* OTP_CONFIG */ 622 typedef enum { 623 OTP_CONFIG_OTP_COPY_TRIM = (1 << OTP_CONFIG_OTP_COPY_MODE_POS), 624 OTP_CONFIG_OTP_COPY_ST_DATA = (3 << OTP_CONFIG_OTP_COPY_MODE_POS), 625 } OTP_CONFIG_COPY_MODE_t; 626 627 /* 628 * APEX_CONFIG2_MREG1 629 * Register Name: APEX_CONFIG2 630 */ 631 632 /* LOW_ENERGY_AMP_TH_SEL */ 633 typedef enum { 634 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_30_MG = (0 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 635 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_35_MG = (1 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 636 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_40_MG = (2 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 637 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_45_MG = (3 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 638 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_50_MG = (4 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 639 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_55_MG = (5 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 640 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_60_MG = (6 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 641 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_65_MG = (7 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 642 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_70_MG = (8 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 643 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_75_MG = (9 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 644 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_80_MG = (10 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 645 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_85_MG = (11 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 646 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_90_MG = (12 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 647 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_95_MG = (13 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 648 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_100_MG = (14 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 649 APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_105_MG = (15 << APEX_CONFIG2_LOW_ENERGY_AMP_TH_SEL_POS), 650 } APEX_CONFIG2_LOW_ENERGY_AMP_TH_t; 651 652 /* DMP_POWER_SAVE_TIME_SEL */ 653 typedef enum { 654 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_0_S = 0x0, 655 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_4_S = 0x1, 656 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_8_S = 0x2, 657 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_12_S = 0x3, 658 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_16_S = 0x4, 659 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_20_S = 0x5, 660 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_24_S = 0x6, 661 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_28_S = 0x7, 662 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_32_S = 0x8, 663 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_36_S = 0x9, 664 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_40_S = 0xA, 665 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_44_S = 0xB, 666 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_48_S = 0xC, 667 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_52_S = 0xD, 668 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_56_S = 0xE, 669 APEX_CONFIG2_DMP_POWER_SAVE_TIME_SEL_60_S = 0xF, 670 } APEX_CONFIG2_DMP_POWER_SAVE_TIME_t; 671 672 /* 673 * APEX_CONFIG3_MREG1 674 * Register Name: APEX_CONFIG3 675 */ 676 677 /* PEDO_AMP_TH_SEL */ 678 typedef enum { 679 APEX_CONFIG3_PEDO_AMP_TH_30_MG = (0 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 680 APEX_CONFIG3_PEDO_AMP_TH_34_MG = (1 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 681 APEX_CONFIG3_PEDO_AMP_TH_38_MG = (2 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 682 APEX_CONFIG3_PEDO_AMP_TH_42_MG = (3 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 683 APEX_CONFIG3_PEDO_AMP_TH_46_MG = (4 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 684 APEX_CONFIG3_PEDO_AMP_TH_50_MG = (5 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 685 APEX_CONFIG3_PEDO_AMP_TH_54_MG = (6 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 686 APEX_CONFIG3_PEDO_AMP_TH_58_MG = (7 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 687 APEX_CONFIG3_PEDO_AMP_TH_62_MG = (8 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 688 APEX_CONFIG3_PEDO_AMP_TH_66_MG = (9 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 689 APEX_CONFIG3_PEDO_AMP_TH_70_MG = (10 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 690 APEX_CONFIG3_PEDO_AMP_TH_74_MG = (11 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 691 APEX_CONFIG3_PEDO_AMP_TH_78_MG = (12 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 692 APEX_CONFIG3_PEDO_AMP_TH_82_MG = (13 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 693 APEX_CONFIG3_PEDO_AMP_TH_86_MG = (14 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 694 APEX_CONFIG3_PEDO_AMP_TH_90_MG = (15 << APEX_CONFIG3_PED_AMP_TH_SEL_POS), 695 } APEX_CONFIG3_PEDO_AMP_TH_t; 696 697 /* 698 * APEX_CONFIG4_MREG1 699 * Register Name: APEX_CONFIG4 700 */ 701 702 /* PEDO_SB_TIMER_TH_SEL */ 703 typedef enum { 704 APEX_CONFIG4_PEDO_SB_TIMER_TH_50_SAMPLES = (0 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS), 705 APEX_CONFIG4_PEDO_SB_TIMER_TH_75_SAMPLES = (1 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS), 706 APEX_CONFIG4_PEDO_SB_TIMER_TH_100_SAMPLES = (2 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS), 707 APEX_CONFIG4_PEDO_SB_TIMER_TH_125_SAMPLES = (3 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS), 708 APEX_CONFIG4_PEDO_SB_TIMER_TH_150_SAMPLES = (4 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS), 709 APEX_CONFIG4_PEDO_SB_TIMER_TH_175_SAMPLES = (5 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS), 710 APEX_CONFIG4_PEDO_SB_TIMER_TH_200_SAMPLES = (6 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS), 711 APEX_CONFIG4_PEDO_SB_TIMER_TH_225_SAMPLES = (7 << APEX_CONFIG4_PED_SB_TIMER_TH_SEL_POS), 712 } APEX_CONFIG4_PEDO_SB_TIMER_TH_t; 713 714 /* PEDO_HI_ENRGY_TH_SEL */ 715 typedef enum { 716 APEX_CONFIG4_PEDO_HI_ENRGY_TH_88_MG = (0 << APEX_CONFIG4_PED_HI_EN_TH_SEL_POS), 717 APEX_CONFIG4_PEDO_HI_ENRGY_TH_104_MG = (1 << APEX_CONFIG4_PED_HI_EN_TH_SEL_POS), 718 APEX_CONFIG4_PEDO_HI_ENRGY_TH_133_MG = (2 << APEX_CONFIG4_PED_HI_EN_TH_SEL_POS), 719 APEX_CONFIG4_PEDO_HI_ENRGY_TH_155_MG = (3 << APEX_CONFIG4_PED_HI_EN_TH_SEL_POS), 720 } APEX_CONFIG4_PEDO_HI_ENRGY_TH_t; 721 722 /* 723 * APEX_CONFIG5_MREG1 724 * Register Name: APEX_CONFIG5 725 */ 726 727 /* TILT_WAIT_TIME_SEL */ 728 typedef enum { 729 APEX_CONFIG5_TILT_WAIT_TIME_0_S = (0 << APEX_CONFIG5_TILT_WAIT_TIME_SEL_POS), 730 APEX_CONFIG5_TILT_WAIT_TIME_2_S = (1 << APEX_CONFIG5_TILT_WAIT_TIME_SEL_POS), 731 APEX_CONFIG5_TILT_WAIT_TIME_4_S = (2 << APEX_CONFIG5_TILT_WAIT_TIME_SEL_POS), 732 APEX_CONFIG5_TILT_WAIT_TIME_6_S = (3 << APEX_CONFIG5_TILT_WAIT_TIME_SEL_POS), 733 } APEX_CONFIG5_TILT_WAIT_TIME_t; 734 735 /* LOWG_PEAK_TH_HYST_SEL */ 736 typedef enum { 737 APEX_CONFIG5_LOWG_PEAK_TH_HYST_31_MG = (0 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS), 738 APEX_CONFIG5_LOWG_PEAK_TH_HYST_63_MG = (1 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS), 739 APEX_CONFIG5_LOWG_PEAK_TH_HYST_94_MG = (2 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS), 740 APEX_CONFIG5_LOWG_PEAK_TH_HYST_125_MG = (3 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS), 741 APEX_CONFIG5_LOWG_PEAK_TH_HYST_156_MG = (4 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS), 742 APEX_CONFIG5_LOWG_PEAK_TH_HYST_188_MG = (5 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS), 743 APEX_CONFIG5_LOWG_PEAK_TH_HYST_219_MG = (6 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS), 744 APEX_CONFIG5_LOWG_PEAK_TH_HYST_250_MG = (7 << APEX_CONFIG5_LOWG_PEAK_TH_HYST_SEL_POS), 745 } APEX_CONFIG5_LOWG_PEAK_TH_HYST_t; 746 747 /* HIGHG_PEAK_TH_HYST_SEL */ 748 typedef enum { 749 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_31_MG = (0 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS), 750 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_63_MG = (1 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS), 751 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_94_MG = (2 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS), 752 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_125_MG = (3 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS), 753 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_156_MG = (4 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS), 754 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_188_MG = (5 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS), 755 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_219_MG = (6 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS), 756 APEX_CONFIG5_HIGHG_PEAK_TH_HYST_250_MG = (7 << APEX_CONFIG5_HIGHG_PEAK_TH_HYST_SEL_POS), 757 } APEX_CONFIG5_HIGHG_PEAK_TH_HYST_t; 758 759 /* 760 * APEX_CONFIG9_MREG1 761 * Register Name: APEX_CONFIG9 762 */ 763 764 /* FF_DEBOUNCE_DURATION_SEL */ 765 typedef enum { 766 APEX_CONFIG9_FF_DEBOUNCE_DURATION_0_MS = (0 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 767 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1250_MS = (1 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 768 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1375_MS = (2 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 769 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1500_MS = (3 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 770 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1625_MS = (4 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 771 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1750_MS = (5 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 772 APEX_CONFIG9_FF_DEBOUNCE_DURATION_1875_MS = (6 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 773 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2000_MS = (7 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 774 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2125_MS = (8 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 775 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2250_MS = (9 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 776 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2375_MS = (10 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 777 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2500_MS = (11 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 778 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2625_MS = (12 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 779 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2750_MS = (13 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 780 APEX_CONFIG9_FF_DEBOUNCE_DURATION_2875_MS = (14 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 781 APEX_CONFIG9_FF_DEBOUNCE_DURATION_3000_MS = (15 << APEX_CONFIG9_FF_DEBOUNCE_DURATION_SEL_POS), 782 } APEX_CONFIG9_FF_DEBOUNCE_DURATION_t; 783 784 /* SMD_SENSITIVITY_SEL */ 785 typedef enum { 786 APEX_CONFIG9_SMD_SENSITIVITY_0 = (0 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS), 787 APEX_CONFIG9_SMD_SENSITIVITY_1 = (1 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS), 788 APEX_CONFIG9_SMD_SENSITIVITY_2 = (2 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS), 789 APEX_CONFIG9_SMD_SENSITIVITY_3 = (3 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS), 790 APEX_CONFIG9_SMD_SENSITIVITY_4 = (4 << APEX_CONFIG9_SMD_SENSITIVITY_SEL_POS), 791 } APEX_CONFIG9_SMD_SENSITIVITY_t; 792 793 /* SMD_SENSITIVITY_MODE */ 794 typedef enum { 795 APEX_CONFIG9_SENSITIVITY_MODE_NORMAL = (0 << APEX_CONFIG9_SENSITIVITY_MODE_POS), 796 APEX_CONFIG9_SENSITIVITY_MODE_SLOW_WALK = (1 << APEX_CONFIG9_SENSITIVITY_MODE_POS), 797 } APEX_CONFIG9_SENSITIVITY_MODE_t; 798 799 /* 800 * APEX_CONFIG10_MREG1 801 * Register Name: APEX_CONFIG10 802 */ 803 804 /* LOWG_PEAK_TH_SEL */ 805 typedef enum { 806 APEX_CONFIG10_LOWG_PEAK_TH_31_MG = (0x00 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 807 APEX_CONFIG10_LOWG_PEAK_TH_63_MG = (0x01 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 808 APEX_CONFIG10_LOWG_PEAK_TH_94_MG = (0x02 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 809 APEX_CONFIG10_LOWG_PEAK_TH_125_MG = (0x03 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 810 APEX_CONFIG10_LOWG_PEAK_TH_156_MG = (0x04 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 811 APEX_CONFIG10_LOWG_PEAK_TH_188_MG = (0x05 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 812 APEX_CONFIG10_LOWG_PEAK_TH_219_MG = (0x06 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 813 APEX_CONFIG10_LOWG_PEAK_TH_250_MG = (0x07 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 814 APEX_CONFIG10_LOWG_PEAK_TH_281_MG = (0x08 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 815 APEX_CONFIG10_LOWG_PEAK_TH_313_MG = (0x09 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 816 APEX_CONFIG10_LOWG_PEAK_TH_344_MG = (0x0A << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 817 APEX_CONFIG10_LOWG_PEAK_TH_375_MG = (0x0B << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 818 APEX_CONFIG10_LOWG_PEAK_TH_406_MG = (0x0C << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 819 APEX_CONFIG10_LOWG_PEAK_TH_438_MG = (0x0D << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 820 APEX_CONFIG10_LOWG_PEAK_TH_469_MG = (0x0E << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 821 APEX_CONFIG10_LOWG_PEAK_TH_500_MG = (0x0F << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 822 APEX_CONFIG10_LOWG_PEAK_TH_531_MG = (0x10 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 823 APEX_CONFIG10_LOWG_PEAK_TH_563_MG = (0x11 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 824 APEX_CONFIG10_LOWG_PEAK_TH_594_MG = (0x12 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 825 APEX_CONFIG10_LOWG_PEAK_TH_625_MG = (0x13 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 826 APEX_CONFIG10_LOWG_PEAK_TH_656_MG = (0x14 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 827 APEX_CONFIG10_LOWG_PEAK_TH_688_MG = (0x15 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 828 APEX_CONFIG10_LOWG_PEAK_TH_719_MG = (0x16 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 829 APEX_CONFIG10_LOWG_PEAK_TH_750_MG = (0x17 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 830 APEX_CONFIG10_LOWG_PEAK_TH_781_MG = (0x18 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 831 APEX_CONFIG10_LOWG_PEAK_TH_813_MG = (0x19 << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 832 APEX_CONFIG10_LOWG_PEAK_TH_844_MG = (0x1A << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 833 APEX_CONFIG10_LOWG_PEAK_TH_875_MG = (0x1B << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 834 APEX_CONFIG10_LOWG_PEAK_TH_906_MG = (0x1C << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 835 APEX_CONFIG10_LOWG_PEAK_TH_938_MG = (0x1D << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 836 APEX_CONFIG10_LOWG_PEAK_TH_969_MG = (0x1E << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 837 APEX_CONFIG10_LOWG_PEAK_TH_1000_MG = (0x1F << APEX_CONFIG10_LOWG_PEAK_TH_SEL_POS), 838 } APEX_CONFIG10_LOWG_PEAK_TH_t; 839 840 /* LOWG_TIME_TH_SEL */ 841 typedef enum { 842 APEX_CONFIG10_LOWG_TIME_TH_1_SAMPLE = (0x00 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS), 843 APEX_CONFIG10_LOWG_TIME_TH_2_SAMPLES = (0x01 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS), 844 APEX_CONFIG10_LOWG_TIME_TH_3_SAMPLES = (0x02 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS), 845 APEX_CONFIG10_LOWG_TIME_TH_4_SAMPLES = (0x03 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS), 846 APEX_CONFIG10_LOWG_TIME_TH_5_SAMPLES = (0x04 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS), 847 APEX_CONFIG10_LOWG_TIME_TH_6_SAMPLES = (0x05 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS), 848 APEX_CONFIG10_LOWG_TIME_TH_7_SAMPLES = (0x06 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS), 849 APEX_CONFIG10_LOWG_TIME_TH_8_SAMPLES = (0x07 << APEX_CONFIG10_LOWG_TIME_TH_SEL_POS), 850 } APEX_CONFIG10_LOWG_TIME_TH_SAMPLES_t; 851 852 /* 853 * APEX_CONFIG11_MREG1 854 * Register Name: APEX_CONFIG11 855 */ 856 857 /* HIGHG_PEAK_TH_SEL */ 858 typedef enum { 859 APEX_CONFIG11_HIGHG_PEAK_TH_250_MG = (0x00 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 860 APEX_CONFIG11_HIGHG_PEAK_TH_500_MG = (0x01 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 861 APEX_CONFIG11_HIGHG_PEAK_TH_750_MG = (0x02 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 862 APEX_CONFIG11_HIGHG_PEAK_TH_1000MG = (0x03 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 863 APEX_CONFIG11_HIGHG_PEAK_TH_1250_MG = (0x04 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 864 APEX_CONFIG11_HIGHG_PEAK_TH_1500_MG = (0x05 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 865 APEX_CONFIG11_HIGHG_PEAK_TH_1750_MG = (0x06 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 866 APEX_CONFIG11_HIGHG_PEAK_TH_2000_MG = (0x07 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 867 APEX_CONFIG11_HIGHG_PEAK_TH_2250_MG = (0x08 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 868 APEX_CONFIG11_HIGHG_PEAK_TH_2500_MG = (0x09 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 869 APEX_CONFIG11_HIGHG_PEAK_TH_2750_MG = (0x0A << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 870 APEX_CONFIG11_HIGHG_PEAK_TH_3000_MG = (0x0B << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 871 APEX_CONFIG11_HIGHG_PEAK_TH_3250_MG = (0x0C << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 872 APEX_CONFIG11_HIGHG_PEAK_TH_3500_MG = (0x0D << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 873 APEX_CONFIG11_HIGHG_PEAK_TH_3750_MG = (0x0E << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 874 APEX_CONFIG11_HIGHG_PEAK_TH_4000_MG = (0x0F << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 875 APEX_CONFIG11_HIGHG_PEAK_TH_4250_MG = (0x10 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 876 APEX_CONFIG11_HIGHG_PEAK_TH_4500_MG = (0x11 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 877 APEX_CONFIG11_HIGHG_PEAK_TH_4750_MG = (0x12 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 878 APEX_CONFIG11_HIGHG_PEAK_TH_5000_MG = (0x13 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 879 APEX_CONFIG11_HIGHG_PEAK_TH_5250_MG = (0x14 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 880 APEX_CONFIG11_HIGHG_PEAK_TH_5500_MG = (0x15 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 881 APEX_CONFIG11_HIGHG_PEAK_TH_5750_MG = (0x16 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 882 APEX_CONFIG11_HIGHG_PEAK_TH_6000_MG = (0x17 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 883 APEX_CONFIG11_HIGHG_PEAK_TH_6250_MG = (0x18 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 884 APEX_CONFIG11_HIGHG_PEAK_TH_6500_MG = (0x19 << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 885 APEX_CONFIG11_HIGHG_PEAK_TH_6750_MG = (0x1A << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 886 APEX_CONFIG11_HIGHG_PEAK_TH_7000_MG = (0x1B << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 887 APEX_CONFIG11_HIGHG_PEAK_TH_7250_MG = (0x1C << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 888 APEX_CONFIG11_HIGHG_PEAK_TH_7500_MG = (0x1D << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 889 APEX_CONFIG11_HIGHG_PEAK_TH_7750_MG = (0x1E << APEX_CONFIG11_HIGHG_PEAK_TH_SEL_POS), 890 } APEX_CONFIG11_HIGHG_PEAK_TH_t; 891 892 /* HIGHG_TIME_TH_SEL */ 893 typedef enum { 894 APEX_CONFIG11_HIGHG_TIME_TH_1_SAMPLE = (0x00 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS), 895 APEX_CONFIG11_HIGHG_TIME_TH_2_SAMPLES = (0x01 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS), 896 APEX_CONFIG11_HIGHG_TIME_TH_3_SAMPLES = (0x02 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS), 897 APEX_CONFIG11_HIGHG_TIME_TH_4_SAMPLES = (0x03 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS), 898 APEX_CONFIG11_HIGHG_TIME_TH_5_SAMPLES = (0x04 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS), 899 APEX_CONFIG11_HIGHG_TIME_TH_6_SAMPLES = (0x05 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS), 900 APEX_CONFIG11_HIGHG_TIME_TH_7_SAMPLES = (0x06 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS), 901 APEX_CONFIG11_HIGHG_TIME_TH_8_SAMPLES = (0x07 << APEX_CONFIG11_HIGHG_TIME_TH_SEL_POS), 902 } APEX_CONFIG11_HIGHG_TIME_TH_SAMPLES_t; 903 904 /* 905 * FDR_CONFIG_MREG1 906 * Register Name: FDR_CONFIG 907 */ 908 909 /* FDR_SEL */ 910 typedef enum { 911 FDR_CONFIG_FDR_SEL_DIS = (0x0 << FDR_CONFIG_FDR_SEL_POS), 912 FDR_CONFIG_FDR_SEL_FACTOR_2 = (0x8 << FDR_CONFIG_FDR_SEL_POS), 913 FDR_CONFIG_FDR_SEL_FACTOR_4 = (0x9 << FDR_CONFIG_FDR_SEL_POS), 914 FDR_CONFIG_FDR_SEL_FACTOR_8 = (0xA << FDR_CONFIG_FDR_SEL_POS), 915 FDR_CONFIG_FDR_SEL_FACTOR_16 = (0xB << FDR_CONFIG_FDR_SEL_POS), 916 FDR_CONFIG_FDR_SEL_FACTOR_32 = (0xC << FDR_CONFIG_FDR_SEL_POS), 917 FDR_CONFIG_FDR_SEL_FACTOR_64 = (0xD << FDR_CONFIG_FDR_SEL_POS), 918 FDR_CONFIG_FDR_SEL_FACTOR_128 = (0xE << FDR_CONFIG_FDR_SEL_POS), 919 FDR_CONFIG_FDR_SEL_FACTOR_256 = (0xF << FDR_CONFIG_FDR_SEL_POS), 920 } FDR_CONFIG_FDR_SEL_t; 921 922 /* 923 * APEX_CONFIG12_MREG1 924 * Register Name: APEX_CONFIG12 925 */ 926 /* FF_MAX_DURATION_SEL */ 927 typedef enum { 928 APEX_CONFIG12_FF_MAX_DURATION_102_CM = (0 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 929 APEX_CONFIG12_FF_MAX_DURATION_120_CM = (1 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 930 APEX_CONFIG12_FF_MAX_DURATION_139_CM = (2 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 931 APEX_CONFIG12_FF_MAX_DURATION_159_CM = (3 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 932 APEX_CONFIG12_FF_MAX_DURATION_181_CM = (4 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 933 APEX_CONFIG12_FF_MAX_DURATION_204_CM = (5 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 934 APEX_CONFIG12_FF_MAX_DURATION_228_CM = (6 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 935 APEX_CONFIG12_FF_MAX_DURATION_254_CM = (7 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 936 APEX_CONFIG12_FF_MAX_DURATION_281_CM = (8 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 937 APEX_CONFIG12_FF_MAX_DURATION_310_CM = (9 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 938 APEX_CONFIG12_FF_MAX_DURATION_339_CM = (10 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 939 APEX_CONFIG12_FF_MAX_DURATION_371_CM = (11 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 940 APEX_CONFIG12_FF_MAX_DURATION_403_CM = (12 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 941 APEX_CONFIG12_FF_MAX_DURATION_438_CM = (13 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 942 APEX_CONFIG12_FF_MAX_DURATION_473_CM = (14 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 943 APEX_CONFIG12_FF_MAX_DURATION_510_CM = (15 << APEX_CONFIG12_FF_MAX_DURATION_SEL_POS), 944 } APEX_CONFIG12_FF_MAX_DURATION_t; 945 946 /* FF_MIN_DURATION_SEL */ 947 typedef enum { 948 APEX_CONFIG12_FF_MIN_DURATION_10_CM = (0 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 949 APEX_CONFIG12_FF_MIN_DURATION_12_CM = (1 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 950 APEX_CONFIG12_FF_MIN_DURATION_13_CM = (2 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 951 APEX_CONFIG12_FF_MIN_DURATION_16_CM = (3 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 952 APEX_CONFIG12_FF_MIN_DURATION_18_CM = (4 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 953 APEX_CONFIG12_FF_MIN_DURATION_20_CM = (5 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 954 APEX_CONFIG12_FF_MIN_DURATION_23_CM = (6 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 955 APEX_CONFIG12_FF_MIN_DURATION_25_CM = (7 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 956 APEX_CONFIG12_FF_MIN_DURATION_28_CM = (8 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 957 APEX_CONFIG12_FF_MIN_DURATION_31_CM = (9 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 958 APEX_CONFIG12_FF_MIN_DURATION_34_CM = (10 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 959 APEX_CONFIG12_FF_MIN_DURATION_38_CM = (11 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 960 APEX_CONFIG12_FF_MIN_DURATION_41_CM = (12 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 961 APEX_CONFIG12_FF_MIN_DURATION_45_CM = (13 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 962 APEX_CONFIG12_FF_MIN_DURATION_48_CM = (14 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 963 APEX_CONFIG12_FF_MIN_DURATION_52_CM = (15 << APEX_CONFIG12_FF_MIN_DURATION_SEL_POS), 964 } APEX_CONFIG12_FF_MIN_DURATION_t; 965 966 /* --------------------------------------------------------------------------- 967 * register bank MREG2 968 * ---------------------------------------------------------------------------- */ 969 970 /* 971 * OTP_CTRL7_MREG2 972 * Register Name: OTP_CTRL7 973 */ 974 975 /* OTP_CTRL7 */ 976 typedef enum { 977 OTP_CTRL7_OTP_RELOAD_EN = (1 << OTP_CTRL7_OTP_RELOAD_POS), 978 OTP_CTRL7_OTP_RELOAD_DIS = (0 << OTP_CTRL7_OTP_RELOAD_POS), 979 } OTP_CTRL7_OTP_RELOAD_t; 980 981 /* OTP_PWR_DOWN */ 982 typedef enum { 983 OTP_CTRL7_PWR_DOWN_EN = (1 << OTP_CTRL7_OTP_PWR_DOWN_POS), 984 OTP_CTRL7_PWR_DOWN_DIS = (0 << OTP_CTRL7_OTP_PWR_DOWN_POS), 985 } OTP_CTRL7_PWR_DOWN_t; 986 987 #ifdef __cplusplus 988 } 989 #endif 990 991 #endif /* #ifndef _INV_IMU_DEFS_H_ */ 992
