1 /*
2  *  Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  *  Redistribution and use in source and binary forms, with or without
5  *  modification, are permitted provided that the following conditions
6  *  are met:
7  *
8  *    Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  *
11  *    Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the
14  *    distribution.
15  *
16  *    Neither the name of Texas Instruments Incorporated nor the names of
17  *    its contributors may be used to endorse or promote products derived
18  *    from this software without specific prior written permission.
19  *
20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
33 
34 //*****************************************************************************
35 //
36 // hw_ints.h - Macros that define the interrupt assignment on CC3200.
37 //
38 //*****************************************************************************
39 
40 #ifndef __HW_INTS_H__
41 #define __HW_INTS_H__
42 
43 //*****************************************************************************
44 //
45 // The following are defines for the fault assignments.
46 //
47 //*****************************************************************************
48 #define FAULT_NMI               2           // NMI fault
49 #define FAULT_HARD              3           // Hard fault
50 #define FAULT_MPU               4           // MPU fault
51 #define FAULT_BUS               5           // Bus fault
52 #define FAULT_USAGE             6           // Usage fault
53 #define FAULT_SVCALL            11          // SVCall
54 #define FAULT_DEBUG             12          // Debug monitor
55 #define FAULT_PENDSV            14          // PendSV
56 #define FAULT_SYSTICK           15          // System Tick
57 
58 //*****************************************************************************
59 //
60 // The following are defines for the interrupt assignments.
61 //
62 //*****************************************************************************
63 #define INT_GPIOA0              16          // GPIO Port S0
64 #define INT_GPIOA1              17          // GPIO Port S1
65 #define INT_GPIOA2              18          // GPIO Port S2
66 #define INT_GPIOA3              19          // GPIO Port S3
67 #define INT_UARTA0              21          // UART0 Rx and Tx
68 #define INT_UARTA1              22          // UART1 Rx and Tx
69 #define INT_I2CA0               24          // I2C controller
70 #define INT_ADCCH0              30          // ADC Sequence 0
71 #define INT_ADCCH1              31          // ADC Sequence 1
72 #define INT_ADCCH2              32          // ADC Sequence 2
73 #define INT_ADCCH3              33          // ADC Sequence 3
74 #define INT_WDT                 34          // Watchdog Timer0
75 #define INT_TIMERA0A            35          // Timer 0 subtimer A
76 #define INT_TIMERA0B            36          // Timer 0 subtimer B
77 #define INT_TIMERA1A            37          // Timer 1 subtimer A
78 #define INT_TIMERA1B            38          // Timer 1 subtimer B
79 #define INT_TIMERA2A            39          // Timer 2 subtimer A
80 #define INT_TIMERA2B            40          // Timer 2 subtimer B
81 #define INT_FLASH               45          // FLASH Control
82 #define INT_TIMERA3A            51          // Timer 3 subtimer A
83 #define INT_TIMERA3B            52          // Timer 3 subtimer B
84 #define INT_UDMA                62          // uDMA controller
85 #define INT_UDMAERR             63          // uDMA Error
86 #define INT_SHA                 164         // SHA
87 #define INT_AES                 167         // AES
88 #define INT_DES                 169         // DES
89 #define INT_MMCHS               175         // SDIO
90 #define INT_I2S                 177         // McAPS
91 #define INT_CAMERA              179         // Camera
92 #define INT_NWPIC               187         // Interprocessor communication
93 #define INT_PRCM                188         // Power, Reset and Clock Module
94 #define INT_SSPI                191         // Shared SPI
95 #define INT_GSPI                192         // Generic SPI
96 #define INT_LSPI                193         // Link SPI
97 
98 //*****************************************************************************
99 //
100 // The following are defines for the total number of interrupts.
101 //
102 //*****************************************************************************
103 #define NUM_INTERRUPTS          195 //The above number plus 2?
104 
105 
106 //*****************************************************************************
107 //
108 // The following are defines for the total number of priority levels.
109 //
110 //*****************************************************************************
111 #define NUM_PRIORITY            8
112 #define NUM_PRIORITY_BITS       3
113 
114 
115 #endif // __HW_INTS_H__
116