| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_USDHC.h | 85 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/ |
| D | K32L3A60_cm4.h | 21196 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
23216 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| D | K32L3A60_cm0plus.h | 21306 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
23326 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 20050 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
38976 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
39715 __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ member
44028 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S04/ |
| D | LPC55S04.h | 8064 __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ member
19475 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x3E0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S06/ |
| D | LPC55S06.h | 8064 __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ member
19475 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x3E0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 20835 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
43242 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
43981 __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ member
48294 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 21514 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
41377 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
42108 __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ member
46421 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 22300 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
45571 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
46302 __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ member
50615 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 22373 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
45507 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
46238 __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ member
50551 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 19028 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
37430 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
41967 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 19008 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
37409 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
41946 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/ |
| D | MIMXRT685S_dsp.h | 27702 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
31867 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S16/ |
| D | LPC55S16.h | 8496 __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ member
20205 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x3E0 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S14/ |
| D | LPC55S14.h | 8495 __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ member
20204 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x3E0 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/ |
| D | MIMXRT1041.h | 21137 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
40493 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
45030 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/ |
| D | K32L2A31A.h | 16982 …__IO uint32_t INT_STATUS; /**< TRNG Interrupt Status Register, offset: 0xAC… member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/ |
| D | K32L2A41A.h | 16982 …__IO uint32_t INT_STATUS; /**< TRNG Interrupt Status Register, offset: 0xAC… member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/ |
| D | MIMXRT1042.h | 21139 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
43903 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
48440 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 34262 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
39204 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 34263 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
39205 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 13082 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
29183 __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/ |
| D | MIMXRT1165_cm4.h | 35303 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
51345 …__IO uint32_t INT_STATUS; /**< Interrupt Status Register for domain 0..Inte… member
72352 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x204 */ member
78922 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| D | MIMXRT1165_cm7.h | 35305 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
51348 …__IO uint32_t INT_STATUS; /**< Interrupt Status Register for domain 0..Inte… member
71450 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x204 */ member
78020 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/ |
| D | MIMXRT1171.h | 35617 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ member
51878 …__IO uint32_t INT_STATUS; /**< Interrupt Status Register for domain 0..Inte… member
71952 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x204 */ member
78522 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ member
|
