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Searched defs:INT_ENABLE (Results 1 – 25 of 35) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S06/
DLPC55S06.h8065 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
19476 __I uint32_t INT_ENABLE; /**< Interrupt Enable Register, offset: 0x3E4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S04/
DLPC55S04.h8065 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
19476 __I uint32_t INT_ENABLE; /**< Interrupt Enable Register, offset: 0x3E4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S16/
DLPC55S16.h8497 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
20206 __I uint32_t INT_ENABLE; /**< Interrupt Enable Register, offset: 0x3E4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S14/
DLPC55S14.h8496 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
20205 __I uint32_t INT_ENABLE; /**< Interrupt Enable Register, offset: 0x3E4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502/
DLPC5502.h7683 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502CPXXXX/
DLPC5502CPXXXX.h7638 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504CPXXXX/
DLPC5504CPXXXX.h7638 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504/
DLPC5504.h7683 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506/
DLPC5506.h7683 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506CPXXXX/
DLPC5506CPXXXX.h7638 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5526/
DLPC5526.h7123 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5528/
DLPC5528.h7122 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5512/
DLPC5512.h8113 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h7505 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h7504 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5514/
DLPC5514.h8114 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5516/
DLPC5516.h8115 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core1.h7505 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
DLPC55S66_cm33_core0.h7505 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h7504 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
DLPC55S69_cm33_core0.h7504 __I uint32_t INT_ENABLE; /**< Interrupt enable bits, offset: 0xFE4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h52603 __IO uint32_t INT_ENABLE; /**< Interrupt Enable register, offset: 0xFE4 */ member
57983 __I uint8_t INT_ENABLE; /**< Interrupt Enable, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h52603 __IO uint32_t INT_ENABLE; /**< Interrupt Enable register, offset: 0xFE4 */ member
57983 __I uint8_t INT_ENABLE; /**< Interrupt Enable, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h51876 …__IO uint32_t INT_ENABLE; /**< Interrupt Enable Register for domain 0..Inte… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h51349 …__IO uint32_t INT_ENABLE; /**< Interrupt Enable Register for domain 0..Inte… member

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