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Searched defs:INTR_M_MASKED (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_scb.h94 __IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */ member
Dcyip_scb_v2.h96 __IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_scb_v2.h96 __IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_scb_v4.h100 __IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */ member