1 /* 2 * Copyright (c) 2021, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ 9 10 /* Peripheral: 11 * range: 0 - 0xFF, starting from 0 12 * 13 * Instance: 14 * range: 0 - 0xFF, starting from 0 15 */ 16 #define IMX_CCM_PERIPHERAL_MASK 0xFF00UL 17 #define IMX_CCM_INSTANCE_MASK 0xFFUL 18 19 #define IMX_CCM_CORESYS_CLK 0 20 #define IMX_CCM_PLATFORM_CLK 0x1UL 21 #define IMX_CCM_BUS_CLK 0x2UL 22 /* LPUART */ 23 #define IMX_CCM_LPUART_CLK 0x300UL 24 #define IMX_CCM_LPUART1_CLK 0x300UL 25 #define IMX_CCM_LPUART2_CLK 0x301UL 26 #define IMX_CCM_LPUART3_CLK 0x302UL 27 #define IMX_CCM_LPUART4_CLK 0x303UL 28 #define IMX_CCM_LPUART5_CLK 0x304UL 29 #define IMX_CCM_LPUART6_CLK 0x305UL 30 #define IMX_CCM_LPUART7_CLK 0x306UL 31 #define IMX_CCM_LPUART8_CLK 0x307UL 32 #define IMX_CCM_LPUART9_CLK 0x308UL 33 #define IMX_CCM_LPUART10_CLK 0x309UL 34 #define IMX_CCM_LPUART11_CLK 0x30aUL 35 #define IMX_CCM_LPUART12_CLK 0x30bUL 36 37 /* LPI2C */ 38 #define IMX_CCM_LPI2C_CLK 0x400UL 39 #define IMX_CCM_LPI2C1_CLK 0x400UL 40 #define IMX_CCM_LPI2C2_CLK 0x401UL 41 #define IMX_CCM_LPI2C3_CLK 0x402UL 42 #define IMX_CCM_LPI2C4_CLK 0x403UL 43 #define IMX_CCM_LPI2C5_CLK 0x404UL 44 #define IMX_CCM_LPI2C6_CLK 0x405UL 45 46 /* LPSPI */ 47 #define IMX_CCM_LPSPI_CLK 0x500UL 48 #define IMX_CCM_LPSPI1_CLK 0x500UL 49 #define IMX_CCM_LPSPI2_CLK 0x501UL 50 #define IMX_CCM_LPSPI3_CLK 0x502UL 51 #define IMX_CCM_LPSPI4_CLK 0x503UL 52 #define IMX_CCM_LPSPI5_CLK 0x504UL 53 #define IMX_CCM_LPSPI6_CLK 0x505UL 54 55 /* USDHC */ 56 #define IMX_CCM_USDHC1_CLK 0x600UL 57 #define IMX_CCM_USDHC2_CLK 0x601UL 58 59 /* DMA */ 60 #define IMX_CCM_EDMA_CLK 0x700UL 61 #define IMX_CCM_EDMA_LPSR_CLK 0x701UL 62 63 /* PWM */ 64 #define IMX_CCM_PWM_CLK 0x800UL 65 66 /* CAN */ 67 #define IMX_CCM_CAN_CLK 0x900UL 68 #define IMX_CCM_CAN1_CLK 0x900UL 69 #define IMX_CCM_CAN2_CLK 0x901UL 70 #define IMX_CCM_CAN3_CLK 0x902UL 71 72 /* GPT */ 73 #define IMX_CCM_GPT_CLK 0x1000UL 74 #define IMX_CCM_GPT1_CLK 0x1000UL 75 #define IMX_CCM_GPT2_CLK 0x1001UL 76 #define IMX_CCM_GPT3_CLK 0x1002UL 77 #define IMX_CCM_GPT4_CLK 0x1003UL 78 #define IMX_CCM_GPT5_CLK 0x1004UL 79 #define IMX_CCM_GPT6_CLK 0x1005UL 80 81 /* SAI */ 82 #define IMX_CCM_SAI1_CLK 0x2000UL 83 #define IMX_CCM_SAI2_CLK 0x2001UL 84 #define IMX_CCM_SAI3_CLK 0x2002UL 85 #define IMX_CCM_SAI4_CLK 0x2003UL 86 87 88 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */ 89
