1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_FLEXCAN.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_FLEXCAN 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_FLEXCAN_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_FLEXCAN_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- FLEXCAN Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup FLEXCAN_Peripheral_Access_Layer FLEXCAN Peripheral Access Layer 68 * @{ 69 */ 70 71 /** FLEXCAN - Size of Registers Arrays */ 72 #define FLEXCAN_RXIMR_COUNT 128u 73 #define FLEXCAN_HR_TIME_STAMP_COUNT 128u 74 #define FLEXCAN_ERFFEL_COUNT 128u 75 76 /** FLEXCAN - Register Layout Typedef */ 77 typedef struct { 78 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 79 __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */ 80 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */ 81 uint8_t RESERVED_0[4]; 82 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ 83 __IO uint32_t RX14MASK; /**< Rx 14 Mask Register, offset: 0x14 */ 84 __IO uint32_t RX15MASK; /**< Rx 15 Mask Register, offset: 0x18 */ 85 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ 86 __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */ 87 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */ 88 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */ 89 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */ 90 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */ 91 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */ 92 __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */ 93 uint8_t RESERVED_1[8]; 94 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ 95 __IO uint32_t RXFGMASK; /**< Legacy Rx FIFO Global Mask Register, offset: 0x48 */ 96 __I uint32_t RXFIR; /**< Legacy Rx FIFO Information Register, offset: 0x4C */ 97 __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ 98 uint8_t RESERVED_2[20]; 99 __IO uint32_t IMASK4; /**< Interrupt Masks 4 Register, offset: 0x68 */ 100 __IO uint32_t IMASK3; /**< Interrupt Masks 3 Register, offset: 0x6C */ 101 __IO uint32_t IFLAG4; /**< Interrupt Flags 4 Register, offset: 0x70 */ 102 __IO uint32_t IFLAG3; /**< Interrupt Flags 3 Register, offset: 0x74 */ 103 uint8_t RESERVED_3[2056]; 104 __IO uint32_t RXIMR[FLEXCAN_RXIMR_COUNT]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ 105 uint8_t RESERVED_4[96]; 106 __IO uint32_t MECR; /**< Memory Error Control Register, offset: 0xAE0 */ 107 __IO uint32_t ERRIAR; /**< Error Injection Address Register, offset: 0xAE4 */ 108 __IO uint32_t ERRIDPR; /**< Error Injection Data Pattern Register, offset: 0xAE8 */ 109 __IO uint32_t ERRIPPR; /**< Error Injection Parity Pattern Register, offset: 0xAEC */ 110 __I uint32_t RERRAR; /**< Error Report Address Register, offset: 0xAF0 */ 111 __I uint32_t RERRDR; /**< Error Report Data Register, offset: 0xAF4 */ 112 __I uint32_t RERRSYNR; /**< Error Report Syndrome Register, offset: 0xAF8 */ 113 __IO uint32_t ERRSR; /**< Error Status Register, offset: 0xAFC */ 114 uint8_t RESERVED_5[240]; 115 __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ 116 __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ 117 __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */ 118 __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ 119 __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */ 120 __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */ 121 __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */ 122 __IO uint32_t ERFCR; /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */ 123 __IO uint32_t ERFIER; /**< Enhanced Rx FIFO Interrupt Enable Register, offset: 0xC10 */ 124 __IO uint32_t ERFSR; /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */ 125 uint8_t RESERVED_6[24]; 126 __IO uint32_t HR_TIME_STAMP[FLEXCAN_HR_TIME_STAMP_COUNT]; /**< High Resolution Time Stamp, array offset: 0xC30, array step: 0x4 */ 127 uint8_t RESERVED_7[8656]; 128 __IO uint32_t ERFFEL[FLEXCAN_ERFFEL_COUNT]; /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ 129 } FLEXCAN_Type, *FLEXCAN_MemMapPtr; 130 131 /** Number of instances of the FLEXCAN module. */ 132 #define FLEXCAN_INSTANCE_COUNT (24u) 133 134 /* FLEXCAN - Peripheral instance base addresses */ 135 /** Peripheral CE_CAN_0 base address */ 136 #define IP_CE_CAN_0_BASE (0x449A0000u) 137 /** Peripheral CE_CAN_0 base pointer */ 138 #define IP_CE_CAN_0 ((FLEXCAN_Type *)IP_CE_CAN_0_BASE) 139 /** Peripheral CE_CAN_1 base address */ 140 #define IP_CE_CAN_1_BASE (0x449B0000u) 141 /** Peripheral CE_CAN_1 base pointer */ 142 #define IP_CE_CAN_1 ((FLEXCAN_Type *)IP_CE_CAN_1_BASE) 143 /** Peripheral CE_CAN_2 base address */ 144 #define IP_CE_CAN_2_BASE (0x449C0000u) 145 /** Peripheral CE_CAN_2 base pointer */ 146 #define IP_CE_CAN_2 ((FLEXCAN_Type *)IP_CE_CAN_2_BASE) 147 /** Peripheral CE_CAN_3 base address */ 148 #define IP_CE_CAN_3_BASE (0x449D0000u) 149 /** Peripheral CE_CAN_3 base pointer */ 150 #define IP_CE_CAN_3 ((FLEXCAN_Type *)IP_CE_CAN_3_BASE) 151 /** Peripheral CE_CAN_4 base address */ 152 #define IP_CE_CAN_4_BASE (0x449E0000u) 153 /** Peripheral CE_CAN_4 base pointer */ 154 #define IP_CE_CAN_4 ((FLEXCAN_Type *)IP_CE_CAN_4_BASE) 155 /** Peripheral CE_CAN_5 base address */ 156 #define IP_CE_CAN_5_BASE (0x449F0000u) 157 /** Peripheral CE_CAN_5 base pointer */ 158 #define IP_CE_CAN_5 ((FLEXCAN_Type *)IP_CE_CAN_5_BASE) 159 /** Peripheral CE_CAN_6 base address */ 160 #define IP_CE_CAN_6_BASE (0x44BA0000u) 161 /** Peripheral CE_CAN_6 base pointer */ 162 #define IP_CE_CAN_6 ((FLEXCAN_Type *)IP_CE_CAN_6_BASE) 163 /** Peripheral CE_CAN_7 base address */ 164 #define IP_CE_CAN_7_BASE (0x44BB0000u) 165 /** Peripheral CE_CAN_7 base pointer */ 166 #define IP_CE_CAN_7 ((FLEXCAN_Type *)IP_CE_CAN_7_BASE) 167 /** Peripheral CE_CAN_8 base address */ 168 #define IP_CE_CAN_8_BASE (0x44BC0000u) 169 /** Peripheral CE_CAN_8 base pointer */ 170 #define IP_CE_CAN_8 ((FLEXCAN_Type *)IP_CE_CAN_8_BASE) 171 /** Peripheral CE_CAN_9 base address */ 172 #define IP_CE_CAN_9_BASE (0x44BD0000u) 173 /** Peripheral CE_CAN_9 base pointer */ 174 #define IP_CE_CAN_9 ((FLEXCAN_Type *)IP_CE_CAN_9_BASE) 175 /** Peripheral CE_CAN_10 base address */ 176 #define IP_CE_CAN_10_BASE (0x44BE0000u) 177 /** Peripheral CE_CAN_10 base pointer */ 178 #define IP_CE_CAN_10 ((FLEXCAN_Type *)IP_CE_CAN_10_BASE) 179 /** Peripheral CE_CAN_11 base address */ 180 #define IP_CE_CAN_11_BASE (0x44BF0000u) 181 /** Peripheral CE_CAN_11 base pointer */ 182 #define IP_CE_CAN_11 ((FLEXCAN_Type *)IP_CE_CAN_11_BASE) 183 /** Peripheral CE_CAN_12 base address */ 184 #define IP_CE_CAN_12_BASE (0x44DA0000u) 185 /** Peripheral CE_CAN_12 base pointer */ 186 #define IP_CE_CAN_12 ((FLEXCAN_Type *)IP_CE_CAN_12_BASE) 187 /** Peripheral CE_CAN_13 base address */ 188 #define IP_CE_CAN_13_BASE (0x44DB0000u) 189 /** Peripheral CE_CAN_13 base pointer */ 190 #define IP_CE_CAN_13 ((FLEXCAN_Type *)IP_CE_CAN_13_BASE) 191 /** Peripheral CE_CAN_14 base address */ 192 #define IP_CE_CAN_14_BASE (0x44DC0000u) 193 /** Peripheral CE_CAN_14 base pointer */ 194 #define IP_CE_CAN_14 ((FLEXCAN_Type *)IP_CE_CAN_14_BASE) 195 /** Peripheral CE_CAN_15 base address */ 196 #define IP_CE_CAN_15_BASE (0x44DD0000u) 197 /** Peripheral CE_CAN_15 base pointer */ 198 #define IP_CE_CAN_15 ((FLEXCAN_Type *)IP_CE_CAN_15_BASE) 199 /** Peripheral CE_CAN_16 base address */ 200 #define IP_CE_CAN_16_BASE (0x44DE0000u) 201 /** Peripheral CE_CAN_16 base pointer */ 202 #define IP_CE_CAN_16 ((FLEXCAN_Type *)IP_CE_CAN_16_BASE) 203 /** Peripheral CE_CAN_17 base address */ 204 #define IP_CE_CAN_17_BASE (0x44DF0000u) 205 /** Peripheral CE_CAN_17 base pointer */ 206 #define IP_CE_CAN_17 ((FLEXCAN_Type *)IP_CE_CAN_17_BASE) 207 /** Peripheral CE_CAN_18 base address */ 208 #define IP_CE_CAN_18_BASE (0x44FA0000u) 209 /** Peripheral CE_CAN_18 base pointer */ 210 #define IP_CE_CAN_18 ((FLEXCAN_Type *)IP_CE_CAN_18_BASE) 211 /** Peripheral CE_CAN_19 base address */ 212 #define IP_CE_CAN_19_BASE (0x44FB0000u) 213 /** Peripheral CE_CAN_19 base pointer */ 214 #define IP_CE_CAN_19 ((FLEXCAN_Type *)IP_CE_CAN_19_BASE) 215 /** Peripheral CE_CAN_20 base address */ 216 #define IP_CE_CAN_20_BASE (0x44FC0000u) 217 /** Peripheral CE_CAN_20 base pointer */ 218 #define IP_CE_CAN_20 ((FLEXCAN_Type *)IP_CE_CAN_20_BASE) 219 /** Peripheral CE_CAN_21 base address */ 220 #define IP_CE_CAN_21_BASE (0x44FD0000u) 221 /** Peripheral CE_CAN_21 base pointer */ 222 #define IP_CE_CAN_21 ((FLEXCAN_Type *)IP_CE_CAN_21_BASE) 223 /** Peripheral CE_CAN_22 base address */ 224 #define IP_CE_CAN_22_BASE (0x44FE0000u) 225 /** Peripheral CE_CAN_22 base pointer */ 226 #define IP_CE_CAN_22 ((FLEXCAN_Type *)IP_CE_CAN_22_BASE) 227 /** Peripheral CE_CAN_23 base address */ 228 #define IP_CE_CAN_23_BASE (0x44FF0000u) 229 /** Peripheral CE_CAN_23 base pointer */ 230 #define IP_CE_CAN_23 ((FLEXCAN_Type *)IP_CE_CAN_23_BASE) 231 /** Array initializer of FLEXCAN peripheral base addresses */ 232 #define IP_FLEXCAN_BASE_ADDRS { IP_CE_CAN_0_BASE, IP_CE_CAN_1_BASE, IP_CE_CAN_2_BASE, IP_CE_CAN_3_BASE, IP_CE_CAN_4_BASE, IP_CE_CAN_5_BASE, IP_CE_CAN_6_BASE, IP_CE_CAN_7_BASE, IP_CE_CAN_8_BASE, IP_CE_CAN_9_BASE, IP_CE_CAN_10_BASE, IP_CE_CAN_11_BASE, IP_CE_CAN_12_BASE, IP_CE_CAN_13_BASE, IP_CE_CAN_14_BASE, IP_CE_CAN_15_BASE, IP_CE_CAN_16_BASE, IP_CE_CAN_17_BASE, IP_CE_CAN_18_BASE, IP_CE_CAN_19_BASE, IP_CE_CAN_20_BASE, IP_CE_CAN_21_BASE, IP_CE_CAN_22_BASE, IP_CE_CAN_23_BASE } 233 /** Array initializer of FLEXCAN peripheral base pointers */ 234 #define IP_FLEXCAN_BASE_PTRS { IP_CE_CAN_0, IP_CE_CAN_1, IP_CE_CAN_2, IP_CE_CAN_3, IP_CE_CAN_4, IP_CE_CAN_5, IP_CE_CAN_6, IP_CE_CAN_7, IP_CE_CAN_8, IP_CE_CAN_9, IP_CE_CAN_10, IP_CE_CAN_11, IP_CE_CAN_12, IP_CE_CAN_13, IP_CE_CAN_14, IP_CE_CAN_15, IP_CE_CAN_16, IP_CE_CAN_17, IP_CE_CAN_18, IP_CE_CAN_19, IP_CE_CAN_20, IP_CE_CAN_21, IP_CE_CAN_22, IP_CE_CAN_23 } 235 236 /* ---------------------------------------------------------------------------- 237 -- FLEXCAN Register Masks 238 ---------------------------------------------------------------------------- */ 239 240 /*! 241 * @addtogroup FLEXCAN_Register_Masks FLEXCAN Register Masks 242 * @{ 243 */ 244 245 /*! @name MCR - Module Configuration Register */ 246 /*! @{ */ 247 248 #define FLEXCAN_MCR_MAXMB_MASK (0x7FU) 249 #define FLEXCAN_MCR_MAXMB_SHIFT (0U) 250 #define FLEXCAN_MCR_MAXMB_WIDTH (7U) 251 #define FLEXCAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_MAXMB_SHIFT)) & FLEXCAN_MCR_MAXMB_MASK) 252 253 #define FLEXCAN_MCR_IDAM_MASK (0x300U) 254 #define FLEXCAN_MCR_IDAM_SHIFT (8U) 255 #define FLEXCAN_MCR_IDAM_WIDTH (2U) 256 #define FLEXCAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_IDAM_SHIFT)) & FLEXCAN_MCR_IDAM_MASK) 257 258 #define FLEXCAN_MCR_FDEN_MASK (0x800U) 259 #define FLEXCAN_MCR_FDEN_SHIFT (11U) 260 #define FLEXCAN_MCR_FDEN_WIDTH (1U) 261 #define FLEXCAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_FDEN_SHIFT)) & FLEXCAN_MCR_FDEN_MASK) 262 263 #define FLEXCAN_MCR_AEN_MASK (0x1000U) 264 #define FLEXCAN_MCR_AEN_SHIFT (12U) 265 #define FLEXCAN_MCR_AEN_WIDTH (1U) 266 #define FLEXCAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_AEN_SHIFT)) & FLEXCAN_MCR_AEN_MASK) 267 268 #define FLEXCAN_MCR_LPRIOEN_MASK (0x2000U) 269 #define FLEXCAN_MCR_LPRIOEN_SHIFT (13U) 270 #define FLEXCAN_MCR_LPRIOEN_WIDTH (1U) 271 #define FLEXCAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_LPRIOEN_SHIFT)) & FLEXCAN_MCR_LPRIOEN_MASK) 272 273 #define FLEXCAN_MCR_DMA_MASK (0x8000U) 274 #define FLEXCAN_MCR_DMA_SHIFT (15U) 275 #define FLEXCAN_MCR_DMA_WIDTH (1U) 276 #define FLEXCAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_DMA_SHIFT)) & FLEXCAN_MCR_DMA_MASK) 277 278 #define FLEXCAN_MCR_IRMQ_MASK (0x10000U) 279 #define FLEXCAN_MCR_IRMQ_SHIFT (16U) 280 #define FLEXCAN_MCR_IRMQ_WIDTH (1U) 281 #define FLEXCAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_IRMQ_SHIFT)) & FLEXCAN_MCR_IRMQ_MASK) 282 283 #define FLEXCAN_MCR_SRXDIS_MASK (0x20000U) 284 #define FLEXCAN_MCR_SRXDIS_SHIFT (17U) 285 #define FLEXCAN_MCR_SRXDIS_WIDTH (1U) 286 #define FLEXCAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_SRXDIS_SHIFT)) & FLEXCAN_MCR_SRXDIS_MASK) 287 288 #define FLEXCAN_MCR_LPMACK_MASK (0x100000U) 289 #define FLEXCAN_MCR_LPMACK_SHIFT (20U) 290 #define FLEXCAN_MCR_LPMACK_WIDTH (1U) 291 #define FLEXCAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_LPMACK_SHIFT)) & FLEXCAN_MCR_LPMACK_MASK) 292 293 #define FLEXCAN_MCR_WRNEN_MASK (0x200000U) 294 #define FLEXCAN_MCR_WRNEN_SHIFT (21U) 295 #define FLEXCAN_MCR_WRNEN_WIDTH (1U) 296 #define FLEXCAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_WRNEN_SHIFT)) & FLEXCAN_MCR_WRNEN_MASK) 297 298 #define FLEXCAN_MCR_FRZACK_MASK (0x1000000U) 299 #define FLEXCAN_MCR_FRZACK_SHIFT (24U) 300 #define FLEXCAN_MCR_FRZACK_WIDTH (1U) 301 #define FLEXCAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_FRZACK_SHIFT)) & FLEXCAN_MCR_FRZACK_MASK) 302 303 #define FLEXCAN_MCR_SOFTRST_MASK (0x2000000U) 304 #define FLEXCAN_MCR_SOFTRST_SHIFT (25U) 305 #define FLEXCAN_MCR_SOFTRST_WIDTH (1U) 306 #define FLEXCAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_SOFTRST_SHIFT)) & FLEXCAN_MCR_SOFTRST_MASK) 307 308 #define FLEXCAN_MCR_NOTRDY_MASK (0x8000000U) 309 #define FLEXCAN_MCR_NOTRDY_SHIFT (27U) 310 #define FLEXCAN_MCR_NOTRDY_WIDTH (1U) 311 #define FLEXCAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_NOTRDY_SHIFT)) & FLEXCAN_MCR_NOTRDY_MASK) 312 313 #define FLEXCAN_MCR_HALT_MASK (0x10000000U) 314 #define FLEXCAN_MCR_HALT_SHIFT (28U) 315 #define FLEXCAN_MCR_HALT_WIDTH (1U) 316 #define FLEXCAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_HALT_SHIFT)) & FLEXCAN_MCR_HALT_MASK) 317 318 #define FLEXCAN_MCR_RFEN_MASK (0x20000000U) 319 #define FLEXCAN_MCR_RFEN_SHIFT (29U) 320 #define FLEXCAN_MCR_RFEN_WIDTH (1U) 321 #define FLEXCAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_RFEN_SHIFT)) & FLEXCAN_MCR_RFEN_MASK) 322 323 #define FLEXCAN_MCR_FRZ_MASK (0x40000000U) 324 #define FLEXCAN_MCR_FRZ_SHIFT (30U) 325 #define FLEXCAN_MCR_FRZ_WIDTH (1U) 326 #define FLEXCAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_FRZ_SHIFT)) & FLEXCAN_MCR_FRZ_MASK) 327 328 #define FLEXCAN_MCR_MDIS_MASK (0x80000000U) 329 #define FLEXCAN_MCR_MDIS_SHIFT (31U) 330 #define FLEXCAN_MCR_MDIS_WIDTH (1U) 331 #define FLEXCAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MCR_MDIS_SHIFT)) & FLEXCAN_MCR_MDIS_MASK) 332 /*! @} */ 333 334 /*! @name CTRL1 - Control 1 Register */ 335 /*! @{ */ 336 337 #define FLEXCAN_CTRL1_PROPSEG_MASK (0x7U) 338 #define FLEXCAN_CTRL1_PROPSEG_SHIFT (0U) 339 #define FLEXCAN_CTRL1_PROPSEG_WIDTH (3U) 340 #define FLEXCAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PROPSEG_SHIFT)) & FLEXCAN_CTRL1_PROPSEG_MASK) 341 342 #define FLEXCAN_CTRL1_LOM_MASK (0x8U) 343 #define FLEXCAN_CTRL1_LOM_SHIFT (3U) 344 #define FLEXCAN_CTRL1_LOM_WIDTH (1U) 345 #define FLEXCAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_LOM_SHIFT)) & FLEXCAN_CTRL1_LOM_MASK) 346 347 #define FLEXCAN_CTRL1_LBUF_MASK (0x10U) 348 #define FLEXCAN_CTRL1_LBUF_SHIFT (4U) 349 #define FLEXCAN_CTRL1_LBUF_WIDTH (1U) 350 #define FLEXCAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_LBUF_SHIFT)) & FLEXCAN_CTRL1_LBUF_MASK) 351 352 #define FLEXCAN_CTRL1_TSYN_MASK (0x20U) 353 #define FLEXCAN_CTRL1_TSYN_SHIFT (5U) 354 #define FLEXCAN_CTRL1_TSYN_WIDTH (1U) 355 #define FLEXCAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_TSYN_SHIFT)) & FLEXCAN_CTRL1_TSYN_MASK) 356 357 #define FLEXCAN_CTRL1_BOFFREC_MASK (0x40U) 358 #define FLEXCAN_CTRL1_BOFFREC_SHIFT (6U) 359 #define FLEXCAN_CTRL1_BOFFREC_WIDTH (1U) 360 #define FLEXCAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_BOFFREC_SHIFT)) & FLEXCAN_CTRL1_BOFFREC_MASK) 361 362 #define FLEXCAN_CTRL1_SMP_MASK (0x80U) 363 #define FLEXCAN_CTRL1_SMP_SHIFT (7U) 364 #define FLEXCAN_CTRL1_SMP_WIDTH (1U) 365 #define FLEXCAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_SMP_SHIFT)) & FLEXCAN_CTRL1_SMP_MASK) 366 367 #define FLEXCAN_CTRL1_RWRNMSK_MASK (0x400U) 368 #define FLEXCAN_CTRL1_RWRNMSK_SHIFT (10U) 369 #define FLEXCAN_CTRL1_RWRNMSK_WIDTH (1U) 370 #define FLEXCAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_RWRNMSK_SHIFT)) & FLEXCAN_CTRL1_RWRNMSK_MASK) 371 372 #define FLEXCAN_CTRL1_TWRNMSK_MASK (0x800U) 373 #define FLEXCAN_CTRL1_TWRNMSK_SHIFT (11U) 374 #define FLEXCAN_CTRL1_TWRNMSK_WIDTH (1U) 375 #define FLEXCAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_TWRNMSK_SHIFT)) & FLEXCAN_CTRL1_TWRNMSK_MASK) 376 377 #define FLEXCAN_CTRL1_LPB_MASK (0x1000U) 378 #define FLEXCAN_CTRL1_LPB_SHIFT (12U) 379 #define FLEXCAN_CTRL1_LPB_WIDTH (1U) 380 #define FLEXCAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_LPB_SHIFT)) & FLEXCAN_CTRL1_LPB_MASK) 381 382 #define FLEXCAN_CTRL1_ERRMSK_MASK (0x4000U) 383 #define FLEXCAN_CTRL1_ERRMSK_SHIFT (14U) 384 #define FLEXCAN_CTRL1_ERRMSK_WIDTH (1U) 385 #define FLEXCAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_ERRMSK_SHIFT)) & FLEXCAN_CTRL1_ERRMSK_MASK) 386 387 #define FLEXCAN_CTRL1_BOFFMSK_MASK (0x8000U) 388 #define FLEXCAN_CTRL1_BOFFMSK_SHIFT (15U) 389 #define FLEXCAN_CTRL1_BOFFMSK_WIDTH (1U) 390 #define FLEXCAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_BOFFMSK_SHIFT)) & FLEXCAN_CTRL1_BOFFMSK_MASK) 391 392 #define FLEXCAN_CTRL1_PSEG2_MASK (0x70000U) 393 #define FLEXCAN_CTRL1_PSEG2_SHIFT (16U) 394 #define FLEXCAN_CTRL1_PSEG2_WIDTH (3U) 395 #define FLEXCAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PSEG2_SHIFT)) & FLEXCAN_CTRL1_PSEG2_MASK) 396 397 #define FLEXCAN_CTRL1_PSEG1_MASK (0x380000U) 398 #define FLEXCAN_CTRL1_PSEG1_SHIFT (19U) 399 #define FLEXCAN_CTRL1_PSEG1_WIDTH (3U) 400 #define FLEXCAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PSEG1_SHIFT)) & FLEXCAN_CTRL1_PSEG1_MASK) 401 402 #define FLEXCAN_CTRL1_RJW_MASK (0xC00000U) 403 #define FLEXCAN_CTRL1_RJW_SHIFT (22U) 404 #define FLEXCAN_CTRL1_RJW_WIDTH (2U) 405 #define FLEXCAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_RJW_SHIFT)) & FLEXCAN_CTRL1_RJW_MASK) 406 407 #define FLEXCAN_CTRL1_PRESDIV_MASK (0xFF000000U) 408 #define FLEXCAN_CTRL1_PRESDIV_SHIFT (24U) 409 #define FLEXCAN_CTRL1_PRESDIV_WIDTH (8U) 410 #define FLEXCAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL1_PRESDIV_SHIFT)) & FLEXCAN_CTRL1_PRESDIV_MASK) 411 /*! @} */ 412 413 /*! @name TIMER - Free Running Timer */ 414 /*! @{ */ 415 416 #define FLEXCAN_TIMER_TIMER_MASK (0xFFFFU) 417 #define FLEXCAN_TIMER_TIMER_SHIFT (0U) 418 #define FLEXCAN_TIMER_TIMER_WIDTH (16U) 419 #define FLEXCAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_TIMER_TIMER_SHIFT)) & FLEXCAN_TIMER_TIMER_MASK) 420 /*! @} */ 421 422 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ 423 /*! @{ */ 424 425 #define FLEXCAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) 426 #define FLEXCAN_RXMGMASK_MG_SHIFT (0U) 427 #define FLEXCAN_RXMGMASK_MG_WIDTH (32U) 428 #define FLEXCAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXMGMASK_MG_SHIFT)) & FLEXCAN_RXMGMASK_MG_MASK) 429 /*! @} */ 430 431 /*! @name RX14MASK - Rx 14 Mask Register */ 432 /*! @{ */ 433 434 #define FLEXCAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) 435 #define FLEXCAN_RX14MASK_RX14M_SHIFT (0U) 436 #define FLEXCAN_RX14MASK_RX14M_WIDTH (32U) 437 #define FLEXCAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RX14MASK_RX14M_SHIFT)) & FLEXCAN_RX14MASK_RX14M_MASK) 438 /*! @} */ 439 440 /*! @name RX15MASK - Rx 15 Mask Register */ 441 /*! @{ */ 442 443 #define FLEXCAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) 444 #define FLEXCAN_RX15MASK_RX15M_SHIFT (0U) 445 #define FLEXCAN_RX15MASK_RX15M_WIDTH (32U) 446 #define FLEXCAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RX15MASK_RX15M_SHIFT)) & FLEXCAN_RX15MASK_RX15M_MASK) 447 /*! @} */ 448 449 /*! @name ECR - Error Counter */ 450 /*! @{ */ 451 452 #define FLEXCAN_ECR_TXERRCNT_MASK (0xFFU) 453 #define FLEXCAN_ECR_TXERRCNT_SHIFT (0U) 454 #define FLEXCAN_ECR_TXERRCNT_WIDTH (8U) 455 #define FLEXCAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ECR_TXERRCNT_SHIFT)) & FLEXCAN_ECR_TXERRCNT_MASK) 456 457 #define FLEXCAN_ECR_RXERRCNT_MASK (0xFF00U) 458 #define FLEXCAN_ECR_RXERRCNT_SHIFT (8U) 459 #define FLEXCAN_ECR_RXERRCNT_WIDTH (8U) 460 #define FLEXCAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ECR_RXERRCNT_SHIFT)) & FLEXCAN_ECR_RXERRCNT_MASK) 461 462 #define FLEXCAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) 463 #define FLEXCAN_ECR_TXERRCNT_FAST_SHIFT (16U) 464 #define FLEXCAN_ECR_TXERRCNT_FAST_WIDTH (8U) 465 #define FLEXCAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ECR_TXERRCNT_FAST_SHIFT)) & FLEXCAN_ECR_TXERRCNT_FAST_MASK) 466 467 #define FLEXCAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) 468 #define FLEXCAN_ECR_RXERRCNT_FAST_SHIFT (24U) 469 #define FLEXCAN_ECR_RXERRCNT_FAST_WIDTH (8U) 470 #define FLEXCAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ECR_RXERRCNT_FAST_SHIFT)) & FLEXCAN_ECR_RXERRCNT_FAST_MASK) 471 /*! @} */ 472 473 /*! @name ESR1 - Error and Status 1 Register */ 474 /*! @{ */ 475 476 #define FLEXCAN_ESR1_ERRINT_MASK (0x2U) 477 #define FLEXCAN_ESR1_ERRINT_SHIFT (1U) 478 #define FLEXCAN_ESR1_ERRINT_WIDTH (1U) 479 #define FLEXCAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ERRINT_SHIFT)) & FLEXCAN_ESR1_ERRINT_MASK) 480 481 #define FLEXCAN_ESR1_BOFFINT_MASK (0x4U) 482 #define FLEXCAN_ESR1_BOFFINT_SHIFT (2U) 483 #define FLEXCAN_ESR1_BOFFINT_WIDTH (1U) 484 #define FLEXCAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BOFFINT_SHIFT)) & FLEXCAN_ESR1_BOFFINT_MASK) 485 486 #define FLEXCAN_ESR1_RX_MASK (0x8U) 487 #define FLEXCAN_ESR1_RX_SHIFT (3U) 488 #define FLEXCAN_ESR1_RX_WIDTH (1U) 489 #define FLEXCAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_RX_SHIFT)) & FLEXCAN_ESR1_RX_MASK) 490 491 #define FLEXCAN_ESR1_FLTCONF_MASK (0x30U) 492 #define FLEXCAN_ESR1_FLTCONF_SHIFT (4U) 493 #define FLEXCAN_ESR1_FLTCONF_WIDTH (2U) 494 #define FLEXCAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_FLTCONF_SHIFT)) & FLEXCAN_ESR1_FLTCONF_MASK) 495 496 #define FLEXCAN_ESR1_TX_MASK (0x40U) 497 #define FLEXCAN_ESR1_TX_SHIFT (6U) 498 #define FLEXCAN_ESR1_TX_WIDTH (1U) 499 #define FLEXCAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_TX_SHIFT)) & FLEXCAN_ESR1_TX_MASK) 500 501 #define FLEXCAN_ESR1_IDLE_MASK (0x80U) 502 #define FLEXCAN_ESR1_IDLE_SHIFT (7U) 503 #define FLEXCAN_ESR1_IDLE_WIDTH (1U) 504 #define FLEXCAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_IDLE_SHIFT)) & FLEXCAN_ESR1_IDLE_MASK) 505 506 #define FLEXCAN_ESR1_RXWRN_MASK (0x100U) 507 #define FLEXCAN_ESR1_RXWRN_SHIFT (8U) 508 #define FLEXCAN_ESR1_RXWRN_WIDTH (1U) 509 #define FLEXCAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_RXWRN_SHIFT)) & FLEXCAN_ESR1_RXWRN_MASK) 510 511 #define FLEXCAN_ESR1_TXWRN_MASK (0x200U) 512 #define FLEXCAN_ESR1_TXWRN_SHIFT (9U) 513 #define FLEXCAN_ESR1_TXWRN_WIDTH (1U) 514 #define FLEXCAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_TXWRN_SHIFT)) & FLEXCAN_ESR1_TXWRN_MASK) 515 516 #define FLEXCAN_ESR1_STFERR_MASK (0x400U) 517 #define FLEXCAN_ESR1_STFERR_SHIFT (10U) 518 #define FLEXCAN_ESR1_STFERR_WIDTH (1U) 519 #define FLEXCAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_STFERR_SHIFT)) & FLEXCAN_ESR1_STFERR_MASK) 520 521 #define FLEXCAN_ESR1_FRMERR_MASK (0x800U) 522 #define FLEXCAN_ESR1_FRMERR_SHIFT (11U) 523 #define FLEXCAN_ESR1_FRMERR_WIDTH (1U) 524 #define FLEXCAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_FRMERR_SHIFT)) & FLEXCAN_ESR1_FRMERR_MASK) 525 526 #define FLEXCAN_ESR1_CRCERR_MASK (0x1000U) 527 #define FLEXCAN_ESR1_CRCERR_SHIFT (12U) 528 #define FLEXCAN_ESR1_CRCERR_WIDTH (1U) 529 #define FLEXCAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_CRCERR_SHIFT)) & FLEXCAN_ESR1_CRCERR_MASK) 530 531 #define FLEXCAN_ESR1_ACKERR_MASK (0x2000U) 532 #define FLEXCAN_ESR1_ACKERR_SHIFT (13U) 533 #define FLEXCAN_ESR1_ACKERR_WIDTH (1U) 534 #define FLEXCAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ACKERR_SHIFT)) & FLEXCAN_ESR1_ACKERR_MASK) 535 536 #define FLEXCAN_ESR1_BIT0ERR_MASK (0x4000U) 537 #define FLEXCAN_ESR1_BIT0ERR_SHIFT (14U) 538 #define FLEXCAN_ESR1_BIT0ERR_WIDTH (1U) 539 #define FLEXCAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BIT0ERR_SHIFT)) & FLEXCAN_ESR1_BIT0ERR_MASK) 540 541 #define FLEXCAN_ESR1_BIT1ERR_MASK (0x8000U) 542 #define FLEXCAN_ESR1_BIT1ERR_SHIFT (15U) 543 #define FLEXCAN_ESR1_BIT1ERR_WIDTH (1U) 544 #define FLEXCAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BIT1ERR_SHIFT)) & FLEXCAN_ESR1_BIT1ERR_MASK) 545 546 #define FLEXCAN_ESR1_RWRNINT_MASK (0x10000U) 547 #define FLEXCAN_ESR1_RWRNINT_SHIFT (16U) 548 #define FLEXCAN_ESR1_RWRNINT_WIDTH (1U) 549 #define FLEXCAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_RWRNINT_SHIFT)) & FLEXCAN_ESR1_RWRNINT_MASK) 550 551 #define FLEXCAN_ESR1_TWRNINT_MASK (0x20000U) 552 #define FLEXCAN_ESR1_TWRNINT_SHIFT (17U) 553 #define FLEXCAN_ESR1_TWRNINT_WIDTH (1U) 554 #define FLEXCAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_TWRNINT_SHIFT)) & FLEXCAN_ESR1_TWRNINT_MASK) 555 556 #define FLEXCAN_ESR1_SYNCH_MASK (0x40000U) 557 #define FLEXCAN_ESR1_SYNCH_SHIFT (18U) 558 #define FLEXCAN_ESR1_SYNCH_WIDTH (1U) 559 #define FLEXCAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_SYNCH_SHIFT)) & FLEXCAN_ESR1_SYNCH_MASK) 560 561 #define FLEXCAN_ESR1_BOFFDONEINT_MASK (0x80000U) 562 #define FLEXCAN_ESR1_BOFFDONEINT_SHIFT (19U) 563 #define FLEXCAN_ESR1_BOFFDONEINT_WIDTH (1U) 564 #define FLEXCAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BOFFDONEINT_SHIFT)) & FLEXCAN_ESR1_BOFFDONEINT_MASK) 565 566 #define FLEXCAN_ESR1_ERRINT_FAST_MASK (0x100000U) 567 #define FLEXCAN_ESR1_ERRINT_FAST_SHIFT (20U) 568 #define FLEXCAN_ESR1_ERRINT_FAST_WIDTH (1U) 569 #define FLEXCAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ERRINT_FAST_SHIFT)) & FLEXCAN_ESR1_ERRINT_FAST_MASK) 570 571 #define FLEXCAN_ESR1_ERROVR_MASK (0x200000U) 572 #define FLEXCAN_ESR1_ERROVR_SHIFT (21U) 573 #define FLEXCAN_ESR1_ERROVR_WIDTH (1U) 574 #define FLEXCAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_ERROVR_SHIFT)) & FLEXCAN_ESR1_ERROVR_MASK) 575 576 #define FLEXCAN_ESR1_STFERR_FAST_MASK (0x4000000U) 577 #define FLEXCAN_ESR1_STFERR_FAST_SHIFT (26U) 578 #define FLEXCAN_ESR1_STFERR_FAST_WIDTH (1U) 579 #define FLEXCAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_STFERR_FAST_SHIFT)) & FLEXCAN_ESR1_STFERR_FAST_MASK) 580 581 #define FLEXCAN_ESR1_FRMERR_FAST_MASK (0x8000000U) 582 #define FLEXCAN_ESR1_FRMERR_FAST_SHIFT (27U) 583 #define FLEXCAN_ESR1_FRMERR_FAST_WIDTH (1U) 584 #define FLEXCAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_FRMERR_FAST_SHIFT)) & FLEXCAN_ESR1_FRMERR_FAST_MASK) 585 586 #define FLEXCAN_ESR1_CRCERR_FAST_MASK (0x10000000U) 587 #define FLEXCAN_ESR1_CRCERR_FAST_SHIFT (28U) 588 #define FLEXCAN_ESR1_CRCERR_FAST_WIDTH (1U) 589 #define FLEXCAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_CRCERR_FAST_SHIFT)) & FLEXCAN_ESR1_CRCERR_FAST_MASK) 590 591 #define FLEXCAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) 592 #define FLEXCAN_ESR1_BIT0ERR_FAST_SHIFT (30U) 593 #define FLEXCAN_ESR1_BIT0ERR_FAST_WIDTH (1U) 594 #define FLEXCAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BIT0ERR_FAST_SHIFT)) & FLEXCAN_ESR1_BIT0ERR_FAST_MASK) 595 596 #define FLEXCAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) 597 #define FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT (31U) 598 #define FLEXCAN_ESR1_BIT1ERR_FAST_WIDTH (1U) 599 #define FLEXCAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT)) & FLEXCAN_ESR1_BIT1ERR_FAST_MASK) 600 /*! @} */ 601 602 /*! @name IMASK2 - Interrupt Masks 2 Register */ 603 /*! @{ */ 604 605 #define FLEXCAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) 606 #define FLEXCAN_IMASK2_BUF63TO32M_SHIFT (0U) 607 #define FLEXCAN_IMASK2_BUF63TO32M_WIDTH (32U) 608 #define FLEXCAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IMASK2_BUF63TO32M_SHIFT)) & FLEXCAN_IMASK2_BUF63TO32M_MASK) 609 /*! @} */ 610 611 /*! @name IMASK1 - Interrupt Masks 1 Register */ 612 /*! @{ */ 613 614 #define FLEXCAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) 615 #define FLEXCAN_IMASK1_BUF31TO0M_SHIFT (0U) 616 #define FLEXCAN_IMASK1_BUF31TO0M_WIDTH (32U) 617 #define FLEXCAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IMASK1_BUF31TO0M_SHIFT)) & FLEXCAN_IMASK1_BUF31TO0M_MASK) 618 /*! @} */ 619 620 /*! @name IFLAG2 - Interrupt Flags 2 Register */ 621 /*! @{ */ 622 623 #define FLEXCAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) 624 #define FLEXCAN_IFLAG2_BUF63TO32I_SHIFT (0U) 625 #define FLEXCAN_IFLAG2_BUF63TO32I_WIDTH (32U) 626 #define FLEXCAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG2_BUF63TO32I_SHIFT)) & FLEXCAN_IFLAG2_BUF63TO32I_MASK) 627 /*! @} */ 628 629 /*! @name IFLAG1 - Interrupt Flags 1 Register */ 630 /*! @{ */ 631 632 #define FLEXCAN_IFLAG1_BUF0I_MASK (0x1U) 633 #define FLEXCAN_IFLAG1_BUF0I_SHIFT (0U) 634 #define FLEXCAN_IFLAG1_BUF0I_WIDTH (1U) 635 #define FLEXCAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF0I_SHIFT)) & FLEXCAN_IFLAG1_BUF0I_MASK) 636 637 #define FLEXCAN_IFLAG1_BUF4TO1I_MASK (0x1EU) 638 #define FLEXCAN_IFLAG1_BUF4TO1I_SHIFT (1U) 639 #define FLEXCAN_IFLAG1_BUF4TO1I_WIDTH (4U) 640 #define FLEXCAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF4TO1I_SHIFT)) & FLEXCAN_IFLAG1_BUF4TO1I_MASK) 641 642 #define FLEXCAN_IFLAG1_BUF5I_MASK (0x20U) 643 #define FLEXCAN_IFLAG1_BUF5I_SHIFT (5U) 644 #define FLEXCAN_IFLAG1_BUF5I_WIDTH (1U) 645 #define FLEXCAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF5I_SHIFT)) & FLEXCAN_IFLAG1_BUF5I_MASK) 646 647 #define FLEXCAN_IFLAG1_BUF6I_MASK (0x40U) 648 #define FLEXCAN_IFLAG1_BUF6I_SHIFT (6U) 649 #define FLEXCAN_IFLAG1_BUF6I_WIDTH (1U) 650 #define FLEXCAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF6I_SHIFT)) & FLEXCAN_IFLAG1_BUF6I_MASK) 651 652 #define FLEXCAN_IFLAG1_BUF7I_MASK (0x80U) 653 #define FLEXCAN_IFLAG1_BUF7I_SHIFT (7U) 654 #define FLEXCAN_IFLAG1_BUF7I_WIDTH (1U) 655 #define FLEXCAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF7I_SHIFT)) & FLEXCAN_IFLAG1_BUF7I_MASK) 656 657 #define FLEXCAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) 658 #define FLEXCAN_IFLAG1_BUF31TO8I_SHIFT (8U) 659 #define FLEXCAN_IFLAG1_BUF31TO8I_WIDTH (24U) 660 #define FLEXCAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG1_BUF31TO8I_SHIFT)) & FLEXCAN_IFLAG1_BUF31TO8I_MASK) 661 /*! @} */ 662 663 /*! @name CTRL2 - Control 2 Register */ 664 /*! @{ */ 665 666 #define FLEXCAN_CTRL2_TSTAMPCAP_MASK (0xC0U) 667 #define FLEXCAN_CTRL2_TSTAMPCAP_SHIFT (6U) 668 #define FLEXCAN_CTRL2_TSTAMPCAP_WIDTH (2U) 669 #define FLEXCAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_TSTAMPCAP_SHIFT)) & FLEXCAN_CTRL2_TSTAMPCAP_MASK) 670 671 #define FLEXCAN_CTRL2_MBTSBASE_MASK (0x300U) 672 #define FLEXCAN_CTRL2_MBTSBASE_SHIFT (8U) 673 #define FLEXCAN_CTRL2_MBTSBASE_WIDTH (2U) 674 #define FLEXCAN_CTRL2_MBTSBASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_MBTSBASE_SHIFT)) & FLEXCAN_CTRL2_MBTSBASE_MASK) 675 676 #define FLEXCAN_CTRL2_EDFLTDIS_MASK (0x800U) 677 #define FLEXCAN_CTRL2_EDFLTDIS_SHIFT (11U) 678 #define FLEXCAN_CTRL2_EDFLTDIS_WIDTH (1U) 679 #define FLEXCAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_EDFLTDIS_SHIFT)) & FLEXCAN_CTRL2_EDFLTDIS_MASK) 680 681 #define FLEXCAN_CTRL2_ISOCANFDEN_MASK (0x1000U) 682 #define FLEXCAN_CTRL2_ISOCANFDEN_SHIFT (12U) 683 #define FLEXCAN_CTRL2_ISOCANFDEN_WIDTH (1U) 684 #define FLEXCAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_ISOCANFDEN_SHIFT)) & FLEXCAN_CTRL2_ISOCANFDEN_MASK) 685 686 #define FLEXCAN_CTRL2_BTE_MASK (0x2000U) 687 #define FLEXCAN_CTRL2_BTE_SHIFT (13U) 688 #define FLEXCAN_CTRL2_BTE_WIDTH (1U) 689 #define FLEXCAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_BTE_SHIFT)) & FLEXCAN_CTRL2_BTE_MASK) 690 691 #define FLEXCAN_CTRL2_PREXCEN_MASK (0x4000U) 692 #define FLEXCAN_CTRL2_PREXCEN_SHIFT (14U) 693 #define FLEXCAN_CTRL2_PREXCEN_WIDTH (1U) 694 #define FLEXCAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_PREXCEN_SHIFT)) & FLEXCAN_CTRL2_PREXCEN_MASK) 695 696 #define FLEXCAN_CTRL2_TIMER_SRC_MASK (0x8000U) 697 #define FLEXCAN_CTRL2_TIMER_SRC_SHIFT (15U) 698 #define FLEXCAN_CTRL2_TIMER_SRC_WIDTH (1U) 699 #define FLEXCAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_TIMER_SRC_SHIFT)) & FLEXCAN_CTRL2_TIMER_SRC_MASK) 700 701 #define FLEXCAN_CTRL2_EACEN_MASK (0x10000U) 702 #define FLEXCAN_CTRL2_EACEN_SHIFT (16U) 703 #define FLEXCAN_CTRL2_EACEN_WIDTH (1U) 704 #define FLEXCAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_EACEN_SHIFT)) & FLEXCAN_CTRL2_EACEN_MASK) 705 706 #define FLEXCAN_CTRL2_RRS_MASK (0x20000U) 707 #define FLEXCAN_CTRL2_RRS_SHIFT (17U) 708 #define FLEXCAN_CTRL2_RRS_WIDTH (1U) 709 #define FLEXCAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_RRS_SHIFT)) & FLEXCAN_CTRL2_RRS_MASK) 710 711 #define FLEXCAN_CTRL2_MRP_MASK (0x40000U) 712 #define FLEXCAN_CTRL2_MRP_SHIFT (18U) 713 #define FLEXCAN_CTRL2_MRP_WIDTH (1U) 714 #define FLEXCAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_MRP_SHIFT)) & FLEXCAN_CTRL2_MRP_MASK) 715 716 #define FLEXCAN_CTRL2_TASD_MASK (0xF80000U) 717 #define FLEXCAN_CTRL2_TASD_SHIFT (19U) 718 #define FLEXCAN_CTRL2_TASD_WIDTH (5U) 719 #define FLEXCAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_TASD_SHIFT)) & FLEXCAN_CTRL2_TASD_MASK) 720 721 #define FLEXCAN_CTRL2_RFFN_MASK (0xF000000U) 722 #define FLEXCAN_CTRL2_RFFN_SHIFT (24U) 723 #define FLEXCAN_CTRL2_RFFN_WIDTH (4U) 724 #define FLEXCAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_RFFN_SHIFT)) & FLEXCAN_CTRL2_RFFN_MASK) 725 726 #define FLEXCAN_CTRL2_WRMFRZ_MASK (0x10000000U) 727 #define FLEXCAN_CTRL2_WRMFRZ_SHIFT (28U) 728 #define FLEXCAN_CTRL2_WRMFRZ_WIDTH (1U) 729 #define FLEXCAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_WRMFRZ_SHIFT)) & FLEXCAN_CTRL2_WRMFRZ_MASK) 730 731 #define FLEXCAN_CTRL2_ECRWRE_MASK (0x20000000U) 732 #define FLEXCAN_CTRL2_ECRWRE_SHIFT (29U) 733 #define FLEXCAN_CTRL2_ECRWRE_WIDTH (1U) 734 #define FLEXCAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_ECRWRE_SHIFT)) & FLEXCAN_CTRL2_ECRWRE_MASK) 735 736 #define FLEXCAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) 737 #define FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT (30U) 738 #define FLEXCAN_CTRL2_BOFFDONEMSK_WIDTH (1U) 739 #define FLEXCAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT)) & FLEXCAN_CTRL2_BOFFDONEMSK_MASK) 740 741 #define FLEXCAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) 742 #define FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT (31U) 743 #define FLEXCAN_CTRL2_ERRMSK_FAST_WIDTH (1U) 744 #define FLEXCAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT)) & FLEXCAN_CTRL2_ERRMSK_FAST_MASK) 745 /*! @} */ 746 747 /*! @name ESR2 - Error and Status 2 Register */ 748 /*! @{ */ 749 750 #define FLEXCAN_ESR2_IMB_MASK (0x2000U) 751 #define FLEXCAN_ESR2_IMB_SHIFT (13U) 752 #define FLEXCAN_ESR2_IMB_WIDTH (1U) 753 #define FLEXCAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR2_IMB_SHIFT)) & FLEXCAN_ESR2_IMB_MASK) 754 755 #define FLEXCAN_ESR2_VPS_MASK (0x4000U) 756 #define FLEXCAN_ESR2_VPS_SHIFT (14U) 757 #define FLEXCAN_ESR2_VPS_WIDTH (1U) 758 #define FLEXCAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR2_VPS_SHIFT)) & FLEXCAN_ESR2_VPS_MASK) 759 760 #define FLEXCAN_ESR2_LPTM_MASK (0x7F0000U) 761 #define FLEXCAN_ESR2_LPTM_SHIFT (16U) 762 #define FLEXCAN_ESR2_LPTM_WIDTH (7U) 763 #define FLEXCAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ESR2_LPTM_SHIFT)) & FLEXCAN_ESR2_LPTM_MASK) 764 /*! @} */ 765 766 /*! @name CRCR - CRC Register */ 767 /*! @{ */ 768 769 #define FLEXCAN_CRCR_TXCRC_MASK (0x7FFFU) 770 #define FLEXCAN_CRCR_TXCRC_SHIFT (0U) 771 #define FLEXCAN_CRCR_TXCRC_WIDTH (15U) 772 #define FLEXCAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CRCR_TXCRC_SHIFT)) & FLEXCAN_CRCR_TXCRC_MASK) 773 774 #define FLEXCAN_CRCR_MBCRC_MASK (0x7F0000U) 775 #define FLEXCAN_CRCR_MBCRC_SHIFT (16U) 776 #define FLEXCAN_CRCR_MBCRC_WIDTH (7U) 777 #define FLEXCAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CRCR_MBCRC_SHIFT)) & FLEXCAN_CRCR_MBCRC_MASK) 778 /*! @} */ 779 780 /*! @name RXFGMASK - Legacy Rx FIFO Global Mask Register */ 781 /*! @{ */ 782 783 #define FLEXCAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) 784 #define FLEXCAN_RXFGMASK_FGM_SHIFT (0U) 785 #define FLEXCAN_RXFGMASK_FGM_WIDTH (32U) 786 #define FLEXCAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFGMASK_FGM_SHIFT)) & FLEXCAN_RXFGMASK_FGM_MASK) 787 /*! @} */ 788 789 /*! @name RXFIR - Legacy Rx FIFO Information Register */ 790 /*! @{ */ 791 792 #define FLEXCAN_RXFIR_IDHIT_MASK (0x1FFU) 793 #define FLEXCAN_RXFIR_IDHIT_SHIFT (0U) 794 #define FLEXCAN_RXFIR_IDHIT_WIDTH (9U) 795 #define FLEXCAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXFIR_IDHIT_SHIFT)) & FLEXCAN_RXFIR_IDHIT_MASK) 796 /*! @} */ 797 798 /*! @name CBT - CAN Bit Timing Register */ 799 /*! @{ */ 800 801 #define FLEXCAN_CBT_EPSEG2_MASK (0x1FU) 802 #define FLEXCAN_CBT_EPSEG2_SHIFT (0U) 803 #define FLEXCAN_CBT_EPSEG2_WIDTH (5U) 804 #define FLEXCAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPSEG2_SHIFT)) & FLEXCAN_CBT_EPSEG2_MASK) 805 806 #define FLEXCAN_CBT_EPSEG1_MASK (0x3E0U) 807 #define FLEXCAN_CBT_EPSEG1_SHIFT (5U) 808 #define FLEXCAN_CBT_EPSEG1_WIDTH (5U) 809 #define FLEXCAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPSEG1_SHIFT)) & FLEXCAN_CBT_EPSEG1_MASK) 810 811 #define FLEXCAN_CBT_EPROPSEG_MASK (0xFC00U) 812 #define FLEXCAN_CBT_EPROPSEG_SHIFT (10U) 813 #define FLEXCAN_CBT_EPROPSEG_WIDTH (6U) 814 #define FLEXCAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPROPSEG_SHIFT)) & FLEXCAN_CBT_EPROPSEG_MASK) 815 816 #define FLEXCAN_CBT_ERJW_MASK (0x1F0000U) 817 #define FLEXCAN_CBT_ERJW_SHIFT (16U) 818 #define FLEXCAN_CBT_ERJW_WIDTH (5U) 819 #define FLEXCAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_ERJW_SHIFT)) & FLEXCAN_CBT_ERJW_MASK) 820 821 #define FLEXCAN_CBT_EPRESDIV_MASK (0x7FE00000U) 822 #define FLEXCAN_CBT_EPRESDIV_SHIFT (21U) 823 #define FLEXCAN_CBT_EPRESDIV_WIDTH (10U) 824 #define FLEXCAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_EPRESDIV_SHIFT)) & FLEXCAN_CBT_EPRESDIV_MASK) 825 826 #define FLEXCAN_CBT_BTF_MASK (0x80000000U) 827 #define FLEXCAN_CBT_BTF_SHIFT (31U) 828 #define FLEXCAN_CBT_BTF_WIDTH (1U) 829 #define FLEXCAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_CBT_BTF_SHIFT)) & FLEXCAN_CBT_BTF_MASK) 830 /*! @} */ 831 832 /*! @name IMASK4 - Interrupt Masks 4 Register */ 833 /*! @{ */ 834 835 #define FLEXCAN_IMASK4_BUF127TO96M_MASK (0xFFFFFFFFU) 836 #define FLEXCAN_IMASK4_BUF127TO96M_SHIFT (0U) 837 #define FLEXCAN_IMASK4_BUF127TO96M_WIDTH (32U) 838 #define FLEXCAN_IMASK4_BUF127TO96M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IMASK4_BUF127TO96M_SHIFT)) & FLEXCAN_IMASK4_BUF127TO96M_MASK) 839 /*! @} */ 840 841 /*! @name IMASK3 - Interrupt Masks 3 Register */ 842 /*! @{ */ 843 844 #define FLEXCAN_IMASK3_BUF95TO64M_MASK (0xFFFFFFFFU) 845 #define FLEXCAN_IMASK3_BUF95TO64M_SHIFT (0U) 846 #define FLEXCAN_IMASK3_BUF95TO64M_WIDTH (32U) 847 #define FLEXCAN_IMASK3_BUF95TO64M(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IMASK3_BUF95TO64M_SHIFT)) & FLEXCAN_IMASK3_BUF95TO64M_MASK) 848 /*! @} */ 849 850 /*! @name IFLAG4 - Interrupt Flags 4 Register */ 851 /*! @{ */ 852 853 #define FLEXCAN_IFLAG4_BUF127TO96_MASK (0xFFFFFFFFU) 854 #define FLEXCAN_IFLAG4_BUF127TO96_SHIFT (0U) 855 #define FLEXCAN_IFLAG4_BUF127TO96_WIDTH (32U) 856 #define FLEXCAN_IFLAG4_BUF127TO96(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG4_BUF127TO96_SHIFT)) & FLEXCAN_IFLAG4_BUF127TO96_MASK) 857 /*! @} */ 858 859 /*! @name IFLAG3 - Interrupt Flags 3 Register */ 860 /*! @{ */ 861 862 #define FLEXCAN_IFLAG3_BUF95TO64_MASK (0xFFFFFFFFU) 863 #define FLEXCAN_IFLAG3_BUF95TO64_SHIFT (0U) 864 #define FLEXCAN_IFLAG3_BUF95TO64_WIDTH (32U) 865 #define FLEXCAN_IFLAG3_BUF95TO64(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_IFLAG3_BUF95TO64_SHIFT)) & FLEXCAN_IFLAG3_BUF95TO64_MASK) 866 /*! @} */ 867 868 /*! @name RXIMR - Rx Individual Mask Registers */ 869 /*! @{ */ 870 871 #define FLEXCAN_RXIMR_MI_MASK (0xFFFFFFFFU) 872 #define FLEXCAN_RXIMR_MI_SHIFT (0U) 873 #define FLEXCAN_RXIMR_MI_WIDTH (32U) 874 #define FLEXCAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RXIMR_MI_SHIFT)) & FLEXCAN_RXIMR_MI_MASK) 875 /*! @} */ 876 877 /*! @name MECR - Memory Error Control Register */ 878 /*! @{ */ 879 880 #define FLEXCAN_MECR_NCEFAFRZ_MASK (0x80U) 881 #define FLEXCAN_MECR_NCEFAFRZ_SHIFT (7U) 882 #define FLEXCAN_MECR_NCEFAFRZ_WIDTH (1U) 883 #define FLEXCAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_NCEFAFRZ_SHIFT)) & FLEXCAN_MECR_NCEFAFRZ_MASK) 884 885 #define FLEXCAN_MECR_ECCDIS_MASK (0x100U) 886 #define FLEXCAN_MECR_ECCDIS_SHIFT (8U) 887 #define FLEXCAN_MECR_ECCDIS_WIDTH (1U) 888 #define FLEXCAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_ECCDIS_SHIFT)) & FLEXCAN_MECR_ECCDIS_MASK) 889 890 #define FLEXCAN_MECR_RERRDIS_MASK (0x200U) 891 #define FLEXCAN_MECR_RERRDIS_SHIFT (9U) 892 #define FLEXCAN_MECR_RERRDIS_WIDTH (1U) 893 #define FLEXCAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_RERRDIS_SHIFT)) & FLEXCAN_MECR_RERRDIS_MASK) 894 895 #define FLEXCAN_MECR_EXTERRIE_MASK (0x2000U) 896 #define FLEXCAN_MECR_EXTERRIE_SHIFT (13U) 897 #define FLEXCAN_MECR_EXTERRIE_WIDTH (1U) 898 #define FLEXCAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_EXTERRIE_SHIFT)) & FLEXCAN_MECR_EXTERRIE_MASK) 899 900 #define FLEXCAN_MECR_FAERRIE_MASK (0x4000U) 901 #define FLEXCAN_MECR_FAERRIE_SHIFT (14U) 902 #define FLEXCAN_MECR_FAERRIE_WIDTH (1U) 903 #define FLEXCAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_FAERRIE_SHIFT)) & FLEXCAN_MECR_FAERRIE_MASK) 904 905 #define FLEXCAN_MECR_HAERRIE_MASK (0x8000U) 906 #define FLEXCAN_MECR_HAERRIE_SHIFT (15U) 907 #define FLEXCAN_MECR_HAERRIE_WIDTH (1U) 908 #define FLEXCAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_HAERRIE_SHIFT)) & FLEXCAN_MECR_HAERRIE_MASK) 909 910 #define FLEXCAN_MECR_ECRWRDIS_MASK (0x80000000U) 911 #define FLEXCAN_MECR_ECRWRDIS_SHIFT (31U) 912 #define FLEXCAN_MECR_ECRWRDIS_WIDTH (1U) 913 #define FLEXCAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_MECR_ECRWRDIS_SHIFT)) & FLEXCAN_MECR_ECRWRDIS_MASK) 914 /*! @} */ 915 916 /*! @name ERRIAR - Error Injection Address Register */ 917 /*! @{ */ 918 919 #define FLEXCAN_ERRIAR_INJADDR_L_MASK (0x3U) 920 #define FLEXCAN_ERRIAR_INJADDR_L_SHIFT (0U) 921 #define FLEXCAN_ERRIAR_INJADDR_L_WIDTH (2U) 922 #define FLEXCAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIAR_INJADDR_L_SHIFT)) & FLEXCAN_ERRIAR_INJADDR_L_MASK) 923 924 #define FLEXCAN_ERRIAR_INJADDR_H_MASK (0x3FFCU) 925 #define FLEXCAN_ERRIAR_INJADDR_H_SHIFT (2U) 926 #define FLEXCAN_ERRIAR_INJADDR_H_WIDTH (12U) 927 #define FLEXCAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIAR_INJADDR_H_SHIFT)) & FLEXCAN_ERRIAR_INJADDR_H_MASK) 928 /*! @} */ 929 930 /*! @name ERRIDPR - Error Injection Data Pattern Register */ 931 /*! @{ */ 932 933 #define FLEXCAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU) 934 #define FLEXCAN_ERRIDPR_DFLIP_SHIFT (0U) 935 #define FLEXCAN_ERRIDPR_DFLIP_WIDTH (32U) 936 #define FLEXCAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIDPR_DFLIP_SHIFT)) & FLEXCAN_ERRIDPR_DFLIP_MASK) 937 /*! @} */ 938 939 /*! @name ERRIPPR - Error Injection Parity Pattern Register */ 940 /*! @{ */ 941 942 #define FLEXCAN_ERRIPPR_PFLIP0_MASK (0x1FU) 943 #define FLEXCAN_ERRIPPR_PFLIP0_SHIFT (0U) 944 #define FLEXCAN_ERRIPPR_PFLIP0_WIDTH (5U) 945 #define FLEXCAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP0_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP0_MASK) 946 947 #define FLEXCAN_ERRIPPR_PFLIP1_MASK (0x1F00U) 948 #define FLEXCAN_ERRIPPR_PFLIP1_SHIFT (8U) 949 #define FLEXCAN_ERRIPPR_PFLIP1_WIDTH (5U) 950 #define FLEXCAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP1_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP1_MASK) 951 952 #define FLEXCAN_ERRIPPR_PFLIP2_MASK (0x1F0000U) 953 #define FLEXCAN_ERRIPPR_PFLIP2_SHIFT (16U) 954 #define FLEXCAN_ERRIPPR_PFLIP2_WIDTH (5U) 955 #define FLEXCAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP2_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP2_MASK) 956 957 #define FLEXCAN_ERRIPPR_PFLIP3_MASK (0x1F000000U) 958 #define FLEXCAN_ERRIPPR_PFLIP3_SHIFT (24U) 959 #define FLEXCAN_ERRIPPR_PFLIP3_WIDTH (5U) 960 #define FLEXCAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP3_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP3_MASK) 961 /*! @} */ 962 963 /*! @name RERRAR - Error Report Address Register */ 964 /*! @{ */ 965 966 #define FLEXCAN_RERRAR_ERRADDR_MASK (0x3FFFU) 967 #define FLEXCAN_RERRAR_ERRADDR_SHIFT (0U) 968 #define FLEXCAN_RERRAR_ERRADDR_WIDTH (14U) 969 #define FLEXCAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRAR_ERRADDR_SHIFT)) & FLEXCAN_RERRAR_ERRADDR_MASK) 970 971 #define FLEXCAN_RERRAR_SAID_MASK (0x70000U) 972 #define FLEXCAN_RERRAR_SAID_SHIFT (16U) 973 #define FLEXCAN_RERRAR_SAID_WIDTH (3U) 974 #define FLEXCAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRAR_SAID_SHIFT)) & FLEXCAN_RERRAR_SAID_MASK) 975 976 #define FLEXCAN_RERRAR_NCE_MASK (0x1000000U) 977 #define FLEXCAN_RERRAR_NCE_SHIFT (24U) 978 #define FLEXCAN_RERRAR_NCE_WIDTH (1U) 979 #define FLEXCAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRAR_NCE_SHIFT)) & FLEXCAN_RERRAR_NCE_MASK) 980 /*! @} */ 981 982 /*! @name RERRDR - Error Report Data Register */ 983 /*! @{ */ 984 985 #define FLEXCAN_RERRDR_RDATA_MASK (0xFFFFFFFFU) 986 #define FLEXCAN_RERRDR_RDATA_SHIFT (0U) 987 #define FLEXCAN_RERRDR_RDATA_WIDTH (32U) 988 #define FLEXCAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRDR_RDATA_SHIFT)) & FLEXCAN_RERRDR_RDATA_MASK) 989 /*! @} */ 990 991 /*! @name RERRSYNR - Error Report Syndrome Register */ 992 /*! @{ */ 993 994 #define FLEXCAN_RERRSYNR_SYND0_MASK (0x1FU) 995 #define FLEXCAN_RERRSYNR_SYND0_SHIFT (0U) 996 #define FLEXCAN_RERRSYNR_SYND0_WIDTH (5U) 997 #define FLEXCAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND0_SHIFT)) & FLEXCAN_RERRSYNR_SYND0_MASK) 998 999 #define FLEXCAN_RERRSYNR_BE0_MASK (0x80U) 1000 #define FLEXCAN_RERRSYNR_BE0_SHIFT (7U) 1001 #define FLEXCAN_RERRSYNR_BE0_WIDTH (1U) 1002 #define FLEXCAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_BE0_SHIFT)) & FLEXCAN_RERRSYNR_BE0_MASK) 1003 1004 #define FLEXCAN_RERRSYNR_SYND1_MASK (0x1F00U) 1005 #define FLEXCAN_RERRSYNR_SYND1_SHIFT (8U) 1006 #define FLEXCAN_RERRSYNR_SYND1_WIDTH (5U) 1007 #define FLEXCAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND1_SHIFT)) & FLEXCAN_RERRSYNR_SYND1_MASK) 1008 1009 #define FLEXCAN_RERRSYNR_BE1_MASK (0x8000U) 1010 #define FLEXCAN_RERRSYNR_BE1_SHIFT (15U) 1011 #define FLEXCAN_RERRSYNR_BE1_WIDTH (1U) 1012 #define FLEXCAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_BE1_SHIFT)) & FLEXCAN_RERRSYNR_BE1_MASK) 1013 1014 #define FLEXCAN_RERRSYNR_SYND2_MASK (0x1F0000U) 1015 #define FLEXCAN_RERRSYNR_SYND2_SHIFT (16U) 1016 #define FLEXCAN_RERRSYNR_SYND2_WIDTH (5U) 1017 #define FLEXCAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND2_SHIFT)) & FLEXCAN_RERRSYNR_SYND2_MASK) 1018 1019 #define FLEXCAN_RERRSYNR_BE2_MASK (0x800000U) 1020 #define FLEXCAN_RERRSYNR_BE2_SHIFT (23U) 1021 #define FLEXCAN_RERRSYNR_BE2_WIDTH (1U) 1022 #define FLEXCAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_BE2_SHIFT)) & FLEXCAN_RERRSYNR_BE2_MASK) 1023 1024 #define FLEXCAN_RERRSYNR_SYND3_MASK (0x1F000000U) 1025 #define FLEXCAN_RERRSYNR_SYND3_SHIFT (24U) 1026 #define FLEXCAN_RERRSYNR_SYND3_WIDTH (5U) 1027 #define FLEXCAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND3_SHIFT)) & FLEXCAN_RERRSYNR_SYND3_MASK) 1028 1029 #define FLEXCAN_RERRSYNR_BE3_MASK (0x80000000U) 1030 #define FLEXCAN_RERRSYNR_BE3_SHIFT (31U) 1031 #define FLEXCAN_RERRSYNR_BE3_WIDTH (1U) 1032 #define FLEXCAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_RERRSYNR_BE3_SHIFT)) & FLEXCAN_RERRSYNR_BE3_MASK) 1033 /*! @} */ 1034 1035 /*! @name ERRSR - Error Status Register */ 1036 /*! @{ */ 1037 1038 #define FLEXCAN_ERRSR_CEIOF_MASK (0x1U) 1039 #define FLEXCAN_ERRSR_CEIOF_SHIFT (0U) 1040 #define FLEXCAN_ERRSR_CEIOF_WIDTH (1U) 1041 #define FLEXCAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_CEIOF_SHIFT)) & FLEXCAN_ERRSR_CEIOF_MASK) 1042 1043 #define FLEXCAN_ERRSR_FANCEIOF_MASK (0x4U) 1044 #define FLEXCAN_ERRSR_FANCEIOF_SHIFT (2U) 1045 #define FLEXCAN_ERRSR_FANCEIOF_WIDTH (1U) 1046 #define FLEXCAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_FANCEIOF_SHIFT)) & FLEXCAN_ERRSR_FANCEIOF_MASK) 1047 1048 #define FLEXCAN_ERRSR_HANCEIOF_MASK (0x8U) 1049 #define FLEXCAN_ERRSR_HANCEIOF_SHIFT (3U) 1050 #define FLEXCAN_ERRSR_HANCEIOF_WIDTH (1U) 1051 #define FLEXCAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_HANCEIOF_SHIFT)) & FLEXCAN_ERRSR_HANCEIOF_MASK) 1052 1053 #define FLEXCAN_ERRSR_CEIF_MASK (0x10000U) 1054 #define FLEXCAN_ERRSR_CEIF_SHIFT (16U) 1055 #define FLEXCAN_ERRSR_CEIF_WIDTH (1U) 1056 #define FLEXCAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_CEIF_SHIFT)) & FLEXCAN_ERRSR_CEIF_MASK) 1057 1058 #define FLEXCAN_ERRSR_FANCEIF_MASK (0x40000U) 1059 #define FLEXCAN_ERRSR_FANCEIF_SHIFT (18U) 1060 #define FLEXCAN_ERRSR_FANCEIF_WIDTH (1U) 1061 #define FLEXCAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_FANCEIF_SHIFT)) & FLEXCAN_ERRSR_FANCEIF_MASK) 1062 1063 #define FLEXCAN_ERRSR_HANCEIF_MASK (0x80000U) 1064 #define FLEXCAN_ERRSR_HANCEIF_SHIFT (19U) 1065 #define FLEXCAN_ERRSR_HANCEIF_WIDTH (1U) 1066 #define FLEXCAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERRSR_HANCEIF_SHIFT)) & FLEXCAN_ERRSR_HANCEIF_MASK) 1067 /*! @} */ 1068 1069 /*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ 1070 /*! @{ */ 1071 1072 #define FLEXCAN_EPRS_ENPRESDIV_MASK (0x3FFU) 1073 #define FLEXCAN_EPRS_ENPRESDIV_SHIFT (0U) 1074 #define FLEXCAN_EPRS_ENPRESDIV_WIDTH (10U) 1075 #define FLEXCAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_EPRS_ENPRESDIV_SHIFT)) & FLEXCAN_EPRS_ENPRESDIV_MASK) 1076 1077 #define FLEXCAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) 1078 #define FLEXCAN_EPRS_EDPRESDIV_SHIFT (16U) 1079 #define FLEXCAN_EPRS_EDPRESDIV_WIDTH (10U) 1080 #define FLEXCAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_EPRS_EDPRESDIV_SHIFT)) & FLEXCAN_EPRS_EDPRESDIV_MASK) 1081 /*! @} */ 1082 1083 /*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ 1084 /*! @{ */ 1085 1086 #define FLEXCAN_ENCBT_NTSEG1_MASK (0xFFU) 1087 #define FLEXCAN_ENCBT_NTSEG1_SHIFT (0U) 1088 #define FLEXCAN_ENCBT_NTSEG1_WIDTH (8U) 1089 #define FLEXCAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ENCBT_NTSEG1_SHIFT)) & FLEXCAN_ENCBT_NTSEG1_MASK) 1090 1091 #define FLEXCAN_ENCBT_NTSEG2_MASK (0x7F000U) 1092 #define FLEXCAN_ENCBT_NTSEG2_SHIFT (12U) 1093 #define FLEXCAN_ENCBT_NTSEG2_WIDTH (7U) 1094 #define FLEXCAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ENCBT_NTSEG2_SHIFT)) & FLEXCAN_ENCBT_NTSEG2_MASK) 1095 1096 #define FLEXCAN_ENCBT_NRJW_MASK (0x1FC00000U) 1097 #define FLEXCAN_ENCBT_NRJW_SHIFT (22U) 1098 #define FLEXCAN_ENCBT_NRJW_WIDTH (7U) 1099 #define FLEXCAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ENCBT_NRJW_SHIFT)) & FLEXCAN_ENCBT_NRJW_MASK) 1100 /*! @} */ 1101 1102 /*! @name EDCBT - Enhanced Data Phase CAN bit Timing */ 1103 /*! @{ */ 1104 1105 #define FLEXCAN_EDCBT_DTSEG1_MASK (0x1FU) 1106 #define FLEXCAN_EDCBT_DTSEG1_SHIFT (0U) 1107 #define FLEXCAN_EDCBT_DTSEG1_WIDTH (5U) 1108 #define FLEXCAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_EDCBT_DTSEG1_SHIFT)) & FLEXCAN_EDCBT_DTSEG1_MASK) 1109 1110 #define FLEXCAN_EDCBT_DTSEG2_MASK (0xF000U) 1111 #define FLEXCAN_EDCBT_DTSEG2_SHIFT (12U) 1112 #define FLEXCAN_EDCBT_DTSEG2_WIDTH (4U) 1113 #define FLEXCAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_EDCBT_DTSEG2_SHIFT)) & FLEXCAN_EDCBT_DTSEG2_MASK) 1114 1115 #define FLEXCAN_EDCBT_DRJW_MASK (0x3C00000U) 1116 #define FLEXCAN_EDCBT_DRJW_SHIFT (22U) 1117 #define FLEXCAN_EDCBT_DRJW_WIDTH (4U) 1118 #define FLEXCAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_EDCBT_DRJW_SHIFT)) & FLEXCAN_EDCBT_DRJW_MASK) 1119 /*! @} */ 1120 1121 /*! @name ETDC - Enhanced Transceiver Delay Compensation */ 1122 /*! @{ */ 1123 1124 #define FLEXCAN_ETDC_ETDCVAL_MASK (0xFFU) 1125 #define FLEXCAN_ETDC_ETDCVAL_SHIFT (0U) 1126 #define FLEXCAN_ETDC_ETDCVAL_WIDTH (8U) 1127 #define FLEXCAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ETDC_ETDCVAL_SHIFT)) & FLEXCAN_ETDC_ETDCVAL_MASK) 1128 1129 #define FLEXCAN_ETDC_ETDCFAIL_MASK (0x8000U) 1130 #define FLEXCAN_ETDC_ETDCFAIL_SHIFT (15U) 1131 #define FLEXCAN_ETDC_ETDCFAIL_WIDTH (1U) 1132 #define FLEXCAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ETDC_ETDCFAIL_SHIFT)) & FLEXCAN_ETDC_ETDCFAIL_MASK) 1133 1134 #define FLEXCAN_ETDC_ETDCOFF_MASK (0x7F0000U) 1135 #define FLEXCAN_ETDC_ETDCOFF_SHIFT (16U) 1136 #define FLEXCAN_ETDC_ETDCOFF_WIDTH (7U) 1137 #define FLEXCAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ETDC_ETDCOFF_SHIFT)) & FLEXCAN_ETDC_ETDCOFF_MASK) 1138 1139 #define FLEXCAN_ETDC_TDMDIS_MASK (0x40000000U) 1140 #define FLEXCAN_ETDC_TDMDIS_SHIFT (30U) 1141 #define FLEXCAN_ETDC_TDMDIS_WIDTH (1U) 1142 #define FLEXCAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ETDC_TDMDIS_SHIFT)) & FLEXCAN_ETDC_TDMDIS_MASK) 1143 1144 #define FLEXCAN_ETDC_ETDCEN_MASK (0x80000000U) 1145 #define FLEXCAN_ETDC_ETDCEN_SHIFT (31U) 1146 #define FLEXCAN_ETDC_ETDCEN_WIDTH (1U) 1147 #define FLEXCAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ETDC_ETDCEN_SHIFT)) & FLEXCAN_ETDC_ETDCEN_MASK) 1148 /*! @} */ 1149 1150 /*! @name FDCTRL - CAN FD Control Register */ 1151 /*! @{ */ 1152 1153 #define FLEXCAN_FDCTRL_TDCVAL_MASK (0x3FU) 1154 #define FLEXCAN_FDCTRL_TDCVAL_SHIFT (0U) 1155 #define FLEXCAN_FDCTRL_TDCVAL_WIDTH (6U) 1156 #define FLEXCAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_TDCVAL_SHIFT)) & FLEXCAN_FDCTRL_TDCVAL_MASK) 1157 1158 #define FLEXCAN_FDCTRL_TDCOFF_MASK (0x1F00U) 1159 #define FLEXCAN_FDCTRL_TDCOFF_SHIFT (8U) 1160 #define FLEXCAN_FDCTRL_TDCOFF_WIDTH (5U) 1161 #define FLEXCAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_TDCOFF_SHIFT)) & FLEXCAN_FDCTRL_TDCOFF_MASK) 1162 1163 #define FLEXCAN_FDCTRL_TDCFAIL_MASK (0x4000U) 1164 #define FLEXCAN_FDCTRL_TDCFAIL_SHIFT (14U) 1165 #define FLEXCAN_FDCTRL_TDCFAIL_WIDTH (1U) 1166 #define FLEXCAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_TDCFAIL_SHIFT)) & FLEXCAN_FDCTRL_TDCFAIL_MASK) 1167 1168 #define FLEXCAN_FDCTRL_TDCEN_MASK (0x8000U) 1169 #define FLEXCAN_FDCTRL_TDCEN_SHIFT (15U) 1170 #define FLEXCAN_FDCTRL_TDCEN_WIDTH (1U) 1171 #define FLEXCAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_TDCEN_SHIFT)) & FLEXCAN_FDCTRL_TDCEN_MASK) 1172 1173 #define FLEXCAN_FDCTRL_MBDSR0_MASK (0x30000U) 1174 #define FLEXCAN_FDCTRL_MBDSR0_SHIFT (16U) 1175 #define FLEXCAN_FDCTRL_MBDSR0_WIDTH (2U) 1176 #define FLEXCAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR0_SHIFT)) & FLEXCAN_FDCTRL_MBDSR0_MASK) 1177 1178 #define FLEXCAN_FDCTRL_MBDSR1_MASK (0x180000U) 1179 #define FLEXCAN_FDCTRL_MBDSR1_SHIFT (19U) 1180 #define FLEXCAN_FDCTRL_MBDSR1_WIDTH (2U) 1181 #define FLEXCAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR1_SHIFT)) & FLEXCAN_FDCTRL_MBDSR1_MASK) 1182 1183 #define FLEXCAN_FDCTRL_MBDSR2_MASK (0xC00000U) 1184 #define FLEXCAN_FDCTRL_MBDSR2_SHIFT (22U) 1185 #define FLEXCAN_FDCTRL_MBDSR2_WIDTH (2U) 1186 #define FLEXCAN_FDCTRL_MBDSR2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR2_SHIFT)) & FLEXCAN_FDCTRL_MBDSR2_MASK) 1187 1188 #define FLEXCAN_FDCTRL_MBDSR3_MASK (0x6000000U) 1189 #define FLEXCAN_FDCTRL_MBDSR3_SHIFT (25U) 1190 #define FLEXCAN_FDCTRL_MBDSR3_WIDTH (2U) 1191 #define FLEXCAN_FDCTRL_MBDSR3(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR3_SHIFT)) & FLEXCAN_FDCTRL_MBDSR3_MASK) 1192 1193 #define FLEXCAN_FDCTRL_FDRATE_MASK (0x80000000U) 1194 #define FLEXCAN_FDCTRL_FDRATE_SHIFT (31U) 1195 #define FLEXCAN_FDCTRL_FDRATE_WIDTH (1U) 1196 #define FLEXCAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCTRL_FDRATE_SHIFT)) & FLEXCAN_FDCTRL_FDRATE_MASK) 1197 /*! @} */ 1198 1199 /*! @name FDCBT - CAN FD Bit Timing Register */ 1200 /*! @{ */ 1201 1202 #define FLEXCAN_FDCBT_FPSEG2_MASK (0x7U) 1203 #define FLEXCAN_FDCBT_FPSEG2_SHIFT (0U) 1204 #define FLEXCAN_FDCBT_FPSEG2_WIDTH (3U) 1205 #define FLEXCAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCBT_FPSEG2_SHIFT)) & FLEXCAN_FDCBT_FPSEG2_MASK) 1206 1207 #define FLEXCAN_FDCBT_FPSEG1_MASK (0xE0U) 1208 #define FLEXCAN_FDCBT_FPSEG1_SHIFT (5U) 1209 #define FLEXCAN_FDCBT_FPSEG1_WIDTH (3U) 1210 #define FLEXCAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCBT_FPSEG1_SHIFT)) & FLEXCAN_FDCBT_FPSEG1_MASK) 1211 1212 #define FLEXCAN_FDCBT_FPROPSEG_MASK (0x7C00U) 1213 #define FLEXCAN_FDCBT_FPROPSEG_SHIFT (10U) 1214 #define FLEXCAN_FDCBT_FPROPSEG_WIDTH (5U) 1215 #define FLEXCAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCBT_FPROPSEG_SHIFT)) & FLEXCAN_FDCBT_FPROPSEG_MASK) 1216 1217 #define FLEXCAN_FDCBT_FRJW_MASK (0x70000U) 1218 #define FLEXCAN_FDCBT_FRJW_SHIFT (16U) 1219 #define FLEXCAN_FDCBT_FRJW_WIDTH (3U) 1220 #define FLEXCAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCBT_FRJW_SHIFT)) & FLEXCAN_FDCBT_FRJW_MASK) 1221 1222 #define FLEXCAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) 1223 #define FLEXCAN_FDCBT_FPRESDIV_SHIFT (20U) 1224 #define FLEXCAN_FDCBT_FPRESDIV_WIDTH (10U) 1225 #define FLEXCAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCBT_FPRESDIV_SHIFT)) & FLEXCAN_FDCBT_FPRESDIV_MASK) 1226 /*! @} */ 1227 1228 /*! @name FDCRC - CAN FD CRC Register */ 1229 /*! @{ */ 1230 1231 #define FLEXCAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) 1232 #define FLEXCAN_FDCRC_FD_TXCRC_SHIFT (0U) 1233 #define FLEXCAN_FDCRC_FD_TXCRC_WIDTH (21U) 1234 #define FLEXCAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCRC_FD_TXCRC_SHIFT)) & FLEXCAN_FDCRC_FD_TXCRC_MASK) 1235 1236 #define FLEXCAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) 1237 #define FLEXCAN_FDCRC_FD_MBCRC_SHIFT (24U) 1238 #define FLEXCAN_FDCRC_FD_MBCRC_WIDTH (7U) 1239 #define FLEXCAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_FDCRC_FD_MBCRC_SHIFT)) & FLEXCAN_FDCRC_FD_MBCRC_MASK) 1240 /*! @} */ 1241 1242 /*! @name ERFCR - Enhanced Rx FIFO Control Register */ 1243 /*! @{ */ 1244 1245 #define FLEXCAN_ERFCR_ERFWM_MASK (0x1FU) 1246 #define FLEXCAN_ERFCR_ERFWM_SHIFT (0U) 1247 #define FLEXCAN_ERFCR_ERFWM_WIDTH (5U) 1248 #define FLEXCAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFCR_ERFWM_SHIFT)) & FLEXCAN_ERFCR_ERFWM_MASK) 1249 1250 #define FLEXCAN_ERFCR_NFE_MASK (0x3F00U) 1251 #define FLEXCAN_ERFCR_NFE_SHIFT (8U) 1252 #define FLEXCAN_ERFCR_NFE_WIDTH (6U) 1253 #define FLEXCAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFCR_NFE_SHIFT)) & FLEXCAN_ERFCR_NFE_MASK) 1254 1255 #define FLEXCAN_ERFCR_NEXIF_MASK (0x7F0000U) 1256 #define FLEXCAN_ERFCR_NEXIF_SHIFT (16U) 1257 #define FLEXCAN_ERFCR_NEXIF_WIDTH (7U) 1258 #define FLEXCAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFCR_NEXIF_SHIFT)) & FLEXCAN_ERFCR_NEXIF_MASK) 1259 1260 #define FLEXCAN_ERFCR_DMALW_MASK (0x7C000000U) 1261 #define FLEXCAN_ERFCR_DMALW_SHIFT (26U) 1262 #define FLEXCAN_ERFCR_DMALW_WIDTH (5U) 1263 #define FLEXCAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFCR_DMALW_SHIFT)) & FLEXCAN_ERFCR_DMALW_MASK) 1264 1265 #define FLEXCAN_ERFCR_ERFEN_MASK (0x80000000U) 1266 #define FLEXCAN_ERFCR_ERFEN_SHIFT (31U) 1267 #define FLEXCAN_ERFCR_ERFEN_WIDTH (1U) 1268 #define FLEXCAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFCR_ERFEN_SHIFT)) & FLEXCAN_ERFCR_ERFEN_MASK) 1269 /*! @} */ 1270 1271 /*! @name ERFIER - Enhanced Rx FIFO Interrupt Enable Register */ 1272 /*! @{ */ 1273 1274 #define FLEXCAN_ERFIER_ERFDAIE_MASK (0x10000000U) 1275 #define FLEXCAN_ERFIER_ERFDAIE_SHIFT (28U) 1276 #define FLEXCAN_ERFIER_ERFDAIE_WIDTH (1U) 1277 #define FLEXCAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFIER_ERFDAIE_SHIFT)) & FLEXCAN_ERFIER_ERFDAIE_MASK) 1278 1279 #define FLEXCAN_ERFIER_ERFWMIIE_MASK (0x20000000U) 1280 #define FLEXCAN_ERFIER_ERFWMIIE_SHIFT (29U) 1281 #define FLEXCAN_ERFIER_ERFWMIIE_WIDTH (1U) 1282 #define FLEXCAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFIER_ERFWMIIE_SHIFT)) & FLEXCAN_ERFIER_ERFWMIIE_MASK) 1283 1284 #define FLEXCAN_ERFIER_ERFOVFIE_MASK (0x40000000U) 1285 #define FLEXCAN_ERFIER_ERFOVFIE_SHIFT (30U) 1286 #define FLEXCAN_ERFIER_ERFOVFIE_WIDTH (1U) 1287 #define FLEXCAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFIER_ERFOVFIE_SHIFT)) & FLEXCAN_ERFIER_ERFOVFIE_MASK) 1288 1289 #define FLEXCAN_ERFIER_ERFUFWIE_MASK (0x80000000U) 1290 #define FLEXCAN_ERFIER_ERFUFWIE_SHIFT (31U) 1291 #define FLEXCAN_ERFIER_ERFUFWIE_WIDTH (1U) 1292 #define FLEXCAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFIER_ERFUFWIE_SHIFT)) & FLEXCAN_ERFIER_ERFUFWIE_MASK) 1293 /*! @} */ 1294 1295 /*! @name ERFSR - Enhanced Rx FIFO Status Register */ 1296 /*! @{ */ 1297 1298 #define FLEXCAN_ERFSR_ERFEL_MASK (0x3FU) 1299 #define FLEXCAN_ERFSR_ERFEL_SHIFT (0U) 1300 #define FLEXCAN_ERFSR_ERFEL_WIDTH (6U) 1301 #define FLEXCAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFEL_SHIFT)) & FLEXCAN_ERFSR_ERFEL_MASK) 1302 1303 #define FLEXCAN_ERFSR_ERFF_MASK (0x10000U) 1304 #define FLEXCAN_ERFSR_ERFF_SHIFT (16U) 1305 #define FLEXCAN_ERFSR_ERFF_WIDTH (1U) 1306 #define FLEXCAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFF_SHIFT)) & FLEXCAN_ERFSR_ERFF_MASK) 1307 1308 #define FLEXCAN_ERFSR_ERFE_MASK (0x20000U) 1309 #define FLEXCAN_ERFSR_ERFE_SHIFT (17U) 1310 #define FLEXCAN_ERFSR_ERFE_WIDTH (1U) 1311 #define FLEXCAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFE_SHIFT)) & FLEXCAN_ERFSR_ERFE_MASK) 1312 1313 #define FLEXCAN_ERFSR_ERFCLR_MASK (0x8000000U) 1314 #define FLEXCAN_ERFSR_ERFCLR_SHIFT (27U) 1315 #define FLEXCAN_ERFSR_ERFCLR_WIDTH (1U) 1316 #define FLEXCAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFCLR_SHIFT)) & FLEXCAN_ERFSR_ERFCLR_MASK) 1317 1318 #define FLEXCAN_ERFSR_ERFDA_MASK (0x10000000U) 1319 #define FLEXCAN_ERFSR_ERFDA_SHIFT (28U) 1320 #define FLEXCAN_ERFSR_ERFDA_WIDTH (1U) 1321 #define FLEXCAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFDA_SHIFT)) & FLEXCAN_ERFSR_ERFDA_MASK) 1322 1323 #define FLEXCAN_ERFSR_ERFWMI_MASK (0x20000000U) 1324 #define FLEXCAN_ERFSR_ERFWMI_SHIFT (29U) 1325 #define FLEXCAN_ERFSR_ERFWMI_WIDTH (1U) 1326 #define FLEXCAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFWMI_SHIFT)) & FLEXCAN_ERFSR_ERFWMI_MASK) 1327 1328 #define FLEXCAN_ERFSR_ERFOVF_MASK (0x40000000U) 1329 #define FLEXCAN_ERFSR_ERFOVF_SHIFT (30U) 1330 #define FLEXCAN_ERFSR_ERFOVF_WIDTH (1U) 1331 #define FLEXCAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFOVF_SHIFT)) & FLEXCAN_ERFSR_ERFOVF_MASK) 1332 1333 #define FLEXCAN_ERFSR_ERFUFW_MASK (0x80000000U) 1334 #define FLEXCAN_ERFSR_ERFUFW_SHIFT (31U) 1335 #define FLEXCAN_ERFSR_ERFUFW_WIDTH (1U) 1336 #define FLEXCAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFSR_ERFUFW_SHIFT)) & FLEXCAN_ERFSR_ERFUFW_MASK) 1337 /*! @} */ 1338 1339 /*! @name HR_TIME_STAMP - High Resolution Time Stamp */ 1340 /*! @{ */ 1341 1342 #define FLEXCAN_HR_TIME_STAMP_TS_MASK (0xFFFFFFFFU) 1343 #define FLEXCAN_HR_TIME_STAMP_TS_SHIFT (0U) 1344 #define FLEXCAN_HR_TIME_STAMP_TS_WIDTH (32U) 1345 #define FLEXCAN_HR_TIME_STAMP_TS(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_HR_TIME_STAMP_TS_SHIFT)) & FLEXCAN_HR_TIME_STAMP_TS_MASK) 1346 /*! @} */ 1347 1348 /*! @name ERFFEL - Enhanced Rx FIFO Filter Element */ 1349 /*! @{ */ 1350 1351 #define FLEXCAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) 1352 #define FLEXCAN_ERFFEL_FEL_SHIFT (0U) 1353 #define FLEXCAN_ERFFEL_FEL_WIDTH (32U) 1354 #define FLEXCAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCAN_ERFFEL_FEL_SHIFT)) & FLEXCAN_ERFFEL_FEL_MASK) 1355 /*! @} */ 1356 1357 /*! 1358 * @} 1359 */ /* end of group FLEXCAN_Register_Masks */ 1360 1361 /*! 1362 * @} 1363 */ /* end of group FLEXCAN_Peripheral_Access_Layer */ 1364 1365 #endif /* #if !defined(S32Z2_FLEXCAN_H_) */ 1366
