1 /* 2 ****************************************************************************** 3 * @file ilps28qsw_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * ilps28qsw_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2024 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ILPS28QSW_REGS_H 23 #define ILPS28QSW_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ILPS28QSW 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ILPS28QSW_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format **/ 172 #define ILPS28QSW_I2C_ADD 0xB9U 173 174 /** Device Identification (Who am I) **/ 175 #define ILPS28QSW_ID 0xB4U 176 177 /** 178 * @} 179 * 180 */ 181 182 #define ILPS28QSW_INTERRUPT_CFG 0x0BU 183 typedef struct 184 { 185 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 186 uint8_t phe : 1; 187 uint8_t ple : 1; 188 uint8_t lir : 1; 189 uint8_t not_used_01 : 1; 190 uint8_t reset_az : 1; 191 uint8_t autozero : 1; 192 uint8_t reset_arp : 1; 193 uint8_t autorefp : 1; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t autorefp : 1; 196 uint8_t reset_arp : 1; 197 uint8_t autozero : 1; 198 uint8_t reset_az : 1; 199 uint8_t not_used_01 : 1; 200 uint8_t lir : 1; 201 uint8_t ple : 1; 202 uint8_t phe : 1; 203 #endif /* DRV_BYTE_ORDER */ 204 } ilps28qsw_interrupt_cfg_t; 205 206 #define ILPS28QSW_THS_P_L 0x0CU 207 typedef struct 208 { 209 uint8_t ths : 8; 210 } ilps28qsw_ths_p_l_t; 211 212 #define ILPS28QSW_THS_P_H 0x0DU 213 typedef struct 214 { 215 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 216 uint8_t ths : 7; 217 uint8_t not_used_01 : 1; 218 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 219 uint8_t not_used_01 : 1; 220 uint8_t ths : 7; 221 #endif /* DRV_BYTE_ORDER */ 222 } ilps28qsw_ths_p_h_t; 223 224 #define ILPS28QSW_IF_CTRL 0x0EU 225 typedef struct 226 { 227 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 228 uint8_t not_used_01 : 4; 229 uint8_t sda_pu_en : 1; 230 uint8_t not_used_02 : 3; 231 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 232 uint8_t not_used_02 : 3; 233 uint8_t sda_pu_en : 1; 234 uint8_t not_used_01 : 4; 235 #endif /* DRV_BYTE_ORDER */ 236 } ilps28qsw_if_ctrl_t; 237 238 #define ILPS28QSW_WHO_AM_I 0x0FU 239 #define ILPS28QSW_CTRL_REG1 0x10U 240 typedef struct 241 { 242 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 243 uint8_t avg : 3; 244 uint8_t odr : 4; 245 uint8_t not_used_01 : 1; 246 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 247 uint8_t not_used_01 : 1; 248 uint8_t odr : 4; 249 uint8_t avg : 3; 250 #endif /* DRV_BYTE_ORDER */ 251 } ilps28qsw_ctrl_reg1_t; 252 253 #define ILPS28QSW_CTRL_REG2 0x11U 254 typedef struct 255 { 256 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 257 uint8_t oneshot : 1; 258 uint8_t not_used_01 : 1; 259 uint8_t swreset : 1; 260 uint8_t bdu : 1; 261 uint8_t en_lpfp : 1; 262 uint8_t lfpf_cfg : 1; 263 uint8_t fs_mode : 1; 264 uint8_t boot : 1; 265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 266 uint8_t boot : 1; 267 uint8_t fs_mode : 1; 268 uint8_t lfpf_cfg : 1; 269 uint8_t en_lpfp : 1; 270 uint8_t bdu : 1; 271 uint8_t swreset : 1; 272 uint8_t not_used_01 : 1; 273 uint8_t oneshot : 1; 274 #endif /* DRV_BYTE_ORDER */ 275 } ilps28qsw_ctrl_reg2_t; 276 277 #define ILPS28QSW_CTRL_REG3 0x12U 278 typedef struct 279 { 280 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 281 uint8_t if_add_inc : 1; 282 uint8_t not_used_01 : 4; 283 uint8_t ah_qvar_p_auto_en : 1; 284 uint8_t not_used_02 : 1; 285 uint8_t ah_qvar_en : 1; 286 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 287 uint8_t ah_qvar_en : 1; 288 uint8_t not_used_02 : 1; 289 uint8_t ah_qvar_p_auto_en : 1; 290 uint8_t not_used_01 : 4; 291 uint8_t if_add_inc : 1; 292 #endif /* DRV_BYTE_ORDER */ 293 } ilps28qsw_ctrl_reg3_t; 294 295 #define ILPS28QSW_FIFO_CTRL 0x14U 296 typedef struct 297 { 298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 299 uint8_t f_mode : 2; 300 uint8_t trig_modes : 1; 301 uint8_t stop_on_wtm : 1; 302 uint8_t ah_qvar_p_fifo_en : 1; 303 uint8_t not_used_01 : 3; 304 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 305 uint8_t not_used_01 : 3; 306 uint8_t ah_qvar_p_fifo_en : 1; 307 uint8_t stop_on_wtm : 1; 308 uint8_t trig_modes : 1; 309 uint8_t f_mode : 2; 310 #endif /* DRV_BYTE_ORDER */ 311 } ilps28qsw_fifo_ctrl_t; 312 313 #define ILPS28QSW_FIFO_WTM 0x15U 314 typedef struct 315 { 316 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 317 uint8_t wtm : 7; 318 uint8_t not_used_01 : 1; 319 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 320 uint8_t not_used_01 : 1; 321 uint8_t wtm : 7; 322 #endif /* DRV_BYTE_ORDER */ 323 } ilps28qsw_fifo_wtm_t; 324 325 #define ILPS28QSW_REF_P_L 0x16U 326 typedef struct 327 { 328 uint8_t refp : 8; 329 } ilps28qsw_ref_p_l_t; 330 331 #define ILPS28QSW_REF_P_H 0x17U 332 typedef struct 333 { 334 uint8_t refp : 8; 335 } ilps28qsw_ref_p_h_t; 336 337 #define ILPS28QSW_I3C_IF_CTRL 0x19U 338 typedef struct 339 { 340 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 341 uint8_t I3C_Bus_Avb_Sel : 2; 342 uint8_t not_used_02 : 3; 343 uint8_t asf_on : 1; 344 uint8_t not_used_01 : 2; 345 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 346 uint8_t not_used_01 : 2; 347 uint8_t asf_on : 1; 348 uint8_t not_used_02 : 3; 349 uint8_t I3C_Bus_Avb_Sel : 2; 350 #endif /* DRV_BYTE_ORDER */ 351 } ilps28qsw_i3c_if_ctrl_t; 352 353 #define ILPS28QSW_RPDS_L 0x1AU 354 #define ILPS28QSW_RPDS_H 0x1BU 355 #define ILPS28QSW_INT_SOURCE 0x24U 356 typedef struct 357 { 358 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 359 uint8_t ph : 1; 360 uint8_t pl : 1; 361 uint8_t ia : 1; 362 uint8_t not_used_01 : 4; 363 uint8_t boot_on : 1; 364 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 365 uint8_t boot_on : 1; 366 uint8_t not_used_01 : 4; 367 uint8_t ia : 1; 368 uint8_t pl : 1; 369 uint8_t ph : 1; 370 #endif /* DRV_BYTE_ORDER */ 371 } ilps28qsw_int_source_t; 372 373 #define ILPS28QSW_FIFO_STATUS1 0x25U 374 typedef struct 375 { 376 uint8_t fss : 8; 377 } ilps28qsw_fifo_status1_t; 378 379 #define ILPS28QSW_FIFO_STATUS2 0x26U 380 typedef struct 381 { 382 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 383 uint8_t not_used_01 : 5; 384 uint8_t fifo_full_ia : 1; 385 uint8_t fifo_ovr_ia : 1; 386 uint8_t fifo_wtm_ia : 1; 387 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 388 uint8_t fifo_wtm_ia : 1; 389 uint8_t fifo_ovr_ia : 1; 390 uint8_t fifo_full_ia : 1; 391 uint8_t not_used_01 : 5; 392 #endif /* DRV_BYTE_ORDER */ 393 } ilps28qsw_fifo_status2_t; 394 395 #define ILPS28QSW_STATUS 0x27U 396 typedef struct 397 { 398 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 399 uint8_t p_da : 1; 400 uint8_t t_da : 1; 401 uint8_t not_used_01 : 2; 402 uint8_t p_or : 1; 403 uint8_t t_or : 1; 404 uint8_t not_used_02 : 2; 405 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 406 uint8_t not_used_02 : 2; 407 uint8_t t_or : 1; 408 uint8_t p_or : 1; 409 uint8_t not_used_01 : 2; 410 uint8_t t_da : 1; 411 uint8_t p_da : 1; 412 #endif /* DRV_BYTE_ORDER */ 413 } ilps28qsw_status_t; 414 415 #define ILPS28QSW_PRESS_OUT_XL 0x28U 416 #define ILPS28QSW_PRESS_OUT_L 0x29U 417 #define ILPS28QSW_PRESS_OUT_H 0x2AU 418 #define ILPS28QSW_TEMP_OUT_L 0x2BU 419 #define ILPS28QSW_TEMP_OUT_H 0x2CU 420 421 #define ILPS28QSW_FIFO_DATA_OUT_PRESS_XL 0x78U 422 #define ILPS28QSW_FIFO_DATA_OUT_PRESS_L 0x79U 423 #define ILPS28QSW_FIFO_DATA_OUT_PRESS_H 0x7AU 424 425 /** 426 * @defgroup ILPS28QSW_Register_Union 427 * @brief This union group all the registers that has a bitfield 428 * description. 429 * This union is useful but not need by the driver. 430 * 431 * REMOVING this union you are compliant with: 432 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 433 * 434 * @{ 435 * 436 */ 437 438 typedef union 439 { 440 ilps28qsw_interrupt_cfg_t interrupt_cfg; 441 ilps28qsw_ths_p_l_t ths_p_l; 442 ilps28qsw_ths_p_h_t ths_p_h; 443 ilps28qsw_if_ctrl_t if_ctrl; 444 ilps28qsw_ctrl_reg1_t ctrl_reg1; 445 ilps28qsw_ctrl_reg2_t ctrl_reg2; 446 ilps28qsw_ctrl_reg3_t ctrl_reg3; 447 ilps28qsw_fifo_ctrl_t fifo_ctrl; 448 ilps28qsw_fifo_wtm_t fifo_wtm; 449 ilps28qsw_ref_p_l_t ref_p_l; 450 ilps28qsw_ref_p_h_t ref_p_h; 451 ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl; 452 ilps28qsw_int_source_t int_source; 453 ilps28qsw_fifo_status1_t fifo_status1; 454 ilps28qsw_fifo_status2_t fifo_status2; 455 ilps28qsw_status_t status; 456 bitwise_t bitwise; 457 uint8_t byte; 458 } ilps28qsw_reg_t; 459 460 #ifndef __weak 461 #define __weak __attribute__((weak)) 462 #endif /* __weak */ 463 464 /* 465 * These are the basic platform dependent I/O routines to read 466 * and write device registers connected on a standard bus. 467 * The driver keeps offering a default implementation based on function 468 * pointers to read/write routines for backward compatibility. 469 * The __weak directive allows the final application to overwrite 470 * them with a custom implementation. 471 */ 472 473 int32_t ilps28qsw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 474 uint8_t *data, uint16_t len); 475 int32_t ilps28qsw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 476 uint8_t *data, uint16_t len); 477 478 extern float_t ilps28qsw_from_fs1260_to_hPa(int32_t lsb); 479 extern float_t ilps28qsw_from_fs4060_to_hPa(int32_t lsb); 480 481 extern float_t ilps28qsw_from_lsb_to_celsius(int16_t lsb); 482 483 extern float_t ilps28qsw_from_lsb_to_mv(int32_t lsb); 484 485 typedef struct 486 { 487 uint8_t whoami; 488 } ilps28qsw_id_t; 489 int32_t ilps28qsw_id_get(const stmdev_ctx_t *ctx, ilps28qsw_id_t *val); 490 491 typedef enum 492 { 493 ILPS28QSW_AUTO = 0x00, /* anti-spike filters managed by protocol */ 494 ILPS28QSW_ALWAYS_ON = 0x01, /* anti-spike filters always on */ 495 } ilps28qsw_filter_t; 496 497 typedef enum 498 { 499 ILPS28QSW_BUS_AVB_TIME_50us = 0x00, /* bus available time equal to 50 us */ 500 ILPS28QSW_BUS_AVB_TIME_2us = 0x01, /* bus available time equal to 2 us */ 501 ILPS28QSW_BUS_AVB_TIME_1ms = 0x02, /* bus available time equal to 1 ms */ 502 ILPS28QSW_BUS_AVB_TIME_25ms = 0x03, /* bus available time equal to 25 ms */ 503 } ilps28qsw_bus_avb_time_t; 504 505 typedef struct 506 { 507 ilps28qsw_filter_t filter; 508 ilps28qsw_bus_avb_time_t bus_avb_time; 509 } ilps28qsw_bus_mode_t; 510 int32_t ilps28qsw_bus_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val); 511 int32_t ilps28qsw_bus_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val); 512 513 typedef enum 514 { 515 ILPS28QSW_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 516 ILPS28QSW_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 517 ILPS28QSW_RESET = 0x02, /* Reset configuration registers */ 518 } ilps28qsw_init_t; 519 int32_t ilps28qsw_init_set(const stmdev_ctx_t *ctx, ilps28qsw_init_t val); 520 521 typedef struct 522 { 523 uint8_t sw_reset : 1; /* Restoring configuration registers. */ 524 uint8_t boot : 1; /* Restoring calibration parameters. */ 525 uint8_t drdy_pres : 1; /* Pressure data ready. */ 526 uint8_t drdy_temp : 1; /* Temperature data ready. */ 527 uint8_t ovr_pres : 1; /* Pressure data overrun. */ 528 uint8_t ovr_temp : 1; /* Temperature data overrun. */ 529 uint8_t end_meas : 1; /* Single measurement is finished. */ 530 uint8_t ref_done : 1; /* Auto-Zero value is set. */ 531 } ilps28qsw_stat_t; 532 int32_t ilps28qsw_status_get(const stmdev_ctx_t *ctx, ilps28qsw_stat_t *val); 533 534 typedef struct 535 { 536 uint8_t sda_pull_up : 1; /* 1 = pull-up always disabled */ 537 } ilps28qsw_pin_conf_t; 538 int32_t ilps28qsw_pin_conf_set(const stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val); 539 int32_t ilps28qsw_pin_conf_get(const stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val); 540 541 typedef struct 542 { 543 uint8_t drdy_pres : 1; /* Pressure data ready */ 544 uint8_t drdy_temp : 1; /* Temperature data ready */ 545 uint8_t over_pres : 1; /* Over pressure event */ 546 uint8_t under_pres : 1; /* Under pressure event */ 547 uint8_t thrsld_pres : 1; /* Over/Under pressure event */ 548 uint8_t fifo_full : 1; /* FIFO full */ 549 uint8_t fifo_ovr : 1; /* FIFO overrun */ 550 uint8_t fifo_th : 1; /* FIFO threshold reached */ 551 } ilps28qsw_all_sources_t; 552 int32_t ilps28qsw_all_sources_get(const stmdev_ctx_t *ctx, 553 ilps28qsw_all_sources_t *val); 554 555 typedef enum 556 { 557 ILPS28QSW_1260hPa = 0x00, 558 ILPS28QSW_4060hPa = 0x01, 559 } ilps28qsw_fs_t; 560 561 typedef enum 562 { 563 ILPS28QSW_ONE_SHOT = 0x00, /* Device in power down till software trigger */ 564 ILPS28QSW_1Hz = 0x01, 565 ILPS28QSW_4Hz = 0x02, 566 ILPS28QSW_10Hz = 0x03, 567 ILPS28QSW_25Hz = 0x04, 568 ILPS28QSW_50Hz = 0x05, 569 ILPS28QSW_75Hz = 0x06, 570 ILPS28QSW_100Hz = 0x07, 571 ILPS28QSW_200Hz = 0x08, 572 } ilps28qsw_odr_t; 573 574 typedef enum 575 { 576 ILPS28QSW_4_AVG = 0, 577 ILPS28QSW_8_AVG = 1, 578 ILPS28QSW_16_AVG = 2, 579 ILPS28QSW_32_AVG = 3, 580 ILPS28QSW_64_AVG = 4, 581 ILPS28QSW_128_AVG = 5, 582 ILPS28QSW_256_AVG = 6, 583 ILPS28QSW_512_AVG = 7, 584 } ilps28qsw_avg_t; 585 586 typedef enum 587 { 588 ILPS28QSW_LPF_DISABLE = 0, 589 ILPS28QSW_LPF_ODR_DIV_4 = 1, 590 ILPS28QSW_LPF_ODR_DIV_9 = 3, 591 } ilps28qsw_lpf_t; 592 593 typedef struct 594 { 595 ilps28qsw_fs_t fs; 596 ilps28qsw_odr_t odr; 597 ilps28qsw_avg_t avg; 598 ilps28qsw_lpf_t lpf; 599 uint8_t interleaved_mode; 600 } ilps28qsw_md_t; 601 int32_t ilps28qsw_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_md_t *val); 602 int32_t ilps28qsw_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_md_t *val); 603 604 int32_t ilps28qsw_trigger_sw(const stmdev_ctx_t *ctx, ilps28qsw_md_t *md); 605 606 typedef struct 607 { 608 struct 609 { 610 float_t hpa; 611 int32_t raw; /* 32 bit signed-left algned format left */ 612 } pressure; 613 struct 614 { 615 float_t deg_c; 616 int16_t raw; 617 } heat; 618 struct 619 { 620 int32_t lsb; /* 24 bit properly right aligned */ 621 } ah_qvar; 622 } ilps28qsw_data_t; 623 int32_t ilps28qsw_data_get(const stmdev_ctx_t *ctx, ilps28qsw_md_t *md, 624 ilps28qsw_data_t *data); 625 626 int32_t ilps28qsw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); 627 int32_t ilps28qsw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); 628 629 typedef struct 630 { 631 float_t mv; /* value converted in mV */ 632 int32_t lsb; /* 24 bit properly right aligned */ 633 int32_t raw; /* 32 bit signed-left algned format left */ 634 } ilps28qsw_ah_qvar_data_t; 635 int32_t ilps28qsw_ah_qvar_data_get(const stmdev_ctx_t *ctx, 636 ilps28qsw_ah_qvar_data_t *data); 637 638 typedef enum 639 { 640 ILPS28QSW_BYPASS = 0, 641 ILPS28QSW_FIFO = 1, 642 ILPS28QSW_STREAM = 2, 643 ILPS28QSW_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ 644 ILPS28QSW_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ 645 ILPS28QSW_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ 646 } ilps28qsw_operation_t; 647 648 typedef struct 649 { 650 ilps28qsw_operation_t operation; 651 uint8_t watermark : 7; /* (0 disable) max 128.*/ 652 } ilps28qsw_fifo_md_t; 653 int32_t ilps28qsw_fifo_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); 654 int32_t ilps28qsw_fifo_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); 655 656 int32_t ilps28qsw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 657 658 typedef struct 659 { 660 float_t hpa; 661 int32_t lsb; /* 24 bit properly right aligned */ 662 int32_t raw; 663 } ilps28qsw_fifo_data_t; 664 int32_t ilps28qsw_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, 665 ilps28qsw_md_t *md, ilps28qsw_fifo_data_t *data); 666 667 typedef struct 668 { 669 uint8_t int_latched : 1; /* int events are: int on threshold, FIFO */ 670 } ilps28qsw_int_mode_t; 671 int32_t ilps28qsw_interrupt_mode_set(const stmdev_ctx_t *ctx, 672 ilps28qsw_int_mode_t *val); 673 int32_t ilps28qsw_interrupt_mode_get(const stmdev_ctx_t *ctx, 674 ilps28qsw_int_mode_t *val); 675 676 int32_t ilps28qsw_ah_qvar_disable(const stmdev_ctx_t *ctx); 677 int32_t ilps28qsw_ah_qvar_en_set(const stmdev_ctx_t *ctx, uint8_t val); 678 int32_t ilps28qsw_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 679 680 typedef struct 681 { 682 uint16_t threshold; /* Threshold in hPa * 16 (@1260hPa) 683 * Threshold in hPa * 8 (@4060hPa) 684 */ 685 uint8_t over_th : 1; /* Pressure data over threshold event */ 686 uint8_t under_th : 1; /* Pressure data under threshold event */ 687 } ilps28qsw_int_th_md_t; 688 int32_t ilps28qsw_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, 689 ilps28qsw_int_th_md_t *val); 690 int32_t ilps28qsw_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, 691 ilps28qsw_int_th_md_t *val); 692 693 typedef enum 694 { 695 ILPS28QSW_OUT_AND_INTERRUPT = 0, 696 ILPS28QSW_ONLY_INTERRUPT = 1, 697 ILPS28QSW_RST_REFS = 2, 698 } ilps28qsw_apply_ref_t; 699 700 typedef struct 701 { 702 ilps28qsw_apply_ref_t apply_ref; 703 uint8_t get_ref : 1; /* Use current pressure value as reference */ 704 } ilps28qsw_ref_md_t; 705 int32_t ilps28qsw_reference_mode_set(const stmdev_ctx_t *ctx, 706 ilps28qsw_ref_md_t *val); 707 int32_t ilps28qsw_reference_mode_get(const stmdev_ctx_t *ctx, 708 ilps28qsw_ref_md_t *val); 709 710 int32_t ilps28qsw_refp_get(const stmdev_ctx_t *ctx, int16_t *val); 711 712 int32_t ilps28qsw_opc_set(const stmdev_ctx_t *ctx, int16_t val); 713 int32_t ilps28qsw_opc_get(const stmdev_ctx_t *ctx, int16_t *val); 714 715 /** 716 *@} 717 * 718 */ 719 720 #ifdef __cplusplus 721 } 722 #endif 723 724 #endif /* ILPS28QSW_REGS_H */ 725 726 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 727
