1 /** 2 ****************************************************************************** 3 * @file ilps22qs_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * ilps22qs_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ILPS22QS_REGS_H 23 #define ILPS22QS_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ILPS22QS 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ILPS22QS_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format **/ 172 #define ILPS22QS_I2C_ADD 0xB9U 173 174 /** Device Identification (Who am I) **/ 175 #define ILPS22QS_ID 0xB4U 176 177 /** 178 * @} 179 * 180 */ 181 182 #define ILPS22QS_INTERRUPT_CFG 0x0BU 183 typedef struct 184 { 185 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 186 uint8_t phe : 1; 187 uint8_t ple : 1; 188 uint8_t lir : 1; 189 uint8_t not_used_01 : 1; 190 uint8_t reset_az : 1; 191 uint8_t autozero : 1; 192 uint8_t reset_arp : 1; 193 uint8_t autorefp : 1; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t autorefp : 1; 196 uint8_t reset_arp : 1; 197 uint8_t autozero : 1; 198 uint8_t reset_az : 1; 199 uint8_t not_used_01 : 1; 200 uint8_t lir : 1; 201 uint8_t ple : 1; 202 uint8_t phe : 1; 203 #endif /* DRV_BYTE_ORDER */ 204 } ilps22qs_interrupt_cfg_t; 205 206 #define ILPS22QS_THS_P_L 0x0CU 207 typedef struct 208 { 209 uint8_t ths : 8; 210 } ilps22qs_ths_p_l_t; 211 212 #define ILPS22QS_THS_P_H 0x0DU 213 typedef struct 214 { 215 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 216 uint8_t ths : 7; 217 uint8_t not_used_01 : 1; 218 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 219 uint8_t not_used_01 : 1; 220 uint8_t ths : 7; 221 #endif /* DRV_BYTE_ORDER */ 222 } ilps22qs_ths_p_h_t; 223 224 #define ILPS22QS_IF_CTRL 0x0EU 225 typedef struct 226 { 227 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 228 uint8_t not_used_01 : 1; 229 uint8_t cs_pu_dis : 1; 230 uint8_t not_used_02 : 2; 231 uint8_t sda_pu_en : 1; 232 uint8_t en_spi_read : 1; 233 uint8_t i2c_i3c_dis : 1; 234 uint8_t not_used_03 : 1; 235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 236 uint8_t not_used_03 : 1; 237 uint8_t i2c_i3c_dis : 1; 238 uint8_t en_spi_read : 1; 239 uint8_t sda_pu_en : 1; 240 uint8_t not_used_02 : 2; 241 uint8_t cs_pu_dis : 1; 242 uint8_t not_used_01 : 1; 243 #endif /* DRV_BYTE_ORDER */ 244 } ilps22qs_if_ctrl_t; 245 246 #define ILPS22QS_WHO_AM_I 0x0FU 247 #define ILPS22QS_CTRL_REG1 0x10U 248 typedef struct 249 { 250 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 251 uint8_t avg : 3; 252 uint8_t odr : 4; 253 uint8_t not_used_01 : 1; 254 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 255 uint8_t not_used_01 : 1; 256 uint8_t odr : 4; 257 uint8_t avg : 3; 258 #endif /* DRV_BYTE_ORDER */ 259 } ilps22qs_ctrl_reg1_t; 260 261 #define ILPS22QS_CTRL_REG2 0x11U 262 typedef struct 263 { 264 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 265 uint8_t oneshot : 1; 266 uint8_t not_used_01 : 1; 267 uint8_t swreset : 1; 268 uint8_t bdu : 1; 269 uint8_t en_lpfp : 1; 270 uint8_t lfpf_cfg : 1; 271 uint8_t fs_mode : 1; 272 uint8_t boot : 1; 273 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 274 uint8_t boot : 1; 275 uint8_t fs_mode : 1; 276 uint8_t lfpf_cfg : 1; 277 uint8_t en_lpfp : 1; 278 uint8_t bdu : 1; 279 uint8_t swreset : 1; 280 uint8_t not_used_01 : 1; 281 uint8_t oneshot : 1; 282 #endif /* DRV_BYTE_ORDER */ 283 } ilps22qs_ctrl_reg2_t; 284 285 #define ILPS22QS_CTRL_REG3 0x12U 286 typedef struct 287 { 288 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 289 uint8_t if_add_inc : 1; 290 uint8_t not_used_01 : 4; 291 uint8_t ah_qvar_p_auto_en: 1; 292 uint8_t not_used_02 : 1; 293 uint8_t ah_qvar_en : 1; 294 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 295 uint8_t ah_qvar_en : 1; 296 uint8_t not_used_02 : 1; 297 uint8_t ah_qvar_p_auto_en: 1; 298 uint8_t not_used_01 : 4; 299 uint8_t if_add_inc : 1; 300 #endif /* DRV_BYTE_ORDER */ 301 } ilps22qs_ctrl_reg3_t; 302 303 #define ILPS22QS_FIFO_CTRL 0x14U 304 typedef struct 305 { 306 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 307 uint8_t f_mode : 2; 308 uint8_t trig_modes : 1; 309 uint8_t stop_on_wtm : 1; 310 uint8_t ah_qvar_p_fifo_en: 1; 311 uint8_t not_used_01 : 3; 312 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 313 uint8_t not_used_01 : 3; 314 uint8_t ah_qvar_p_fifo_en: 1; 315 uint8_t stop_on_wtm : 1; 316 uint8_t trig_modes : 1; 317 uint8_t f_mode : 2; 318 #endif /* DRV_BYTE_ORDER */ 319 } ilps22qs_fifo_ctrl_t; 320 321 #define ILPS22QS_FIFO_WTM 0x15U 322 typedef struct 323 { 324 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 325 uint8_t wtm : 7; 326 uint8_t not_used_01 : 1; 327 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 328 uint8_t not_used_01 : 1; 329 uint8_t wtm : 7; 330 #endif /* DRV_BYTE_ORDER */ 331 } ilps22qs_fifo_wtm_t; 332 333 #define ILPS22QS_REF_P_L 0x16U 334 typedef struct 335 { 336 uint8_t refp : 8; 337 } ilps22qs_ref_p_l_t; 338 339 #define ILPS22QS_REF_P_H 0x17U 340 typedef struct 341 { 342 uint8_t refp : 8; 343 } ilps22qs_ref_p_h_t; 344 345 #define ILPS22QS_I3C_IF_CTRL 0x19U 346 typedef struct 347 { 348 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 349 uint8_t not_used_02 : 5; 350 uint8_t asf_on : 1; 351 uint8_t not_used_01 : 2; 352 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 353 uint8_t not_used_01 : 2; 354 uint8_t asf_on : 1; 355 uint8_t not_used_02 : 5; 356 #endif /* DRV_BYTE_ORDER */ 357 } ilps22qs_i3c_if_ctrl_t; 358 359 #define ILPS22QS_RPDS_L 0x1AU 360 #define ILPS22QS_RPDS_H 0x1BU 361 #define ILPS22QS_INT_SOURCE 0x24U 362 typedef struct 363 { 364 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 365 uint8_t ph : 1; 366 uint8_t pl : 1; 367 uint8_t ia : 1; 368 uint8_t not_used_01 : 4; 369 uint8_t boot_on : 1; 370 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 371 uint8_t boot_on : 1; 372 uint8_t not_used_01 : 4; 373 uint8_t ia : 1; 374 uint8_t pl : 1; 375 uint8_t ph : 1; 376 #endif /* DRV_BYTE_ORDER */ 377 } ilps22qs_int_source_t; 378 379 #define ILPS22QS_FIFO_STATUS1 0x25U 380 typedef struct 381 { 382 uint8_t fss : 8; 383 } ilps22qs_fifo_status1_t; 384 385 #define ILPS22QS_FIFO_STATUS2 0x26U 386 typedef struct 387 { 388 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 389 uint8_t not_used_01 : 5; 390 uint8_t fifo_full_ia : 1; 391 uint8_t fifo_ovr_ia : 1; 392 uint8_t fifo_wtm_ia : 1; 393 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 394 uint8_t fifo_wtm_ia : 1; 395 uint8_t fifo_ovr_ia : 1; 396 uint8_t fifo_full_ia : 1; 397 uint8_t not_used_01 : 5; 398 #endif /* DRV_BYTE_ORDER */ 399 } ilps22qs_fifo_status2_t; 400 401 #define ILPS22QS_STATUS 0x27U 402 typedef struct 403 { 404 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 405 uint8_t p_da : 1; 406 uint8_t t_da : 1; 407 uint8_t not_used_01 : 2; 408 uint8_t p_or : 1; 409 uint8_t t_or : 1; 410 uint8_t not_used_02 : 2; 411 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 412 uint8_t not_used_02 : 2; 413 uint8_t t_or : 1; 414 uint8_t p_or : 1; 415 uint8_t not_used_01 : 2; 416 uint8_t t_da : 1; 417 uint8_t p_da : 1; 418 #endif /* DRV_BYTE_ORDER */ 419 } ilps22qs_status_t; 420 421 #define ILPS22QS_PRESS_OUT_XL 0x28U 422 #define ILPS22QS_PRESS_OUT_L 0x29U 423 #define ILPS22QS_PRESS_OUT_H 0x2AU 424 #define ILPS22QS_TEMP_OUT_L 0x2BU 425 #define ILPS22QS_TEMP_OUT_H 0x2CU 426 #define ILPS22QS_ANALOGIC_HUB_DISABLE 0x5FU 427 #define ILPS22QS_FIFO_DATA_OUT_PRESS_XL 0x78U 428 #define ILPS22QS_FIFO_DATA_OUT_PRESS_L 0x79U 429 #define ILPS22QS_FIFO_DATA_OUT_PRESS_H 0x7AU 430 431 /** 432 * @defgroup ILPS22QS_Register_Union 433 * @brief This union group all the registers that has a bitfield 434 * description. 435 * This union is useful but not need by the driver. 436 * 437 * REMOVING this union you are compliant with: 438 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 439 * 440 * @{ 441 * 442 */ 443 444 typedef union 445 { 446 ilps22qs_interrupt_cfg_t interrupt_cfg; 447 ilps22qs_ths_p_l_t ths_p_l; 448 ilps22qs_ths_p_h_t ths_p_h; 449 ilps22qs_if_ctrl_t if_ctrl; 450 ilps22qs_ctrl_reg1_t ctrl_reg1; 451 ilps22qs_ctrl_reg2_t ctrl_reg2; 452 ilps22qs_ctrl_reg3_t ctrl_reg3; 453 ilps22qs_fifo_ctrl_t fifo_ctrl; 454 ilps22qs_fifo_wtm_t fifo_wtm; 455 ilps22qs_ref_p_l_t ref_p_l; 456 ilps22qs_ref_p_h_t ref_p_h; 457 ilps22qs_i3c_if_ctrl_t i3c_if_ctrl; 458 ilps22qs_int_source_t int_source; 459 ilps22qs_fifo_status1_t fifo_status1; 460 ilps22qs_fifo_status2_t fifo_status2; 461 ilps22qs_status_t status; 462 bitwise_t bitwise; 463 uint8_t byte; 464 } ilps22qs_reg_t; 465 466 #ifndef __weak 467 #define __weak __attribute__((weak)) 468 #endif /* __weak */ 469 470 /* 471 * These are the basic platform dependent I/O routines to read 472 * and write device registers connected on a standard bus. 473 * The driver keeps offering a default implementation based on function 474 * pointers to read/write routines for backward compatibility. 475 * The __weak directive allows the final application to overwrite 476 * them with a custom implementation. 477 */ 478 479 int32_t ilps22qs_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 480 uint8_t *data, uint16_t len); 481 int32_t ilps22qs_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 482 uint8_t *data, uint16_t len); 483 484 extern float_t ilps22qs_from_fs1260_to_hPa(int32_t lsb); 485 extern float_t ilps22qs_from_fs4000_to_hPa(int32_t lsb); 486 extern float_t ilps22qs_from_lsb_to_celsius(int16_t lsb); 487 extern float_t ilps22qs_from_lsb_to_mv(int32_t lsb); 488 489 typedef struct 490 { 491 uint8_t whoami; 492 } ilps22qs_id_t; 493 int32_t ilps22qs_id_get(const stmdev_ctx_t *ctx, ilps22qs_id_t *val); 494 495 typedef enum 496 { 497 ILPS22QS_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 498 ILPS22QS_SPI_3W = 0x03, /* Only SPI: SDO / SDI share the same pin */ 499 } ilps22qs_interface_t; 500 501 typedef enum 502 { 503 ILPS22QS_FILTER_AUTO = 0x00, /* Disable anti-spike filters */ 504 ILPS22QS_FILTER_ALWAYS_ON = 0x01, /* Enable anti-spike filters */ 505 } ilps22qs_filter_t; 506 507 typedef struct 508 { 509 ilps22qs_interface_t interface; 510 ilps22qs_filter_t filter; 511 } ilps22qs_bus_mode_t; 512 int32_t ilps22qs_bus_mode_set(const stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val); 513 int32_t ilps22qs_bus_mode_get(const stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val); 514 515 typedef enum 516 { 517 ILPS22QS_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 518 ILPS22QS_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 519 ILPS22QS_RESET = 0x02, /* Reset configuration registers */ 520 } ilps22qs_init_t; 521 int32_t ilps22qs_init_set(const stmdev_ctx_t *ctx, ilps22qs_init_t val); 522 523 typedef struct 524 { 525 uint8_t sw_reset : 1; /* Restoring configuration registers. */ 526 uint8_t boot : 1; /* Restoring calibration parameters. */ 527 uint8_t drdy_pres : 1; /* Pressure data ready. */ 528 uint8_t drdy_temp : 1; /* Temperature data ready. */ 529 uint8_t ovr_pres : 1; /* Pressure data overrun. */ 530 uint8_t ovr_temp : 1; /* Temperature data overrun. */ 531 uint8_t end_meas : 1; /* Single measurement is finished. */ 532 uint8_t ref_done : 1; /* Auto-Zero value is set. */ 533 } ilps22qs_stat_t; 534 int32_t ilps22qs_status_get(const stmdev_ctx_t *ctx, ilps22qs_stat_t *val); 535 536 typedef struct 537 { 538 uint8_t sda_pull_up : 1; /* 1 = pull-up enabled */ 539 uint8_t cs_pull_up : 1; /* 1 = pull-up enabled */ 540 } ilps22qs_pin_conf_t; 541 int32_t ilps22qs_pin_conf_set(const stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val); 542 int32_t ilps22qs_pin_conf_get(const stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val); 543 544 typedef struct 545 { 546 uint8_t drdy_pres : 1; /* Pressure data ready */ 547 uint8_t drdy_temp : 1; /* Temperature data ready */ 548 uint8_t over_pres : 1; /* Over pressure event */ 549 uint8_t under_pres : 1; /* Under pressure event */ 550 uint8_t thrsld_pres : 1; /* Over/Under pressure event */ 551 uint8_t fifo_full : 1; /* FIFO full */ 552 uint8_t fifo_ovr : 1; /* FIFO overrun */ 553 uint8_t fifo_th : 1; /* FIFO threshold reached */ 554 } ilps22qs_all_sources_t; 555 int32_t ilps22qs_all_sources_get(const stmdev_ctx_t *ctx, ilps22qs_all_sources_t *val); 556 557 typedef enum 558 { 559 ILPS22QS_1260hPa = 0x00, 560 ILPS22QS_4060hPa = 0x01, 561 } ilps22qs_fs_t; 562 563 typedef enum 564 { 565 ILPS22QS_ONE_SHOT = 0x00, /* Device in power down till software trigger */ 566 ILPS22QS_1Hz = 0x01, 567 ILPS22QS_4Hz = 0x02, 568 ILPS22QS_10Hz = 0x03, 569 ILPS22QS_25Hz = 0x04, 570 ILPS22QS_50Hz = 0x05, 571 ILPS22QS_75Hz = 0x06, 572 ILPS22QS_100Hz = 0x07, 573 ILPS22QS_200Hz = 0x08, 574 } ilps22qs_odr_t; 575 576 typedef enum 577 { 578 ILPS22QS_4_AVG = 0, 579 ILPS22QS_8_AVG = 1, 580 ILPS22QS_16_AVG = 2, 581 ILPS22QS_32_AVG = 3, 582 ILPS22QS_64_AVG = 4, 583 ILPS22QS_128_AVG = 5, 584 ILPS22QS_256_AVG = 6, 585 ILPS22QS_512_AVG = 7, 586 } ilps22qs_avg_t; 587 588 typedef enum 589 { 590 ILPS22QS_LPF_DISABLE = 0, 591 ILPS22QS_LPF_ODR_DIV_4 = 1, 592 ILPS22QS_LPF_ODR_DIV_9 = 3, 593 } ilps22qs_lpf_t; 594 595 typedef struct 596 { 597 uint8_t interleaved_mode; 598 ilps22qs_fs_t fs; 599 ilps22qs_odr_t odr; 600 ilps22qs_avg_t avg; 601 ilps22qs_lpf_t lpf; 602 } ilps22qs_md_t; 603 int32_t ilps22qs_mode_set(const stmdev_ctx_t *ctx, ilps22qs_md_t *val); 604 int32_t ilps22qs_mode_get(const stmdev_ctx_t *ctx, ilps22qs_md_t *val); 605 606 int32_t ilps22qs_trigger_sw(const stmdev_ctx_t *ctx, ilps22qs_md_t *md); 607 608 typedef struct 609 { 610 struct 611 { 612 float_t hpa; 613 int32_t raw; /* 32 bit signed-left algned format left */ 614 } pressure; 615 struct 616 { 617 float_t deg_c; 618 int16_t raw; 619 } heat; 620 struct 621 { 622 int32_t lsb; /* 24 bit properly right aligned */ 623 } ah_qvar; 624 } ilps22qs_data_t; 625 int32_t ilps22qs_data_get(const stmdev_ctx_t *ctx, ilps22qs_md_t *md, 626 ilps22qs_data_t *data); 627 628 int32_t ilps22qs_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff); 629 int32_t ilps22qs_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff); 630 631 typedef struct 632 { 633 float_t mv; /* value converted in mV */ 634 int32_t lsb; /* 24 bit properly right aligned */ 635 int32_t raw; /* 32 bit signed-left algned format left */ 636 } ilps22qs_ah_qvar_data_t; 637 int32_t ilps22qs_ah_qvar_data_get(const stmdev_ctx_t *ctx, 638 ilps22qs_ah_qvar_data_t *data); 639 640 typedef enum 641 { 642 ILPS22QS_BYPASS = 0, 643 ILPS22QS_FIFO = 1, 644 ILPS22QS_STREAM = 2, 645 ILPS22QS_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ 646 ILPS22QS_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ 647 ILPS22QS_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ 648 } ilps22qs_operation_t; 649 650 typedef struct 651 { 652 ilps22qs_operation_t operation; 653 uint8_t watermark : 7; /* (0 disable) max 128.*/ 654 } ilps22qs_fifo_md_t; 655 int32_t ilps22qs_fifo_mode_set(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val); 656 int32_t ilps22qs_fifo_mode_get(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val); 657 658 int32_t ilps22qs_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 659 660 typedef struct 661 { 662 float_t hpa; 663 int32_t lsb; /* 24 bit properly right aligned */ 664 int32_t raw; 665 } ilps22qs_fifo_data_t; 666 int32_t ilps22qs_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp, 667 ilps22qs_md_t *md, ilps22qs_fifo_data_t *data); 668 669 typedef struct 670 { 671 uint8_t int_latched : 1; /* int events are: int on threshold, FIFO */ 672 } ilps22qs_int_mode_t; 673 int32_t ilps22qs_interrupt_mode_set(const stmdev_ctx_t *ctx, ilps22qs_int_mode_t *val); 674 int32_t ilps22qs_interrupt_mode_get(const stmdev_ctx_t *ctx, ilps22qs_int_mode_t *val); 675 676 int32_t ilps22qs_ah_qvar_disable(const stmdev_ctx_t *ctx); 677 int32_t ilps22qs_ah_qvar_en_set(const stmdev_ctx_t *ctx, uint8_t val); 678 int32_t ilps22qs_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 679 680 typedef struct 681 { 682 uint16_t threshold; /* Threshold in hPa * 16 (@1260hPa) 683 * Threshold in hPa * 8 (@4060hPa) 684 */ 685 uint8_t over_th : 1; /* Pressure data over threshold event */ 686 uint8_t under_th : 1; /* Pressure data under threshold event */ 687 } ilps22qs_int_th_md_t; 688 int32_t ilps22qs_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, 689 ilps22qs_int_th_md_t *val); 690 int32_t ilps22qs_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, 691 ilps22qs_int_th_md_t *val); 692 693 typedef enum 694 { 695 ILPS22QS_OUT_AND_INTERRUPT = 0, 696 ILPS22QS_ONLY_INTERRUPT = 1, 697 ILPS22QS_RST_REFS = 2, 698 } ilps22qs_apply_ref_t; 699 700 typedef struct 701 { 702 ilps22qs_apply_ref_t apply_ref; 703 uint8_t get_ref : 1; /* Use current pressure value as reference */ 704 } ilps22qs_ref_md_t; 705 int32_t ilps22qs_reference_mode_set(const stmdev_ctx_t *ctx, 706 ilps22qs_ref_md_t *val); 707 int32_t ilps22qs_reference_mode_get(const stmdev_ctx_t *ctx, 708 ilps22qs_ref_md_t *val); 709 710 int32_t ilps22qs_opc_set(const stmdev_ctx_t *ctx, int16_t val); 711 int32_t ilps22qs_opc_get(const stmdev_ctx_t *ctx, int16_t *val); 712 713 /** 714 *@} 715 * 716 */ 717 718 #ifdef __cplusplus 719 } 720 #endif 721 722 #endif /* ILPS22QS_REGS_H */ 723 724 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 725
