1 /** 2 ****************************************************************************** 3 * @file iis328dq_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * iis328dq_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef IIS328DQ_REGS_H 23 #define IIS328DQ_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup IIS328DQ 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 167 /** @defgroup IIS328DQ_Infos 168 * @{ 169 * 170 */ 171 172 /** I2C Device Address 8 bit format if SA0=0 -> 0x31 if SA0=1 -> 0x33 **/ 173 #define IIS328DQ_I2C_ADD_L 0x31 174 #define IIS328DQ_I2C_ADD_H 0x33 175 176 /** Device Identification (Who am I) **/ 177 #define IIS328DQ_ID 0x32 178 179 /** 180 * @} 181 * 182 */ 183 184 #define IIS328DQ_WHO_AM_I 0x0FU 185 #define IIS328DQ_CTRL_REG1 0x20U 186 typedef struct 187 { 188 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 189 uint8_t xen : 1; 190 uint8_t yen : 1; 191 uint8_t zen : 1; 192 uint8_t dr : 2; 193 uint8_t pm : 3; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t pm : 3; 196 uint8_t dr : 2; 197 uint8_t zen : 1; 198 uint8_t yen : 1; 199 uint8_t xen : 1; 200 #endif /* DRV_BYTE_ORDER */ 201 } iis328dq_ctrl_reg1_t; 202 203 #define IIS328DQ_CTRL_REG2 0x21U 204 typedef struct 205 { 206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 207 uint8_t hpcf : 2; 208 uint8_t hpen : 2; 209 uint8_t fds : 1; 210 uint8_t hpm : 2; 211 uint8_t boot : 1; 212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 213 uint8_t boot : 1; 214 uint8_t hpm : 2; 215 uint8_t fds : 1; 216 uint8_t hpen : 2; 217 uint8_t hpcf : 2; 218 #endif /* DRV_BYTE_ORDER */ 219 } iis328dq_ctrl_reg2_t; 220 221 #define IIS328DQ_CTRL_REG3 0x22U 222 typedef struct 223 { 224 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 225 uint8_t i1_cfg : 2; 226 uint8_t lir1 : 1; 227 uint8_t i2_cfg : 2; 228 uint8_t lir2 : 1; 229 uint8_t pp_od : 1; 230 uint8_t ihl : 1; 231 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 232 uint8_t ihl : 1; 233 uint8_t pp_od : 1; 234 uint8_t lir2 : 1; 235 uint8_t i2_cfg : 2; 236 uint8_t lir1 : 1; 237 uint8_t i1_cfg : 2; 238 #endif /* DRV_BYTE_ORDER */ 239 } iis328dq_ctrl_reg3_t; 240 241 #define IIS328DQ_CTRL_REG4 0x23U 242 typedef struct 243 { 244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 245 uint8_t sim : 1; 246 uint8_t st : 3; /* STsign + ST */ 247 uint8_t fs : 2; 248 uint8_t ble : 1; 249 uint8_t bdu : 1; 250 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 251 uint8_t bdu : 1; 252 uint8_t ble : 1; 253 uint8_t fs : 2; 254 uint8_t st : 3; /* STsign + ST */ 255 uint8_t sim : 1; 256 #endif /* DRV_BYTE_ORDER */ 257 } iis328dq_ctrl_reg4_t; 258 259 #define IIS328DQ_CTRL_REG5 0x24U 260 typedef struct 261 { 262 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 263 uint8_t turnon : 2; 264 uint8_t not_used_01 : 6; 265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 266 uint8_t not_used_01 : 6; 267 uint8_t turnon : 2; 268 #endif /* DRV_BYTE_ORDER */ 269 } iis328dq_ctrl_reg5_t; 270 271 #define IIS328DQ_HP_FILTER_RESET 0x25U 272 #define IIS328DQ_REFERENCE 0x26U 273 #define IIS328DQ_STATUS_REG 0x27U 274 typedef struct 275 { 276 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 277 uint8_t xda : 1; 278 uint8_t yda : 1; 279 uint8_t zda : 1; 280 uint8_t zyxda : 1; 281 uint8_t _xor : 1; 282 uint8_t yor : 1; 283 uint8_t zor : 1; 284 uint8_t zyxor : 1; 285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 286 uint8_t zyxor : 1; 287 uint8_t zor : 1; 288 uint8_t yor : 1; 289 uint8_t _xor : 1; 290 uint8_t zyxda : 1; 291 uint8_t zda : 1; 292 uint8_t yda : 1; 293 uint8_t xda : 1; 294 #endif /* DRV_BYTE_ORDER */ 295 } iis328dq_status_reg_t; 296 297 #define IIS328DQ_OUT_X_L 0x28U 298 #define IIS328DQ_OUT_X_H 0x29U 299 #define IIS328DQ_OUT_Y_L 0x2AU 300 #define IIS328DQ_OUT_Y_H 0x2BU 301 #define IIS328DQ_OUT_Z_L 0x2CU 302 #define IIS328DQ_OUT_Z_H 0x2DU 303 #define IIS328DQ_INT1_CFG 0x30U 304 typedef struct 305 { 306 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 307 uint8_t xlie : 1; 308 uint8_t xhie : 1; 309 uint8_t ylie : 1; 310 uint8_t yhie : 1; 311 uint8_t zlie : 1; 312 uint8_t zhie : 1; 313 uint8_t _6d : 1; 314 uint8_t aoi : 1; 315 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 316 uint8_t aoi : 1; 317 uint8_t _6d : 1; 318 uint8_t zhie : 1; 319 uint8_t zlie : 1; 320 uint8_t yhie : 1; 321 uint8_t ylie : 1; 322 uint8_t xhie : 1; 323 uint8_t xlie : 1; 324 #endif /* DRV_BYTE_ORDER */ 325 } iis328dq_int1_cfg_t; 326 327 #define IIS328DQ_INT1_SRC 0x31U 328 typedef struct 329 { 330 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 331 uint8_t xl : 1; 332 uint8_t xh : 1; 333 uint8_t yl : 1; 334 uint8_t yh : 1; 335 uint8_t zl : 1; 336 uint8_t zh : 1; 337 uint8_t ia : 1; 338 uint8_t not_used_01 : 1; 339 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 340 uint8_t not_used_01 : 1; 341 uint8_t ia : 1; 342 uint8_t zh : 1; 343 uint8_t zl : 1; 344 uint8_t yh : 1; 345 uint8_t yl : 1; 346 uint8_t xh : 1; 347 uint8_t xl : 1; 348 #endif /* DRV_BYTE_ORDER */ 349 } iis328dq_int1_src_t; 350 351 #define IIS328DQ_INT1_THS 0x32U 352 typedef struct 353 { 354 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 355 uint8_t ths : 7; 356 uint8_t not_used_01 : 1; 357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 358 uint8_t not_used_01 : 1; 359 uint8_t ths : 7; 360 #endif /* DRV_BYTE_ORDER */ 361 } iis328dq_int1_ths_t; 362 363 #define IIS328DQ_INT1_DURATION 0x33U 364 typedef struct 365 { 366 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 367 uint8_t d : 7; 368 uint8_t not_used_01 : 1; 369 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 370 uint8_t not_used_01 : 1; 371 uint8_t d : 7; 372 #endif /* DRV_BYTE_ORDER */ 373 } iis328dq_int1_duration_t; 374 375 #define IIS328DQ_INT2_CFG 0x34U 376 typedef struct 377 { 378 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 379 uint8_t xlie : 1; 380 uint8_t xhie : 1; 381 uint8_t ylie : 1; 382 uint8_t yhie : 1; 383 uint8_t zlie : 1; 384 uint8_t zhie : 1; 385 uint8_t _6d : 1; 386 uint8_t aoi : 1; 387 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 388 uint8_t aoi : 1; 389 uint8_t _6d : 1; 390 uint8_t zhie : 1; 391 uint8_t zlie : 1; 392 uint8_t yhie : 1; 393 uint8_t ylie : 1; 394 uint8_t xhie : 1; 395 uint8_t xlie : 1; 396 #endif /* DRV_BYTE_ORDER */ 397 } iis328dq_int2_cfg_t; 398 399 #define IIS328DQ_INT2_SRC 0x35U 400 typedef struct 401 { 402 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 403 uint8_t xl : 1; 404 uint8_t xh : 1; 405 uint8_t yl : 1; 406 uint8_t yh : 1; 407 uint8_t zl : 1; 408 uint8_t zh : 1; 409 uint8_t ia : 1; 410 uint8_t not_used_01 : 1; 411 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 412 uint8_t not_used_01 : 1; 413 uint8_t ia : 1; 414 uint8_t zh : 1; 415 uint8_t zl : 1; 416 uint8_t yh : 1; 417 uint8_t yl : 1; 418 uint8_t xh : 1; 419 uint8_t xl : 1; 420 #endif /* DRV_BYTE_ORDER */ 421 } iis328dq_int2_src_t; 422 423 #define IIS328DQ_INT2_THS 0x36U 424 typedef struct 425 { 426 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 427 uint8_t ths : 7; 428 uint8_t not_used_01 : 1; 429 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 430 uint8_t not_used_01 : 1; 431 uint8_t ths : 7; 432 #endif /* DRV_BYTE_ORDER */ 433 } iis328dq_int2_ths_t; 434 435 #define IIS328DQ_INT2_DURATION 0x37U 436 typedef struct 437 { 438 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 439 uint8_t d : 7; 440 uint8_t not_used_01 : 1; 441 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 442 uint8_t not_used_01 : 1; 443 uint8_t d : 7; 444 #endif /* DRV_BYTE_ORDER */ 445 } iis328dq_int2_duration_t; 446 447 /** 448 * @defgroup IIS328DQ_Register_Union 449 * @brief This union group all the registers having a bit-field 450 * description. 451 * This union is useful but it's not needed by the driver. 452 * 453 * REMOVING this union you are compliant with: 454 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 455 * 456 * @{ 457 * 458 */ 459 typedef union 460 { 461 iis328dq_ctrl_reg1_t ctrl_reg1; 462 iis328dq_ctrl_reg2_t ctrl_reg2; 463 iis328dq_ctrl_reg3_t ctrl_reg3; 464 iis328dq_ctrl_reg4_t ctrl_reg4; 465 iis328dq_ctrl_reg5_t ctrl_reg5; 466 iis328dq_status_reg_t status_reg; 467 iis328dq_int1_cfg_t int1_cfg; 468 iis328dq_int1_src_t int1_src; 469 iis328dq_int1_ths_t int1_ths; 470 iis328dq_int1_duration_t int1_duration; 471 iis328dq_int2_cfg_t int2_cfg; 472 iis328dq_int2_src_t int2_src; 473 iis328dq_int2_ths_t int2_ths; 474 iis328dq_int2_duration_t int2_duration; 475 bitwise_t bitwise; 476 uint8_t byte; 477 } iis328dq_reg_t; 478 479 /** 480 * @} 481 * 482 */ 483 484 #ifndef __weak 485 #define __weak __attribute__((weak)) 486 #endif /* __weak */ 487 488 /* 489 * These are the basic platform dependent I/O routines to read 490 * and write device registers connected on a standard bus. 491 * The driver keeps offering a default implementation based on function 492 * pointers to read/write routines for backward compatibility. 493 * The __weak directive allows the final application to overwrite 494 * them with a custom implementation. 495 */ 496 497 int32_t iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 498 uint8_t *data, 499 uint16_t len); 500 int32_t iis328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 501 uint8_t *data, 502 uint16_t len); 503 504 float_t iis328dq_from_fs2_to_mg(int16_t lsb); 505 float_t iis328dq_from_fs4_to_mg(int16_t lsb); 506 float_t iis328dq_from_fs8_to_mg(int16_t lsb); 507 508 int32_t iis328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); 509 int32_t iis328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); 510 511 int32_t iis328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); 512 int32_t iis328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); 513 514 int32_t iis328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); 515 int32_t iis328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); 516 517 typedef enum 518 { 519 IIS328DQ_ODR_OFF = 0x00, 520 IIS328DQ_ODR_Hz5 = 0x02, 521 IIS328DQ_ODR_1Hz = 0x03, 522 IIS328DQ_ODR_5Hz2 = 0x04, 523 IIS328DQ_ODR_5Hz = 0x05, 524 IIS328DQ_ODR_10Hz = 0x06, 525 IIS328DQ_ODR_50Hz = 0x01, 526 IIS328DQ_ODR_100Hz = 0x11, 527 IIS328DQ_ODR_400Hz = 0x21, 528 IIS328DQ_ODR_1kHz = 0x31, 529 } iis328dq_dr_t; 530 int32_t iis328dq_data_rate_set(stmdev_ctx_t *ctx, iis328dq_dr_t val); 531 int32_t iis328dq_data_rate_get(stmdev_ctx_t *ctx, iis328dq_dr_t *val); 532 533 typedef enum 534 { 535 IIS328DQ_NORMAL_MODE = 0, 536 IIS328DQ_REF_MODE_ENABLE = 1, 537 } iis328dq_hpm_t; 538 int32_t iis328dq_reference_mode_set(stmdev_ctx_t *ctx, 539 iis328dq_hpm_t val); 540 int32_t iis328dq_reference_mode_get(stmdev_ctx_t *ctx, 541 iis328dq_hpm_t *val); 542 543 typedef enum 544 { 545 IIS328DQ_2g = 0, 546 IIS328DQ_4g = 1, 547 IIS328DQ_8g = 3, 548 } iis328dq_fs_t; 549 int32_t iis328dq_full_scale_set(stmdev_ctx_t *ctx, iis328dq_fs_t val); 550 int32_t iis328dq_full_scale_get(stmdev_ctx_t *ctx, 551 iis328dq_fs_t *val); 552 553 int32_t iis328dq_block_data_update_set(stmdev_ctx_t *ctx, 554 uint8_t val); 555 int32_t iis328dq_block_data_update_get(stmdev_ctx_t *ctx, 556 uint8_t *val); 557 558 int32_t iis328dq_status_reg_get(stmdev_ctx_t *ctx, 559 iis328dq_status_reg_t *val); 560 561 int32_t iis328dq_flag_data_ready_get(stmdev_ctx_t *ctx, 562 uint8_t *val); 563 564 int32_t iis328dq_acceleration_raw_get(stmdev_ctx_t *ctx, 565 int16_t *val); 566 567 int32_t iis328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 568 569 int32_t iis328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val); 570 int32_t iis328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 571 572 typedef enum 573 { 574 IIS328DQ_ST_DISABLE = 0, 575 IIS328DQ_ST_POSITIVE = 1, 576 IIS328DQ_ST_NEGATIVE = 5, 577 } iis328dq_st_t; 578 int32_t iis328dq_self_test_set(stmdev_ctx_t *ctx, iis328dq_st_t val); 579 int32_t iis328dq_self_test_get(stmdev_ctx_t *ctx, iis328dq_st_t *val); 580 581 typedef enum 582 { 583 IIS328DQ_LSB_AT_LOW_ADD = 0, 584 IIS328DQ_MSB_AT_LOW_ADD = 1, 585 } iis328dq_ble_t; 586 int32_t iis328dq_data_format_set(stmdev_ctx_t *ctx, 587 iis328dq_ble_t val); 588 int32_t iis328dq_data_format_get(stmdev_ctx_t *ctx, 589 iis328dq_ble_t *val); 590 591 typedef enum 592 { 593 IIS328DQ_CUT_OFF_8Hz = 0, 594 IIS328DQ_CUT_OFF_16Hz = 1, 595 IIS328DQ_CUT_OFF_32Hz = 2, 596 IIS328DQ_CUT_OFF_64Hz = 3, 597 } iis328dq_hpcf_t; 598 int32_t iis328dq_hp_bandwidth_set(stmdev_ctx_t *ctx, 599 iis328dq_hpcf_t val); 600 int32_t iis328dq_hp_bandwidth_get(stmdev_ctx_t *ctx, 601 iis328dq_hpcf_t *val); 602 603 typedef enum 604 { 605 IIS328DQ_HP_DISABLE = 0, 606 IIS328DQ_HP_ON_OUT = 4, 607 IIS328DQ_HP_ON_INT1 = 1, 608 IIS328DQ_HP_ON_INT2 = 2, 609 IIS328DQ_HP_ON_INT1_INT2 = 3, 610 IIS328DQ_HP_ON_INT1_INT2_OUT = 7, 611 IIS328DQ_HP_ON_INT2_OUT = 6, 612 IIS328DQ_HP_ON_INT1_OUT = 5, 613 } iis328dq_hpen_t; 614 int32_t iis328dq_hp_path_set(stmdev_ctx_t *ctx, iis328dq_hpen_t val); 615 int32_t iis328dq_hp_path_get(stmdev_ctx_t *ctx, iis328dq_hpen_t *val); 616 617 int32_t iis328dq_hp_reset_get(stmdev_ctx_t *ctx); 618 619 int32_t iis328dq_hp_reference_value_set(stmdev_ctx_t *ctx, 620 uint8_t val); 621 int32_t iis328dq_hp_reference_value_get(stmdev_ctx_t *ctx, 622 uint8_t *val); 623 624 typedef enum 625 { 626 IIS328DQ_SPI_4_WIRE = 0, 627 IIS328DQ_SPI_3_WIRE = 1, 628 } iis328dq_sim_t; 629 int32_t iis328dq_spi_mode_set(stmdev_ctx_t *ctx, iis328dq_sim_t val); 630 int32_t iis328dq_spi_mode_get(stmdev_ctx_t *ctx, iis328dq_sim_t *val); 631 632 typedef enum 633 { 634 IIS328DQ_PAD1_INT1_SRC = 0, 635 IIS328DQ_PAD1_INT1_OR_INT2_SRC = 1, 636 IIS328DQ_PAD1_DRDY = 2, 637 IIS328DQ_PAD1_BOOT = 3, 638 } iis328dq_i1_cfg_t; 639 int32_t iis328dq_pin_int1_route_set(stmdev_ctx_t *ctx, 640 iis328dq_i1_cfg_t val); 641 int32_t iis328dq_pin_int1_route_get(stmdev_ctx_t *ctx, 642 iis328dq_i1_cfg_t *val); 643 644 typedef enum 645 { 646 IIS328DQ_INT1_PULSED = 0, 647 IIS328DQ_INT1_LATCHED = 1, 648 } iis328dq_lir1_t; 649 int32_t iis328dq_int1_notification_set(stmdev_ctx_t *ctx, 650 iis328dq_lir1_t val); 651 int32_t iis328dq_int1_notification_get(stmdev_ctx_t *ctx, 652 iis328dq_lir1_t *val); 653 654 typedef enum 655 { 656 IIS328DQ_PAD2_INT2_SRC = 0, 657 IIS328DQ_PAD2_INT1_OR_INT2_SRC = 1, 658 IIS328DQ_PAD2_DRDY = 2, 659 IIS328DQ_PAD2_BOOT = 3, 660 } iis328dq_i2_cfg_t; 661 int32_t iis328dq_pin_int2_route_set(stmdev_ctx_t *ctx, 662 iis328dq_i2_cfg_t val); 663 int32_t iis328dq_pin_int2_route_get(stmdev_ctx_t *ctx, 664 iis328dq_i2_cfg_t *val); 665 666 typedef enum 667 { 668 IIS328DQ_INT2_PULSED = 0, 669 IIS328DQ_INT2_LATCHED = 1, 670 } iis328dq_lir2_t; 671 int32_t iis328dq_int2_notification_set(stmdev_ctx_t *ctx, 672 iis328dq_lir2_t val); 673 int32_t iis328dq_int2_notification_get(stmdev_ctx_t *ctx, 674 iis328dq_lir2_t *val); 675 676 typedef enum 677 { 678 IIS328DQ_PUSH_PULL = 0, 679 IIS328DQ_OPEN_DRAIN = 1, 680 } iis328dq_pp_od_t; 681 int32_t iis328dq_pin_mode_set(stmdev_ctx_t *ctx, 682 iis328dq_pp_od_t val); 683 int32_t iis328dq_pin_mode_get(stmdev_ctx_t *ctx, 684 iis328dq_pp_od_t *val); 685 686 typedef enum 687 { 688 IIS328DQ_ACTIVE_HIGH = 0, 689 IIS328DQ_ACTIVE_LOW = 1, 690 } iis328dq_ihl_t; 691 int32_t iis328dq_pin_polarity_set(stmdev_ctx_t *ctx, 692 iis328dq_ihl_t val); 693 int32_t iis328dq_pin_polarity_get(stmdev_ctx_t *ctx, 694 iis328dq_ihl_t *val); 695 696 typedef struct 697 { 698 uint8_t int1_xlie : 1; 699 uint8_t int1_xhie : 1; 700 uint8_t int1_ylie : 1; 701 uint8_t int1_yhie : 1; 702 uint8_t int1_zlie : 1; 703 uint8_t int1_zhie : 1; 704 } int1_on_th_conf_t; 705 int32_t iis328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx, 706 int1_on_th_conf_t val); 707 int32_t iis328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx, 708 int1_on_th_conf_t *val); 709 710 typedef enum 711 { 712 IIS328DQ_INT1_ON_THRESHOLD_OR = 0, 713 IIS328DQ_INT1_ON_THRESHOLD_AND = 1, 714 } iis328dq_int1_aoi_t; 715 int32_t iis328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx, 716 iis328dq_int1_aoi_t val); 717 int32_t iis328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx, 718 iis328dq_int1_aoi_t *val); 719 720 int32_t iis328dq_int1_src_get(stmdev_ctx_t *ctx, 721 iis328dq_int1_src_t *val); 722 723 int32_t iis328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val); 724 int32_t iis328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); 725 726 int32_t iis328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val); 727 int32_t iis328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 728 729 typedef struct 730 { 731 uint8_t int2_xlie : 1; 732 uint8_t int2_xhie : 1; 733 uint8_t int2_ylie : 1; 734 uint8_t int2_yhie : 1; 735 uint8_t int2_zlie : 1; 736 uint8_t int2_zhie : 1; 737 } int2_on_th_conf_t; 738 int32_t iis328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx, 739 int2_on_th_conf_t val); 740 int32_t iis328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx, 741 int2_on_th_conf_t *val); 742 743 typedef enum 744 { 745 IIS328DQ_INT2_ON_THRESHOLD_OR = 0, 746 IIS328DQ_INT2_ON_THRESHOLD_AND = 1, 747 } iis328dq_int2_aoi_t; 748 int32_t iis328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx, 749 iis328dq_int2_aoi_t val); 750 int32_t iis328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx, 751 iis328dq_int2_aoi_t *val); 752 753 int32_t iis328dq_int2_src_get(stmdev_ctx_t *ctx, 754 iis328dq_int2_src_t *val); 755 756 int32_t iis328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val); 757 int32_t iis328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val); 758 759 int32_t iis328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val); 760 int32_t iis328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 761 762 int32_t iis328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val); 763 int32_t iis328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val); 764 765 typedef enum 766 { 767 IIS328DQ_6D_INT1_DISABLE = 0, 768 IIS328DQ_6D_INT1_MOVEMENT = 1, 769 IIS328DQ_6D_INT1_POSITION = 3, 770 } iis328dq_int1_6d_t; 771 int32_t iis328dq_int1_6d_mode_set(stmdev_ctx_t *ctx, 772 iis328dq_int1_6d_t val); 773 int32_t iis328dq_int1_6d_mode_get(stmdev_ctx_t *ctx, 774 iis328dq_int1_6d_t *val); 775 776 int32_t iis328dq_int1_6d_src_get(stmdev_ctx_t *ctx, 777 iis328dq_int1_src_t *val); 778 779 int32_t iis328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val); 780 int32_t iis328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, 781 uint8_t *val); 782 783 typedef enum 784 { 785 IIS328DQ_6D_INT2_DISABLE = 0, 786 IIS328DQ_6D_INT2_MOVEMENT = 1, 787 IIS328DQ_6D_INT2_POSITION = 3, 788 } iis328dq_int2_6d_t; 789 int32_t iis328dq_int2_6d_mode_set(stmdev_ctx_t *ctx, 790 iis328dq_int2_6d_t val); 791 int32_t iis328dq_int2_6d_mode_get(stmdev_ctx_t *ctx, 792 iis328dq_int2_6d_t *val); 793 794 int32_t iis328dq_int2_6d_src_get(stmdev_ctx_t *ctx, 795 iis328dq_int2_src_t *val); 796 797 int32_t iis328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val); 798 int32_t iis328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, 799 uint8_t *val); 800 801 /** 802 *@} 803 * 804 */ 805 806 #ifdef __cplusplus 807 } 808 #endif 809 810 #endif /* IIS328DQ_REGS_H */ 811 812 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 813
