1 /** 2 ****************************************************************************** 3 * @file iis2iclx_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * iis2iclx_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef IIS2ICLX_REGS_H 23 #define IIS2ICLX_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup IIS2ICLX 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup IIS2ICLX Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define IIS2ICLX_I2C_ADD_L 0xD5U 173 #define IIS2ICLX_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define IIS2ICLX_ID 0x6BU 177 178 /** 179 * @} 180 * 181 */ 182 183 #define IIS2ICLX_FUNC_CFG_ACCESS 0x01U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 6; 188 uint8_t reg_access : 189 2; /* shub_reg_access + func_cfg_access */ 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t reg_access : 192 2; /* shub_reg_access + func_cfg_access */ 193 uint8_t not_used_01 : 6; 194 #endif /* DRV_BYTE_ORDER */ 195 } iis2iclx_func_cfg_access_t; 196 197 #define IIS2ICLX_PIN_CTRL 0x02U 198 typedef struct 199 { 200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 201 uint8_t not_used_01 : 6; 202 uint8_t sdo_pu_en : 1; 203 uint8_t not_used_02 : 1; 204 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 205 uint8_t not_used_02 : 1; 206 uint8_t sdo_pu_en : 1; 207 uint8_t not_used_01 : 6; 208 #endif /* DRV_BYTE_ORDER */ 209 } iis2iclx_pin_ctrl_t; 210 211 #define IIS2ICLX_FIFO_CTRL1 0x07U 212 typedef struct 213 { 214 uint8_t wtm : 8; 215 } iis2iclx_fifo_ctrl1_t; 216 217 #define IIS2ICLX_FIFO_CTRL2 0x08U 218 typedef struct 219 { 220 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 221 uint8_t wtm : 1; 222 uint8_t not_used_01 : 3; 223 uint8_t odrchg_en : 1; 224 uint8_t not_used_02 : 2; 225 uint8_t stop_on_wtm : 1; 226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 227 uint8_t stop_on_wtm : 1; 228 uint8_t not_used_02 : 2; 229 uint8_t odrchg_en : 1; 230 uint8_t not_used_01 : 3; 231 uint8_t wtm : 1; 232 #endif /* DRV_BYTE_ORDER */ 233 } iis2iclx_fifo_ctrl2_t; 234 235 #define IIS2ICLX_FIFO_CTRL3 0x09U 236 typedef struct 237 { 238 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 239 uint8_t bdr_xl : 4; 240 uint8_t not_used_01 : 4; 241 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 242 uint8_t not_used_01 : 4; 243 uint8_t bdr_xl : 4; 244 #endif /* DRV_BYTE_ORDER */ 245 } iis2iclx_fifo_ctrl3_t; 246 247 #define IIS2ICLX_FIFO_CTRL4 0x0AU 248 typedef struct 249 { 250 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 251 uint8_t fifo_mode : 3; 252 uint8_t not_used_01 : 1; 253 uint8_t odr_t_batch : 2; 254 uint8_t odr_ts_batch : 2; 255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 256 uint8_t odr_ts_batch : 2; 257 uint8_t odr_t_batch : 2; 258 uint8_t not_used_01 : 1; 259 uint8_t fifo_mode : 3; 260 #endif /* DRV_BYTE_ORDER */ 261 } iis2iclx_fifo_ctrl4_t; 262 263 #define IIS2ICLX_COUNTER_BDR_REG1 0x0BU 264 typedef struct 265 { 266 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 267 uint8_t cnt_bdr_th : 1; 268 uint8_t not_used_01 : 5; 269 uint8_t rst_counter_bdr : 1; 270 uint8_t dataready_pulsed : 1; 271 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 272 uint8_t dataready_pulsed : 1; 273 uint8_t rst_counter_bdr : 1; 274 uint8_t not_used_01 : 5; 275 uint8_t cnt_bdr_th : 1; 276 #endif /* DRV_BYTE_ORDER */ 277 } iis2iclx_counter_bdr_reg1_t; 278 279 #define IIS2ICLX_COUNTER_BDR_REG2 0x0CU 280 typedef struct 281 { 282 uint8_t cnt_bdr_th : 8; 283 } iis2iclx_counter_bdr_reg2_t; 284 285 #define IIS2ICLX_INT1_CTRL 0x0DU 286 typedef struct 287 { 288 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 289 uint8_t int1_drdy_xl : 1; 290 uint8_t not_used_01 : 1; 291 uint8_t int1_boot : 1; 292 uint8_t int1_fifo_th : 1; 293 uint8_t int1_fifo_ovr : 1; 294 uint8_t int1_fifo_full : 1; 295 uint8_t int1_cnt_bdr : 1; 296 uint8_t den_drdy_flag : 1; 297 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 298 uint8_t den_drdy_flag : 1; 299 uint8_t int1_cnt_bdr : 1; 300 uint8_t int1_fifo_full : 1; 301 uint8_t int1_fifo_ovr : 1; 302 uint8_t int1_fifo_th : 1; 303 uint8_t int1_boot : 1; 304 uint8_t not_used_01 : 1; 305 uint8_t int1_drdy_xl : 1; 306 #endif /* DRV_BYTE_ORDER */ 307 } iis2iclx_int1_ctrl_t; 308 309 #define IIS2ICLX_INT2_CTRL 0x0EU 310 typedef struct 311 { 312 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 313 uint8_t int2_drdy_xl : 1; 314 uint8_t not_used_01 : 1; 315 uint8_t int2_drdy_temp : 1; 316 uint8_t int2_fifo_th : 1; 317 uint8_t int2_fifo_ovr : 1; 318 uint8_t int2_fifo_full : 1; 319 uint8_t int2_cnt_bdr : 1; 320 uint8_t not_used_02 : 1; 321 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 322 uint8_t not_used_02 : 1; 323 uint8_t int2_cnt_bdr : 1; 324 uint8_t int2_fifo_full : 1; 325 uint8_t int2_fifo_ovr : 1; 326 uint8_t int2_fifo_th : 1; 327 uint8_t int2_drdy_temp : 1; 328 uint8_t not_used_01 : 1; 329 uint8_t int2_drdy_xl : 1; 330 #endif /* DRV_BYTE_ORDER */ 331 } iis2iclx_int2_ctrl_t; 332 333 #define IIS2ICLX_WHO_AM_I 0x0FU 334 #define IIS2ICLX_CTRL1_XL 0x10U 335 typedef struct 336 { 337 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 338 uint8_t not_used_01 : 1; 339 uint8_t lpf2_xl_en : 1; 340 uint8_t fs_xl : 2; 341 uint8_t odr_xl : 4; 342 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 343 uint8_t odr_xl : 4; 344 uint8_t fs_xl : 2; 345 uint8_t lpf2_xl_en : 1; 346 uint8_t not_used_01 : 1; 347 #endif /* DRV_BYTE_ORDER */ 348 } iis2iclx_ctrl1_xl_t; 349 350 #define IIS2ICLX_CTRL3_C 0x12U 351 typedef struct 352 { 353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 354 uint8_t sw_reset : 1; 355 uint8_t not_used_01 : 1; 356 uint8_t if_inc : 1; 357 uint8_t sim : 1; 358 uint8_t pp_od : 1; 359 uint8_t h_lactive : 1; 360 uint8_t bdu : 1; 361 uint8_t boot : 1; 362 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 363 uint8_t boot : 1; 364 uint8_t bdu : 1; 365 uint8_t h_lactive : 1; 366 uint8_t pp_od : 1; 367 uint8_t sim : 1; 368 uint8_t if_inc : 1; 369 uint8_t not_used_01 : 1; 370 uint8_t sw_reset : 1; 371 #endif /* DRV_BYTE_ORDER */ 372 } iis2iclx_ctrl3_c_t; 373 374 #define IIS2ICLX_CTRL4_C 0x13U 375 typedef struct 376 { 377 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 378 uint8_t not_used_01 : 2; 379 uint8_t i2c_disable : 1; 380 uint8_t drdy_mask : 1; 381 uint8_t not_used_02 : 1; 382 uint8_t int2_on_int1 : 1; 383 uint8_t not_used_03 : 2; 384 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 385 uint8_t not_used_03 : 2; 386 uint8_t int2_on_int1 : 1; 387 uint8_t not_used_02 : 1; 388 uint8_t drdy_mask : 1; 389 uint8_t i2c_disable : 1; 390 uint8_t not_used_01 : 2; 391 #endif /* DRV_BYTE_ORDER */ 392 } iis2iclx_ctrl4_c_t; 393 394 #define IIS2ICLX_CTRL5_C 0x14U 395 typedef struct 396 { 397 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 398 uint8_t st_xl : 2; 399 uint8_t not_used_01 : 6; 400 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 401 uint8_t not_used_01 : 6; 402 uint8_t st_xl : 2; 403 #endif /* DRV_BYTE_ORDER */ 404 } iis2iclx_ctrl5_c_t; 405 406 #define IIS2ICLX_CTRL6_C 0x15U 407 typedef struct 408 { 409 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 410 uint8_t not_used_01 : 3; 411 uint8_t usr_off_w : 1; 412 uint8_t not_used_02 : 1; 413 uint8_t den_mode : 414 3; /* trig_en + lvl1_en + lvl2_en */ 415 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 416 uint8_t den_mode : 417 3; /* trig_en + lvl1_en + lvl2_en */ 418 uint8_t not_used_02 : 1; 419 uint8_t usr_off_w : 1; 420 uint8_t not_used_01 : 3; 421 #endif /* DRV_BYTE_ORDER */ 422 } iis2iclx_ctrl6_c_t; 423 424 #define IIS2ICLX_CTRL7_XL 0x16U 425 typedef struct 426 { 427 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 428 uint8_t not_used_01 : 1; 429 uint8_t usr_off_on_out : 1; 430 uint8_t not_used_02 : 6; 431 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 432 uint8_t not_used_02 : 6; 433 uint8_t usr_off_on_out : 1; 434 uint8_t not_used_01 : 1; 435 #endif /* DRV_BYTE_ORDER */ 436 } iis2iclx_ctrl7_xl_t; 437 438 #define IIS2ICLX_CTRL8_XL 0x17U 439 typedef struct 440 { 441 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 442 uint8_t not_used_01 : 2; 443 uint8_t hp_slope_xl_en : 1; 444 uint8_t fastsettl_mode_xl : 1; 445 uint8_t hp_ref_mode_xl : 1; 446 uint8_t hpcf_xl : 3; 447 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 448 uint8_t hpcf_xl : 3; 449 uint8_t hp_ref_mode_xl : 1; 450 uint8_t fastsettl_mode_xl : 1; 451 uint8_t hp_slope_xl_en : 1; 452 uint8_t not_used_01 : 2; 453 #endif /* DRV_BYTE_ORDER */ 454 } iis2iclx_ctrl8_xl_t; 455 456 #define IIS2ICLX_CTRL9_XL 0x18U 457 typedef struct 458 { 459 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 460 uint8_t not_used_01 : 1; 461 uint8_t device_conf : 1; 462 uint8_t den_lh : 1; 463 uint8_t den_en : 3; 464 uint8_t den_y : 1; 465 uint8_t den_x : 1; 466 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 467 uint8_t den_x : 1; 468 uint8_t den_y : 1; 469 uint8_t den_en : 3; 470 uint8_t den_lh : 1; 471 uint8_t device_conf : 1; 472 uint8_t not_used_01 : 1; 473 #endif /* DRV_BYTE_ORDER */ 474 } iis2iclx_ctrl9_xl_t; 475 476 #define IIS2ICLX_CTRL10_C 0x19U 477 typedef struct 478 { 479 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 480 uint8_t not_used_01 : 5; 481 uint8_t timestamp_en : 1; 482 uint8_t not_used_02 : 2; 483 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 484 uint8_t not_used_02 : 2; 485 uint8_t timestamp_en : 1; 486 uint8_t not_used_01 : 5; 487 #endif /* DRV_BYTE_ORDER */ 488 } iis2iclx_ctrl10_c_t; 489 490 #define IIS2ICLX_ALL_INT_SRC 0x1AU 491 typedef struct 492 { 493 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 494 uint8_t not_used_01 : 1; 495 uint8_t wu_ia : 1; 496 uint8_t single_tap : 1; 497 uint8_t double_tap : 1; 498 uint8_t not_used_02 : 1; 499 uint8_t sleep_change_ia : 1; 500 uint8_t not_used_03 : 1; 501 uint8_t timestamp_endcount : 1; 502 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 503 uint8_t timestamp_endcount : 1; 504 uint8_t not_used_03 : 1; 505 uint8_t sleep_change_ia : 1; 506 uint8_t not_used_02 : 1; 507 uint8_t double_tap : 1; 508 uint8_t single_tap : 1; 509 uint8_t wu_ia : 1; 510 uint8_t not_used_01 : 1; 511 #endif /* DRV_BYTE_ORDER */ 512 } iis2iclx_all_int_src_t; 513 514 #define IIS2ICLX_WAKE_UP_SRC 0x1BU 515 typedef struct 516 { 517 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 518 uint8_t not_used_01 : 1; 519 uint8_t y_wu : 1; 520 uint8_t x_wu : 1; 521 uint8_t wu_ia : 1; 522 uint8_t sleep_state : 1; 523 uint8_t not_used_02 : 1; 524 uint8_t sleep_change_ia : 1; 525 uint8_t not_used_03 : 1; 526 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 527 uint8_t not_used_03 : 1; 528 uint8_t sleep_change_ia : 1; 529 uint8_t not_used_02 : 1; 530 uint8_t sleep_state : 1; 531 uint8_t wu_ia : 1; 532 uint8_t x_wu : 1; 533 uint8_t y_wu : 1; 534 uint8_t not_used_01 : 1; 535 #endif /* DRV_BYTE_ORDER */ 536 } iis2iclx_wake_up_src_t; 537 538 #define IIS2ICLX_TAP_SRC 0x1CU 539 typedef struct 540 { 541 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 542 uint8_t not_used_01 : 1; 543 uint8_t y_tap : 1; 544 uint8_t x_tap : 1; 545 uint8_t tap_sign : 1; 546 uint8_t double_tap : 1; 547 uint8_t single_tap : 1; 548 uint8_t tap_ia : 1; 549 uint8_t not_used_02 : 1; 550 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 551 uint8_t not_used_02 : 1; 552 uint8_t tap_ia : 1; 553 uint8_t single_tap : 1; 554 uint8_t double_tap : 1; 555 uint8_t tap_sign : 1; 556 uint8_t x_tap : 1; 557 uint8_t y_tap : 1; 558 uint8_t not_used_01 : 1; 559 #endif /* DRV_BYTE_ORDER */ 560 } iis2iclx_tap_src_t; 561 562 #define IIS2ICLX_DEN_SRC 0x1DU 563 typedef struct 564 { 565 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 566 uint8_t not_used_01 : 7; 567 uint8_t den_drdy : 1; 568 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 569 uint8_t den_drdy : 1; 570 uint8_t not_used_01 : 7; 571 #endif /* DRV_BYTE_ORDER */ 572 } iis2iclx_den_src_t; 573 574 #define IIS2ICLX_STATUS_REG 0x1EU 575 typedef struct 576 { 577 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 578 uint8_t xlda : 1; 579 uint8_t not_used_01 : 1; 580 uint8_t tda : 1; 581 uint8_t not_used_02 : 5; 582 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 583 uint8_t not_used_02 : 5; 584 uint8_t tda : 1; 585 uint8_t not_used_01 : 1; 586 uint8_t xlda : 1; 587 #endif /* DRV_BYTE_ORDER */ 588 } iis2iclx_status_reg_t; 589 590 #define IIS2ICLX_OUT_TEMP_L 0x20U 591 #define IIS2ICLX_OUT_TEMP_H 0x21U 592 #define IIS2ICLX_OUTX_L_A 0x28U 593 #define IIS2ICLX_OUTX_H_A 0x29U 594 #define IIS2ICLX_OUTY_L_A 0x2AU 595 #define IIS2ICLX_OUTY_H_A 0x2BU 596 #define IIS2ICLX_EMB_FUNC_STATUS_MAINPAGE 0x35U 597 typedef struct 598 { 599 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 600 uint8_t not_used_01 : 7; 601 uint8_t is_fsm_lc : 1; 602 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 603 uint8_t is_fsm_lc : 1; 604 uint8_t not_used_01 : 7; 605 #endif /* DRV_BYTE_ORDER */ 606 } iis2iclx_emb_func_status_mainpage_t; 607 608 #define IIS2ICLX_FSM_STATUS_A_MAINPAGE 0x36U 609 typedef struct 610 { 611 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 612 uint8_t is_fsm1 : 1; 613 uint8_t is_fsm2 : 1; 614 uint8_t is_fsm3 : 1; 615 uint8_t is_fsm4 : 1; 616 uint8_t is_fsm5 : 1; 617 uint8_t is_fsm6 : 1; 618 uint8_t is_fsm7 : 1; 619 uint8_t is_fsm8 : 1; 620 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 621 uint8_t is_fsm8 : 1; 622 uint8_t is_fsm7 : 1; 623 uint8_t is_fsm6 : 1; 624 uint8_t is_fsm5 : 1; 625 uint8_t is_fsm4 : 1; 626 uint8_t is_fsm3 : 1; 627 uint8_t is_fsm2 : 1; 628 uint8_t is_fsm1 : 1; 629 #endif /* DRV_BYTE_ORDER */ 630 } iis2iclx_fsm_status_a_mainpage_t; 631 632 #define IIS2ICLX_FSM_STATUS_B_MAINPAGE 0x37U 633 typedef struct 634 { 635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 636 uint8_t is_fsm9 : 1; 637 uint8_t is_fsm10 : 1; 638 uint8_t is_fsm11 : 1; 639 uint8_t is_fsm12 : 1; 640 uint8_t is_fsm13 : 1; 641 uint8_t is_fsm14 : 1; 642 uint8_t is_fsm15 : 1; 643 uint8_t is_fsm16 : 1; 644 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 645 uint8_t is_fsm16 : 1; 646 uint8_t is_fsm15 : 1; 647 uint8_t is_fsm14 : 1; 648 uint8_t is_fsm13 : 1; 649 uint8_t is_fsm12 : 1; 650 uint8_t is_fsm11 : 1; 651 uint8_t is_fsm10 : 1; 652 uint8_t is_fsm09 : 1; 653 #endif /* DRV_BYTE_ORDER */ 654 } iis2iclx_fsm_status_b_mainpage_t; 655 656 #define IIS2ICLX_MLC_STATUS_MAINPAGE 0x38U 657 typedef struct 658 { 659 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 660 uint8_t is_mlc1 : 1; 661 uint8_t is_mlc2 : 1; 662 uint8_t is_mlc3 : 1; 663 uint8_t is_mlc4 : 1; 664 uint8_t is_mlc5 : 1; 665 uint8_t is_mlc6 : 1; 666 uint8_t is_mlc7 : 1; 667 uint8_t is_mlc8 : 1; 668 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 669 uint8_t is_mlc8 : 1; 670 uint8_t is_mlc7 : 1; 671 uint8_t is_mlc6 : 1; 672 uint8_t is_mlc5 : 1; 673 uint8_t is_mlc4 : 1; 674 uint8_t is_mlc3 : 1; 675 uint8_t is_mlc2 : 1; 676 uint8_t is_mlc1 : 1; 677 #endif /* DRV_BYTE_ORDER */ 678 } iis2iclx_mlc_status_mainpage_t; 679 680 #define IIS2ICLX_STATUS_MASTER_MAINPAGE 0x39U 681 typedef struct 682 { 683 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 684 uint8_t sens_hub_endop : 1; 685 uint8_t not_used_01 : 2; 686 uint8_t slave0_nack : 1; 687 uint8_t slave1_nack : 1; 688 uint8_t slave2_nack : 1; 689 uint8_t slave3_nack : 1; 690 uint8_t wr_once_done : 1; 691 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 692 uint8_t wr_once_done : 1; 693 uint8_t slave3_nack : 1; 694 uint8_t slave2_nack : 1; 695 uint8_t slave1_nack : 1; 696 uint8_t slave0_nack : 1; 697 uint8_t not_used_01 : 2; 698 uint8_t sens_hub_endop : 1; 699 #endif /* DRV_BYTE_ORDER */ 700 } iis2iclx_status_master_mainpage_t; 701 702 #define IIS2ICLX_FIFO_STATUS1 0x3AU 703 typedef struct 704 { 705 uint8_t diff_fifo : 8; 706 } iis2iclx_fifo_status1_t; 707 708 #define IIS2ICLX_FIFO_STATUS2 0x3BU 709 typedef struct 710 { 711 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 712 uint8_t diff_fifo : 2; 713 uint8_t not_used_01 : 1; 714 uint8_t over_run_latched : 1; 715 uint8_t counter_bdr_ia : 1; 716 uint8_t fifo_full_ia : 1; 717 uint8_t fifo_ovr_ia : 1; 718 uint8_t fifo_wtm_ia : 1; 719 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 720 uint8_t fifo_wtm_ia : 1; 721 uint8_t fifo_ovr_ia : 1; 722 uint8_t fifo_full_ia : 1; 723 uint8_t counter_bdr_ia : 1; 724 uint8_t over_run_latched : 1; 725 uint8_t not_used_01 : 1; 726 uint8_t diff_fifo : 2; 727 #endif /* DRV_BYTE_ORDER */ 728 } iis2iclx_fifo_status2_t; 729 730 #define IIS2ICLX_TIMESTAMP0 0x40U 731 #define IIS2ICLX_TIMESTAMP1 0x41U 732 #define IIS2ICLX_TIMESTAMP2 0x42U 733 #define IIS2ICLX_TIMESTAMP3 0x43U 734 #define IIS2ICLX_TAP_CFG0 0x56U 735 typedef struct 736 { 737 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 738 uint8_t lir : 1; 739 uint8_t not_used_01 : 1; 740 uint8_t tap_y_en : 1; 741 uint8_t tap_x_en : 1; 742 uint8_t slope_fds : 1; 743 uint8_t sleep_status_on_int : 1; 744 uint8_t int_clr_on_read : 1; 745 uint8_t not_used_02 : 1; 746 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 747 uint8_t not_used_02 : 1; 748 uint8_t int_clr_on_read : 1; 749 uint8_t sleep_status_on_int : 1; 750 uint8_t slope_fds : 1; 751 uint8_t tap_x_en : 1; 752 uint8_t tap_y_en : 1; 753 uint8_t not_used_01 : 1; 754 uint8_t lir : 1; 755 #endif /* DRV_BYTE_ORDER */ 756 } iis2iclx_tap_cfg0_t; 757 758 #define IIS2ICLX_TAP_CFG1 0x57U 759 typedef struct 760 { 761 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 762 uint8_t tap_ths_x : 5; 763 uint8_t tap_priority : 1; 764 uint8_t not_used_01 : 2; 765 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 766 uint8_t not_used_01 : 2; 767 uint8_t tap_priority : 1; 768 uint8_t tap_ths_x : 5; 769 #endif /* DRV_BYTE_ORDER */ 770 } iis2iclx_tap_cfg1_t; 771 772 #define IIS2ICLX_TAP_CFG2 0x58U 773 typedef struct 774 { 775 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 776 uint8_t tap_ths_y : 5; 777 uint8_t not_used_01 : 2; 778 uint8_t interrupts_enable : 1; 779 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 780 uint8_t interrupts_enable : 1; 781 uint8_t not_used_01 : 2; 782 uint8_t tap_ths_y : 5; 783 #endif /* DRV_BYTE_ORDER */ 784 } iis2iclx_tap_cfg2_t; 785 786 #define IIS2ICLX_INT_DUR2 0x5AU 787 typedef struct 788 { 789 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 790 uint8_t shock : 2; 791 uint8_t quiet : 2; 792 uint8_t dur : 4; 793 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 794 uint8_t dur : 4; 795 uint8_t quiet : 2; 796 uint8_t shock : 2; 797 #endif /* DRV_BYTE_ORDER */ 798 } iis2iclx_int_dur2_t; 799 800 #define IIS2ICLX_WAKE_UP_THS 0x5BU 801 typedef struct 802 { 803 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 804 uint8_t wk_ths : 6; 805 uint8_t usr_off_on_wu : 1; 806 uint8_t single_double_tap : 1; 807 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 808 uint8_t single_double_tap : 1; 809 uint8_t usr_off_on_wu : 1; 810 uint8_t wk_ths : 6; 811 #endif /* DRV_BYTE_ORDER */ 812 } iis2iclx_wake_up_ths_t; 813 814 #define IIS2ICLX_WAKE_UP_DUR 0x5CU 815 typedef struct 816 { 817 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 818 uint8_t sleep_dur : 4; 819 uint8_t wake_ths_w : 1; 820 uint8_t wake_dur : 2; 821 uint8_t not_used_01 : 1; 822 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 823 uint8_t not_used_01 : 1; 824 uint8_t wake_dur : 2; 825 uint8_t wake_ths_w : 1; 826 uint8_t sleep_dur : 4; 827 #endif /* DRV_BYTE_ORDER */ 828 } iis2iclx_wake_up_dur_t; 829 830 #define IIS2ICLX_MD1_CFG 0x5EU 831 typedef struct 832 { 833 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 834 uint8_t int1_shub : 1; 835 uint8_t int1_emb_func : 1; 836 uint8_t not_used_01 : 1; 837 uint8_t int1_double_tap : 1; 838 uint8_t not_used_02 : 1; 839 uint8_t int1_wu : 1; 840 uint8_t int1_single_tap : 1; 841 uint8_t int1_sleep_change : 1; 842 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 843 uint8_t int1_sleep_change : 1; 844 uint8_t int1_single_tap : 1; 845 uint8_t int1_wu : 1; 846 uint8_t not_used_02 : 1; 847 uint8_t int1_double_tap : 1; 848 uint8_t not_used_01 : 1; 849 uint8_t int1_emb_func : 1; 850 uint8_t int1_shub : 1; 851 #endif /* DRV_BYTE_ORDER */ 852 } iis2iclx_md1_cfg_t; 853 854 #define IIS2ICLX_MD2_CFG 0x5FU 855 typedef struct 856 { 857 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 858 uint8_t int2_timestamp : 1; 859 uint8_t int2_emb_func : 1; 860 uint8_t not_used_01 : 1; 861 uint8_t int2_double_tap : 1; 862 uint8_t not_used_02 : 1; 863 uint8_t int2_wu : 1; 864 uint8_t int2_single_tap : 1; 865 uint8_t int2_sleep_change : 1; 866 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 867 uint8_t int2_sleep_change : 1; 868 uint8_t int2_single_tap : 1; 869 uint8_t int2_wu : 1; 870 uint8_t not_used_02 : 1; 871 uint8_t int2_double_tap : 1; 872 uint8_t not_used_01 : 1; 873 uint8_t int2_emb_func : 1; 874 uint8_t int2_timestamp : 1; 875 #endif /* DRV_BYTE_ORDER */ 876 } iis2iclx_md2_cfg_t; 877 878 #define IIS2ICLX_INTERNAL_FREQ_FINE 0x63U 879 typedef struct 880 { 881 uint8_t freq_fine : 8; 882 } iis2iclx_internal_freq_fine_t; 883 884 #define IIS2ICLX_X_OFS_USR 0x73U 885 #define IIS2ICLX_Y_OFS_USR 0x74U 886 #define IIS2ICLX_FIFO_DATA_OUT_TAG 0x78U 887 typedef struct 888 { 889 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 890 uint8_t tag_parity : 1; 891 uint8_t tag_cnt : 2; 892 uint8_t tag_sensor : 5; 893 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 894 uint8_t tag_sensor : 5; 895 uint8_t tag_cnt : 2; 896 uint8_t tag_parity : 1; 897 #endif /* DRV_BYTE_ORDER */ 898 } iis2iclx_fifo_data_out_tag_t; 899 900 #define IIS2ICLX_FIFO_DATA_OUT_X_L 0x79U 901 #define IIS2ICLX_FIFO_DATA_OUT_X_H 0x7AU 902 #define IIS2ICLX_FIFO_DATA_OUT_Y_L 0x7BU 903 #define IIS2ICLX_FIFO_DATA_OUT_Y_H 0x7CU 904 #define IIS2ICLX_FIFO_DATA_OUT_Z_L 0x7DU 905 #define IIS2ICLX_FIFO_DATA_OUT_Z_H 0x7EU 906 #define IIS2ICLX_PAGE_SEL 0x02U 907 typedef struct 908 { 909 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 910 uint8_t not_used_01 : 4; 911 uint8_t page_sel : 4; 912 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 913 uint8_t page_sel : 4; 914 uint8_t not_used_01 : 4; 915 #endif /* DRV_BYTE_ORDER */ 916 } iis2iclx_page_sel_t; 917 918 #define IIS2ICLX_EMB_FUNC_EN_B 0x05U 919 typedef struct 920 { 921 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 922 uint8_t fsm_en : 1; 923 uint8_t not_used_01 : 3; 924 uint8_t mlc_en : 1; 925 uint8_t not_used_02 : 3; 926 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 927 uint8_t not_used_02 : 3; 928 uint8_t mlc_en : 1; 929 uint8_t not_used_01 : 3; 930 uint8_t fsm_en : 1; 931 #endif /* DRV_BYTE_ORDER */ 932 } iis2iclx_emb_func_en_b_t; 933 934 #define IIS2ICLX_PAGE_ADDRESS 0x08U 935 typedef struct 936 { 937 uint8_t page_addr : 8; 938 } iis2iclx_page_address_t; 939 940 #define IIS2ICLX_PAGE_VALUE 0x09U 941 typedef struct 942 { 943 uint8_t page_value : 8; 944 } iis2iclx_page_value_t; 945 946 #define IIS2ICLX_EMB_FUNC_INT1 0x0AU 947 typedef struct 948 { 949 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 950 uint8_t not_used_01 : 7; 951 uint8_t int1_fsm_lc : 1; 952 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 953 uint8_t int1_fsm_lc : 1; 954 uint8_t not_used_01 : 7; 955 #endif /* DRV_BYTE_ORDER */ 956 } iis2iclx_emb_func_int1_t; 957 958 #define IIS2ICLX_FSM_INT1_A 0x0BU 959 typedef struct 960 { 961 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 962 uint8_t int1_fsm1 : 1; 963 uint8_t int1_fsm2 : 1; 964 uint8_t int1_fsm3 : 1; 965 uint8_t int1_fsm4 : 1; 966 uint8_t int1_fsm5 : 1; 967 uint8_t int1_fsm6 : 1; 968 uint8_t int1_fsm7 : 1; 969 uint8_t int1_fsm8 : 1; 970 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 971 uint8_t int1_fsm8 : 1; 972 uint8_t int1_fsm7 : 1; 973 uint8_t int1_fsm6 : 1; 974 uint8_t int1_fsm5 : 1; 975 uint8_t int1_fsm4 : 1; 976 uint8_t int1_fsm3 : 1; 977 uint8_t int1_fsm2 : 1; 978 uint8_t int1_fsm1 : 1; 979 #endif /* DRV_BYTE_ORDER */ 980 } iis2iclx_fsm_int1_a_t; 981 982 #define IIS2ICLX_FSM_INT1_B 0x0CU 983 typedef struct 984 { 985 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 986 uint8_t int1_fsm9 : 1; 987 uint8_t int1_fsm10 : 1; 988 uint8_t int1_fsm11 : 1; 989 uint8_t int1_fsm12 : 1; 990 uint8_t int1_fsm13 : 1; 991 uint8_t int1_fsm14 : 1; 992 uint8_t int1_fsm15 : 1; 993 uint8_t int1_fsm16 : 1; 994 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 995 uint8_t int1_fsm16 : 1; 996 uint8_t int1_fsm15 : 1; 997 uint8_t int1_fsm14 : 1; 998 uint8_t int1_fsm13 : 1; 999 uint8_t int1_fsm12 : 1; 1000 uint8_t int1_fsm11 : 1; 1001 uint8_t int1_fsm10 : 1; 1002 uint8_t int1_fsm9 : 1; 1003 #endif /* DRV_BYTE_ORDER */ 1004 } iis2iclx_fsm_int1_b_t; 1005 1006 #define IIS2ICLX_MLC_INT1 0x0DU 1007 typedef struct 1008 { 1009 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1010 uint8_t int1_mlc1 : 1; 1011 uint8_t int1_mlc2 : 1; 1012 uint8_t int1_mlc3 : 1; 1013 uint8_t int1_mlc4 : 1; 1014 uint8_t int1_mlc5 : 1; 1015 uint8_t int1_mlc6 : 1; 1016 uint8_t int1_mlc7 : 1; 1017 uint8_t int1_mlc8 : 1; 1018 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1019 uint8_t int1_mlc8 : 1; 1020 uint8_t int1_mlc7 : 1; 1021 uint8_t int1_mlc6 : 1; 1022 uint8_t int1_mlc5 : 1; 1023 uint8_t int1_mlc4 : 1; 1024 uint8_t int1_mlc3 : 1; 1025 uint8_t int1_mlc2 : 1; 1026 uint8_t int1_mlc1 : 1; 1027 #endif /* DRV_BYTE_ORDER */ 1028 } iis2iclx_mlc_int1_t; 1029 1030 #define IIS2ICLX_EMB_FUNC_INT2 0x0EU 1031 typedef struct 1032 { 1033 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1034 uint8_t not_used_01 : 7; 1035 uint8_t int2_fsm_lc : 1; 1036 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1037 uint8_t int2_fsm_lc : 1; 1038 uint8_t not_used_01 : 7; 1039 #endif /* DRV_BYTE_ORDER */ 1040 } iis2iclx_emb_func_int2_t; 1041 1042 #define IIS2ICLX_FSM_INT2_A 0x0FU 1043 typedef struct 1044 { 1045 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1046 uint8_t int2_fsm1 : 1; 1047 uint8_t int2_fsm2 : 1; 1048 uint8_t int2_fsm3 : 1; 1049 uint8_t int2_fsm4 : 1; 1050 uint8_t int2_fsm5 : 1; 1051 uint8_t int2_fsm6 : 1; 1052 uint8_t int2_fsm7 : 1; 1053 uint8_t int2_fsm8 : 1; 1054 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1055 uint8_t int2_fsm8 : 1; 1056 uint8_t int2_fsm7 : 1; 1057 uint8_t int2_fsm6 : 1; 1058 uint8_t int2_fsm5 : 1; 1059 uint8_t int2_fsm4 : 1; 1060 uint8_t int2_fsm3 : 1; 1061 uint8_t int2_fsm2 : 1; 1062 uint8_t int2_fsm1 : 1; 1063 #endif /* DRV_BYTE_ORDER */ 1064 } iis2iclx_fsm_int2_a_t; 1065 1066 #define IIS2ICLX_FSM_INT2_B 0x10U 1067 typedef struct 1068 { 1069 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1070 uint8_t int2_fsm9 : 1; 1071 uint8_t int2_fsm10 : 1; 1072 uint8_t int2_fsm11 : 1; 1073 uint8_t int2_fsm12 : 1; 1074 uint8_t int2_fsm13 : 1; 1075 uint8_t int2_fsm14 : 1; 1076 uint8_t int2_fsm15 : 1; 1077 uint8_t int2_fsm16 : 1; 1078 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1079 uint8_t int2_fsm16 : 1; 1080 uint8_t int2_fsm15 : 1; 1081 uint8_t int2_fsm14 : 1; 1082 uint8_t int2_fsm13 : 1; 1083 uint8_t int2_fsm12 : 1; 1084 uint8_t int2_fsm11 : 1; 1085 uint8_t int2_fsm10 : 1; 1086 uint8_t int2_fsm9 : 1; 1087 #endif /* DRV_BYTE_ORDER */ 1088 } iis2iclx_fsm_int2_b_t; 1089 1090 #define IIS2ICLX_MLC_INT2 0x11U 1091 typedef struct 1092 { 1093 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1094 uint8_t int2_mlc1 : 1; 1095 uint8_t int2_mlc2 : 1; 1096 uint8_t int2_mlc3 : 1; 1097 uint8_t int2_mlc4 : 1; 1098 uint8_t int2_mlc5 : 1; 1099 uint8_t int2_mlc6 : 1; 1100 uint8_t int2_mlc7 : 1; 1101 uint8_t int2_mlc8 : 1; 1102 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1103 uint8_t int2_mlc8 : 1; 1104 uint8_t int2_mlc7 : 1; 1105 uint8_t int2_mlc6 : 1; 1106 uint8_t int2_mlc5 : 1; 1107 uint8_t int2_mlc4 : 1; 1108 uint8_t int2_mlc3 : 1; 1109 uint8_t int2_mlc2 : 1; 1110 uint8_t int2_mlc1 : 1; 1111 #endif /* DRV_BYTE_ORDER */ 1112 } iis2iclx_mlc_int2_t; 1113 1114 #define IIS2ICLX_EMB_FUNC_STATUS 0x12U 1115 typedef struct 1116 { 1117 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1118 uint8_t not_used_01 : 7; 1119 uint8_t is_fsm_lc : 1; 1120 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1121 uint8_t is_fsm_lc : 1; 1122 uint8_t not_used_01 : 7; 1123 #endif /* DRV_BYTE_ORDER */ 1124 } iis2iclx_emb_func_status_t; 1125 1126 #define IIS2ICLX_FSM_STATUS_A 0x13U 1127 typedef struct 1128 { 1129 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1130 uint8_t is_fsm1 : 1; 1131 uint8_t is_fsm2 : 1; 1132 uint8_t is_fsm3 : 1; 1133 uint8_t is_fsm4 : 1; 1134 uint8_t is_fsm5 : 1; 1135 uint8_t is_fsm6 : 1; 1136 uint8_t is_fsm7 : 1; 1137 uint8_t is_fsm8 : 1; 1138 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1139 uint8_t is_fsm8 : 1; 1140 uint8_t is_fsm7 : 1; 1141 uint8_t is_fsm6 : 1; 1142 uint8_t is_fsm5 : 1; 1143 uint8_t is_fsm4 : 1; 1144 uint8_t is_fsm3 : 1; 1145 uint8_t is_fsm2 : 1; 1146 uint8_t is_fsm1 : 1; 1147 #endif /* DRV_BYTE_ORDER */ 1148 } iis2iclx_fsm_status_a_t; 1149 1150 #define IIS2ICLX_FSM_STATUS_B 0x14U 1151 typedef struct 1152 { 1153 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1154 uint8_t is_fsm9 : 1; 1155 uint8_t is_fsm10 : 1; 1156 uint8_t is_fsm11 : 1; 1157 uint8_t is_fsm12 : 1; 1158 uint8_t is_fsm13 : 1; 1159 uint8_t is_fsm14 : 1; 1160 uint8_t is_fsm15 : 1; 1161 uint8_t is_fsm16 : 1; 1162 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1163 uint8_t is_fsm16 : 1; 1164 uint8_t is_fsm15 : 1; 1165 uint8_t is_fsm14 : 1; 1166 uint8_t is_fsm13 : 1; 1167 uint8_t is_fsm12 : 1; 1168 uint8_t is_fsm11 : 1; 1169 uint8_t is_fsm10 : 1; 1170 uint8_t is_fsm9 : 1; 1171 #endif /* DRV_BYTE_ORDER */ 1172 } iis2iclx_fsm_status_b_t; 1173 1174 #define IIS2ICLX_MLC_STATUS 0x15U 1175 typedef struct 1176 { 1177 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1178 uint8_t is_mlc1 : 1; 1179 uint8_t is_mlc2 : 1; 1180 uint8_t is_mlc3 : 1; 1181 uint8_t is_mlc4 : 1; 1182 uint8_t is_mlc5 : 1; 1183 uint8_t is_mlc6 : 1; 1184 uint8_t is_mlc7 : 1; 1185 uint8_t is_mlc8 : 1; 1186 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1187 uint8_t is_mlc8 : 1; 1188 uint8_t is_mlc7 : 1; 1189 uint8_t is_mlc6 : 1; 1190 uint8_t is_mlc5 : 1; 1191 uint8_t is_mlc4 : 1; 1192 uint8_t is_mlc3 : 1; 1193 uint8_t is_mlc2 : 1; 1194 uint8_t is_mlc1 : 1; 1195 #endif /* DRV_BYTE_ORDER */ 1196 } iis2iclx_mlc_status_t; 1197 1198 #define IIS2ICLX_PAGE_RW 0x17U 1199 typedef struct 1200 { 1201 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1202 uint8_t not_used_01 : 5; 1203 uint8_t page_rw : 2; /* page_write + page_read */ 1204 uint8_t emb_func_lir : 1; 1205 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1206 uint8_t emb_func_lir : 1; 1207 uint8_t page_rw : 2; /* page_write + page_read */ 1208 uint8_t not_used_01 : 5; 1209 #endif /* DRV_BYTE_ORDER */ 1210 } iis2iclx_page_rw_t; 1211 1212 #define IIS2ICLX_FSM_ENABLE_A 0x46U 1213 typedef struct 1214 { 1215 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1216 uint8_t fsm1_en : 1; 1217 uint8_t fsm2_en : 1; 1218 uint8_t fsm3_en : 1; 1219 uint8_t fsm4_en : 1; 1220 uint8_t fsm5_en : 1; 1221 uint8_t fsm6_en : 1; 1222 uint8_t fsm7_en : 1; 1223 uint8_t fsm8_en : 1; 1224 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1225 uint8_t fsm8_en : 1; 1226 uint8_t fsm7_en : 1; 1227 uint8_t fsm6_en : 1; 1228 uint8_t fsm5_en : 1; 1229 uint8_t fsm4_en : 1; 1230 uint8_t fsm3_en : 1; 1231 uint8_t fsm2_en : 1; 1232 uint8_t fsm1_en : 1; 1233 #endif /* DRV_BYTE_ORDER */ 1234 } iis2iclx_fsm_enable_a_t; 1235 1236 #define IIS2ICLX_FSM_ENABLE_B 0x47U 1237 typedef struct 1238 { 1239 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1240 uint8_t fsm9_en : 1; 1241 uint8_t fsm10_en : 1; 1242 uint8_t fsm11_en : 1; 1243 uint8_t fsm12_en : 1; 1244 uint8_t fsm13_en : 1; 1245 uint8_t fsm14_en : 1; 1246 uint8_t fsm15_en : 1; 1247 uint8_t fsm16_en : 1; 1248 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1249 uint8_t fsm16_en : 1; 1250 uint8_t fsm15_en : 1; 1251 uint8_t fsm14_en : 1; 1252 uint8_t fsm13_en : 1; 1253 uint8_t fsm12_en : 1; 1254 uint8_t fsm11_en : 1; 1255 uint8_t fsm10_en : 1; 1256 uint8_t fsm9_en : 1; 1257 #endif /* DRV_BYTE_ORDER */ 1258 } iis2iclx_fsm_enable_b_t; 1259 1260 #define IIS2ICLX_FSM_LONG_COUNTER_L 0x48U 1261 #define IIS2ICLX_FSM_LONG_COUNTER_H 0x49U 1262 #define IIS2ICLX_FSM_LONG_COUNTER_CLEAR 0x4AU 1263 typedef struct 1264 { 1265 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1266 uint8_t fsm_lc_clr : 1267 2; /* fsm_lc_cleared + fsm_lc_clear */ 1268 uint8_t not_used_01 : 6; 1269 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1270 uint8_t not_used_01 : 6; 1271 uint8_t fsm_lc_clr : 1272 2; /* fsm_lc_cleared + fsm_lc_clear */ 1273 #endif /* DRV_BYTE_ORDER */ 1274 } iis2iclx_fsm_long_counter_clear_t; 1275 1276 #define IIS2ICLX_FSM_OUTS1 0x4CU 1277 typedef struct 1278 { 1279 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1280 uint8_t n_v : 1; 1281 uint8_t p_v : 1; 1282 uint8_t n_z : 1; 1283 uint8_t p_z : 1; 1284 uint8_t n_y : 1; 1285 uint8_t p_y : 1; 1286 uint8_t n_x : 1; 1287 uint8_t p_x : 1; 1288 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1289 uint8_t p_x : 1; 1290 uint8_t n_x : 1; 1291 uint8_t p_y : 1; 1292 uint8_t n_y : 1; 1293 uint8_t p_z : 1; 1294 uint8_t n_z : 1; 1295 uint8_t p_v : 1; 1296 uint8_t n_v : 1; 1297 #endif /* DRV_BYTE_ORDER */ 1298 } iis2iclx_fsm_outs1_t; 1299 1300 #define IIS2ICLX_FSM_OUTS2 0x4DU 1301 typedef struct 1302 { 1303 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1304 uint8_t n_v : 1; 1305 uint8_t p_v : 1; 1306 uint8_t n_z : 1; 1307 uint8_t p_z : 1; 1308 uint8_t n_y : 1; 1309 uint8_t p_y : 1; 1310 uint8_t n_x : 1; 1311 uint8_t p_x : 1; 1312 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1313 uint8_t p_x : 1; 1314 uint8_t n_x : 1; 1315 uint8_t p_y : 1; 1316 uint8_t n_y : 1; 1317 uint8_t p_z : 1; 1318 uint8_t n_z : 1; 1319 uint8_t p_v : 1; 1320 uint8_t n_v : 1; 1321 #endif /* DRV_BYTE_ORDER */ 1322 } iis2iclx_fsm_outs2_t; 1323 1324 #define IIS2ICLX_FSM_OUTS3 0x4EU 1325 typedef struct 1326 { 1327 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1328 uint8_t n_v : 1; 1329 uint8_t p_v : 1; 1330 uint8_t n_z : 1; 1331 uint8_t p_z : 1; 1332 uint8_t n_y : 1; 1333 uint8_t p_y : 1; 1334 uint8_t n_x : 1; 1335 uint8_t p_x : 1; 1336 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1337 uint8_t p_x : 1; 1338 uint8_t n_x : 1; 1339 uint8_t p_y : 1; 1340 uint8_t n_y : 1; 1341 uint8_t p_z : 1; 1342 uint8_t n_z : 1; 1343 uint8_t p_v : 1; 1344 uint8_t n_v : 1; 1345 #endif /* DRV_BYTE_ORDER */ 1346 } iis2iclx_fsm_outs3_t; 1347 1348 #define IIS2ICLX_FSM_OUTS4 0x4FU 1349 typedef struct 1350 { 1351 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1352 uint8_t n_v : 1; 1353 uint8_t p_v : 1; 1354 uint8_t n_z : 1; 1355 uint8_t p_z : 1; 1356 uint8_t n_y : 1; 1357 uint8_t p_y : 1; 1358 uint8_t n_x : 1; 1359 uint8_t p_x : 1; 1360 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1361 uint8_t p_x : 1; 1362 uint8_t n_x : 1; 1363 uint8_t p_y : 1; 1364 uint8_t n_y : 1; 1365 uint8_t p_z : 1; 1366 uint8_t n_z : 1; 1367 uint8_t p_v : 1; 1368 uint8_t n_v : 1; 1369 #endif /* DRV_BYTE_ORDER */ 1370 } iis2iclx_fsm_outs4_t; 1371 1372 #define IIS2ICLX_FSM_OUTS5 0x50U 1373 typedef struct 1374 { 1375 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1376 uint8_t n_v : 1; 1377 uint8_t p_v : 1; 1378 uint8_t n_z : 1; 1379 uint8_t p_z : 1; 1380 uint8_t n_y : 1; 1381 uint8_t p_y : 1; 1382 uint8_t n_x : 1; 1383 uint8_t p_x : 1; 1384 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1385 uint8_t p_x : 1; 1386 uint8_t n_x : 1; 1387 uint8_t p_y : 1; 1388 uint8_t n_y : 1; 1389 uint8_t p_z : 1; 1390 uint8_t n_z : 1; 1391 uint8_t p_v : 1; 1392 uint8_t n_v : 1; 1393 #endif /* DRV_BYTE_ORDER */ 1394 } iis2iclx_fsm_outs5_t; 1395 1396 #define IIS2ICLX_FSM_OUTS6 0x51U 1397 typedef struct 1398 { 1399 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1400 uint8_t n_v : 1; 1401 uint8_t p_v : 1; 1402 uint8_t n_z : 1; 1403 uint8_t p_z : 1; 1404 uint8_t n_y : 1; 1405 uint8_t p_y : 1; 1406 uint8_t n_x : 1; 1407 uint8_t p_x : 1; 1408 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1409 uint8_t p_x : 1; 1410 uint8_t n_x : 1; 1411 uint8_t p_y : 1; 1412 uint8_t n_y : 1; 1413 uint8_t p_z : 1; 1414 uint8_t n_z : 1; 1415 uint8_t p_v : 1; 1416 uint8_t n_v : 1; 1417 #endif /* DRV_BYTE_ORDER */ 1418 } iis2iclx_fsm_outs6_t; 1419 1420 #define IIS2ICLX_FSM_OUTS7 0x52U 1421 typedef struct 1422 { 1423 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1424 uint8_t n_v : 1; 1425 uint8_t p_v : 1; 1426 uint8_t n_z : 1; 1427 uint8_t p_z : 1; 1428 uint8_t n_y : 1; 1429 uint8_t p_y : 1; 1430 uint8_t n_x : 1; 1431 uint8_t p_x : 1; 1432 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1433 uint8_t p_x : 1; 1434 uint8_t n_x : 1; 1435 uint8_t p_y : 1; 1436 uint8_t n_y : 1; 1437 uint8_t p_z : 1; 1438 uint8_t n_z : 1; 1439 uint8_t p_v : 1; 1440 uint8_t n_v : 1; 1441 #endif /* DRV_BYTE_ORDER */ 1442 } iis2iclx_fsm_outs7_t; 1443 1444 #define IIS2ICLX_FSM_OUTS8 0x53U 1445 typedef struct 1446 { 1447 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1448 uint8_t n_v : 1; 1449 uint8_t p_v : 1; 1450 uint8_t n_z : 1; 1451 uint8_t p_z : 1; 1452 uint8_t n_y : 1; 1453 uint8_t p_y : 1; 1454 uint8_t n_x : 1; 1455 uint8_t p_x : 1; 1456 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1457 uint8_t p_x : 1; 1458 uint8_t n_x : 1; 1459 uint8_t p_y : 1; 1460 uint8_t n_y : 1; 1461 uint8_t p_z : 1; 1462 uint8_t n_z : 1; 1463 uint8_t p_v : 1; 1464 uint8_t n_v : 1; 1465 #endif /* DRV_BYTE_ORDER */ 1466 } iis2iclx_fsm_outs8_t; 1467 1468 #define IIS2ICLX_FSM_OUTS9 0x54U 1469 typedef struct 1470 { 1471 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1472 uint8_t n_v : 1; 1473 uint8_t p_v : 1; 1474 uint8_t n_z : 1; 1475 uint8_t p_z : 1; 1476 uint8_t n_y : 1; 1477 uint8_t p_y : 1; 1478 uint8_t n_x : 1; 1479 uint8_t p_x : 1; 1480 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1481 uint8_t p_x : 1; 1482 uint8_t n_x : 1; 1483 uint8_t p_y : 1; 1484 uint8_t n_y : 1; 1485 uint8_t p_z : 1; 1486 uint8_t n_z : 1; 1487 uint8_t p_v : 1; 1488 uint8_t n_v : 1; 1489 #endif /* DRV_BYTE_ORDER */ 1490 } iis2iclx_fsm_outs9_t; 1491 1492 #define IIS2ICLX_FSM_OUTS10 0x55U 1493 typedef struct 1494 { 1495 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1496 uint8_t n_v : 1; 1497 uint8_t p_v : 1; 1498 uint8_t n_z : 1; 1499 uint8_t p_z : 1; 1500 uint8_t n_y : 1; 1501 uint8_t p_y : 1; 1502 uint8_t n_x : 1; 1503 uint8_t p_x : 1; 1504 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1505 uint8_t p_x : 1; 1506 uint8_t n_x : 1; 1507 uint8_t p_y : 1; 1508 uint8_t n_y : 1; 1509 uint8_t p_z : 1; 1510 uint8_t n_z : 1; 1511 uint8_t p_v : 1; 1512 uint8_t n_v : 1; 1513 #endif /* DRV_BYTE_ORDER */ 1514 } iis2iclx_fsm_outs10_t; 1515 1516 #define IIS2ICLX_FSM_OUTS11 0x56U 1517 typedef struct 1518 { 1519 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1520 uint8_t n_v : 1; 1521 uint8_t p_v : 1; 1522 uint8_t n_z : 1; 1523 uint8_t p_z : 1; 1524 uint8_t n_y : 1; 1525 uint8_t p_y : 1; 1526 uint8_t n_x : 1; 1527 uint8_t p_x : 1; 1528 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1529 uint8_t p_x : 1; 1530 uint8_t n_x : 1; 1531 uint8_t p_y : 1; 1532 uint8_t n_y : 1; 1533 uint8_t p_z : 1; 1534 uint8_t n_z : 1; 1535 uint8_t p_v : 1; 1536 uint8_t n_v : 1; 1537 #endif /* DRV_BYTE_ORDER */ 1538 } iis2iclx_fsm_outs11_t; 1539 1540 #define IIS2ICLX_FSM_OUTS12 0x57U 1541 typedef struct 1542 { 1543 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1544 uint8_t n_v : 1; 1545 uint8_t p_v : 1; 1546 uint8_t n_z : 1; 1547 uint8_t p_z : 1; 1548 uint8_t n_y : 1; 1549 uint8_t p_y : 1; 1550 uint8_t n_x : 1; 1551 uint8_t p_x : 1; 1552 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1553 uint8_t p_x : 1; 1554 uint8_t n_x : 1; 1555 uint8_t p_y : 1; 1556 uint8_t n_y : 1; 1557 uint8_t p_z : 1; 1558 uint8_t n_z : 1; 1559 uint8_t p_v : 1; 1560 uint8_t n_v : 1; 1561 #endif /* DRV_BYTE_ORDER */ 1562 } iis2iclx_fsm_outs12_t; 1563 1564 #define IIS2ICLX_FSM_OUTS13 0x58U 1565 typedef struct 1566 { 1567 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1568 uint8_t n_v : 1; 1569 uint8_t p_v : 1; 1570 uint8_t n_z : 1; 1571 uint8_t p_z : 1; 1572 uint8_t n_y : 1; 1573 uint8_t p_y : 1; 1574 uint8_t n_x : 1; 1575 uint8_t p_x : 1; 1576 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1577 uint8_t p_x : 1; 1578 uint8_t n_x : 1; 1579 uint8_t p_y : 1; 1580 uint8_t n_y : 1; 1581 uint8_t p_z : 1; 1582 uint8_t n_z : 1; 1583 uint8_t p_v : 1; 1584 uint8_t n_v : 1; 1585 #endif /* DRV_BYTE_ORDER */ 1586 } iis2iclx_fsm_outs13_t; 1587 1588 #define IIS2ICLX_FSM_OUTS14 0x59U 1589 typedef struct 1590 { 1591 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1592 uint8_t n_v : 1; 1593 uint8_t p_v : 1; 1594 uint8_t n_z : 1; 1595 uint8_t p_z : 1; 1596 uint8_t n_y : 1; 1597 uint8_t p_y : 1; 1598 uint8_t n_x : 1; 1599 uint8_t p_x : 1; 1600 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1601 uint8_t p_x : 1; 1602 uint8_t n_x : 1; 1603 uint8_t p_y : 1; 1604 uint8_t n_y : 1; 1605 uint8_t p_z : 1; 1606 uint8_t n_z : 1; 1607 uint8_t p_v : 1; 1608 uint8_t n_v : 1; 1609 #endif /* DRV_BYTE_ORDER */ 1610 } iis2iclx_fsm_outs14_t; 1611 1612 #define IIS2ICLX_FSM_OUTS15 0x5AU 1613 typedef struct 1614 { 1615 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1616 uint8_t n_v : 1; 1617 uint8_t p_v : 1; 1618 uint8_t n_z : 1; 1619 uint8_t p_z : 1; 1620 uint8_t n_y : 1; 1621 uint8_t p_y : 1; 1622 uint8_t n_x : 1; 1623 uint8_t p_x : 1; 1624 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1625 uint8_t p_x : 1; 1626 uint8_t n_x : 1; 1627 uint8_t p_y : 1; 1628 uint8_t n_y : 1; 1629 uint8_t p_z : 1; 1630 uint8_t n_z : 1; 1631 uint8_t p_v : 1; 1632 uint8_t n_v : 1; 1633 #endif /* DRV_BYTE_ORDER */ 1634 } iis2iclx_fsm_outs15_t; 1635 1636 #define IIS2ICLX_FSM_OUTS16 0x5BU 1637 typedef struct 1638 { 1639 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1640 uint8_t n_v : 1; 1641 uint8_t p_v : 1; 1642 uint8_t n_z : 1; 1643 uint8_t p_z : 1; 1644 uint8_t n_y : 1; 1645 uint8_t p_y : 1; 1646 uint8_t n_x : 1; 1647 uint8_t p_x : 1; 1648 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1649 uint8_t p_x : 1; 1650 uint8_t n_x : 1; 1651 uint8_t p_y : 1; 1652 uint8_t n_y : 1; 1653 uint8_t p_z : 1; 1654 uint8_t n_z : 1; 1655 uint8_t p_v : 1; 1656 uint8_t n_v : 1; 1657 #endif /* DRV_BYTE_ORDER */ 1658 } iis2iclx_fsm_outs16_t; 1659 1660 #define IIS2ICLX_EMB_FUNC_ODR_CFG_B 0x5FU 1661 typedef struct 1662 { 1663 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1664 uint8_t not_used_01 : 3; 1665 uint8_t fsm_odr : 2; 1666 uint8_t not_used_02 : 3; 1667 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1668 uint8_t not_used_02 : 3; 1669 uint8_t fsm_odr : 2; 1670 uint8_t not_used_01 : 3; 1671 #endif /* DRV_BYTE_ORDER */ 1672 } iis2iclx_emb_func_odr_cfg_b_t; 1673 1674 #define IIS2ICLX_EMB_FUNC_ODR_CFG_C 0x60U 1675 typedef struct 1676 { 1677 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1678 uint8_t not_used_01 : 4; 1679 uint8_t mlc_odr : 2; 1680 uint8_t not_used_02 : 2; 1681 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1682 uint8_t not_used_02 : 2; 1683 uint8_t mlc_odr : 2; 1684 uint8_t not_used_01 : 4; 1685 #endif /* DRV_BYTE_ORDER */ 1686 } iis2iclx_emb_func_odr_cfg_c_t; 1687 1688 #define IIS2ICLX_EMB_FUNC_INIT_B 0x67U 1689 typedef struct 1690 { 1691 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1692 uint8_t fsm_init : 1; 1693 uint8_t not_used_01 : 3; 1694 uint8_t mlc_init : 1; 1695 uint8_t not_used_02 : 3; 1696 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1697 uint8_t not_used_02 : 3; 1698 uint8_t mlc_init : 1; 1699 uint8_t not_used_01 : 3; 1700 uint8_t fsm_init : 1; 1701 #endif /* DRV_BYTE_ORDER */ 1702 } iis2iclx_emb_func_init_b_t; 1703 1704 #define IIS2ICLX_MLC0_SRC 0x70U 1705 #define IIS2ICLX_MLC1_SRC 0x71U 1706 #define IIS2ICLX_MLC2_SRC 0x72U 1707 #define IIS2ICLX_MLC3_SRC 0x73U 1708 #define IIS2ICLX_MLC4_SRC 0x74U 1709 #define IIS2ICLX_MLC5_SRC 0x75U 1710 #define IIS2ICLX_MLC6_SRC 0x76U 1711 #define IIS2ICLX_MLC7_SRC 0x77U 1712 1713 #define IIS2ICLX_FSM_LC_TIMEOUT_L 0x17AU 1714 #define IIS2ICLX_FSM_LC_TIMEOUT_H 0x17BU 1715 #define IIS2ICLX_FSM_PROGRAMS 0x17CU 1716 #define IIS2ICLX_FSM_START_ADD_L 0x17EU 1717 #define IIS2ICLX_FSM_START_ADD_H 0x17FU 1718 #define IIS2ICLX_SENSOR_HUB_1 0x02U 1719 typedef struct 1720 { 1721 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1722 uint8_t bit0 : 1; 1723 uint8_t bit1 : 1; 1724 uint8_t bit2 : 1; 1725 uint8_t bit3 : 1; 1726 uint8_t bit4 : 1; 1727 uint8_t bit5 : 1; 1728 uint8_t bit6 : 1; 1729 uint8_t bit7 : 1; 1730 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1731 uint8_t bit7 : 1; 1732 uint8_t bit6 : 1; 1733 uint8_t bit5 : 1; 1734 uint8_t bit4 : 1; 1735 uint8_t bit3 : 1; 1736 uint8_t bit2 : 1; 1737 uint8_t bit1 : 1; 1738 uint8_t bit0 : 1; 1739 #endif /* DRV_BYTE_ORDER */ 1740 } iis2iclx_sensor_hub_1_t; 1741 1742 #define IIS2ICLX_SENSOR_HUB_2 0x03U 1743 typedef struct 1744 { 1745 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1746 uint8_t bit0 : 1; 1747 uint8_t bit1 : 1; 1748 uint8_t bit2 : 1; 1749 uint8_t bit3 : 1; 1750 uint8_t bit4 : 1; 1751 uint8_t bit5 : 1; 1752 uint8_t bit6 : 1; 1753 uint8_t bit7 : 1; 1754 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1755 uint8_t bit7 : 1; 1756 uint8_t bit6 : 1; 1757 uint8_t bit5 : 1; 1758 uint8_t bit4 : 1; 1759 uint8_t bit3 : 1; 1760 uint8_t bit2 : 1; 1761 uint8_t bit1 : 1; 1762 uint8_t bit0 : 1; 1763 #endif /* DRV_BYTE_ORDER */ 1764 } iis2iclx_sensor_hub_2_t; 1765 1766 #define IIS2ICLX_SENSOR_HUB_3 0x04U 1767 typedef struct 1768 { 1769 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1770 uint8_t bit0 : 1; 1771 uint8_t bit1 : 1; 1772 uint8_t bit2 : 1; 1773 uint8_t bit3 : 1; 1774 uint8_t bit4 : 1; 1775 uint8_t bit5 : 1; 1776 uint8_t bit6 : 1; 1777 uint8_t bit7 : 1; 1778 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1779 uint8_t bit7 : 1; 1780 uint8_t bit6 : 1; 1781 uint8_t bit5 : 1; 1782 uint8_t bit4 : 1; 1783 uint8_t bit3 : 1; 1784 uint8_t bit2 : 1; 1785 uint8_t bit1 : 1; 1786 uint8_t bit0 : 1; 1787 #endif /* DRV_BYTE_ORDER */ 1788 } iis2iclx_sensor_hub_3_t; 1789 1790 #define IIS2ICLX_SENSOR_HUB_4 0x05U 1791 typedef struct 1792 { 1793 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1794 uint8_t bit0 : 1; 1795 uint8_t bit1 : 1; 1796 uint8_t bit2 : 1; 1797 uint8_t bit3 : 1; 1798 uint8_t bit4 : 1; 1799 uint8_t bit5 : 1; 1800 uint8_t bit6 : 1; 1801 uint8_t bit7 : 1; 1802 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1803 uint8_t bit7 : 1; 1804 uint8_t bit6 : 1; 1805 uint8_t bit5 : 1; 1806 uint8_t bit4 : 1; 1807 uint8_t bit3 : 1; 1808 uint8_t bit2 : 1; 1809 uint8_t bit1 : 1; 1810 uint8_t bit0 : 1; 1811 #endif /* DRV_BYTE_ORDER */ 1812 } iis2iclx_sensor_hub_4_t; 1813 1814 #define IIS2ICLX_SENSOR_HUB_5 0x06U 1815 typedef struct 1816 { 1817 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1818 uint8_t bit0 : 1; 1819 uint8_t bit1 : 1; 1820 uint8_t bit2 : 1; 1821 uint8_t bit3 : 1; 1822 uint8_t bit4 : 1; 1823 uint8_t bit5 : 1; 1824 uint8_t bit6 : 1; 1825 uint8_t bit7 : 1; 1826 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1827 uint8_t bit7 : 1; 1828 uint8_t bit6 : 1; 1829 uint8_t bit5 : 1; 1830 uint8_t bit4 : 1; 1831 uint8_t bit3 : 1; 1832 uint8_t bit2 : 1; 1833 uint8_t bit1 : 1; 1834 uint8_t bit0 : 1; 1835 #endif /* DRV_BYTE_ORDER */ 1836 } iis2iclx_sensor_hub_5_t; 1837 1838 #define IIS2ICLX_SENSOR_HUB_6 0x07U 1839 typedef struct 1840 { 1841 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1842 uint8_t bit0 : 1; 1843 uint8_t bit1 : 1; 1844 uint8_t bit2 : 1; 1845 uint8_t bit3 : 1; 1846 uint8_t bit4 : 1; 1847 uint8_t bit5 : 1; 1848 uint8_t bit6 : 1; 1849 uint8_t bit7 : 1; 1850 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1851 uint8_t bit7 : 1; 1852 uint8_t bit6 : 1; 1853 uint8_t bit5 : 1; 1854 uint8_t bit4 : 1; 1855 uint8_t bit3 : 1; 1856 uint8_t bit2 : 1; 1857 uint8_t bit1 : 1; 1858 uint8_t bit0 : 1; 1859 #endif /* DRV_BYTE_ORDER */ 1860 } iis2iclx_sensor_hub_6_t; 1861 1862 #define IIS2ICLX_SENSOR_HUB_7 0x08U 1863 typedef struct 1864 { 1865 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1866 uint8_t bit0 : 1; 1867 uint8_t bit1 : 1; 1868 uint8_t bit2 : 1; 1869 uint8_t bit3 : 1; 1870 uint8_t bit4 : 1; 1871 uint8_t bit5 : 1; 1872 uint8_t bit6 : 1; 1873 uint8_t bit7 : 1; 1874 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1875 uint8_t bit7 : 1; 1876 uint8_t bit6 : 1; 1877 uint8_t bit5 : 1; 1878 uint8_t bit4 : 1; 1879 uint8_t bit3 : 1; 1880 uint8_t bit2 : 1; 1881 uint8_t bit1 : 1; 1882 uint8_t bit0 : 1; 1883 #endif /* DRV_BYTE_ORDER */ 1884 } iis2iclx_sensor_hub_7_t; 1885 1886 #define IIS2ICLX_SENSOR_HUB_8 0x09U 1887 typedef struct 1888 { 1889 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1890 uint8_t bit0 : 1; 1891 uint8_t bit1 : 1; 1892 uint8_t bit2 : 1; 1893 uint8_t bit3 : 1; 1894 uint8_t bit4 : 1; 1895 uint8_t bit5 : 1; 1896 uint8_t bit6 : 1; 1897 uint8_t bit7 : 1; 1898 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1899 uint8_t bit7 : 1; 1900 uint8_t bit6 : 1; 1901 uint8_t bit5 : 1; 1902 uint8_t bit4 : 1; 1903 uint8_t bit3 : 1; 1904 uint8_t bit2 : 1; 1905 uint8_t bit1 : 1; 1906 uint8_t bit0 : 1; 1907 #endif /* DRV_BYTE_ORDER */ 1908 } iis2iclx_sensor_hub_8_t; 1909 1910 #define IIS2ICLX_SENSOR_HUB_9 0x0AU 1911 typedef struct 1912 { 1913 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1914 uint8_t bit0 : 1; 1915 uint8_t bit1 : 1; 1916 uint8_t bit2 : 1; 1917 uint8_t bit3 : 1; 1918 uint8_t bit4 : 1; 1919 uint8_t bit5 : 1; 1920 uint8_t bit6 : 1; 1921 uint8_t bit7 : 1; 1922 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1923 uint8_t bit7 : 1; 1924 uint8_t bit6 : 1; 1925 uint8_t bit5 : 1; 1926 uint8_t bit4 : 1; 1927 uint8_t bit3 : 1; 1928 uint8_t bit2 : 1; 1929 uint8_t bit1 : 1; 1930 uint8_t bit0 : 1; 1931 #endif /* DRV_BYTE_ORDER */ 1932 } iis2iclx_sensor_hub_9_t; 1933 1934 #define IIS2ICLX_SENSOR_HUB_10 0x0BU 1935 typedef struct 1936 { 1937 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1938 uint8_t bit0 : 1; 1939 uint8_t bit1 : 1; 1940 uint8_t bit2 : 1; 1941 uint8_t bit3 : 1; 1942 uint8_t bit4 : 1; 1943 uint8_t bit5 : 1; 1944 uint8_t bit6 : 1; 1945 uint8_t bit7 : 1; 1946 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1947 uint8_t bit7 : 1; 1948 uint8_t bit6 : 1; 1949 uint8_t bit5 : 1; 1950 uint8_t bit4 : 1; 1951 uint8_t bit3 : 1; 1952 uint8_t bit2 : 1; 1953 uint8_t bit1 : 1; 1954 uint8_t bit0 : 1; 1955 #endif /* DRV_BYTE_ORDER */ 1956 } iis2iclx_sensor_hub_10_t; 1957 1958 #define IIS2ICLX_SENSOR_HUB_11 0x0CU 1959 typedef struct 1960 { 1961 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1962 uint8_t bit0 : 1; 1963 uint8_t bit1 : 1; 1964 uint8_t bit2 : 1; 1965 uint8_t bit3 : 1; 1966 uint8_t bit4 : 1; 1967 uint8_t bit5 : 1; 1968 uint8_t bit6 : 1; 1969 uint8_t bit7 : 1; 1970 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1971 uint8_t bit7 : 1; 1972 uint8_t bit6 : 1; 1973 uint8_t bit5 : 1; 1974 uint8_t bit4 : 1; 1975 uint8_t bit3 : 1; 1976 uint8_t bit2 : 1; 1977 uint8_t bit1 : 1; 1978 uint8_t bit0 : 1; 1979 #endif /* DRV_BYTE_ORDER */ 1980 } iis2iclx_sensor_hub_11_t; 1981 1982 #define IIS2ICLX_SENSOR_HUB_12 0x0DU 1983 typedef struct 1984 { 1985 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1986 uint8_t bit0 : 1; 1987 uint8_t bit1 : 1; 1988 uint8_t bit2 : 1; 1989 uint8_t bit3 : 1; 1990 uint8_t bit4 : 1; 1991 uint8_t bit5 : 1; 1992 uint8_t bit6 : 1; 1993 uint8_t bit7 : 1; 1994 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1995 uint8_t bit7 : 1; 1996 uint8_t bit6 : 1; 1997 uint8_t bit5 : 1; 1998 uint8_t bit4 : 1; 1999 uint8_t bit3 : 1; 2000 uint8_t bit2 : 1; 2001 uint8_t bit1 : 1; 2002 uint8_t bit0 : 1; 2003 #endif /* DRV_BYTE_ORDER */ 2004 } iis2iclx_sensor_hub_12_t; 2005 2006 #define IIS2ICLX_SENSOR_HUB_13 0x0EU 2007 typedef struct 2008 { 2009 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2010 uint8_t bit0 : 1; 2011 uint8_t bit1 : 1; 2012 uint8_t bit2 : 1; 2013 uint8_t bit3 : 1; 2014 uint8_t bit4 : 1; 2015 uint8_t bit5 : 1; 2016 uint8_t bit6 : 1; 2017 uint8_t bit7 : 1; 2018 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2019 uint8_t bit7 : 1; 2020 uint8_t bit6 : 1; 2021 uint8_t bit5 : 1; 2022 uint8_t bit4 : 1; 2023 uint8_t bit3 : 1; 2024 uint8_t bit2 : 1; 2025 uint8_t bit1 : 1; 2026 uint8_t bit0 : 1; 2027 #endif /* DRV_BYTE_ORDER */ 2028 } iis2iclx_sensor_hub_13_t; 2029 2030 #define IIS2ICLX_SENSOR_HUB_14 0x0FU 2031 typedef struct 2032 { 2033 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2034 uint8_t bit0 : 1; 2035 uint8_t bit1 : 1; 2036 uint8_t bit2 : 1; 2037 uint8_t bit3 : 1; 2038 uint8_t bit4 : 1; 2039 uint8_t bit5 : 1; 2040 uint8_t bit6 : 1; 2041 uint8_t bit7 : 1; 2042 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2043 uint8_t bit7 : 1; 2044 uint8_t bit6 : 1; 2045 uint8_t bit5 : 1; 2046 uint8_t bit4 : 1; 2047 uint8_t bit3 : 1; 2048 uint8_t bit2 : 1; 2049 uint8_t bit1 : 1; 2050 uint8_t bit0 : 1; 2051 #endif /* DRV_BYTE_ORDER */ 2052 } iis2iclx_sensor_hub_14_t; 2053 2054 #define IIS2ICLX_SENSOR_HUB_15 0x10U 2055 typedef struct 2056 { 2057 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2058 uint8_t bit0 : 1; 2059 uint8_t bit1 : 1; 2060 uint8_t bit2 : 1; 2061 uint8_t bit3 : 1; 2062 uint8_t bit4 : 1; 2063 uint8_t bit5 : 1; 2064 uint8_t bit6 : 1; 2065 uint8_t bit7 : 1; 2066 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2067 uint8_t bit7 : 1; 2068 uint8_t bit6 : 1; 2069 uint8_t bit5 : 1; 2070 uint8_t bit4 : 1; 2071 uint8_t bit3 : 1; 2072 uint8_t bit2 : 1; 2073 uint8_t bit1 : 1; 2074 uint8_t bit0 : 1; 2075 #endif /* DRV_BYTE_ORDER */ 2076 } iis2iclx_sensor_hub_15_t; 2077 2078 #define IIS2ICLX_SENSOR_HUB_16 0x11U 2079 typedef struct 2080 { 2081 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2082 uint8_t bit0 : 1; 2083 uint8_t bit1 : 1; 2084 uint8_t bit2 : 1; 2085 uint8_t bit3 : 1; 2086 uint8_t bit4 : 1; 2087 uint8_t bit5 : 1; 2088 uint8_t bit6 : 1; 2089 uint8_t bit7 : 1; 2090 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2091 uint8_t bit7 : 1; 2092 uint8_t bit6 : 1; 2093 uint8_t bit5 : 1; 2094 uint8_t bit4 : 1; 2095 uint8_t bit3 : 1; 2096 uint8_t bit2 : 1; 2097 uint8_t bit1 : 1; 2098 uint8_t bit0 : 1; 2099 #endif /* DRV_BYTE_ORDER */ 2100 } iis2iclx_sensor_hub_16_t; 2101 2102 #define IIS2ICLX_SENSOR_HUB_17 0x12U 2103 typedef struct 2104 { 2105 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2106 uint8_t bit0 : 1; 2107 uint8_t bit1 : 1; 2108 uint8_t bit2 : 1; 2109 uint8_t bit3 : 1; 2110 uint8_t bit4 : 1; 2111 uint8_t bit5 : 1; 2112 uint8_t bit6 : 1; 2113 uint8_t bit7 : 1; 2114 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2115 uint8_t bit7 : 1; 2116 uint8_t bit6 : 1; 2117 uint8_t bit5 : 1; 2118 uint8_t bit4 : 1; 2119 uint8_t bit3 : 1; 2120 uint8_t bit2 : 1; 2121 uint8_t bit1 : 1; 2122 uint8_t bit0 : 1; 2123 #endif /* DRV_BYTE_ORDER */ 2124 } iis2iclx_sensor_hub_17_t; 2125 2126 #define IIS2ICLX_SENSOR_HUB_18 0x13U 2127 typedef struct 2128 { 2129 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2130 uint8_t bit0 : 1; 2131 uint8_t bit1 : 1; 2132 uint8_t bit2 : 1; 2133 uint8_t bit3 : 1; 2134 uint8_t bit4 : 1; 2135 uint8_t bit5 : 1; 2136 uint8_t bit6 : 1; 2137 uint8_t bit7 : 1; 2138 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2139 uint8_t bit7 : 1; 2140 uint8_t bit6 : 1; 2141 uint8_t bit5 : 1; 2142 uint8_t bit4 : 1; 2143 uint8_t bit3 : 1; 2144 uint8_t bit2 : 1; 2145 uint8_t bit1 : 1; 2146 uint8_t bit0 : 1; 2147 #endif /* DRV_BYTE_ORDER */ 2148 } iis2iclx_sensor_hub_18_t; 2149 2150 #define IIS2ICLX_MASTER_CONFIG 0x14U 2151 typedef struct 2152 { 2153 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2154 uint8_t aux_sens_on : 2; 2155 uint8_t master_on : 1; 2156 uint8_t shub_pu_en : 1; 2157 uint8_t pass_through_mode : 1; 2158 uint8_t start_config : 1; 2159 uint8_t write_once : 1; 2160 uint8_t rst_master_regs : 1; 2161 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2162 uint8_t rst_master_regs : 1; 2163 uint8_t write_once : 1; 2164 uint8_t start_config : 1; 2165 uint8_t pass_through_mode : 1; 2166 uint8_t shub_pu_en : 1; 2167 uint8_t master_on : 1; 2168 uint8_t aux_sens_on : 2; 2169 #endif /* DRV_BYTE_ORDER */ 2170 } iis2iclx_master_config_t; 2171 2172 #define IIS2ICLX_SLV0_ADD 0x15U 2173 typedef struct 2174 { 2175 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2176 uint8_t rw_0 : 1; 2177 uint8_t slave0 : 7; 2178 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2179 uint8_t slave0 : 7; 2180 uint8_t rw_0 : 1; 2181 #endif /* DRV_BYTE_ORDER */ 2182 } iis2iclx_slv0_add_t; 2183 2184 #define IIS2ICLX_SLV0_SUBADD 0x16U 2185 typedef struct 2186 { 2187 uint8_t slave0_reg : 8; 2188 } iis2iclx_slv0_subadd_t; 2189 2190 #define IIS2ICLX_SLV0_CONFIG 0x17U 2191 typedef struct 2192 { 2193 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2194 uint8_t slave0_numop : 3; 2195 uint8_t batch_ext_sens_0_en : 1; 2196 uint8_t not_used_01 : 2; 2197 uint8_t shub_odr : 2; 2198 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2199 uint8_t shub_odr : 2; 2200 uint8_t not_used_01 : 2; 2201 uint8_t batch_ext_sens_0_en : 1; 2202 uint8_t slave0_numop : 3; 2203 #endif /* DRV_BYTE_ORDER */ 2204 } iis2iclx_slv0_config_t; 2205 2206 #define IIS2ICLX_SLV1_ADD 0x18U 2207 typedef struct 2208 { 2209 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2210 uint8_t r_1 : 1; 2211 uint8_t slave1_add : 7; 2212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2213 uint8_t slave1_add : 7; 2214 uint8_t r_1 : 1; 2215 #endif /* DRV_BYTE_ORDER */ 2216 } iis2iclx_slv1_add_t; 2217 2218 #define IIS2ICLX_SLV1_SUBADD 0x19U 2219 typedef struct 2220 { 2221 uint8_t slave1_reg : 8; 2222 } iis2iclx_slv1_subadd_t; 2223 2224 #define IIS2ICLX_SLV1_CONFIG 0x1AU 2225 typedef struct 2226 { 2227 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2228 uint8_t slave1_numop : 3; 2229 uint8_t batch_ext_sens_1_en : 1; 2230 uint8_t not_used_01 : 4; 2231 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2232 uint8_t not_used_01 : 4; 2233 uint8_t batch_ext_sens_1_en : 1; 2234 uint8_t slave1_numop : 3; 2235 #endif /* DRV_BYTE_ORDER */ 2236 } iis2iclx_slv1_config_t; 2237 2238 #define IIS2ICLX_SLV2_ADD 0x1BU 2239 typedef struct 2240 { 2241 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2242 uint8_t r_2 : 1; 2243 uint8_t slave2_add : 7; 2244 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2245 uint8_t slave2_add : 7; 2246 uint8_t r_2 : 1; 2247 #endif /* DRV_BYTE_ORDER */ 2248 } iis2iclx_slv2_add_t; 2249 2250 #define IIS2ICLX_SLV2_SUBADD 0x1CU 2251 typedef struct 2252 { 2253 uint8_t slave2_reg : 8; 2254 } iis2iclx_slv2_subadd_t; 2255 2256 #define IIS2ICLX_SLV2_CONFIG 0x1DU 2257 typedef struct 2258 { 2259 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2260 uint8_t slave2_numop : 3; 2261 uint8_t batch_ext_sens_2_en : 1; 2262 uint8_t not_used_01 : 4; 2263 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2264 uint8_t not_used_01 : 4; 2265 uint8_t batch_ext_sens_2_en : 1; 2266 uint8_t slave2_numop : 3; 2267 #endif /* DRV_BYTE_ORDER */ 2268 } iis2iclx_slv2_config_t; 2269 2270 #define IIS2ICLX_SLV3_ADD 0x1EU 2271 typedef struct 2272 { 2273 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2274 uint8_t r_3 : 1; 2275 uint8_t slave3_add : 7; 2276 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2277 uint8_t slave3_add : 7; 2278 uint8_t r_3 : 1; 2279 #endif /* DRV_BYTE_ORDER */ 2280 } iis2iclx_slv3_add_t; 2281 2282 #define IIS2ICLX_SLV3_SUBADD 0x1FU 2283 typedef struct 2284 { 2285 uint8_t slave3_reg : 8; 2286 } iis2iclx_slv3_subadd_t; 2287 2288 #define IIS2ICLX_SLV3_CONFIG 0x20U 2289 typedef struct 2290 { 2291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2292 uint8_t slave3_numop : 3; 2293 uint8_t batch_ext_sens_3_en : 1; 2294 uint8_t not_used_01 : 4; 2295 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2296 uint8_t not_used_01 : 4; 2297 uint8_t batch_ext_sens_3_en : 1; 2298 uint8_t slave3_numop : 3; 2299 #endif /* DRV_BYTE_ORDER */ 2300 } iis2iclx_slv3_config_t; 2301 2302 #define IIS2ICLX_DATAWRITE_SLV0 0x21U 2303 typedef struct 2304 { 2305 uint8_t slave0_dataw : 8; 2306 } iis2iclx_datawrite_slv0_t; 2307 2308 #define IIS2ICLX_STATUS_MASTER 0x22U 2309 typedef struct 2310 { 2311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2312 uint8_t sens_hub_endop : 1; 2313 uint8_t not_used_01 : 2; 2314 uint8_t slave0_nack : 1; 2315 uint8_t slave1_nack : 1; 2316 uint8_t slave2_nack : 1; 2317 uint8_t slave3_nack : 1; 2318 uint8_t wr_once_done : 1; 2319 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2320 uint8_t wr_once_done : 1; 2321 uint8_t slave3_nack : 1; 2322 uint8_t slave2_nack : 1; 2323 uint8_t slave1_nack : 1; 2324 uint8_t slave0_nack : 1; 2325 uint8_t not_used_01 : 2; 2326 uint8_t sens_hub_endop : 1; 2327 #endif /* DRV_BYTE_ORDER */ 2328 } iis2iclx_status_master_t; 2329 2330 /** 2331 * @defgroup IIS2ICLX_Register_Union 2332 * @brief This union group all the registers having a bit-field 2333 * description. 2334 * This union is useful but it's not needed by the driver. 2335 * 2336 * REMOVING this union you are compliant with: 2337 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2338 * 2339 * @{ 2340 * 2341 */ 2342 typedef union 2343 { 2344 iis2iclx_func_cfg_access_t func_cfg_access; 2345 iis2iclx_pin_ctrl_t pin_ctrl; 2346 iis2iclx_fifo_ctrl1_t fifo_ctrl1; 2347 iis2iclx_fifo_ctrl2_t fifo_ctrl2; 2348 iis2iclx_fifo_ctrl3_t fifo_ctrl3; 2349 iis2iclx_fifo_ctrl4_t fifo_ctrl4; 2350 iis2iclx_counter_bdr_reg1_t counter_bdr_reg1; 2351 iis2iclx_counter_bdr_reg2_t counter_bdr_reg2; 2352 iis2iclx_int1_ctrl_t int1_ctrl; 2353 iis2iclx_int2_ctrl_t int2_ctrl; 2354 iis2iclx_ctrl1_xl_t ctrl1_xl; 2355 iis2iclx_ctrl3_c_t ctrl3_c; 2356 iis2iclx_ctrl4_c_t ctrl4_c; 2357 iis2iclx_ctrl5_c_t ctrl5_c; 2358 iis2iclx_ctrl6_c_t ctrl6_c; 2359 iis2iclx_ctrl7_xl_t ctrl7_xl; 2360 iis2iclx_ctrl8_xl_t ctrl8_xl; 2361 iis2iclx_ctrl9_xl_t ctrl9_xl; 2362 iis2iclx_ctrl10_c_t ctrl10_c; 2363 iis2iclx_all_int_src_t all_int_src; 2364 iis2iclx_wake_up_src_t wake_up_src; 2365 iis2iclx_tap_src_t tap_src; 2366 iis2iclx_den_src_t den_src; 2367 iis2iclx_status_reg_t status_reg; 2368 iis2iclx_fifo_status1_t fifo_status1; 2369 iis2iclx_fifo_status2_t fifo_status2; 2370 iis2iclx_tap_cfg0_t tap_cfg0; 2371 iis2iclx_tap_cfg1_t tap_cfg1; 2372 iis2iclx_tap_cfg2_t tap_cfg2; 2373 iis2iclx_int_dur2_t int_dur2; 2374 iis2iclx_wake_up_ths_t wake_up_ths; 2375 iis2iclx_wake_up_dur_t wake_up_dur; 2376 iis2iclx_md1_cfg_t md1_cfg; 2377 iis2iclx_md2_cfg_t md2_cfg; 2378 iis2iclx_internal_freq_fine_t internal_freq_fine; 2379 iis2iclx_fifo_data_out_tag_t fifo_data_out_tag; 2380 iis2iclx_page_sel_t page_sel; 2381 iis2iclx_emb_func_en_b_t emb_func_en_b; 2382 iis2iclx_page_address_t page_address; 2383 iis2iclx_page_value_t page_value; 2384 iis2iclx_emb_func_int1_t emb_func_int1; 2385 iis2iclx_fsm_int1_a_t fsm_int1_a; 2386 iis2iclx_fsm_int1_b_t fsm_int1_b; 2387 iis2iclx_mlc_int1_t mlc_int1; 2388 iis2iclx_emb_func_int2_t emb_func_int2; 2389 iis2iclx_fsm_int2_a_t fsm_int2_a; 2390 iis2iclx_fsm_int2_b_t fsm_int2_b; 2391 iis2iclx_mlc_int2_t mlc_int2; 2392 iis2iclx_emb_func_status_t emb_func_status; 2393 iis2iclx_fsm_status_a_t fsm_status_a; 2394 iis2iclx_fsm_status_b_t fsm_status_b; 2395 iis2iclx_mlc_status_mainpage_t mlc_status_mainpage; 2396 iis2iclx_emb_func_odr_cfg_c_t emb_func_odr_cfg_c; 2397 iis2iclx_page_rw_t page_rw; 2398 iis2iclx_fsm_enable_a_t fsm_enable_a; 2399 iis2iclx_fsm_enable_b_t fsm_enable_b; 2400 iis2iclx_fsm_long_counter_clear_t fsm_long_counter_clear; 2401 iis2iclx_fsm_outs1_t fsm_outs1; 2402 iis2iclx_fsm_outs2_t fsm_outs2; 2403 iis2iclx_fsm_outs3_t fsm_outs3; 2404 iis2iclx_fsm_outs4_t fsm_outs4; 2405 iis2iclx_fsm_outs5_t fsm_outs5; 2406 iis2iclx_fsm_outs6_t fsm_outs6; 2407 iis2iclx_fsm_outs7_t fsm_outs7; 2408 iis2iclx_fsm_outs8_t fsm_outs8; 2409 iis2iclx_fsm_outs9_t fsm_outs9; 2410 iis2iclx_fsm_outs10_t fsm_outs10; 2411 iis2iclx_fsm_outs11_t fsm_outs11; 2412 iis2iclx_fsm_outs12_t fsm_outs12; 2413 iis2iclx_fsm_outs13_t fsm_outs13; 2414 iis2iclx_fsm_outs14_t fsm_outs14; 2415 iis2iclx_fsm_outs15_t fsm_outs15; 2416 iis2iclx_fsm_outs16_t fsm_outs16; 2417 iis2iclx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 2418 iis2iclx_emb_func_init_b_t emb_func_init_b; 2419 iis2iclx_sensor_hub_1_t sensor_hub_1; 2420 iis2iclx_sensor_hub_2_t sensor_hub_2; 2421 iis2iclx_sensor_hub_3_t sensor_hub_3; 2422 iis2iclx_sensor_hub_4_t sensor_hub_4; 2423 iis2iclx_sensor_hub_5_t sensor_hub_5; 2424 iis2iclx_sensor_hub_6_t sensor_hub_6; 2425 iis2iclx_sensor_hub_7_t sensor_hub_7; 2426 iis2iclx_sensor_hub_8_t sensor_hub_8; 2427 iis2iclx_sensor_hub_9_t sensor_hub_9; 2428 iis2iclx_sensor_hub_10_t sensor_hub_10; 2429 iis2iclx_sensor_hub_11_t sensor_hub_11; 2430 iis2iclx_sensor_hub_12_t sensor_hub_12; 2431 iis2iclx_sensor_hub_13_t sensor_hub_13; 2432 iis2iclx_sensor_hub_14_t sensor_hub_14; 2433 iis2iclx_sensor_hub_15_t sensor_hub_15; 2434 iis2iclx_sensor_hub_16_t sensor_hub_16; 2435 iis2iclx_sensor_hub_17_t sensor_hub_17; 2436 iis2iclx_sensor_hub_18_t sensor_hub_18; 2437 iis2iclx_master_config_t master_config; 2438 iis2iclx_slv0_add_t slv0_add; 2439 iis2iclx_slv0_subadd_t slv0_subadd; 2440 iis2iclx_slv0_config_t slv0_config; 2441 iis2iclx_slv1_add_t slv1_add; 2442 iis2iclx_slv1_subadd_t slv1_subadd; 2443 iis2iclx_slv1_config_t slv1_config; 2444 iis2iclx_slv2_add_t slv2_add; 2445 iis2iclx_slv2_subadd_t slv2_subadd; 2446 iis2iclx_slv2_config_t slv2_config; 2447 iis2iclx_slv3_add_t slv3_add; 2448 iis2iclx_slv3_subadd_t slv3_subadd; 2449 iis2iclx_slv3_config_t slv3_config; 2450 iis2iclx_datawrite_slv0_t datawrite_slv0; 2451 iis2iclx_status_master_t status_master; 2452 bitwise_t bitwise; 2453 uint8_t byte; 2454 } iis2iclx_reg_t; 2455 2456 /** 2457 * @} 2458 * 2459 */ 2460 2461 #ifndef __weak 2462 #define __weak __attribute__((weak)) 2463 #endif /* __weak */ 2464 2465 /* 2466 * These are the basic platform dependent I/O routines to read 2467 * and write device registers connected on a standard bus. 2468 * The driver keeps offering a default implementation based on function 2469 * pointers to read/write routines for backward compatibility. 2470 * The __weak directive allows the final application to overwrite 2471 * them with a custom implementation. 2472 */ 2473 2474 int32_t iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 2475 uint8_t *data, 2476 uint16_t len); 2477 int32_t iis2iclx_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 2478 uint8_t *data, 2479 uint16_t len); 2480 2481 float_t iis2iclx_from_fs500mg_to_mg(int16_t lsb); 2482 float_t iis2iclx_from_fs1g_to_mg(int16_t lsb); 2483 float_t iis2iclx_from_fs2g_to_mg(int16_t lsb); 2484 float_t iis2iclx_from_fs3g_to_mg(int16_t lsb); 2485 2486 float_t iis2iclx_from_lsb_to_celsius(int16_t lsb); 2487 2488 float_t iis2iclx_from_lsb_to_nsec(int32_t lsb); 2489 2490 typedef enum 2491 { 2492 IIS2ICLX_500mg = 0, 2493 IIS2ICLX_3g = 1, 2494 IIS2ICLX_1g = 2, 2495 IIS2ICLX_2g = 3, 2496 } iis2iclx_fs_xl_t; 2497 int32_t iis2iclx_xl_full_scale_set(stmdev_ctx_t *ctx, 2498 iis2iclx_fs_xl_t val); 2499 int32_t iis2iclx_xl_full_scale_get(stmdev_ctx_t *ctx, 2500 iis2iclx_fs_xl_t *val); 2501 2502 typedef enum 2503 { 2504 IIS2ICLX_XL_ODR_OFF = 0, 2505 IIS2ICLX_XL_ODR_12Hz5 = 1, 2506 IIS2ICLX_XL_ODR_26Hz = 2, 2507 IIS2ICLX_XL_ODR_52Hz = 3, 2508 IIS2ICLX_XL_ODR_104Hz = 4, 2509 IIS2ICLX_XL_ODR_208Hz = 5, 2510 IIS2ICLX_XL_ODR_416Hz = 6, 2511 IIS2ICLX_XL_ODR_833Hz = 7, 2512 } iis2iclx_odr_xl_t; 2513 int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx, 2514 iis2iclx_odr_xl_t val); 2515 int32_t iis2iclx_xl_data_rate_get(stmdev_ctx_t *ctx, 2516 iis2iclx_odr_xl_t *val); 2517 2518 int32_t iis2iclx_block_data_update_set(stmdev_ctx_t *ctx, 2519 uint8_t val); 2520 int32_t iis2iclx_block_data_update_get(stmdev_ctx_t *ctx, 2521 uint8_t *val); 2522 2523 typedef enum 2524 { 2525 IIS2ICLX_LSb_1mg = 0, 2526 IIS2ICLX_LSb_16mg = 1, 2527 } iis2iclx_usr_off_w_t; 2528 int32_t iis2iclx_xl_offset_weight_set(stmdev_ctx_t *ctx, 2529 iis2iclx_usr_off_w_t val); 2530 int32_t iis2iclx_xl_offset_weight_get(stmdev_ctx_t *ctx, 2531 iis2iclx_usr_off_w_t *val); 2532 2533 typedef enum 2534 { 2535 IIS2ICLX_HIGH_PERFORMANCE_MD = 0, 2536 IIS2ICLX_LOW_NORMAL_POWER_MD = 1, 2537 } iis2iclx_xl_hm_mode_t; 2538 int32_t iis2iclx_xl_power_mode_set(stmdev_ctx_t *ctx, 2539 iis2iclx_xl_hm_mode_t val); 2540 int32_t iis2iclx_xl_power_mode_get(stmdev_ctx_t *ctx, 2541 iis2iclx_xl_hm_mode_t *val); 2542 2543 typedef enum 2544 { 2545 IIS2ICLX_GY_HIGH_PERFORMANCE = 0, 2546 IIS2ICLX_GY_NORMAL = 1, 2547 } iis2iclx_g_hm_mode_t; 2548 int32_t iis2iclx_gy_power_mode_set(stmdev_ctx_t *ctx, 2549 iis2iclx_g_hm_mode_t val); 2550 int32_t iis2iclx_gy_power_mode_get(stmdev_ctx_t *ctx, 2551 iis2iclx_g_hm_mode_t *val); 2552 2553 typedef struct 2554 { 2555 iis2iclx_all_int_src_t all_int_src; 2556 iis2iclx_wake_up_src_t wake_up_src; 2557 iis2iclx_tap_src_t tap_src; 2558 iis2iclx_den_src_t den_src; 2559 iis2iclx_status_reg_t status_reg; 2560 iis2iclx_emb_func_status_t emb_func_status; 2561 iis2iclx_fsm_status_a_t fsm_status_a; 2562 iis2iclx_fsm_status_b_t fsm_status_b; 2563 } iis2iclx_all_sources_t; 2564 int32_t iis2iclx_all_sources_get(stmdev_ctx_t *ctx, 2565 iis2iclx_all_sources_t *val); 2566 2567 int32_t iis2iclx_status_reg_get(stmdev_ctx_t *ctx, 2568 iis2iclx_status_reg_t *val); 2569 2570 int32_t iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t *ctx, 2571 uint8_t *val); 2572 2573 int32_t iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t *ctx, 2574 uint8_t *val); 2575 2576 int32_t iis2iclx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, 2577 uint8_t *buff); 2578 int32_t iis2iclx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, 2579 uint8_t *buff); 2580 2581 int32_t iis2iclx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, 2582 uint8_t *buff); 2583 int32_t iis2iclx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, 2584 uint8_t *buff); 2585 2586 int32_t iis2iclx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val); 2587 int32_t iis2iclx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val); 2588 2589 int32_t iis2iclx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); 2590 int32_t iis2iclx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); 2591 2592 int32_t iis2iclx_timestamp_raw_get(stmdev_ctx_t *ctx, int32_t *val); 2593 2594 int32_t iis2iclx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 2595 2596 int32_t iis2iclx_acceleration_raw_get(stmdev_ctx_t *ctx, 2597 int16_t *val); 2598 2599 int32_t iis2iclx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); 2600 2601 int32_t iis2iclx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val); 2602 int32_t iis2iclx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val); 2603 2604 int32_t iis2iclx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val); 2605 int32_t iis2iclx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val); 2606 2607 typedef enum 2608 { 2609 IIS2ICLX_USER_BANK = 0, 2610 IIS2ICLX_SENSOR_HUB_BANK = 1, 2611 IIS2ICLX_EMBEDDED_FUNC_BANK = 2, 2612 } iis2iclx_reg_access_t; 2613 int32_t iis2iclx_mem_bank_set(stmdev_ctx_t *ctx, 2614 iis2iclx_reg_access_t val); 2615 int32_t iis2iclx_mem_bank_get(stmdev_ctx_t *ctx, 2616 iis2iclx_reg_access_t *val); 2617 2618 int32_t iis2iclx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address, 2619 uint8_t *val); 2620 int32_t iis2iclx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address, 2621 uint8_t *buf, uint8_t len); 2622 int32_t iis2iclx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add, 2623 uint8_t *val); 2624 int32_t iis2iclx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address, 2625 uint8_t *val); 2626 2627 typedef enum 2628 { 2629 IIS2ICLX_DRDY_LATCHED = 0, 2630 IIS2ICLX_DRDY_PULSED = 1, 2631 } iis2iclx_dataready_pulsed_t; 2632 int32_t iis2iclx_data_ready_mode_set(stmdev_ctx_t *ctx, 2633 iis2iclx_dataready_pulsed_t val); 2634 int32_t iis2iclx_data_ready_mode_get(stmdev_ctx_t *ctx, 2635 iis2iclx_dataready_pulsed_t *val); 2636 2637 int32_t iis2iclx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 2638 2639 int32_t iis2iclx_reset_set(stmdev_ctx_t *ctx, uint8_t val); 2640 int32_t iis2iclx_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 2641 2642 int32_t iis2iclx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); 2643 int32_t iis2iclx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); 2644 2645 int32_t iis2iclx_boot_set(stmdev_ctx_t *ctx, uint8_t val); 2646 int32_t iis2iclx_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 2647 2648 typedef enum 2649 { 2650 IIS2ICLX_XL_ST_DISABLE = 0, 2651 IIS2ICLX_XL_ST_POSITIVE = 1, 2652 IIS2ICLX_XL_ST_NEGATIVE = 2, 2653 } iis2iclx_st_xl_t; 2654 int32_t iis2iclx_xl_self_test_set(stmdev_ctx_t *ctx, 2655 iis2iclx_st_xl_t val); 2656 int32_t iis2iclx_xl_self_test_get(stmdev_ctx_t *ctx, 2657 iis2iclx_st_xl_t *val); 2658 2659 int32_t iis2iclx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val); 2660 int32_t iis2iclx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val); 2661 2662 int32_t iis2iclx_filter_settling_mask_set(stmdev_ctx_t *ctx, 2663 uint8_t val); 2664 int32_t iis2iclx_filter_settling_mask_get(stmdev_ctx_t *ctx, 2665 uint8_t *val); 2666 2667 typedef enum 2668 { 2669 IIS2ICLX_HP_PATH_DISABLE_ON_OUT = 0x00, 2670 IIS2ICLX_SLOPE_ODR_DIV_4 = 0x10, 2671 IIS2ICLX_HP_ODR_DIV_10 = 0x11, 2672 IIS2ICLX_HP_ODR_DIV_20 = 0x12, 2673 IIS2ICLX_HP_ODR_DIV_45 = 0x13, 2674 IIS2ICLX_HP_ODR_DIV_100 = 0x14, 2675 IIS2ICLX_HP_ODR_DIV_200 = 0x15, 2676 IIS2ICLX_HP_ODR_DIV_400 = 0x16, 2677 IIS2ICLX_HP_ODR_DIV_800 = 0x17, 2678 IIS2ICLX_HP_REF_MD_ODR_DIV_10 = 0x31, 2679 IIS2ICLX_HP_REF_MD_ODR_DIV_20 = 0x32, 2680 IIS2ICLX_HP_REF_MD_ODR_DIV_45 = 0x33, 2681 IIS2ICLX_HP_REF_MD_ODR_DIV_100 = 0x34, 2682 IIS2ICLX_HP_REF_MD_ODR_DIV_200 = 0x35, 2683 IIS2ICLX_HP_REF_MD_ODR_DIV_400 = 0x36, 2684 IIS2ICLX_HP_REF_MD_ODR_DIV_800 = 0x37, 2685 IIS2ICLX_LP_ODR_DIV_10 = 0x01, 2686 IIS2ICLX_LP_ODR_DIV_20 = 0x02, 2687 IIS2ICLX_LP_ODR_DIV_45 = 0x03, 2688 IIS2ICLX_LP_ODR_DIV_100 = 0x04, 2689 IIS2ICLX_LP_ODR_DIV_200 = 0x05, 2690 IIS2ICLX_LP_ODR_DIV_400 = 0x06, 2691 IIS2ICLX_LP_ODR_DIV_800 = 0x07, 2692 } iis2iclx_hp_slope_xl_en_t; 2693 int32_t iis2iclx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx, 2694 iis2iclx_hp_slope_xl_en_t val); 2695 int32_t iis2iclx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx, 2696 iis2iclx_hp_slope_xl_en_t *val); 2697 2698 int32_t iis2iclx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val); 2699 int32_t iis2iclx_xl_fast_settling_get(stmdev_ctx_t *ctx, 2700 uint8_t *val); 2701 2702 typedef enum 2703 { 2704 IIS2ICLX_USE_SLOPE = 0, 2705 IIS2ICLX_USE_HPF = 1, 2706 } iis2iclx_slope_fds_t; 2707 int32_t iis2iclx_xl_hp_path_internal_set(stmdev_ctx_t *ctx, 2708 iis2iclx_slope_fds_t val); 2709 int32_t iis2iclx_xl_hp_path_internal_get(stmdev_ctx_t *ctx, 2710 iis2iclx_slope_fds_t *val); 2711 2712 typedef enum 2713 { 2714 IIS2ICLX_PULL_UP_DISC = 0, 2715 IIS2ICLX_PULL_UP_CONNECT = 1, 2716 } iis2iclx_sdo_pu_en_t; 2717 int32_t iis2iclx_sdo_sa0_mode_set(stmdev_ctx_t *ctx, 2718 iis2iclx_sdo_pu_en_t val); 2719 int32_t iis2iclx_sdo_sa0_mode_get(stmdev_ctx_t *ctx, 2720 iis2iclx_sdo_pu_en_t *val); 2721 2722 typedef enum 2723 { 2724 IIS2ICLX_SPI_4_WIRE = 0, 2725 IIS2ICLX_SPI_3_WIRE = 1, 2726 } iis2iclx_sim_t; 2727 int32_t iis2iclx_spi_mode_set(stmdev_ctx_t *ctx, iis2iclx_sim_t val); 2728 int32_t iis2iclx_spi_mode_get(stmdev_ctx_t *ctx, iis2iclx_sim_t *val); 2729 2730 typedef enum 2731 { 2732 IIS2ICLX_I2C_ENABLE = 0, 2733 IIS2ICLX_I2C_DISABLE = 1, 2734 } iis2iclx_i2c_disable_t; 2735 int32_t iis2iclx_i2c_interface_set(stmdev_ctx_t *ctx, 2736 iis2iclx_i2c_disable_t val); 2737 int32_t iis2iclx_i2c_interface_get(stmdev_ctx_t *ctx, 2738 iis2iclx_i2c_disable_t *val); 2739 2740 typedef struct 2741 { 2742 iis2iclx_int1_ctrl_t int1_ctrl; 2743 iis2iclx_md1_cfg_t md1_cfg; 2744 iis2iclx_emb_func_int1_t emb_func_int1; 2745 iis2iclx_fsm_int1_a_t fsm_int1_a; 2746 iis2iclx_fsm_int1_b_t fsm_int1_b; 2747 iis2iclx_mlc_int1_t mlc_int1; 2748 } iis2iclx_pin_int1_route_t; 2749 int32_t iis2iclx_pin_int1_route_set(stmdev_ctx_t *ctx, 2750 iis2iclx_pin_int1_route_t *val); 2751 int32_t iis2iclx_pin_int1_route_get(stmdev_ctx_t *ctx, 2752 iis2iclx_pin_int1_route_t *val); 2753 2754 typedef struct 2755 { 2756 iis2iclx_int2_ctrl_t int2_ctrl; 2757 iis2iclx_md2_cfg_t md2_cfg; 2758 iis2iclx_emb_func_int2_t emb_func_int2; 2759 iis2iclx_fsm_int2_a_t fsm_int2_a; 2760 iis2iclx_fsm_int2_b_t fsm_int2_b; 2761 iis2iclx_mlc_int2_t mlc_int2; 2762 } iis2iclx_pin_int2_route_t; 2763 int32_t iis2iclx_pin_int2_route_set(stmdev_ctx_t *ctx, 2764 iis2iclx_pin_int2_route_t *val); 2765 int32_t iis2iclx_pin_int2_route_get(stmdev_ctx_t *ctx, 2766 iis2iclx_pin_int2_route_t *val); 2767 2768 typedef enum 2769 { 2770 IIS2ICLX_PUSH_PULL = 0, 2771 IIS2ICLX_OPEN_DRAIN = 1, 2772 } iis2iclx_pp_od_t; 2773 int32_t iis2iclx_pin_mode_set(stmdev_ctx_t *ctx, 2774 iis2iclx_pp_od_t val); 2775 int32_t iis2iclx_pin_mode_get(stmdev_ctx_t *ctx, 2776 iis2iclx_pp_od_t *val); 2777 2778 typedef enum 2779 { 2780 IIS2ICLX_ACTIVE_HIGH = 0, 2781 IIS2ICLX_ACTIVE_LOW = 1, 2782 } iis2iclx_h_lactive_t; 2783 int32_t iis2iclx_pin_polarity_set(stmdev_ctx_t *ctx, 2784 iis2iclx_h_lactive_t val); 2785 int32_t iis2iclx_pin_polarity_get(stmdev_ctx_t *ctx, 2786 iis2iclx_h_lactive_t *val); 2787 2788 int32_t iis2iclx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); 2789 int32_t iis2iclx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); 2790 2791 typedef enum 2792 { 2793 IIS2ICLX_ALL_INT_PULSED = 0, 2794 IIS2ICLX_BASE_LATCHED_EMB_PULSED = 1, 2795 IIS2ICLX_BASE_PULSED_EMB_LATCHED = 2, 2796 IIS2ICLX_ALL_INT_LATCHED = 3, 2797 } iis2iclx_lir_t; 2798 int32_t iis2iclx_int_notification_set(stmdev_ctx_t *ctx, 2799 iis2iclx_lir_t val); 2800 int32_t iis2iclx_int_notification_get(stmdev_ctx_t *ctx, 2801 iis2iclx_lir_t *val); 2802 2803 typedef enum 2804 { 2805 IIS2ICLX_LSb_FS_DIV_64 = 0, 2806 IIS2ICLX_LSb_FS_DIV_256 = 1, 2807 } iis2iclx_wake_ths_w_t; 2808 int32_t iis2iclx_wkup_ths_weight_set(stmdev_ctx_t *ctx, 2809 iis2iclx_wake_ths_w_t val); 2810 int32_t iis2iclx_wkup_ths_weight_get(stmdev_ctx_t *ctx, 2811 iis2iclx_wake_ths_w_t *val); 2812 2813 int32_t iis2iclx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 2814 int32_t iis2iclx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 2815 2816 int32_t iis2iclx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx, 2817 uint8_t val); 2818 int32_t iis2iclx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx, 2819 uint8_t *val); 2820 2821 int32_t iis2iclx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2822 int32_t iis2iclx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2823 2824 typedef enum 2825 { 2826 IIS2ICLX_DRIVE_SLEEP_CHG_EVENT = 0, 2827 IIS2ICLX_DRIVE_SLEEP_STATUS = 1, 2828 } iis2iclx_sleep_status_on_int_t; 2829 int32_t iis2iclx_act_pin_notification_set(stmdev_ctx_t *ctx, 2830 iis2iclx_sleep_status_on_int_t val); 2831 int32_t iis2iclx_act_pin_notification_get(stmdev_ctx_t *ctx, 2832 iis2iclx_sleep_status_on_int_t *val); 2833 2834 int32_t iis2iclx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2835 int32_t iis2iclx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2836 2837 int32_t iis2iclx_tap_detection_on_y_set(stmdev_ctx_t *ctx, 2838 uint8_t val); 2839 int32_t iis2iclx_tap_detection_on_y_get(stmdev_ctx_t *ctx, 2840 uint8_t *val); 2841 2842 int32_t iis2iclx_tap_detection_on_x_set(stmdev_ctx_t *ctx, 2843 uint8_t val); 2844 int32_t iis2iclx_tap_detection_on_x_get(stmdev_ctx_t *ctx, 2845 uint8_t *val); 2846 2847 int32_t iis2iclx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); 2848 int32_t iis2iclx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); 2849 2850 typedef enum 2851 { 2852 IIS2ICLX_XY = 0, 2853 IIS2ICLX_YX = 1, 2854 } iis2iclx_tap_priority_t; 2855 int32_t iis2iclx_tap_axis_priority_set(stmdev_ctx_t *ctx, 2856 iis2iclx_tap_priority_t val); 2857 int32_t iis2iclx_tap_axis_priority_get(stmdev_ctx_t *ctx, 2858 iis2iclx_tap_priority_t *val); 2859 2860 int32_t iis2iclx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val); 2861 int32_t iis2iclx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val); 2862 2863 int32_t iis2iclx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); 2864 int32_t iis2iclx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); 2865 2866 int32_t iis2iclx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); 2867 int32_t iis2iclx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); 2868 2869 int32_t iis2iclx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); 2870 int32_t iis2iclx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 2871 2872 typedef enum 2873 { 2874 IIS2ICLX_ONLY_SINGLE = 0, 2875 IIS2ICLX_BOTH_SINGLE_DOUBLE = 1, 2876 } iis2iclx_single_double_tap_t; 2877 int32_t iis2iclx_tap_mode_set(stmdev_ctx_t *ctx, 2878 iis2iclx_single_double_tap_t val); 2879 int32_t iis2iclx_tap_mode_get(stmdev_ctx_t *ctx, 2880 iis2iclx_single_double_tap_t *val); 2881 2882 int32_t iis2iclx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); 2883 int32_t iis2iclx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); 2884 2885 int32_t iis2iclx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx, 2886 uint8_t val); 2887 int32_t iis2iclx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx, 2888 uint8_t *val); 2889 2890 int32_t iis2iclx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); 2891 int32_t iis2iclx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, 2892 uint8_t *val); 2893 2894 typedef enum 2895 { 2896 IIS2ICLX_XL_NOT_BATCHED = 0, 2897 IIS2ICLX_XL_BATCHED_AT_1Hz6 = 11, 2898 IIS2ICLX_XL_BATCHED_AT_12Hz5 = 1, 2899 IIS2ICLX_XL_BATCHED_AT_26Hz = 2, 2900 IIS2ICLX_XL_BATCHED_AT_52Hz = 3, 2901 IIS2ICLX_XL_BATCHED_AT_104Hz = 4, 2902 IIS2ICLX_XL_BATCHED_AT_208Hz = 5, 2903 IIS2ICLX_XL_BATCHED_AT_417Hz = 6, 2904 IIS2ICLX_XL_BATCHED_AT_833Hz = 7, 2905 } iis2iclx_bdr_xl_t; 2906 int32_t iis2iclx_fifo_xl_batch_set(stmdev_ctx_t *ctx, 2907 iis2iclx_bdr_xl_t val); 2908 int32_t iis2iclx_fifo_xl_batch_get(stmdev_ctx_t *ctx, 2909 iis2iclx_bdr_xl_t *val); 2910 2911 typedef enum 2912 { 2913 IIS2ICLX_BYPASS_MODE = 0, 2914 IIS2ICLX_FIFO_MODE = 1, 2915 IIS2ICLX_STREAM_TO_FIFO_MODE = 3, 2916 IIS2ICLX_BYPASS_TO_STREAM_MODE = 4, 2917 IIS2ICLX_STREAM_MODE = 6, 2918 IIS2ICLX_BYPASS_TO_FIFO_MODE = 7, 2919 } iis2iclx_fifo_mode_t; 2920 int32_t iis2iclx_fifo_mode_set(stmdev_ctx_t *ctx, 2921 iis2iclx_fifo_mode_t val); 2922 int32_t iis2iclx_fifo_mode_get(stmdev_ctx_t *ctx, 2923 iis2iclx_fifo_mode_t *val); 2924 2925 typedef enum 2926 { 2927 IIS2ICLX_TEMP_NOT_BATCHED = 0, 2928 IIS2ICLX_TEMP_BATCHED_AT_1Hz6 = 1, 2929 IIS2ICLX_TEMP_BATCHED_AT_12Hz5 = 2, 2930 IIS2ICLX_TEMP_BATCHED_AT_52Hz = 3, 2931 } iis2iclx_odr_t_batch_t; 2932 int32_t iis2iclx_fifo_temp_batch_set(stmdev_ctx_t *ctx, 2933 iis2iclx_odr_t_batch_t val); 2934 int32_t iis2iclx_fifo_temp_batch_get(stmdev_ctx_t *ctx, 2935 iis2iclx_odr_t_batch_t *val); 2936 2937 typedef enum 2938 { 2939 IIS2ICLX_NO_DECIMATION = 0, 2940 IIS2ICLX_DEC_1 = 1, 2941 IIS2ICLX_DEC_8 = 2, 2942 IIS2ICLX_DEC_32 = 3, 2943 } iis2iclx_odr_ts_batch_t; 2944 int32_t iis2iclx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx, 2945 iis2iclx_odr_ts_batch_t val); 2946 int32_t iis2iclx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx, 2947 iis2iclx_odr_ts_batch_t *val); 2948 2949 int32_t iis2iclx_rst_batch_counter_set(stmdev_ctx_t *ctx, 2950 uint8_t val); 2951 int32_t iis2iclx_rst_batch_counter_get(stmdev_ctx_t *ctx, 2952 uint8_t *val); 2953 2954 int32_t iis2iclx_batch_counter_threshold_set(stmdev_ctx_t *ctx, 2955 uint16_t val); 2956 int32_t iis2iclx_batch_counter_threshold_get(stmdev_ctx_t *ctx, 2957 uint16_t *val); 2958 2959 int32_t iis2iclx_fifo_data_level_get(stmdev_ctx_t *ctx, 2960 uint16_t *val); 2961 2962 int32_t iis2iclx_fifo_status_get(stmdev_ctx_t *ctx, 2963 iis2iclx_fifo_status2_t *val); 2964 2965 int32_t iis2iclx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 2966 2967 int32_t iis2iclx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 2968 2969 int32_t iis2iclx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 2970 2971 typedef enum 2972 { 2973 IIS2ICLX_XL_NC_TAG = 2, 2974 IIS2ICLX_TEMPERATURE_TAG, 2975 IIS2ICLX_TIMESTAMP_TAG, 2976 IIS2ICLX_CFG_CHANGE_TAG, 2977 IIS2ICLX_SENSORHUB_SLAVE0_TAG, 2978 IIS2ICLX_SENSORHUB_SLAVE1_TAG, 2979 IIS2ICLX_SENSORHUB_SLAVE2_TAG, 2980 IIS2ICLX_SENSORHUB_SLAVE3_TAG, 2981 IIS2ICLX_SENSORHUB_NACK_TAG = 0x19, 2982 } iis2iclx_fifo_tag_t; 2983 int32_t iis2iclx_fifo_sensor_tag_get(stmdev_ctx_t *ctx, 2984 iis2iclx_fifo_tag_t *val); 2985 2986 int32_t iis2iclx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val); 2987 int32_t iis2iclx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, 2988 uint8_t *val); 2989 2990 int32_t iis2iclx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val); 2991 int32_t iis2iclx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, 2992 uint8_t *val); 2993 2994 int32_t iis2iclx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val); 2995 int32_t iis2iclx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, 2996 uint8_t *val); 2997 2998 int32_t iis2iclx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val); 2999 int32_t iis2iclx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, 3000 uint8_t *val); 3001 3002 typedef enum 3003 { 3004 IIS2ICLX_DEN_DISABLE = 0x00, 3005 IIS2ICLX_LEVEL_FIFO = 0x76, 3006 IIS2ICLX_LEVEL_LETCHED = 0x73, 3007 IIS2ICLX_LEVEL_TRIGGER = 0x72, 3008 IIS2ICLX_EDGE_TRIGGER = 0x74, 3009 } iis2iclx_den_mode_t; 3010 int32_t iis2iclx_den_mode_set(stmdev_ctx_t *ctx, 3011 iis2iclx_den_mode_t val); 3012 int32_t iis2iclx_den_mode_get(stmdev_ctx_t *ctx, 3013 iis2iclx_den_mode_t *val); 3014 3015 typedef enum 3016 { 3017 IIS2ICLX_DEN_ACT_LOW = 0, 3018 IIS2ICLX_DEN_ACT_HIGH = 1, 3019 } iis2iclx_den_lh_t; 3020 int32_t iis2iclx_den_polarity_set(stmdev_ctx_t *ctx, 3021 iis2iclx_den_lh_t val); 3022 int32_t iis2iclx_den_polarity_get(stmdev_ctx_t *ctx, 3023 iis2iclx_den_lh_t *val); 3024 3025 int32_t iis2iclx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); 3026 int32_t iis2iclx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); 3027 3028 int32_t iis2iclx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); 3029 int32_t iis2iclx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); 3030 3031 int32_t iis2iclx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx, 3032 uint8_t *val); 3033 3034 int32_t iis2iclx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val); 3035 int32_t iis2iclx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val); 3036 3037 typedef struct 3038 { 3039 iis2iclx_fsm_enable_a_t fsm_enable_a; 3040 iis2iclx_fsm_enable_b_t fsm_enable_b; 3041 } iis2iclx_emb_fsm_enable_t; 3042 int32_t iis2iclx_fsm_enable_set(stmdev_ctx_t *ctx, 3043 iis2iclx_emb_fsm_enable_t *val); 3044 int32_t iis2iclx_fsm_enable_get(stmdev_ctx_t *ctx, 3045 iis2iclx_emb_fsm_enable_t *val); 3046 3047 int32_t iis2iclx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val); 3048 int32_t iis2iclx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val); 3049 3050 typedef enum 3051 { 3052 IIS2ICLX_LC_NORMAL = 0, 3053 IIS2ICLX_LC_CLEAR = 1, 3054 IIS2ICLX_LC_CLEAR_DONE = 2, 3055 } iis2iclx_fsm_lc_clr_t; 3056 int32_t iis2iclx_long_clr_set(stmdev_ctx_t *ctx, 3057 iis2iclx_fsm_lc_clr_t val); 3058 int32_t iis2iclx_long_clr_get(stmdev_ctx_t *ctx, 3059 iis2iclx_fsm_lc_clr_t *val); 3060 3061 typedef struct 3062 { 3063 iis2iclx_fsm_outs1_t fsm_outs1; 3064 iis2iclx_fsm_outs2_t fsm_outs2; 3065 iis2iclx_fsm_outs3_t fsm_outs3; 3066 iis2iclx_fsm_outs4_t fsm_outs4; 3067 iis2iclx_fsm_outs5_t fsm_outs5; 3068 iis2iclx_fsm_outs6_t fsm_outs6; 3069 iis2iclx_fsm_outs7_t fsm_outs7; 3070 iis2iclx_fsm_outs8_t fsm_outs8; 3071 iis2iclx_fsm_outs9_t fsm_outs9; 3072 iis2iclx_fsm_outs10_t fsm_outs10; 3073 iis2iclx_fsm_outs11_t fsm_outs11; 3074 iis2iclx_fsm_outs12_t fsm_outs12; 3075 iis2iclx_fsm_outs13_t fsm_outs13; 3076 iis2iclx_fsm_outs14_t fsm_outs14; 3077 iis2iclx_fsm_outs15_t fsm_outs15; 3078 iis2iclx_fsm_outs16_t fsm_outs16; 3079 } iis2iclx_fsm_out_t; 3080 int32_t iis2iclx_fsm_out_get(stmdev_ctx_t *ctx, 3081 iis2iclx_fsm_out_t *val); 3082 3083 typedef enum 3084 { 3085 IIS2ICLX_ODR_FSM_12Hz5 = 0, 3086 IIS2ICLX_ODR_FSM_26Hz = 1, 3087 IIS2ICLX_ODR_FSM_52Hz = 2, 3088 IIS2ICLX_ODR_FSM_104Hz = 3, 3089 } iis2iclx_fsm_odr_t; 3090 int32_t iis2iclx_fsm_data_rate_set(stmdev_ctx_t *ctx, 3091 iis2iclx_fsm_odr_t val); 3092 int32_t iis2iclx_fsm_data_rate_get(stmdev_ctx_t *ctx, 3093 iis2iclx_fsm_odr_t *val); 3094 3095 int32_t iis2iclx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val); 3096 int32_t iis2iclx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val); 3097 3098 int32_t iis2iclx_long_cnt_int_value_set(stmdev_ctx_t *ctx, 3099 uint16_t val); 3100 int32_t iis2iclx_long_cnt_int_value_get(stmdev_ctx_t *ctx, 3101 uint16_t *val); 3102 3103 int32_t iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, 3104 uint8_t *buff); 3105 int32_t iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, 3106 uint8_t *buff); 3107 3108 int32_t iis2iclx_fsm_start_address_set(stmdev_ctx_t *ctx, 3109 uint16_t val); 3110 int32_t iis2iclx_fsm_start_address_get(stmdev_ctx_t *ctx, 3111 uint16_t *val); 3112 3113 int32_t iis2iclx_mlc_set(stmdev_ctx_t *ctx, uint8_t val); 3114 int32_t iis2iclx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val); 3115 3116 int32_t iis2iclx_mlc_status_get(stmdev_ctx_t *ctx, 3117 iis2iclx_mlc_status_mainpage_t *val); 3118 3119 typedef enum 3120 { 3121 IIS2ICLX_ODR_PRGS_12Hz5 = 0, 3122 IIS2ICLX_ODR_PRGS_26Hz = 1, 3123 IIS2ICLX_ODR_PRGS_52Hz = 2, 3124 IIS2ICLX_ODR_PRGS_104Hz = 3, 3125 } iis2iclx_mlc_odr_t; 3126 int32_t iis2iclx_mlc_data_rate_set(stmdev_ctx_t *ctx, 3127 iis2iclx_mlc_odr_t val); 3128 int32_t iis2iclx_mlc_data_rate_get(stmdev_ctx_t *ctx, 3129 iis2iclx_mlc_odr_t *val); 3130 3131 int32_t iis2iclx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff); 3132 3133 typedef struct 3134 { 3135 iis2iclx_sensor_hub_1_t sh_byte_1; 3136 iis2iclx_sensor_hub_2_t sh_byte_2; 3137 iis2iclx_sensor_hub_3_t sh_byte_3; 3138 iis2iclx_sensor_hub_4_t sh_byte_4; 3139 iis2iclx_sensor_hub_5_t sh_byte_5; 3140 iis2iclx_sensor_hub_6_t sh_byte_6; 3141 iis2iclx_sensor_hub_7_t sh_byte_7; 3142 iis2iclx_sensor_hub_8_t sh_byte_8; 3143 iis2iclx_sensor_hub_9_t sh_byte_9; 3144 iis2iclx_sensor_hub_10_t sh_byte_10; 3145 iis2iclx_sensor_hub_11_t sh_byte_11; 3146 iis2iclx_sensor_hub_12_t sh_byte_12; 3147 iis2iclx_sensor_hub_13_t sh_byte_13; 3148 iis2iclx_sensor_hub_14_t sh_byte_14; 3149 iis2iclx_sensor_hub_15_t sh_byte_15; 3150 iis2iclx_sensor_hub_16_t sh_byte_16; 3151 iis2iclx_sensor_hub_17_t sh_byte_17; 3152 iis2iclx_sensor_hub_18_t sh_byte_18; 3153 } iis2iclx_emb_sh_read_t; 3154 int32_t iis2iclx_sh_read_data_raw_get(stmdev_ctx_t *ctx, 3155 iis2iclx_emb_sh_read_t *val); 3156 3157 typedef enum 3158 { 3159 IIS2ICLX_SLV_0 = 0, 3160 IIS2ICLX_SLV_0_1 = 1, 3161 IIS2ICLX_SLV_0_1_2 = 2, 3162 IIS2ICLX_SLV_0_1_2_3 = 3, 3163 } iis2iclx_aux_sens_on_t; 3164 int32_t iis2iclx_sh_slave_connected_set(stmdev_ctx_t *ctx, 3165 iis2iclx_aux_sens_on_t val); 3166 int32_t iis2iclx_sh_slave_connected_get(stmdev_ctx_t *ctx, 3167 iis2iclx_aux_sens_on_t *val); 3168 3169 int32_t iis2iclx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); 3170 int32_t iis2iclx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); 3171 3172 typedef enum 3173 { 3174 IIS2ICLX_EXT_PULL_UP = 0, 3175 IIS2ICLX_INTERNAL_PULL_UP = 1, 3176 } iis2iclx_shub_pu_en_t; 3177 int32_t iis2iclx_sh_pin_mode_set(stmdev_ctx_t *ctx, 3178 iis2iclx_shub_pu_en_t val); 3179 int32_t iis2iclx_sh_pin_mode_get(stmdev_ctx_t *ctx, 3180 iis2iclx_shub_pu_en_t *val); 3181 3182 int32_t iis2iclx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); 3183 int32_t iis2iclx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); 3184 3185 typedef enum 3186 { 3187 IIS2ICLX_EXT_ON_INT2_PIN = 1, 3188 IIS2ICLX_XL_GY_DRDY = 0, 3189 } iis2iclx_start_config_t; 3190 int32_t iis2iclx_sh_syncro_mode_set(stmdev_ctx_t *ctx, 3191 iis2iclx_start_config_t val); 3192 int32_t iis2iclx_sh_syncro_mode_get(stmdev_ctx_t *ctx, 3193 iis2iclx_start_config_t *val); 3194 3195 typedef enum 3196 { 3197 IIS2ICLX_EACH_SH_CYCLE = 0, 3198 IIS2ICLX_ONLY_FIRST_CYCLE = 1, 3199 } iis2iclx_write_once_t; 3200 int32_t iis2iclx_sh_write_mode_set(stmdev_ctx_t *ctx, 3201 iis2iclx_write_once_t val); 3202 int32_t iis2iclx_sh_write_mode_get(stmdev_ctx_t *ctx, 3203 iis2iclx_write_once_t *val); 3204 3205 int32_t iis2iclx_sh_reset_set(stmdev_ctx_t *ctx); 3206 int32_t iis2iclx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val); 3207 3208 typedef enum 3209 { 3210 IIS2ICLX_SH_ODR_104Hz = 0, 3211 IIS2ICLX_SH_ODR_52Hz = 1, 3212 IIS2ICLX_SH_ODR_26Hz = 2, 3213 IIS2ICLX_SH_ODR_13Hz = 3, 3214 } iis2iclx_shub_odr_t; 3215 int32_t iis2iclx_sh_data_rate_set(stmdev_ctx_t *ctx, 3216 iis2iclx_shub_odr_t val); 3217 int32_t iis2iclx_sh_data_rate_get(stmdev_ctx_t *ctx, 3218 iis2iclx_shub_odr_t *val); 3219 3220 typedef struct 3221 { 3222 uint8_t slv0_add; 3223 uint8_t slv0_subadd; 3224 uint8_t slv0_data; 3225 } iis2iclx_sh_cfg_write_t; 3226 int32_t iis2iclx_sh_cfg_write(stmdev_ctx_t *ctx, 3227 iis2iclx_sh_cfg_write_t *val); 3228 3229 typedef struct 3230 { 3231 uint8_t slv_add; 3232 uint8_t slv_subadd; 3233 uint8_t slv_len; 3234 } iis2iclx_sh_cfg_read_t; 3235 int32_t iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t *ctx, 3236 iis2iclx_sh_cfg_read_t *val); 3237 int32_t iis2iclx_sh_slv1_cfg_read(stmdev_ctx_t *ctx, 3238 iis2iclx_sh_cfg_read_t *val); 3239 int32_t iis2iclx_sh_slv2_cfg_read(stmdev_ctx_t *ctx, 3240 iis2iclx_sh_cfg_read_t *val); 3241 int32_t iis2iclx_sh_slv3_cfg_read(stmdev_ctx_t *ctx, 3242 iis2iclx_sh_cfg_read_t *val); 3243 3244 int32_t iis2iclx_sh_status_get(stmdev_ctx_t *ctx, 3245 iis2iclx_status_master_t *val); 3246 3247 typedef enum 3248 { 3249 IIS2ICLX_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 3250 IIS2ICLX_SPI_4W = 0x01, /* Only SPI: SDO / SDI separated pins */ 3251 IIS2ICLX_SPI_3W = 0x03, /* Only SPI: SDO / SDI share the same pin */ 3252 } iis2iclx_bus_mode_t; 3253 int32_t iis2iclx_bus_mode_set(stmdev_ctx_t *ctx, 3254 iis2iclx_bus_mode_t val); 3255 int32_t iis2iclx_bus_mode_get(stmdev_ctx_t *ctx, 3256 iis2iclx_bus_mode_t *val); 3257 3258 /** 3259 *@} 3260 * 3261 */ 3262 3263 #ifdef __cplusplus 3264 } 3265 #endif 3266 3267 #endif /* IIS2ICLX_REGS_H */ 3268 3269 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3270
