1 /** 2 ****************************************************************************** 3 * @file iis2dh_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * iis2dh_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef IIS2DH_REGS_H 23 #define IIS2DH_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup IIS2DH 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup IIS2DH_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 31 if SA0=1 -> 33 **/ 172 #define IIS2DH_I2C_ADD_L 0x31U 173 #define IIS2DH_I2C_ADD_H 0x33U 174 175 /** Device Identification (Who am I) **/ 176 #define IIS2DH_ID 0x33U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define IIS2DH_STATUS_REG_AUX 0x07U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t not_used_01 : 2; 188 uint8_t tda : 1; 189 uint8_t not_used_02 : 3; 190 uint8_t tor : 1; 191 uint8_t not_used_03 : 1; 192 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 193 uint8_t not_used_03 : 1; 194 uint8_t tor : 1; 195 uint8_t not_used_02 : 3; 196 uint8_t tda : 1; 197 uint8_t not_used_01 : 2; 198 #endif /* DRV_BYTE_ORDER */ 199 } iis2dh_status_reg_aux_t; 200 201 #define IIS2DH_OUT_TEMP_L 0x0CU 202 #define IIS2DH_OUT_TEMP_H 0x0DU 203 #define IIS2DH_INT_COUNTER_REG 0x0EU 204 #define IIS2DH_WHO_AM_I 0x0FU 205 206 #define IIS2DH_TEMP_CFG_REG 0x1FU 207 typedef struct 208 { 209 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 210 uint8_t not_used_01 : 6; 211 uint8_t temp_en : 2; 212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 213 uint8_t temp_en : 2; 214 uint8_t not_used_01 : 6; 215 #endif /* DRV_BYTE_ORDER */ 216 } iis2dh_temp_cfg_reg_t; 217 218 #define IIS2DH_CTRL_REG1 0x20U 219 typedef struct 220 { 221 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 222 uint8_t xen : 1; 223 uint8_t yen : 1; 224 uint8_t zen : 1; 225 uint8_t lpen : 1; 226 uint8_t odr : 4; 227 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 228 uint8_t odr : 4; 229 uint8_t lpen : 1; 230 uint8_t zen : 1; 231 uint8_t yen : 1; 232 uint8_t xen : 1; 233 #endif /* DRV_BYTE_ORDER */ 234 } iis2dh_ctrl_reg1_t; 235 236 #define IIS2DH_CTRL_REG2 0x21U 237 typedef struct 238 { 239 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 240 uint8_t hp : 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */ 241 uint8_t fds : 1; 242 uint8_t hpcf : 2; 243 uint8_t hpm : 2; 244 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 245 uint8_t hpm : 2; 246 uint8_t hpcf : 2; 247 uint8_t fds : 1; 248 uint8_t hp : 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */ 249 #endif /* DRV_BYTE_ORDER */ 250 } iis2dh_ctrl_reg2_t; 251 252 #define IIS2DH_CTRL_REG3 0x22U 253 typedef struct 254 { 255 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 256 uint8_t not_used_01 : 1; 257 uint8_t i1_overrun : 1; 258 uint8_t i1_wtm : 1; 259 uint8_t i1_drdy2 : 1; 260 uint8_t i1_drdy1 : 1; 261 uint8_t i1_aoi2 : 1; 262 uint8_t i1_aoi1 : 1; 263 uint8_t i1_click : 1; 264 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 265 uint8_t i1_click : 1; 266 uint8_t i1_aoi1 : 1; 267 uint8_t i1_aoi2 : 1; 268 uint8_t i1_drdy1 : 1; 269 uint8_t i1_drdy2 : 1; 270 uint8_t i1_wtm : 1; 271 uint8_t i1_overrun : 1; 272 uint8_t not_used_01 : 1; 273 #endif /* DRV_BYTE_ORDER */ 274 } iis2dh_ctrl_reg3_t; 275 276 #define IIS2DH_CTRL_REG4 0x23U 277 typedef struct 278 { 279 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 280 uint8_t sim : 1; 281 uint8_t st : 2; 282 uint8_t hr : 1; 283 uint8_t fs : 2; 284 uint8_t ble : 1; 285 uint8_t bdu : 1; 286 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 287 uint8_t bdu : 1; 288 uint8_t ble : 1; 289 uint8_t fs : 2; 290 uint8_t hr : 1; 291 uint8_t st : 2; 292 uint8_t sim : 1; 293 #endif /* DRV_BYTE_ORDER */ 294 } iis2dh_ctrl_reg4_t; 295 296 #define IIS2DH_CTRL_REG5 0x24U 297 typedef struct 298 { 299 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 300 uint8_t d4d_int2 : 1; 301 uint8_t lir_int2 : 1; 302 uint8_t d4d_int1 : 1; 303 uint8_t lir_int1 : 1; 304 uint8_t not_used_01 : 2; 305 uint8_t fifo_en : 1; 306 uint8_t boot : 1; 307 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 308 uint8_t boot : 1; 309 uint8_t fifo_en : 1; 310 uint8_t not_used_01 : 2; 311 uint8_t lir_int1 : 1; 312 uint8_t d4d_int1 : 1; 313 uint8_t lir_int2 : 1; 314 uint8_t d4d_int2 : 1; 315 #endif /* DRV_BYTE_ORDER */ 316 } iis2dh_ctrl_reg5_t; 317 318 #define IIS2DH_CTRL_REG6 0x25U 319 typedef struct 320 { 321 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 322 uint8_t not_used_01 : 1; 323 uint8_t h_lactive : 1; 324 uint8_t not_used_02 : 1; 325 uint8_t p2_act : 1; 326 uint8_t boot_i2 : 1; 327 uint8_t i2_int2 : 1; 328 uint8_t i2_int1 : 1; 329 uint8_t i2_clicken : 1; 330 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 331 uint8_t i2_clicken : 1; 332 uint8_t i2_int1 : 1; 333 uint8_t i2_int2 : 1; 334 uint8_t boot_i2 : 1; 335 uint8_t p2_act : 1; 336 uint8_t not_used_02 : 1; 337 uint8_t h_lactive : 1; 338 uint8_t not_used_01 : 1; 339 #endif /* DRV_BYTE_ORDER */ 340 } iis2dh_ctrl_reg6_t; 341 342 #define IIS2DH_REFERENCE 0x26U 343 #define IIS2DH_STATUS_REG 0x27U 344 typedef struct 345 { 346 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 347 uint8_t xda : 1; 348 uint8_t yda : 1; 349 uint8_t zda : 1; 350 uint8_t zyxda : 1; 351 uint8_t _xor : 1; 352 uint8_t yor : 1; 353 uint8_t zor : 1; 354 uint8_t zyxor : 1; 355 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 356 uint8_t zyxor : 1; 357 uint8_t zor : 1; 358 uint8_t yor : 1; 359 uint8_t _xor : 1; 360 uint8_t zyxda : 1; 361 uint8_t zda : 1; 362 uint8_t yda : 1; 363 uint8_t xda : 1; 364 #endif /* DRV_BYTE_ORDER */ 365 } iis2dh_status_reg_t; 366 367 #define IIS2DH_OUT_X_L 0x28U 368 #define IIS2DH_OUT_X_H 0x29U 369 #define IIS2DH_OUT_Y_L 0x2AU 370 #define IIS2DH_OUT_Y_H 0x2BU 371 #define IIS2DH_OUT_Z_L 0x2CU 372 #define IIS2DH_OUT_Z_H 0x2DU 373 #define IIS2DH_FIFO_CTRL_REG 0x2EU 374 typedef struct 375 { 376 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 377 uint8_t fth : 5; 378 uint8_t tr : 1; 379 uint8_t fm : 2; 380 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 381 uint8_t fm : 2; 382 uint8_t tr : 1; 383 uint8_t fth : 5; 384 #endif /* DRV_BYTE_ORDER */ 385 } iis2dh_fifo_ctrl_reg_t; 386 387 #define IIS2DH_FIFO_SRC_REG 0x2FU 388 typedef struct 389 { 390 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 391 uint8_t fss : 5; 392 uint8_t empty : 1; 393 uint8_t ovrn_fifo : 1; 394 uint8_t wtm : 1; 395 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 396 uint8_t wtm : 1; 397 uint8_t ovrn_fifo : 1; 398 uint8_t empty : 1; 399 uint8_t fss : 5; 400 #endif /* DRV_BYTE_ORDER */ 401 } iis2dh_fifo_src_reg_t; 402 403 #define IIS2DH_INT1_CFG 0x30U 404 typedef struct 405 { 406 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 407 uint8_t xlie : 1; 408 uint8_t xhie : 1; 409 uint8_t ylie : 1; 410 uint8_t yhie : 1; 411 uint8_t zlie : 1; 412 uint8_t zhie : 1; 413 uint8_t _6d : 1; 414 uint8_t aoi : 1; 415 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 416 uint8_t aoi : 1; 417 uint8_t _6d : 1; 418 uint8_t zhie : 1; 419 uint8_t zlie : 1; 420 uint8_t yhie : 1; 421 uint8_t ylie : 1; 422 uint8_t xhie : 1; 423 uint8_t xlie : 1; 424 #endif /* DRV_BYTE_ORDER */ 425 } iis2dh_int1_cfg_t; 426 427 #define IIS2DH_INT1_SRC 0x31U 428 typedef struct 429 { 430 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 431 uint8_t xl : 1; 432 uint8_t xh : 1; 433 uint8_t yl : 1; 434 uint8_t yh : 1; 435 uint8_t zl : 1; 436 uint8_t zh : 1; 437 uint8_t ia : 1; 438 uint8_t not_used_01 : 1; 439 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 440 uint8_t not_used_01 : 1; 441 uint8_t ia : 1; 442 uint8_t zh : 1; 443 uint8_t zl : 1; 444 uint8_t yh : 1; 445 uint8_t yl : 1; 446 uint8_t xh : 1; 447 uint8_t xl : 1; 448 #endif /* DRV_BYTE_ORDER */ 449 } iis2dh_int1_src_t; 450 451 #define IIS2DH_INT1_THS 0x32U 452 typedef struct 453 { 454 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 455 uint8_t ths : 7; 456 uint8_t not_used_01 : 1; 457 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 458 uint8_t not_used_01 : 1; 459 uint8_t ths : 7; 460 #endif /* DRV_BYTE_ORDER */ 461 } iis2dh_int1_ths_t; 462 463 #define IIS2DH_INT1_DURATION 0x33U 464 typedef struct 465 { 466 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 467 uint8_t d : 7; 468 uint8_t not_used_01 : 1; 469 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 470 uint8_t not_used_01 : 1; 471 uint8_t d : 7; 472 #endif /* DRV_BYTE_ORDER */ 473 } iis2dh_int1_duration_t; 474 475 #define IIS2DH_INT2_CFG 0x34U 476 typedef struct 477 { 478 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 479 uint8_t xlie : 1; 480 uint8_t xhie : 1; 481 uint8_t ylie : 1; 482 uint8_t yhie : 1; 483 uint8_t zlie : 1; 484 uint8_t zhie : 1; 485 uint8_t _6d : 1; 486 uint8_t aoi : 1; 487 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 488 uint8_t aoi : 1; 489 uint8_t _6d : 1; 490 uint8_t zhie : 1; 491 uint8_t zlie : 1; 492 uint8_t yhie : 1; 493 uint8_t ylie : 1; 494 uint8_t xhie : 1; 495 uint8_t xlie : 1; 496 #endif /* DRV_BYTE_ORDER */ 497 } iis2dh_int2_cfg_t; 498 499 #define IIS2DH_INT2_SRC 0x35U 500 typedef struct 501 { 502 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 503 uint8_t xl : 1; 504 uint8_t xh : 1; 505 uint8_t yl : 1; 506 uint8_t yh : 1; 507 uint8_t zl : 1; 508 uint8_t zh : 1; 509 uint8_t ia : 1; 510 uint8_t not_used_01 : 1; 511 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 512 uint8_t not_used_01 : 1; 513 uint8_t ia : 1; 514 uint8_t zh : 1; 515 uint8_t zl : 1; 516 uint8_t yh : 1; 517 uint8_t yl : 1; 518 uint8_t xh : 1; 519 uint8_t xl : 1; 520 #endif /* DRV_BYTE_ORDER */ 521 } iis2dh_int2_src_t; 522 523 #define IIS2DH_INT2_THS 0x36U 524 typedef struct 525 { 526 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 527 uint8_t ths : 7; 528 uint8_t not_used_01 : 1; 529 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 530 uint8_t not_used_01 : 1; 531 uint8_t ths : 7; 532 #endif /* DRV_BYTE_ORDER */ 533 } iis2dh_int2_ths_t; 534 535 #define IIS2DH_INT2_DURATION 0x37U 536 typedef struct 537 { 538 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 539 uint8_t d : 7; 540 uint8_t not_used_01 : 1; 541 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 542 #endif /* DRV_BYTE_ORDER */ 543 } iis2dh_int2_duration_t; 544 545 #define IIS2DH_CLICK_CFG 0x38U 546 typedef struct 547 { 548 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 549 uint8_t xs : 1; 550 uint8_t xd : 1; 551 uint8_t ys : 1; 552 uint8_t yd : 1; 553 uint8_t zs : 1; 554 uint8_t zd : 1; 555 uint8_t not_used_01 : 2; 556 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 557 uint8_t not_used_01 : 2; 558 uint8_t zd : 1; 559 uint8_t zs : 1; 560 uint8_t yd : 1; 561 uint8_t ys : 1; 562 uint8_t xd : 1; 563 uint8_t xs : 1; 564 #endif /* DRV_BYTE_ORDER */ 565 } iis2dh_click_cfg_t; 566 567 #define IIS2DH_CLICK_SRC 0x39U 568 typedef struct 569 { 570 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 571 uint8_t x : 1; 572 uint8_t y : 1; 573 uint8_t z : 1; 574 uint8_t sign : 1; 575 uint8_t sclick : 1; 576 uint8_t dclick : 1; 577 uint8_t ia : 1; 578 uint8_t not_used_01 : 1; 579 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 580 uint8_t not_used_01 : 1; 581 uint8_t ia : 1; 582 uint8_t dclick : 1; 583 uint8_t sclick : 1; 584 uint8_t sign : 1; 585 uint8_t z : 1; 586 uint8_t y : 1; 587 uint8_t x : 1; 588 #endif /* DRV_BYTE_ORDER */ 589 } iis2dh_click_src_t; 590 591 #define IIS2DH_CLICK_THS 0x3AU 592 typedef struct 593 { 594 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 595 uint8_t ths : 7; 596 uint8_t not_used_01 : 1; 597 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 598 uint8_t not_used_01 : 1; 599 uint8_t ths : 7; 600 #endif /* DRV_BYTE_ORDER */ 601 } iis2dh_click_ths_t; 602 603 #define IIS2DH_TIME_LIMIT 0x3BU 604 typedef struct 605 { 606 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 607 uint8_t tli : 7; 608 uint8_t not_used_01 : 1; 609 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 610 uint8_t not_used_01 : 1; 611 uint8_t tli : 7; 612 #endif /* DRV_BYTE_ORDER */ 613 } iis2dh_time_limit_t; 614 615 #define IIS2DH_TIME_LATENCY 0x3CU 616 typedef struct 617 { 618 uint8_t tla : 8; 619 } iis2dh_time_latency_t; 620 621 #define IIS2DH_TIME_WINDOW 0x3DU 622 typedef struct 623 { 624 uint8_t tw : 8; 625 } iis2dh_time_window_t; 626 627 #define IIS2DH_ACT_THS 0x3EU 628 typedef struct 629 { 630 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 631 uint8_t acth : 7; 632 uint8_t not_used_01 : 1; 633 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 634 uint8_t not_used_01 : 1; 635 uint8_t acth : 7; 636 #endif /* DRV_BYTE_ORDER */ 637 } iis2dh_act_ths_t; 638 639 #define IIS2DH_ACT_DUR 0x3FU 640 typedef struct 641 { 642 uint8_t actd : 8; 643 } iis2dh_act_dur_t; 644 645 /** 646 * @defgroup IIS2DH_Register_Union 647 * @brief This union group all the registers having a bit-field 648 * description. 649 * This union is useful but it's not needed by the driver. 650 * 651 * REMOVING this union you are compliant with: 652 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 653 * 654 * @{ 655 * 656 */ 657 typedef union 658 { 659 iis2dh_status_reg_aux_t status_reg_aux; 660 iis2dh_temp_cfg_reg_t temp_cfg_reg; 661 iis2dh_ctrl_reg1_t ctrl_reg1; 662 iis2dh_ctrl_reg2_t ctrl_reg2; 663 iis2dh_ctrl_reg3_t ctrl_reg3; 664 iis2dh_ctrl_reg4_t ctrl_reg4; 665 iis2dh_ctrl_reg5_t ctrl_reg5; 666 iis2dh_ctrl_reg6_t ctrl_reg6; 667 iis2dh_status_reg_t status_reg; 668 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg; 669 iis2dh_fifo_src_reg_t fifo_src_reg; 670 iis2dh_int1_cfg_t int1_cfg; 671 iis2dh_int1_src_t int1_src; 672 iis2dh_int1_ths_t int1_ths; 673 iis2dh_int1_duration_t int1_duration; 674 iis2dh_int2_cfg_t int2_cfg; 675 iis2dh_int2_src_t int2_src; 676 iis2dh_int2_ths_t int2_ths; 677 iis2dh_int2_duration_t int2_duration; 678 iis2dh_click_cfg_t click_cfg; 679 iis2dh_click_src_t click_src; 680 iis2dh_click_ths_t click_ths; 681 iis2dh_time_limit_t time_limit; 682 iis2dh_time_latency_t time_latency; 683 iis2dh_time_window_t time_window; 684 iis2dh_act_ths_t act_ths; 685 iis2dh_act_dur_t act_dur; 686 bitwise_t bitwise; 687 uint8_t byte; 688 } iis2dh_reg_t; 689 690 /** 691 * @} 692 * 693 */ 694 695 #ifndef __weak 696 #define __weak __attribute__((weak)) 697 #endif /* __weak */ 698 699 /* 700 * These are the basic platform dependent I/O routines to read 701 * and write device registers connected on a standard bus. 702 * The driver keeps offering a default implementation based on function 703 * pointers to read/write routines for backward compatibility. 704 * The __weak directive allows the final application to overwrite 705 * them with a custom implementation. 706 */ 707 708 int32_t iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 709 uint16_t len); 710 int32_t iis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 711 uint8_t *data, 712 uint16_t len); 713 714 float_t iis2dh_from_fs2_hr_to_mg(int16_t lsb); 715 float_t iis2dh_from_fs4_hr_to_mg(int16_t lsb); 716 float_t iis2dh_from_fs8_hr_to_mg(int16_t lsb); 717 float_t iis2dh_from_fs16_hr_to_mg(int16_t lsb); 718 float_t iis2dh_from_lsb_hr_to_celsius(int16_t lsb); 719 720 float_t iis2dh_from_fs2_nm_to_mg(int16_t lsb); 721 float_t iis2dh_from_fs4_nm_to_mg(int16_t lsb); 722 float_t iis2dh_from_fs8_nm_to_mg(int16_t lsb); 723 float_t iis2dh_from_fs16_nm_to_mg(int16_t lsb); 724 float_t iis2dh_from_lsb_nm_to_celsius(int16_t lsb); 725 726 float_t iis2dh_from_fs2_lp_to_mg(int16_t lsb); 727 float_t iis2dh_from_fs4_lp_to_mg(int16_t lsb); 728 float_t iis2dh_from_fs8_lp_to_mg(int16_t lsb); 729 float_t iis2dh_from_fs16_lp_to_mg(int16_t lsb); 730 float_t iis2dh_from_lsb_lp_to_celsius(int16_t lsb); 731 732 int32_t iis2dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff); 733 int32_t iis2dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 734 735 int32_t iis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 736 737 int32_t iis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 738 739 typedef enum 740 { 741 IIS2DH_TEMP_DISABLE = 0, 742 IIS2DH_TEMP_ENABLE = 3, 743 } iis2dh_temp_en_t; 744 int32_t iis2dh_temperature_meas_set(stmdev_ctx_t *ctx, 745 iis2dh_temp_en_t val); 746 int32_t iis2dh_temperature_meas_get(stmdev_ctx_t *ctx, 747 iis2dh_temp_en_t *val); 748 749 typedef enum 750 { 751 IIS2DH_HR_12bit = 0, 752 IIS2DH_NM_10bit = 1, 753 IIS2DH_LP_8bit = 2, 754 } iis2dh_op_md_t; 755 int32_t iis2dh_operating_mode_set(stmdev_ctx_t *ctx, 756 iis2dh_op_md_t val); 757 int32_t iis2dh_operating_mode_get(stmdev_ctx_t *ctx, 758 iis2dh_op_md_t *val); 759 760 typedef enum 761 { 762 IIS2DH_POWER_DOWN = 0x00, 763 IIS2DH_ODR_1Hz = 0x01, 764 IIS2DH_ODR_10Hz = 0x02, 765 IIS2DH_ODR_25Hz = 0x03, 766 IIS2DH_ODR_50Hz = 0x04, 767 IIS2DH_ODR_100Hz = 0x05, 768 IIS2DH_ODR_200Hz = 0x06, 769 IIS2DH_ODR_400Hz = 0x07, 770 IIS2DH_ODR_1kHz620_LP = 0x08, 771 IIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP = 0x09, 772 } iis2dh_odr_t; 773 int32_t iis2dh_data_rate_set(stmdev_ctx_t *ctx, iis2dh_odr_t val); 774 int32_t iis2dh_data_rate_get(stmdev_ctx_t *ctx, iis2dh_odr_t *val); 775 776 int32_t iis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx, 777 uint8_t val); 778 int32_t iis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx, 779 uint8_t *val); 780 781 typedef enum 782 { 783 IIS2DH_AGGRESSIVE = 0, 784 IIS2DH_STRONG = 1, 785 IIS2DH_MEDIUM = 2, 786 IIS2DH_LIGHT = 3, 787 } iis2dh_hpcf_t; 788 int32_t iis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx, 789 iis2dh_hpcf_t val); 790 int32_t iis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx, 791 iis2dh_hpcf_t *val); 792 793 typedef enum 794 { 795 IIS2DH_NORMAL_WITH_RST = 0, 796 IIS2DH_REFERENCE_MODE = 1, 797 IIS2DH_NORMAL = 2, 798 IIS2DH_AUTORST_ON_INT = 3, 799 } iis2dh_hpm_t; 800 int32_t iis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, 801 iis2dh_hpm_t val); 802 int32_t iis2dh_high_pass_mode_get(stmdev_ctx_t *ctx, 803 iis2dh_hpm_t *val); 804 805 typedef enum 806 { 807 IIS2DH_2g = 0, 808 IIS2DH_4g = 1, 809 IIS2DH_8g = 2, 810 IIS2DH_16g = 3, 811 } iis2dh_fs_t; 812 int32_t iis2dh_full_scale_set(stmdev_ctx_t *ctx, iis2dh_fs_t val); 813 int32_t iis2dh_full_scale_get(stmdev_ctx_t *ctx, iis2dh_fs_t *val); 814 815 int32_t iis2dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 816 int32_t iis2dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); 817 818 int32_t iis2dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff); 819 int32_t iis2dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff); 820 821 int32_t iis2dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 822 823 int32_t iis2dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val); 824 825 int32_t iis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val); 826 827 int32_t iis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 828 829 typedef enum 830 { 831 IIS2DH_ST_DISABLE = 0, 832 IIS2DH_ST_POSITIVE = 1, 833 IIS2DH_ST_NEGATIVE = 2, 834 } iis2dh_st_t; 835 int32_t iis2dh_self_test_set(stmdev_ctx_t *ctx, iis2dh_st_t val); 836 int32_t iis2dh_self_test_get(stmdev_ctx_t *ctx, iis2dh_st_t *val); 837 838 typedef enum 839 { 840 IIS2DH_LSB_AT_LOW_ADD = 0, 841 IIS2DH_MSB_AT_LOW_ADD = 1, 842 } iis2dh_ble_t; 843 int32_t iis2dh_data_format_set(stmdev_ctx_t *ctx, iis2dh_ble_t val); 844 int32_t iis2dh_data_format_get(stmdev_ctx_t *ctx, iis2dh_ble_t *val); 845 846 int32_t iis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val); 847 int32_t iis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 848 int32_t iis2dh_int_occurrencies_get(stmdev_ctx_t *ctx, uint8_t *val); 849 850 int32_t iis2dh_status_get(stmdev_ctx_t *ctx, 851 iis2dh_status_reg_t *val); 852 853 int32_t iis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx, 854 iis2dh_int1_cfg_t *val); 855 int32_t iis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx, 856 iis2dh_int1_cfg_t *val); 857 858 int32_t iis2dh_int1_gen_source_get(stmdev_ctx_t *ctx, 859 iis2dh_int1_src_t *val); 860 861 int32_t iis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 862 int32_t iis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, 863 uint8_t *val); 864 865 int32_t iis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val); 866 int32_t iis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val); 867 868 int32_t iis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx, 869 iis2dh_int2_cfg_t *val); 870 int32_t iis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx, 871 iis2dh_int2_cfg_t *val); 872 873 int32_t iis2dh_int2_gen_source_get(stmdev_ctx_t *ctx, 874 iis2dh_int2_src_t *val); 875 876 int32_t iis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 877 int32_t iis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, 878 uint8_t *val); 879 880 int32_t iis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val); 881 int32_t iis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val); 882 883 typedef enum 884 { 885 IIS2DH_DISC_FROM_INT_GENERATOR = 0, 886 IIS2DH_ON_INT1_GEN = 1, 887 IIS2DH_ON_INT2_GEN = 2, 888 IIS2DH_ON_TAP_GEN = 4, 889 IIS2DH_ON_INT1_INT2_GEN = 3, 890 IIS2DH_ON_INT1_TAP_GEN = 5, 891 IIS2DH_ON_INT2_TAP_GEN = 6, 892 IIS2DH_ON_INT1_INT2_TAP_GEN = 7, 893 } iis2dh_hp_t; 894 int32_t iis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx, 895 iis2dh_hp_t val); 896 int32_t iis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx, 897 iis2dh_hp_t *val); 898 899 int32_t iis2dh_pin_int1_config_set(stmdev_ctx_t *ctx, 900 iis2dh_ctrl_reg3_t *val); 901 int32_t iis2dh_pin_int1_config_get(stmdev_ctx_t *ctx, 902 iis2dh_ctrl_reg3_t *val); 903 904 int32_t iis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val); 905 int32_t iis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, 906 uint8_t *val); 907 908 typedef enum 909 { 910 IIS2DH_INT2_PULSED = 0, 911 IIS2DH_INT2_LATCHED = 1, 912 } iis2dh_lir_int2_t; 913 int32_t iis2dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx, 914 iis2dh_lir_int2_t val); 915 int32_t iis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx, 916 iis2dh_lir_int2_t *val); 917 918 int32_t iis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val); 919 int32_t iis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, 920 uint8_t *val); 921 922 typedef enum 923 { 924 IIS2DH_INT1_PULSED = 0, 925 IIS2DH_INT1_LATCHED = 1, 926 } iis2dh_lir_int1_t; 927 int32_t iis2dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx, 928 iis2dh_lir_int1_t val); 929 int32_t iis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx, 930 iis2dh_lir_int1_t *val); 931 932 int32_t iis2dh_pin_int2_config_set(stmdev_ctx_t *ctx, 933 iis2dh_ctrl_reg6_t *val); 934 int32_t iis2dh_pin_int2_config_get(stmdev_ctx_t *ctx, 935 iis2dh_ctrl_reg6_t *val); 936 937 int32_t iis2dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val); 938 int32_t iis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val); 939 940 int32_t iis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val); 941 int32_t iis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val); 942 943 typedef enum 944 { 945 IIS2DH_INT1_GEN = 0, 946 IIS2DH_INT2_GEN = 1, 947 } iis2dh_tr_t; 948 int32_t iis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx, 949 iis2dh_tr_t val); 950 int32_t iis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx, 951 iis2dh_tr_t *val); 952 953 typedef enum 954 { 955 IIS2DH_BYPASS_MODE = 0, 956 IIS2DH_FIFO_MODE = 1, 957 IIS2DH_DYNAMIC_STREAM_MODE = 2, 958 IIS2DH_STREAM_TO_FIFO_MODE = 3, 959 } iis2dh_fm_t; 960 int32_t iis2dh_fifo_mode_set(stmdev_ctx_t *ctx, iis2dh_fm_t val); 961 int32_t iis2dh_fifo_mode_get(stmdev_ctx_t *ctx, iis2dh_fm_t *val); 962 963 int32_t iis2dh_fifo_status_get(stmdev_ctx_t *ctx, 964 iis2dh_fifo_src_reg_t *val); 965 966 int32_t iis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val); 967 968 int32_t iis2dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 969 970 int32_t iis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 971 972 int32_t iis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val); 973 974 int32_t iis2dh_tap_conf_set(stmdev_ctx_t *ctx, 975 iis2dh_click_cfg_t *val); 976 int32_t iis2dh_tap_conf_get(stmdev_ctx_t *ctx, 977 iis2dh_click_cfg_t *val); 978 979 int32_t iis2dh_tap_source_get(stmdev_ctx_t *ctx, 980 iis2dh_click_src_t *val); 981 982 int32_t iis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 983 int32_t iis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 984 985 typedef enum 986 { 987 IIS2DH_TAP_PULSED = 0, 988 IIS2DH_TAP_LATCHED = 1, 989 } iis2dh_lir_click_t; 990 int32_t iis2dh_tap_notification_mode_set(stmdev_ctx_t *ctx, 991 iis2dh_lir_click_t val); 992 int32_t iis2dh_tap_notification_mode_get(stmdev_ctx_t *ctx, 993 iis2dh_lir_click_t *val); 994 995 int32_t iis2dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val); 996 int32_t iis2dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 997 998 int32_t iis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val); 999 int32_t iis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val); 1000 1001 int32_t iis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val); 1002 int32_t iis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx, 1003 uint8_t *val); 1004 1005 int32_t iis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val); 1006 int32_t iis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); 1007 1008 int32_t iis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val); 1009 int32_t iis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); 1010 1011 typedef enum 1012 { 1013 IIS2DH_PULL_UP_DISCONNECT = 0, 1014 IIS2DH_PULL_UP_CONNECT = 1, 1015 } iis2dh_sdo_pu_disc_t; 1016 int32_t iis2dh_pin_sdo_sa0_mode_set(stmdev_ctx_t *ctx, 1017 iis2dh_sdo_pu_disc_t val); 1018 int32_t iis2dh_pin_sdo_sa0_mode_get(stmdev_ctx_t *ctx, 1019 iis2dh_sdo_pu_disc_t *val); 1020 1021 typedef enum 1022 { 1023 IIS2DH_SPI_4_WIRE = 0, 1024 IIS2DH_SPI_3_WIRE = 1, 1025 } iis2dh_sim_t; 1026 int32_t iis2dh_spi_mode_set(stmdev_ctx_t *ctx, iis2dh_sim_t val); 1027 int32_t iis2dh_spi_mode_get(stmdev_ctx_t *ctx, iis2dh_sim_t *val); 1028 1029 /** 1030 * @} 1031 * 1032 */ 1033 1034 #ifdef __cplusplus 1035 } 1036 #endif 1037 1038 #endif /* IIS2DH_REGS_H */ 1039 1040 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1041
