1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_SRE_EL1 S3_0_C12_C12_5 83 #define ICC_SRE_EL2 S3_4_C12_C9_5 84 #define ICC_SRE_EL3 S3_6_C12_C12_5 85 #define ICC_CTLR_EL1 S3_0_C12_C12_4 86 #define ICC_CTLR_EL3 S3_6_C12_C12_4 87 #define ICC_PMR_EL1 S3_0_C4_C6_0 88 #define ICC_RPR_EL1 S3_0_C12_C11_3 89 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 90 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 91 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 92 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 93 #define ICC_IAR0_EL1 S3_0_c12_c8_0 94 #define ICC_IAR1_EL1 S3_0_c12_c12_0 95 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 96 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 97 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 98 99 /******************************************************************************* 100 * Definitions for EL2 system registers for save/restore routine 101 ******************************************************************************/ 102 #define CNTPOFF_EL2 S3_4_C14_C0_6 103 #define HAFGRTR_EL2 S3_4_C3_C1_6 104 #define HDFGRTR_EL2 S3_4_C3_C1_4 105 #define HDFGWTR_EL2 S3_4_C3_C1_5 106 #define HFGITR_EL2 S3_4_C1_C1_6 107 #define HFGRTR_EL2 S3_4_C1_C1_4 108 #define HFGWTR_EL2 S3_4_C1_C1_5 109 #define ICH_HCR_EL2 S3_4_C12_C11_0 110 #define ICH_VMCR_EL2 S3_4_C12_C11_7 111 #define MPAMVPM0_EL2 S3_4_C10_C6_0 112 #define MPAMVPM1_EL2 S3_4_C10_C6_1 113 #define MPAMVPM2_EL2 S3_4_C10_C6_2 114 #define MPAMVPM3_EL2 S3_4_C10_C6_3 115 #define MPAMVPM4_EL2 S3_4_C10_C6_4 116 #define MPAMVPM5_EL2 S3_4_C10_C6_5 117 #define MPAMVPM6_EL2 S3_4_C10_C6_6 118 #define MPAMVPM7_EL2 S3_4_C10_C6_7 119 #define MPAMVPMV_EL2 S3_4_C10_C4_1 120 #define TRFCR_EL2 S3_4_C1_C2_1 121 #define PMSCR_EL2 S3_4_C9_C9_0 122 #define TFSR_EL2 S3_4_C5_C6_0 123 124 /******************************************************************************* 125 * Generic timer memory mapped registers & offsets 126 ******************************************************************************/ 127 #define CNTCR_OFF U(0x000) 128 #define CNTCV_OFF U(0x008) 129 #define CNTFID_OFF U(0x020) 130 131 #define CNTCR_EN (U(1) << 0) 132 #define CNTCR_HDBG (U(1) << 1) 133 #define CNTCR_FCREQ(x) ((x) << 8) 134 135 /******************************************************************************* 136 * System register bit definitions 137 ******************************************************************************/ 138 /* CLIDR definitions */ 139 #define LOUIS_SHIFT U(21) 140 #define LOC_SHIFT U(24) 141 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 142 #define CLIDR_FIELD_WIDTH U(3) 143 144 /* CSSELR definitions */ 145 #define LEVEL_SHIFT U(1) 146 147 /* Data cache set/way op type defines */ 148 #define DCISW U(0x0) 149 #define DCCISW U(0x1) 150 #if ERRATA_A53_827319 151 #define DCCSW DCCISW 152 #else 153 #define DCCSW U(0x2) 154 #endif 155 156 /* ID_AA64PFR0_EL1 definitions */ 157 #define ID_AA64PFR0_EL0_SHIFT U(0) 158 #define ID_AA64PFR0_EL1_SHIFT U(4) 159 #define ID_AA64PFR0_EL2_SHIFT U(8) 160 #define ID_AA64PFR0_EL3_SHIFT U(12) 161 162 #define ID_AA64PFR0_AMU_SHIFT U(44) 163 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 164 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 165 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 166 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 167 168 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 169 170 #define ID_AA64PFR0_GIC_SHIFT U(24) 171 #define ID_AA64PFR0_GIC_WIDTH U(4) 172 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 173 174 #define ID_AA64PFR0_SVE_SHIFT U(32) 175 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 176 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 177 #define ID_AA64PFR0_SVE_LENGTH U(4) 178 179 #define ID_AA64PFR0_SEL2_SHIFT U(36) 180 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 181 182 #define ID_AA64PFR0_MPAM_SHIFT U(40) 183 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 184 185 #define ID_AA64PFR0_DIT_SHIFT U(48) 186 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 187 #define ID_AA64PFR0_DIT_LENGTH U(4) 188 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 189 190 #define ID_AA64PFR0_CSV2_SHIFT U(56) 191 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 192 #define ID_AA64PFR0_CSV2_LENGTH U(4) 193 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 194 195 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 196 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 197 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 198 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 199 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 200 201 #define ID_AA64PFR0_RAS_SHIFT U(28) 202 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 203 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 204 #define ID_AA64PFR0_RAS_LENGTH U(4) 205 206 /* Exception level handling */ 207 #define EL_IMPL_NONE ULL(0) 208 #define EL_IMPL_A64ONLY ULL(1) 209 #define EL_IMPL_A64_A32 ULL(2) 210 211 /* ID_AA64DFR0_EL1.TraceVer definitions */ 212 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 213 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 214 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 215 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 216 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 217 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 218 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 219 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 220 221 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 222 #define ID_AA64DFR0_PMS_SHIFT U(32) 223 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 224 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 225 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 226 227 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 228 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 229 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 230 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 231 232 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 233 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 234 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 235 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 236 237 /* ID_AA64DFR0_EL1.BRBE definitions */ 238 #define ID_AA64DFR0_BRBE_SHIFT U(52) 239 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 240 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 241 242 /* ID_AA64ISAR0_EL1 definitions */ 243 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 244 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 245 246 /* ID_AA64ISAR1_EL1 definitions */ 247 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 248 249 #define ID_AA64ISAR1_GPI_SHIFT U(28) 250 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 251 #define ID_AA64ISAR1_GPA_SHIFT U(24) 252 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 253 254 #define ID_AA64ISAR1_API_SHIFT U(8) 255 #define ID_AA64ISAR1_API_MASK ULL(0xf) 256 #define ID_AA64ISAR1_APA_SHIFT U(4) 257 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 258 259 #define ID_AA64ISAR1_SB_SHIFT U(36) 260 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 261 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 262 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 263 264 /* ID_AA64MMFR0_EL1 definitions */ 265 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 266 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 267 268 #define PARANGE_0000 U(32) 269 #define PARANGE_0001 U(36) 270 #define PARANGE_0010 U(40) 271 #define PARANGE_0011 U(42) 272 #define PARANGE_0100 U(44) 273 #define PARANGE_0101 U(48) 274 #define PARANGE_0110 U(52) 275 276 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 277 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 278 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 279 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 280 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 281 282 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 283 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 284 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 285 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 286 287 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 288 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 289 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 290 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 291 292 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 293 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 294 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 295 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 296 297 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 298 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 299 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 300 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 301 302 /* ID_AA64MMFR1_EL1 definitions */ 303 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 304 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 305 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 306 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 307 308 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 309 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 310 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 311 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 312 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 313 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 314 315 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 316 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 317 318 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 319 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 320 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 321 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 322 323 /* ID_AA64MMFR2_EL1 definitions */ 324 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 325 326 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 327 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 328 329 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 330 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 331 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 332 333 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 334 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 335 336 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 337 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 338 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 339 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 340 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 341 342 /* ID_AA64PFR1_EL1 definitions */ 343 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 344 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 345 346 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 347 348 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 349 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 350 351 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 352 353 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 354 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 355 356 /* Memory Tagging Extension is not implemented */ 357 #define MTE_UNIMPLEMENTED U(0) 358 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 359 #define MTE_IMPLEMENTED_EL0 U(1) 360 /* FEAT_MTE2: Full MTE is implemented */ 361 #define MTE_IMPLEMENTED_ELX U(2) 362 /* 363 * FEAT_MTE3: MTE is implemented with support for 364 * asymmetric Tag Check Fault handling 365 */ 366 #define MTE_IMPLEMENTED_ASY U(3) 367 368 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 369 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 370 371 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 372 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 373 374 /* ID_PFR1_EL1 definitions */ 375 #define ID_PFR1_VIRTEXT_SHIFT U(12) 376 #define ID_PFR1_VIRTEXT_MASK U(0xf) 377 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 378 & ID_PFR1_VIRTEXT_MASK) 379 380 /* SCTLR definitions */ 381 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 382 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 383 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 384 385 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 386 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 387 388 #define SCTLR_AARCH32_EL1_RES1 \ 389 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 390 (U(1) << 4) | (U(1) << 3)) 391 392 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 393 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 394 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 395 396 #define SCTLR_M_BIT (ULL(1) << 0) 397 #define SCTLR_A_BIT (ULL(1) << 1) 398 #define SCTLR_C_BIT (ULL(1) << 2) 399 #define SCTLR_SA_BIT (ULL(1) << 3) 400 #define SCTLR_SA0_BIT (ULL(1) << 4) 401 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 402 #define SCTLR_nAA_BIT (ULL(1) << 6) 403 #define SCTLR_ITD_BIT (ULL(1) << 7) 404 #define SCTLR_SED_BIT (ULL(1) << 8) 405 #define SCTLR_UMA_BIT (ULL(1) << 9) 406 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 407 #define SCTLR_EOS_BIT (ULL(1) << 11) 408 #define SCTLR_I_BIT (ULL(1) << 12) 409 #define SCTLR_EnDB_BIT (ULL(1) << 13) 410 #define SCTLR_DZE_BIT (ULL(1) << 14) 411 #define SCTLR_UCT_BIT (ULL(1) << 15) 412 #define SCTLR_NTWI_BIT (ULL(1) << 16) 413 #define SCTLR_NTWE_BIT (ULL(1) << 18) 414 #define SCTLR_WXN_BIT (ULL(1) << 19) 415 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 416 #define SCTLR_IESB_BIT (ULL(1) << 21) 417 #define SCTLR_EIS_BIT (ULL(1) << 22) 418 #define SCTLR_SPAN_BIT (ULL(1) << 23) 419 #define SCTLR_E0E_BIT (ULL(1) << 24) 420 #define SCTLR_EE_BIT (ULL(1) << 25) 421 #define SCTLR_UCI_BIT (ULL(1) << 26) 422 #define SCTLR_EnDA_BIT (ULL(1) << 27) 423 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 424 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 425 #define SCTLR_EnIB_BIT (ULL(1) << 30) 426 #define SCTLR_EnIA_BIT (ULL(1) << 31) 427 #define SCTLR_BT0_BIT (ULL(1) << 35) 428 #define SCTLR_BT1_BIT (ULL(1) << 36) 429 #define SCTLR_BT_BIT (ULL(1) << 36) 430 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 431 #define SCTLR_TCF0_SHIFT U(38) 432 #define SCTLR_TCF0_MASK ULL(3) 433 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 434 435 /* Tag Check Faults in EL0 have no effect on the PE */ 436 #define SCTLR_TCF0_NO_EFFECT U(0) 437 /* Tag Check Faults in EL0 cause a synchronous exception */ 438 #define SCTLR_TCF0_SYNC U(1) 439 /* Tag Check Faults in EL0 are asynchronously accumulated */ 440 #define SCTLR_TCF0_ASYNC U(2) 441 /* 442 * Tag Check Faults in EL0 cause a synchronous exception on reads, 443 * and are asynchronously accumulated on writes 444 */ 445 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 446 447 #define SCTLR_TCF_SHIFT U(40) 448 #define SCTLR_TCF_MASK ULL(3) 449 450 /* Tag Check Faults in EL1 have no effect on the PE */ 451 #define SCTLR_TCF_NO_EFFECT U(0) 452 /* Tag Check Faults in EL1 cause a synchronous exception */ 453 #define SCTLR_TCF_SYNC U(1) 454 /* Tag Check Faults in EL1 are asynchronously accumulated */ 455 #define SCTLR_TCF_ASYNC U(2) 456 /* 457 * Tag Check Faults in EL1 cause a synchronous exception on reads, 458 * and are asynchronously accumulated on writes 459 */ 460 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 461 462 #define SCTLR_ATA0_BIT (ULL(1) << 42) 463 #define SCTLR_ATA_BIT (ULL(1) << 43) 464 #define SCTLR_DSSBS_SHIFT U(44) 465 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 466 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 467 #define SCTLR_TWEDEL_SHIFT U(46) 468 #define SCTLR_TWEDEL_MASK ULL(0xf) 469 #define SCTLR_EnASR_BIT (ULL(1) << 54) 470 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 471 #define SCTLR_EnALS_BIT (ULL(1) << 56) 472 #define SCTLR_EPAN_BIT (ULL(1) << 57) 473 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 474 475 /* CPACR_EL1 definitions */ 476 #define CPACR_EL1_FPEN(x) ((x) << 20) 477 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 478 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 479 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 480 481 /* SCR definitions */ 482 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 483 #define SCR_NSE_SHIFT U(62) 484 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 485 #define SCR_GPF_BIT (UL(1) << 48) 486 #define SCR_TWEDEL_SHIFT U(30) 487 #define SCR_TWEDEL_MASK ULL(0xf) 488 #define SCR_HXEn_BIT (UL(1) << 38) 489 #define SCR_ENTP2_SHIFT U(41) 490 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 491 #define SCR_AMVOFFEN_SHIFT U(35) 492 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 493 #define SCR_TWEDEn_BIT (UL(1) << 29) 494 #define SCR_ECVEN_BIT (UL(1) << 28) 495 #define SCR_FGTEN_BIT (UL(1) << 27) 496 #define SCR_ATA_BIT (UL(1) << 26) 497 #define SCR_EnSCXT_BIT (UL(1) << 25) 498 #define SCR_FIEN_BIT (UL(1) << 21) 499 #define SCR_EEL2_BIT (UL(1) << 18) 500 #define SCR_API_BIT (UL(1) << 17) 501 #define SCR_APK_BIT (UL(1) << 16) 502 #define SCR_TERR_BIT (UL(1) << 15) 503 #define SCR_TWE_BIT (UL(1) << 13) 504 #define SCR_TWI_BIT (UL(1) << 12) 505 #define SCR_ST_BIT (UL(1) << 11) 506 #define SCR_RW_BIT (UL(1) << 10) 507 #define SCR_SIF_BIT (UL(1) << 9) 508 #define SCR_HCE_BIT (UL(1) << 8) 509 #define SCR_SMD_BIT (UL(1) << 7) 510 #define SCR_EA_BIT (UL(1) << 3) 511 #define SCR_FIQ_BIT (UL(1) << 2) 512 #define SCR_IRQ_BIT (UL(1) << 1) 513 #define SCR_NS_BIT (UL(1) << 0) 514 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 515 #define SCR_RESET_VAL SCR_RES1_BITS 516 517 /* MDCR_EL3 definitions */ 518 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 519 #define MDCR_MPMX_BIT (ULL(1) << 35) 520 #define MDCR_MCCD_BIT (ULL(1) << 34) 521 #define MDCR_SBRBE_SHIFT U(32) 522 #define MDCR_SBRBE_MASK ULL(0x3) 523 #define MDCR_NSTB(x) ((x) << 24) 524 #define MDCR_NSTB_EL1 ULL(0x3) 525 #define MDCR_NSTBE (ULL(1) << 26) 526 #define MDCR_MTPME_BIT (ULL(1) << 28) 527 #define MDCR_TDCC_BIT (ULL(1) << 27) 528 #define MDCR_SCCD_BIT (ULL(1) << 23) 529 #define MDCR_EPMAD_BIT (ULL(1) << 21) 530 #define MDCR_EDAD_BIT (ULL(1) << 20) 531 #define MDCR_TTRF_BIT (ULL(1) << 19) 532 #define MDCR_STE_BIT (ULL(1) << 18) 533 #define MDCR_SPME_BIT (ULL(1) << 17) 534 #define MDCR_SDD_BIT (ULL(1) << 16) 535 #define MDCR_SPD32(x) ((x) << 14) 536 #define MDCR_SPD32_LEGACY ULL(0x0) 537 #define MDCR_SPD32_DISABLE ULL(0x2) 538 #define MDCR_SPD32_ENABLE ULL(0x3) 539 #define MDCR_NSPB(x) ((x) << 12) 540 #define MDCR_NSPB_EL1 ULL(0x3) 541 #define MDCR_TDOSA_BIT (ULL(1) << 10) 542 #define MDCR_TDA_BIT (ULL(1) << 9) 543 #define MDCR_TPM_BIT (ULL(1) << 6) 544 #define MDCR_EL3_RESET_VAL ULL(0x0) 545 546 /* MDCR_EL2 definitions */ 547 #define MDCR_EL2_MTPME (U(1) << 28) 548 #define MDCR_EL2_HLP (U(1) << 26) 549 #define MDCR_EL2_E2TB(x) ((x) << 24) 550 #define MDCR_EL2_E2TB_EL1 U(0x3) 551 #define MDCR_EL2_HCCD (U(1) << 23) 552 #define MDCR_EL2_TTRF (U(1) << 19) 553 #define MDCR_EL2_HPMD (U(1) << 17) 554 #define MDCR_EL2_TPMS (U(1) << 14) 555 #define MDCR_EL2_E2PB(x) ((x) << 12) 556 #define MDCR_EL2_E2PB_EL1 U(0x3) 557 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 558 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 559 #define MDCR_EL2_TDA_BIT (U(1) << 9) 560 #define MDCR_EL2_TDE_BIT (U(1) << 8) 561 #define MDCR_EL2_HPME_BIT (U(1) << 7) 562 #define MDCR_EL2_TPM_BIT (U(1) << 6) 563 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 564 #define MDCR_EL2_RESET_VAL U(0x0) 565 566 /* HSTR_EL2 definitions */ 567 #define HSTR_EL2_RESET_VAL U(0x0) 568 #define HSTR_EL2_T_MASK U(0xff) 569 570 /* CNTHP_CTL_EL2 definitions */ 571 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 572 #define CNTHP_CTL_RESET_VAL U(0x0) 573 574 /* VTTBR_EL2 definitions */ 575 #define VTTBR_RESET_VAL ULL(0x0) 576 #define VTTBR_VMID_MASK ULL(0xff) 577 #define VTTBR_VMID_SHIFT U(48) 578 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 579 #define VTTBR_BADDR_SHIFT U(0) 580 581 /* HCR definitions */ 582 #define HCR_RESET_VAL ULL(0x0) 583 #define HCR_AMVOFFEN_SHIFT U(51) 584 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 585 #define HCR_TEA_BIT (ULL(1) << 47) 586 #define HCR_API_BIT (ULL(1) << 41) 587 #define HCR_APK_BIT (ULL(1) << 40) 588 #define HCR_E2H_BIT (ULL(1) << 34) 589 #define HCR_HCD_BIT (ULL(1) << 29) 590 #define HCR_TGE_BIT (ULL(1) << 27) 591 #define HCR_RW_SHIFT U(31) 592 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 593 #define HCR_TWE_BIT (ULL(1) << 14) 594 #define HCR_TWI_BIT (ULL(1) << 13) 595 #define HCR_AMO_BIT (ULL(1) << 5) 596 #define HCR_IMO_BIT (ULL(1) << 4) 597 #define HCR_FMO_BIT (ULL(1) << 3) 598 599 /* ISR definitions */ 600 #define ISR_A_SHIFT U(8) 601 #define ISR_I_SHIFT U(7) 602 #define ISR_F_SHIFT U(6) 603 604 /* CNTHCTL_EL2 definitions */ 605 #define CNTHCTL_RESET_VAL U(0x0) 606 #define EVNTEN_BIT (U(1) << 2) 607 #define EL1PCEN_BIT (U(1) << 1) 608 #define EL1PCTEN_BIT (U(1) << 0) 609 610 /* CNTKCTL_EL1 definitions */ 611 #define EL0PTEN_BIT (U(1) << 9) 612 #define EL0VTEN_BIT (U(1) << 8) 613 #define EL0PCTEN_BIT (U(1) << 0) 614 #define EL0VCTEN_BIT (U(1) << 1) 615 #define EVNTEN_BIT (U(1) << 2) 616 #define EVNTDIR_BIT (U(1) << 3) 617 #define EVNTI_SHIFT U(4) 618 #define EVNTI_MASK U(0xf) 619 620 /* CPTR_EL3 definitions */ 621 #define TCPAC_BIT (U(1) << 31) 622 #define TAM_SHIFT U(30) 623 #define TAM_BIT (U(1) << TAM_SHIFT) 624 #define TTA_BIT (U(1) << 20) 625 #define ESM_BIT (U(1) << 12) 626 #define TFP_BIT (U(1) << 10) 627 #define CPTR_EZ_BIT (U(1) << 8) 628 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 629 ~(CPTR_EZ_BIT | ESM_BIT)) 630 631 /* CPTR_EL2 definitions */ 632 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 633 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 634 #define CPTR_EL2_TAM_SHIFT U(30) 635 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 636 #define CPTR_EL2_SMEN_MASK ULL(0x3) 637 #define CPTR_EL2_SMEN_SHIFT U(24) 638 #define CPTR_EL2_TTA_BIT (U(1) << 20) 639 #define CPTR_EL2_TSM_BIT (U(1) << 12) 640 #define CPTR_EL2_TFP_BIT (U(1) << 10) 641 #define CPTR_EL2_TZ_BIT (U(1) << 8) 642 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 643 644 /* VTCR_EL2 definitions */ 645 #define VTCR_RESET_VAL U(0x0) 646 #define VTCR_EL2_MSA (U(1) << 31) 647 648 /* CPSR/SPSR definitions */ 649 #define DAIF_FIQ_BIT (U(1) << 0) 650 #define DAIF_IRQ_BIT (U(1) << 1) 651 #define DAIF_ABT_BIT (U(1) << 2) 652 #define DAIF_DBG_BIT (U(1) << 3) 653 #define SPSR_DAIF_SHIFT U(6) 654 #define SPSR_DAIF_MASK U(0xf) 655 656 #define SPSR_AIF_SHIFT U(6) 657 #define SPSR_AIF_MASK U(0x7) 658 659 #define SPSR_E_SHIFT U(9) 660 #define SPSR_E_MASK U(0x1) 661 #define SPSR_E_LITTLE U(0x0) 662 #define SPSR_E_BIG U(0x1) 663 664 #define SPSR_T_SHIFT U(5) 665 #define SPSR_T_MASK U(0x1) 666 #define SPSR_T_ARM U(0x0) 667 #define SPSR_T_THUMB U(0x1) 668 669 #define SPSR_M_SHIFT U(4) 670 #define SPSR_M_MASK U(0x1) 671 #define SPSR_M_AARCH64 U(0x0) 672 #define SPSR_M_AARCH32 U(0x1) 673 #define SPSR_M_EL2H U(0x9) 674 675 #define SPSR_EL_SHIFT U(2) 676 #define SPSR_EL_WIDTH U(2) 677 678 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 679 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 680 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 681 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 682 683 #define SPSR_PAN_BIT BIT_64(22) 684 685 #define SPSR_DIT_BIT BIT(24) 686 687 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 688 689 #define DISABLE_ALL_EXCEPTIONS \ 690 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 691 692 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 693 694 /* 695 * RMR_EL3 definitions 696 */ 697 #define RMR_EL3_RR_BIT (U(1) << 1) 698 #define RMR_EL3_AA64_BIT (U(1) << 0) 699 700 /* 701 * HI-VECTOR address for AArch32 state 702 */ 703 #define HI_VECTOR_BASE U(0xFFFF0000) 704 705 /* 706 * TCR defintions 707 */ 708 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 709 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 710 #define TCR_EL1_IPS_SHIFT U(32) 711 #define TCR_EL2_PS_SHIFT U(16) 712 #define TCR_EL3_PS_SHIFT U(16) 713 714 #define TCR_TxSZ_MIN ULL(16) 715 #define TCR_TxSZ_MAX ULL(39) 716 #define TCR_TxSZ_MAX_TTST ULL(48) 717 718 #define TCR_T0SZ_SHIFT U(0) 719 #define TCR_T1SZ_SHIFT U(16) 720 721 /* (internal) physical address size bits in EL3/EL1 */ 722 #define TCR_PS_BITS_4GB ULL(0x0) 723 #define TCR_PS_BITS_64GB ULL(0x1) 724 #define TCR_PS_BITS_1TB ULL(0x2) 725 #define TCR_PS_BITS_4TB ULL(0x3) 726 #define TCR_PS_BITS_16TB ULL(0x4) 727 #define TCR_PS_BITS_256TB ULL(0x5) 728 729 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 730 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 731 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 732 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 733 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 734 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 735 736 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 737 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 738 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 739 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 740 741 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 742 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 743 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 744 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 745 746 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 747 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 748 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 749 750 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 751 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 752 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 753 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 754 755 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 756 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 757 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 758 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 759 760 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 761 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 762 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 763 764 #define TCR_TG0_SHIFT U(14) 765 #define TCR_TG0_MASK ULL(3) 766 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 767 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 768 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 769 770 #define TCR_TG1_SHIFT U(30) 771 #define TCR_TG1_MASK ULL(3) 772 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 773 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 774 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 775 776 #define TCR_EPD0_BIT (ULL(1) << 7) 777 #define TCR_EPD1_BIT (ULL(1) << 23) 778 779 #define MODE_SP_SHIFT U(0x0) 780 #define MODE_SP_MASK U(0x1) 781 #define MODE_SP_EL0 U(0x0) 782 #define MODE_SP_ELX U(0x1) 783 784 #define MODE_RW_SHIFT U(0x4) 785 #define MODE_RW_MASK U(0x1) 786 #define MODE_RW_64 U(0x0) 787 #define MODE_RW_32 U(0x1) 788 789 #define MODE_EL_SHIFT U(0x2) 790 #define MODE_EL_MASK U(0x3) 791 #define MODE_EL_WIDTH U(0x2) 792 #define MODE_EL3 U(0x3) 793 #define MODE_EL2 U(0x2) 794 #define MODE_EL1 U(0x1) 795 #define MODE_EL0 U(0x0) 796 797 #define MODE32_SHIFT U(0) 798 #define MODE32_MASK U(0xf) 799 #define MODE32_usr U(0x0) 800 #define MODE32_fiq U(0x1) 801 #define MODE32_irq U(0x2) 802 #define MODE32_svc U(0x3) 803 #define MODE32_mon U(0x6) 804 #define MODE32_abt U(0x7) 805 #define MODE32_hyp U(0xa) 806 #define MODE32_und U(0xb) 807 #define MODE32_sys U(0xf) 808 809 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 810 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 811 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 812 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 813 814 #define SPSR_64(el, sp, daif) \ 815 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 816 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 817 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 818 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 819 (~(SPSR_SSBS_BIT_AARCH64))) 820 821 #define SPSR_MODE32(mode, isa, endian, aif) \ 822 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 823 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 824 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 825 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 826 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 827 (~(SPSR_SSBS_BIT_AARCH32))) 828 829 /* 830 * TTBR Definitions 831 */ 832 #define TTBR_CNP_BIT ULL(0x1) 833 834 /* 835 * CTR_EL0 definitions 836 */ 837 #define CTR_CWG_SHIFT U(24) 838 #define CTR_CWG_MASK U(0xf) 839 #define CTR_ERG_SHIFT U(20) 840 #define CTR_ERG_MASK U(0xf) 841 #define CTR_DMINLINE_SHIFT U(16) 842 #define CTR_DMINLINE_MASK U(0xf) 843 #define CTR_L1IP_SHIFT U(14) 844 #define CTR_L1IP_MASK U(0x3) 845 #define CTR_IMINLINE_SHIFT U(0) 846 #define CTR_IMINLINE_MASK U(0xf) 847 848 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 849 850 /* Physical timer control register bit fields shifts and masks */ 851 #define CNTP_CTL_ENABLE_SHIFT U(0) 852 #define CNTP_CTL_IMASK_SHIFT U(1) 853 #define CNTP_CTL_ISTATUS_SHIFT U(2) 854 855 #define CNTP_CTL_ENABLE_MASK U(1) 856 #define CNTP_CTL_IMASK_MASK U(1) 857 #define CNTP_CTL_ISTATUS_MASK U(1) 858 859 /* Physical timer control macros */ 860 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 861 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 862 863 /* Exception Syndrome register bits and bobs */ 864 #define ESR_EC_SHIFT U(26) 865 #define ESR_EC_MASK U(0x3f) 866 #define ESR_EC_LENGTH U(6) 867 #define ESR_ISS_SHIFT U(0) 868 #define ESR_ISS_LENGTH U(25) 869 #define EC_UNKNOWN U(0x0) 870 #define EC_WFE_WFI U(0x1) 871 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 872 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 873 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 874 #define EC_AARCH32_CP14_LDC_STC U(0x6) 875 #define EC_FP_SIMD U(0x7) 876 #define EC_AARCH32_CP10_MRC U(0x8) 877 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 878 #define EC_ILLEGAL U(0xe) 879 #define EC_AARCH32_SVC U(0x11) 880 #define EC_AARCH32_HVC U(0x12) 881 #define EC_AARCH32_SMC U(0x13) 882 #define EC_AARCH64_SVC U(0x15) 883 #define EC_AARCH64_HVC U(0x16) 884 #define EC_AARCH64_SMC U(0x17) 885 #define EC_AARCH64_SYS U(0x18) 886 #define EC_IABORT_LOWER_EL U(0x20) 887 #define EC_IABORT_CUR_EL U(0x21) 888 #define EC_PC_ALIGN U(0x22) 889 #define EC_DABORT_LOWER_EL U(0x24) 890 #define EC_DABORT_CUR_EL U(0x25) 891 #define EC_SP_ALIGN U(0x26) 892 #define EC_AARCH32_FP U(0x28) 893 #define EC_AARCH64_FP U(0x2c) 894 #define EC_SERROR U(0x2f) 895 #define EC_BRK U(0x3c) 896 897 /* 898 * External Abort bit in Instruction and Data Aborts synchronous exception 899 * syndromes. 900 */ 901 #define ESR_ISS_EABORT_EA_BIT U(9) 902 903 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 904 905 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 906 #define RMR_RESET_REQUEST_SHIFT U(0x1) 907 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 908 909 /******************************************************************************* 910 * Definitions of register offsets, fields and macros for CPU system 911 * instructions. 912 ******************************************************************************/ 913 914 #define TLBI_ADDR_SHIFT U(12) 915 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 916 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 917 918 /******************************************************************************* 919 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 920 * system level implementation of the Generic Timer. 921 ******************************************************************************/ 922 #define CNTCTLBASE_CNTFRQ U(0x0) 923 #define CNTNSAR U(0x4) 924 #define CNTNSAR_NS_SHIFT(x) (x) 925 926 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 927 #define CNTACR_RPCT_SHIFT U(0x0) 928 #define CNTACR_RVCT_SHIFT U(0x1) 929 #define CNTACR_RFRQ_SHIFT U(0x2) 930 #define CNTACR_RVOFF_SHIFT U(0x3) 931 #define CNTACR_RWVT_SHIFT U(0x4) 932 #define CNTACR_RWPT_SHIFT U(0x5) 933 934 /******************************************************************************* 935 * Definitions of register offsets and fields in the CNTBaseN Frame of the 936 * system level implementation of the Generic Timer. 937 ******************************************************************************/ 938 /* Physical Count register. */ 939 #define CNTPCT_LO U(0x0) 940 /* Counter Frequency register. */ 941 #define CNTBASEN_CNTFRQ U(0x10) 942 /* Physical Timer CompareValue register. */ 943 #define CNTP_CVAL_LO U(0x20) 944 /* Physical Timer Control register. */ 945 #define CNTP_CTL U(0x2c) 946 947 /* PMCR_EL0 definitions */ 948 #define PMCR_EL0_RESET_VAL U(0x0) 949 #define PMCR_EL0_N_SHIFT U(11) 950 #define PMCR_EL0_N_MASK U(0x1f) 951 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 952 #define PMCR_EL0_LP_BIT (U(1) << 7) 953 #define PMCR_EL0_LC_BIT (U(1) << 6) 954 #define PMCR_EL0_DP_BIT (U(1) << 5) 955 #define PMCR_EL0_X_BIT (U(1) << 4) 956 #define PMCR_EL0_D_BIT (U(1) << 3) 957 #define PMCR_EL0_C_BIT (U(1) << 2) 958 #define PMCR_EL0_P_BIT (U(1) << 1) 959 #define PMCR_EL0_E_BIT (U(1) << 0) 960 961 /******************************************************************************* 962 * Definitions for system register interface to SVE 963 ******************************************************************************/ 964 #define ZCR_EL3 S3_6_C1_C2_0 965 #define ZCR_EL2 S3_4_C1_C2_0 966 967 /* ZCR_EL3 definitions */ 968 #define ZCR_EL3_LEN_MASK U(0xf) 969 970 /* ZCR_EL2 definitions */ 971 #define ZCR_EL2_LEN_MASK U(0xf) 972 973 /******************************************************************************* 974 * Definitions for system register interface to SME as needed in EL3 975 ******************************************************************************/ 976 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 977 #define SMCR_EL3 S3_6_C1_C2_6 978 979 /* ID_AA64SMFR0_EL1 definitions */ 980 #define ID_AA64SMFR0_EL1_FA64_BIT (UL(1) << 63) 981 982 /* SMCR_ELx definitions */ 983 #define SMCR_ELX_LEN_SHIFT U(0) 984 #define SMCR_ELX_LEN_MASK U(0x1ff) 985 #define SMCR_ELX_FA64_BIT (U(1) << 31) 986 987 /******************************************************************************* 988 * Definitions of MAIR encodings for device and normal memory 989 ******************************************************************************/ 990 /* 991 * MAIR encodings for device memory attributes. 992 */ 993 #define MAIR_DEV_nGnRnE ULL(0x0) 994 #define MAIR_DEV_nGnRE ULL(0x4) 995 #define MAIR_DEV_nGRE ULL(0x8) 996 #define MAIR_DEV_GRE ULL(0xc) 997 998 /* 999 * MAIR encodings for normal memory attributes. 1000 * 1001 * Cache Policy 1002 * WT: Write Through 1003 * WB: Write Back 1004 * NC: Non-Cacheable 1005 * 1006 * Transient Hint 1007 * NTR: Non-Transient 1008 * TR: Transient 1009 * 1010 * Allocation Policy 1011 * RA: Read Allocate 1012 * WA: Write Allocate 1013 * RWA: Read and Write Allocate 1014 * NA: No Allocation 1015 */ 1016 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1017 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1018 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1019 #define MAIR_NORM_NC ULL(0x4) 1020 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1021 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1022 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1023 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1024 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1025 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1026 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1027 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1028 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1029 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1030 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1031 1032 #define MAIR_NORM_OUTER_SHIFT U(4) 1033 1034 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1035 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1036 1037 /* PAR_EL1 fields */ 1038 #define PAR_F_SHIFT U(0) 1039 #define PAR_F_MASK ULL(0x1) 1040 #define PAR_ADDR_SHIFT U(12) 1041 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1042 1043 /******************************************************************************* 1044 * Definitions for system register interface to SPE 1045 ******************************************************************************/ 1046 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1047 1048 /******************************************************************************* 1049 * Definitions for system register interface to MPAM 1050 ******************************************************************************/ 1051 #define MPAMIDR_EL1 S3_0_C10_C4_4 1052 #define MPAM2_EL2 S3_4_C10_C5_0 1053 #define MPAMHCR_EL2 S3_4_C10_C4_0 1054 #define MPAM3_EL3 S3_6_C10_C5_0 1055 1056 /******************************************************************************* 1057 * Definitions for system register interface to AMU for FEAT_AMUv1 1058 ******************************************************************************/ 1059 #define AMCR_EL0 S3_3_C13_C2_0 1060 #define AMCFGR_EL0 S3_3_C13_C2_1 1061 #define AMCGCR_EL0 S3_3_C13_C2_2 1062 #define AMUSERENR_EL0 S3_3_C13_C2_3 1063 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1064 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1065 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1066 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1067 1068 /* Activity Monitor Group 0 Event Counter Registers */ 1069 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1070 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1071 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1072 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1073 1074 /* Activity Monitor Group 0 Event Type Registers */ 1075 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1076 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1077 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1078 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1079 1080 /* Activity Monitor Group 1 Event Counter Registers */ 1081 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1082 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1083 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1084 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1085 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1086 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1087 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1088 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1089 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1090 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1091 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1092 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1093 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1094 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1095 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1096 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1097 1098 /* Activity Monitor Group 1 Event Type Registers */ 1099 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1100 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1101 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1102 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1103 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1104 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1105 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1106 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1107 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1108 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1109 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1110 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1111 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1112 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1113 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1114 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1115 1116 /* AMCNTENSET0_EL0 definitions */ 1117 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1118 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1119 1120 /* AMCNTENSET1_EL0 definitions */ 1121 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1122 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1123 1124 /* AMCNTENCLR0_EL0 definitions */ 1125 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1126 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1127 1128 /* AMCNTENCLR1_EL0 definitions */ 1129 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1130 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1131 1132 /* AMCFGR_EL0 definitions */ 1133 #define AMCFGR_EL0_NCG_SHIFT U(28) 1134 #define AMCFGR_EL0_NCG_MASK U(0xf) 1135 #define AMCFGR_EL0_N_SHIFT U(0) 1136 #define AMCFGR_EL0_N_MASK U(0xff) 1137 1138 /* AMCGCR_EL0 definitions */ 1139 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1140 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1141 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1142 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1143 1144 /* MPAM register definitions */ 1145 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1146 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1147 1148 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1149 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1150 1151 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1152 1153 /******************************************************************************* 1154 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1155 ******************************************************************************/ 1156 1157 /* Definition for register defining which virtual offsets are implemented. */ 1158 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1159 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1160 #define AMCG1IDR_CTR_SHIFT U(0) 1161 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1162 #define AMCG1IDR_VOFF_SHIFT U(16) 1163 1164 /* New bit added to AMCR_EL0 */ 1165 #define AMCR_CG1RZ_SHIFT U(17) 1166 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1167 1168 /* 1169 * Definitions for virtual offset registers for architected activity monitor 1170 * event counters. 1171 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1172 */ 1173 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1174 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1175 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1176 1177 /* 1178 * Definitions for virtual offset registers for auxiliary activity monitor event 1179 * counters. 1180 */ 1181 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1182 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1183 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1184 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1185 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1186 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1187 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1188 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1189 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1190 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1191 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1192 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1193 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1194 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1195 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1196 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1197 1198 /******************************************************************************* 1199 * Realm management extension register definitions 1200 ******************************************************************************/ 1201 #define GPCCR_EL3 S3_6_C2_C1_6 1202 #define GPTBR_EL3 S3_6_C2_C1_4 1203 1204 /******************************************************************************* 1205 * RAS system registers 1206 ******************************************************************************/ 1207 #define DISR_EL1 S3_0_C12_C1_1 1208 #define DISR_A_BIT U(31) 1209 1210 #define ERRIDR_EL1 S3_0_C5_C3_0 1211 #define ERRIDR_MASK U(0xffff) 1212 1213 #define ERRSELR_EL1 S3_0_C5_C3_1 1214 1215 /* System register access to Standard Error Record registers */ 1216 #define ERXFR_EL1 S3_0_C5_C4_0 1217 #define ERXCTLR_EL1 S3_0_C5_C4_1 1218 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1219 #define ERXADDR_EL1 S3_0_C5_C4_3 1220 #define ERXPFGF_EL1 S3_0_C5_C4_4 1221 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1222 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1223 #define ERXMISC0_EL1 S3_0_C5_C5_0 1224 #define ERXMISC1_EL1 S3_0_C5_C5_1 1225 1226 #define ERXCTLR_ED_SHIFT U(0) 1227 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1228 #define ERXCTLR_UE_BIT (U(1) << 4) 1229 1230 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1231 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1232 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1233 1234 /******************************************************************************* 1235 * Armv8.3 Pointer Authentication Registers 1236 ******************************************************************************/ 1237 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1238 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1239 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1240 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1241 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1242 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1243 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1244 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1245 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1246 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1247 1248 /******************************************************************************* 1249 * Armv8.4 Data Independent Timing Registers 1250 ******************************************************************************/ 1251 #define DIT S3_3_C4_C2_5 1252 #define DIT_BIT BIT(24) 1253 1254 /******************************************************************************* 1255 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1256 ******************************************************************************/ 1257 #define SSBS S3_3_C4_C2_6 1258 1259 /******************************************************************************* 1260 * Armv8.5 - Memory Tagging Extension Registers 1261 ******************************************************************************/ 1262 #define TFSRE0_EL1 S3_0_C5_C6_1 1263 #define TFSR_EL1 S3_0_C5_C6_0 1264 #define RGSR_EL1 S3_0_C1_C0_5 1265 #define GCR_EL1 S3_0_C1_C0_6 1266 1267 /******************************************************************************* 1268 * FEAT_HCX - Extended Hypervisor Configuration Register 1269 ******************************************************************************/ 1270 #define HCRX_EL2 S3_4_C1_C2_2 1271 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1272 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1273 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1274 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1275 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1276 1277 /******************************************************************************* 1278 * Definitions for DynamicIQ Shared Unit registers 1279 ******************************************************************************/ 1280 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1281 1282 /* CLUSTERPWRDN_EL1 register definitions */ 1283 #define DSU_CLUSTER_PWR_OFF 0 1284 #define DSU_CLUSTER_PWR_ON 1 1285 #define DSU_CLUSTER_PWR_MASK U(1) 1286 1287 /******************************************************************************* 1288 * Definitions for CPU Power/Performance Management registers 1289 ******************************************************************************/ 1290 1291 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1292 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1293 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1294 1295 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1296 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1297 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1298 1299 #endif /* ARCH_H */ 1300
