1 /* 2 * Copyright (c) 2020 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* TODO: Add to include/sys/util.h */ 8 #define BITFIELD(val, h, l) (((val) & GENMASK(h, l)) >> l) 9 10 #define PCI_VENDOR_ID_INTEL 0x8086 11 12 /* Supported SKU map */ 13 #define PCI_DEVICE_ID_SKU5 0x4514 14 #define PCI_DEVICE_ID_SKU6 0x4528 15 #define PCI_DEVICE_ID_SKU7 0x452a 16 #define PCI_DEVICE_ID_SKU8 0x4516 17 #define PCI_DEVICE_ID_SKU9 0x452c 18 #define PCI_DEVICE_ID_SKU10 0x452e 19 #define PCI_DEVICE_ID_SKU11 0x4532 20 #define PCI_DEVICE_ID_SKU12 0x4518 21 #define PCI_DEVICE_ID_SKU13 0x451a 22 #define PCI_DEVICE_ID_SKU14 0x4534 23 #define PCI_DEVICE_ID_SKU15 0x4536 24 25 /* TODO: Move to correct place NMI registers */ 26 27 /* NMI Status and Control Register (NMI_STS_CNT) */ 28 #define NMI_STS_CNT_REG 0x61 29 /* Set by any source of PCH SERR (SERR_NMI_STS) */ 30 #define NMI_STS_SRC_SERR BIT(7) 31 /* Mask for all source bits in the NMI_STS_CNT_REG */ 32 #define NMI_STS_SRC_MASK GENMASK(7, 6) 33 34 /** 35 * Writing 1 SERR NMI are disabled and cleared, writing 0 36 * SERR NMIs are enabled 37 */ 38 #define NMI_STS_SERR_EN BIT(2) 39 /* Mask for all enable bits in the NMI_STS_CNT_REG */ 40 #define NMI_STS_MASK_EN GENMASK(3, 0) 41 42 /** 43 * In-Band Error Correction Code (IBECC) protects data at a cache line 44 * granularity (64 Bytes) with 16 bits SECDED code. 45 * Reports following fields: 46 * - CMI (Converged Memory Interface) Address 47 * - Syndrome 48 * - Error Type (Correctable, Uncorrectable) 49 */ 50 51 /** 52 * PCI Configuration space registers area 53 */ 54 55 /* Top of Upper Usable DRAM, offset 0xa8, 64 bit */ 56 #define TOUUD_REG 0x2a 57 #define TOUUD_MASK GENMASK(38, 20) 58 59 /* Top of Low Usable DRAM, offset 0xbc, 32 bit */ 60 #define TOLUD_REG 0x2f 61 #define TOLUD_MASK GENMASK(31, 20) 62 63 /* Total amount of physical memory, offset 0xa0, 64 bit */ 64 #define TOM_REG 0x28 65 #define TOM_MASK GENMASK(38, 20) 66 67 /* Base address for the Host Memory Mapped Configuration space, 68 * offset 0x48, 64 bit 69 */ 70 #define MCHBAR_REG 0x12 71 #define MCHBAR_MASK GENMASK(38, 16) 72 #define MCHBAR_ENABLE BIT(0) 73 /* Size of Host Memory Mapped Configuration space (64K) */ 74 #define MCH_SIZE 0x10000 75 76 /* Capability register, offset 0xec, 32 bit */ 77 #define CAPID0_C_REG 0x3b 78 #define CAPID0_C_IBECC_ENABLED BIT(15) 79 80 /* Register controlling reporting error SERR, offset 0xc8, 16 bit */ 81 #define ERRSTS_REG 0x32 82 #define ERRSTS_IBECC_COR BIT(6) /* Correctable error */ 83 #define ERRSTS_IBECC_UC BIT(7) /* Uncorrectable error */ 84 85 /* Register controlling Host Bridge responses to system errors, 86 * offset 0xca, 16 bit 87 * 88 * TODO: Fix this after PCI access is fixed, now we have to access 89 * ERRSTS_REG with 32 bit access and get this 16 bits 90 */ 91 #define ERRCMD_REG 0x32 92 #define ERRCMD_IBECC_COR BIT(6) /* Correctable error */ 93 #define ERRCMD_IBECC_UC BIT(7) /* Uncorrectable error */ 94 95 /** 96 * Host Memory Mapped Configuration Space (MCHBAR) registers area 97 */ 98 99 #define CHANNEL_HASH 0x5024 100 101 /* ECC Injection Registers */ 102 103 #define IBECC_INJ_ADDR_BASE 0xdd88 104 #define INJ_ADDR_BASE_MASK GENMASK(38, 6) 105 106 #define IBECC_INJ_ADDR_MASK 0xdd80 107 #define INJ_ADDR_BASE_MASK_MASK GENMASK(38, 6) 108 109 #define IBECC_INJ_ADDR_CTRL 0xdd98 110 #define INJ_CTRL_COR 0x1 111 #define INJ_CTRL_UC 0x5 112 113 /* Error Logging Registers */ 114 115 /* ECC Error Log register, 64 bit (ECC_ERROR_LOG) */ 116 #define IBECC_ECC_ERROR_LOG 0xdd70 117 /* Uncorrectable (Multiple-bit) Error Status (MERRSTS) */ 118 #define ECC_ERROR_MERRSTS BIT64(63) 119 /* Correctable Error Status (CERRSTS) */ 120 #define ECC_ERROR_CERRSTS BIT64(62) 121 #define ECC_ERROR_ERRTYPE(val) BITFIELD(val, 63, 62) 122 /* CMI address of the address block of main memory where error happened */ 123 #define ECC_ERROR_ERRADD(val) ((val) & GENMASK(38, 5)) 124 /* ECC Error Syndrome (ERRSYND) */ 125 #define ECC_ERROR_ERRSYND(val) BITFIELD(val, 61, 46) 126 127 /* Parity Error Log (PARITY_ERR_LOG) */ 128 #define IBECC_PARITY_ERROR_LOG 0xdd78 129 /* Error Status (ERRSTS) */ 130 #define PARITY_ERROR_ERRSTS BIT64(63) 131 132 /* Memory configuration registers */ 133 134 #define DRAM_MAX_CHANNELS 2 135 #define DRAM_MAX_DIMMS 2 136 137 /* Memory channel decoding register, 32 bit */ 138 #define MAD_INTER_CHAN 0x5000 139 #define INTER_CHAN_DDR_TYPE(v) BITFIELD(v, 2, 0) 140 /* Enhanced channel mode for LPDDR4 */ 141 #define INTER_CHAN_ECHM(v) BITFIELD(v, 3, 3) 142 /* Channel L mapping to physical channel */ 143 #define INTER_CHAN_CH_L_MAP(v) BITFIELD(v, 4, 4) 144 /* Channel S size in multiples of 0.5GB */ 145 #define INTER_CHAN_CH_S_SIZE BITFIELD(v, 19, 12) 146 147 /* DRAM decode stage 2 registers, 32 bit */ 148 #define MAD_INTRA_CH(index) (0x5004 + index * sizeof(uint32_t)) 149 /* Virtual DIMM L mapping to physical DIMM */ 150 #define DIMM_L_MAP(v) BITFIELD(v, 0, 0) 151 152 /* DIMM channel characteristic 2 registers, 32 bit */ 153 #define MAD_DIMM_CH(index) (0x500c + index * sizeof(uint32_t)) 154 /* Size of DIMM L in 0.5GB multiples */ 155 #define DIMM_L_SIZE(v) (BITFIELD(v, 6, 0) << 29) 156 /* DIMM L width of DDR chips (DLW) */ 157 #define DIMM_L_WIDTH(v) BITFIELD(v, 8, 7) 158 /* Size of DIMM S in 0.5GB multiples */ 159 #define DIMM_S_SIZE(v) (BITFIELD(v, 22, 16) << 29) 160 /* DIMM S width of DDR chips (DSW) */ 161 #define DIMM_S_WIDTH(v) BITFIELD(v, 25, 24) 162 163 164 /* MC Channel Selection register, 32 bit */ 165 #define CHANNEL_HASH 0x5024 166 167 /* MC Enhanced Channel Selection register, 32 bit */ 168 #define CHANNEL_EHASH 0x5028 169 170 struct ibecc_error { 171 uint32_t type; 172 uint64_t address; 173 uint16_t syndrome; 174 }; 175
