1 /*
2 * Copyright 2022 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_
8 #define ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_
9
10 /**
11 * @brief I3C Common Command Codes
12 * @defgroup i3c_ccc I3C Common Command Codes
13 * @ingroup i3c_interface
14 * @{
15 */
16
17 #include <zephyr/types.h>
18 #include <zephyr/device.h>
19 #include <zephyr/toolchain.h>
20 #include <zephyr/sys/util.h>
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /** Maximum CCC ID for broadcast */
27 #define I3C_CCC_BROADCAST_MAX_ID 0x7FU
28
29 /**
30 * Enable Events Command
31 *
32 * @param broadcast True if broadcast, false if direct.
33 */
34 #define I3C_CCC_ENEC(broadcast) ((broadcast) ? 0x00U : 0x80U)
35
36 /**
37 * Disable Events Command
38 *
39 * @param broadcast True if broadcast, false if direct.
40 */
41 #define I3C_CCC_DISEC(broadcast) ((broadcast) ? 0x01U : 0x81U)
42
43 /**
44 * Enter Activity State
45 *
46 * @param as Desired activity state
47 * @param broadcast True if broadcast, false if direct.
48 */
49 #define I3C_CCC_ENTAS(as, broadcast) (((broadcast) ? 0x02U : 0x82U) + (as))
50
51 /**
52 * Enter Activity State 0
53 *
54 * @param broadcast True if broadcast, false if direct.
55 */
56 #define I3C_CCC_ENTAS0(broadcast) I3C_CCC_ENTAS(0, broadcast)
57
58 /**
59 * Enter Activity State 1
60 *
61 * @param broadcast True if broadcast, false if direct.
62 */
63 #define I3C_CCC_ENTAS1(broadcast) I3C_CCC_ENTAS(1, broadcast)
64
65 /**
66 * Enter Activity State 2
67 *
68 * @param broadcast True if broadcast, false if direct.
69 */
70 #define I3C_CCC_ENTAS2(broadcast) I3C_CCC_ENTAS(2, broadcast)
71
72 /**
73 * Enter Activity State 3
74 *
75 * @param broadcast True if broadcast, false if direct.
76 */
77 #define I3C_CCC_ENTAS3(broadcast) I3C_CCC_ENTAS(3, broadcast)
78
79 /** Reset Dynamic Address Assignment (Broadcast) */
80 #define I3C_CCC_RSTDAA 0x06U
81
82 /** Enter Dynamic Address Assignment (Broadcast) */
83 #define I3C_CCC_ENTDAA 0x07U
84
85 /** Define List of Targets (Broadcast) */
86 #define I3C_CCC_DEFTGTS 0x08U
87
88 /**
89 * Set Max Write Length (Broadcast or Direct)
90 *
91 * @param broadcast True if broadcast, false if direct.
92 */
93 #define I3C_CCC_SETMWL(broadcast) ((broadcast) ? 0x09U : 0x89U)
94
95 /**
96 * Set Max Read Length (Broadcast or Direct)
97 *
98 * @param broadcast True if broadcast, false if direct.
99 */
100 #define I3C_CCC_SETMRL(broadcast) ((broadcast) ? 0x0AU : 0x8AU)
101
102 /** Enter Test Mode (Broadcast) */
103 #define I3C_CCC_ENTTM 0x0BU
104
105 /** Set Bus Context (Broadcast) */
106 #define I3C_CCC_SETBUSCON 0x0CU
107
108 /**
109 * Data Transfer Ending Procedure Control
110 *
111 * @param broadcast True if broadcast, false if direct.
112 */
113 #define I3C_CCC_ENDXFER(broadcast) ((broadcast) ? 0x12U : 0x92U)
114
115 /** Enter HDR Mode (HDR-DDR) (Broadcast) */
116 #define I3C_CCC_ENTHDR(x) (0x20U + (x))
117
118 /** Enter HDR Mode 0 (HDR-DDR) (Broadcast) */
119 #define I3C_CCC_ENTHDR0 0x20U
120
121 /** Enter HDR Mode 1 (HDR-TSP) (Broadcast) */
122 #define I3C_CCC_ENTHDR1 0x21U
123
124 /** Enter HDR Mode 2 (HDR-TSL) (Broadcast) */
125 #define I3C_CCC_ENTHDR2 0x22U
126
127 /** Enter HDR Mode 3 (HDR-BT) (Broadcast) */
128 #define I3C_CCC_ENTHDR3 0x23U
129
130 /** Enter HDR Mode 4 (Broadcast) */
131 #define I3C_CCC_ENTHDR4 0x24U
132
133 /** Enter HDR Mode 5 (Broadcast) */
134 #define I3C_CCC_ENTHDR5 0x25U
135
136 /** Enter HDR Mode 6 (Broadcast) */
137 #define I3C_CCC_ENTHDR6 0x26U
138
139 /** Enter HDR Mode 7 (Broadcast) */
140 #define I3C_CCC_ENTHDR7 0x27U
141
142 /**
143 * Exchange Timing Information (Broadcast or Direct)
144 *
145 * @param broadcast True if broadcast, false if direct.
146 */
147 #define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28U : 0x98U)
148
149 /** Set All Addresses to Static Addresses (Broadcast) */
150 #define I3C_CCC_SETAASA 0x29U
151
152 /**
153 * Target Reset Action
154 *
155 * @param broadcast True if broadcast, false if direct.
156 */
157 #define I3C_CCC_RSTACT(broadcast) ((broadcast) ? 0x2AU : 0x9AU)
158
159 /** Define List of Group Address (Broadcast) */
160 #define I3C_CCC_DEFGRPA 0x2BU
161
162 /**
163 * Reset Group Address
164 *
165 * @param broadcast True if broadcast, false if direct.
166 */
167 #define I3C_CCC_RSTGRPA(broadcast) ((broadcast) ? 0x2CU : 0x9CU)
168
169 /** Multi-Lane Data Transfer Control (Broadcast) */
170 #define I3C_CCC_MLANE(broadcast) ((broadcast) ? 0x2DU : 0x9DU)
171
172 /**
173 * Vendor/Standard Extension
174 *
175 * @param broadcast True if broadcast, false if direct.
176 * @param id Extension ID.
177 */
178 #define I3C_CCC_VENDOR(broadcast, id) ((id) + ((broadcast) ? 0x61U : 0xE0U))
179
180 /** Set Dynamic Address from Static Address (Direct) */
181 #define I3C_CCC_SETDASA 0x87U
182
183 /** Set New Dynamic Address (Direct) */
184 #define I3C_CCC_SETNEWDA 0x88U
185
186 /** Get Max Write Length (Direct) */
187 #define I3C_CCC_GETMWL 0x8BU
188
189 /** Get Max Read Length (Direct) */
190 #define I3C_CCC_GETMRL 0x8CU
191
192 /** Get Provisioned ID (Direct) */
193 #define I3C_CCC_GETPID 0x8DU
194
195 /** Get Bus Characteristics Register (Direct) */
196 #define I3C_CCC_GETBCR 0x8EU
197
198 /** Get Device Characteristics Register (Direct) */
199 #define I3C_CCC_GETDCR 0x8FU
200
201 /** Get Device Status (Direct) */
202 #define I3C_CCC_GETSTATUS 0x90U
203
204 /** Get Accept Controller Role (Direct) */
205 #define I3C_CCC_GETACCCR 0x91U
206
207 /** Set Bridge Targets (Direct) */
208 #define I3C_CCC_SETBRGTGT 0x93U
209
210 /** Get Max Data Speed (Direct) */
211 #define I3C_CCC_GETMXDS 0x94U
212
213 /** Get Optional Feature Capabilities (Direct) */
214 #define I3C_CCC_GETCAPS 0x95U
215
216 /** Set Route (Direct) */
217 #define I3C_CCC_SETROUTE 0x96U
218
219 /** Device to Device(s) Tunneling Control (Direct) */
220 #define I3C_CCC_D2DXFER 0x97U
221
222 /** Get Exchange Timing Information (Direct) */
223 #define I3C_CCC_GETXTIME 0x99U
224
225 /** Set Group Address (Direct) */
226 #define I3C_CCC_SETGRPA 0x9BU
227
228 struct i3c_device_desc;
229
230 /**
231 * @brief Payload structure for Direct CCC to one target.
232 */
233 struct i3c_ccc_target_payload {
234 /** Target address */
235 uint8_t addr;
236
237 /** @c 0 for Write, @c 1 for Read */
238 uint8_t rnw:1;
239
240 /**
241 * - For Write CCC, pointer to the byte array of data
242 * to be sent, which may contain the Sub-Command Byte
243 * and additional data.
244 * - For Read CCC, pointer to the byte buffer for data
245 * to be read into.
246 */
247 uint8_t *data;
248
249 /** Length in bytes for @p data. */
250 size_t data_len;
251 };
252
253 /**
254 * @brief Payload structure for one CCC transaction.
255 */
256 struct i3c_ccc_payload {
257 struct {
258 /**
259 * The CCC ID (@c I3C_CCC_*).
260 */
261 uint8_t id;
262
263 /**
264 * Pointer to byte array of data for this CCC.
265 *
266 * This is the bytes following the CCC command in CCC frame.
267 * Set to @c NULL if no associated data.
268 */
269 uint8_t *data;
270
271 /** Length in bytes for optional data array. */
272 size_t data_len;
273 } ccc;
274
275 struct {
276 /**
277 * Array of struct i3c_ccc_target_payload.
278 *
279 * Each element describes the target and associated
280 * payloads for this CCC.
281 *
282 * Use with Direct CCC.
283 */
284 struct i3c_ccc_target_payload *payloads;
285
286 /** Number of targets */
287 size_t num_targets;
288 } targets;
289 };
290
291 /**
292 * @brief Payload for ENEC/DISEC CCC (Target Events Command).
293 */
294 struct i3c_ccc_events {
295 /**
296 * Event byte:
297 * - Bit[0]: ENINT/DISINT:
298 * - Target Interrupt Requests
299 * - Bit[1]: ENCR/DISCR:
300 * - Controller Role Requests
301 * - Bit[3]: ENHJ/DISHJ:
302 * - Hot-Join Event
303 */
304 uint8_t events;
305 } __packed;
306
307 /** Enable Events (ENEC) - Target Interrupt Requests. */
308 #define I3C_CCC_ENEC_EVT_ENINTR BIT(0)
309
310 /** Enable Events (ENEC) - Controller Role Requests. */
311 #define I3C_CCC_ENEC_EVT_ENCR BIT(1)
312
313 /** Enable Events (ENEC) - Hot-Join Event. */
314 #define I3C_CCC_ENEC_EVT_ENHJ BIT(3)
315
316 #define I3C_CCC_ENEC_EVT_ALL \
317 (I3C_CCC_ENEC_EVT_ENINTR | I3C_CCC_ENEC_EVT_ENCR | I3C_CCC_ENEC_EVT_ENHJ)
318
319 /** Disable Events (DISEC) - Target Interrupt Requests. */
320 #define I3C_CCC_DISEC_EVT_DISINTR BIT(0)
321
322 /** Disable Events (DISEC) - Controller Role Requests. */
323 #define I3C_CCC_DISEC_EVT_DISCR BIT(1)
324
325 /** Disable Events (DISEC) - Hot-Join Event. */
326 #define I3C_CCC_DISEC_EVT_DISHJ BIT(3)
327
328 #define I3C_CCC_DISEC_EVT_ALL \
329 (I3C_CCC_DISEC_EVT_DISINTR | I3C_CCC_DISEC_EVT_DISCR | I3C_CCC_DISEC_EVT_DISHJ)
330
331 /*
332 * Events for both enabling and disabling since
333 * they have the same bits.
334 */
335
336 /** Events - Target Interrupt Requests. */
337 #define I3C_CCC_EVT_INTR BIT(0)
338
339 /** Events - Controller Role Requests. */
340 #define I3C_CCC_EVT_CR BIT(1)
341
342 /** Events - Hot-Join Event. */
343 #define I3C_CCC_EVT_HJ BIT(3)
344
345 /** Bitmask for all events. */
346 #define I3C_CCC_EVT_ALL \
347 (I3C_CCC_EVT_INTR | I3C_CCC_EVT_CR | I3C_CCC_EVT_HJ)
348
349 /**
350 * @brief Payload for SETMWL/GETMWL CCC (Set/Get Maximum Write Length).
351 *
352 * @note For drivers and help functions, the raw data coming
353 * back from target device is in big endian. This needs to be
354 * translated back to CPU endianness before passing back to
355 * function caller.
356 */
357 struct i3c_ccc_mwl {
358 /** Maximum Write Length */
359 uint16_t len;
360 } __packed;
361
362 /**
363 * @brief Payload for SETMRL/GETMRL CCC (Set/Get Maximum Read Length).
364 *
365 * @note For drivers and help functions, the raw data coming
366 * back from target device is in big endian. This needs to be
367 * translated back to CPU endianness before passing back to
368 * function caller.
369 */
370 struct i3c_ccc_mrl {
371 /** Maximum Read Length */
372 uint16_t len;
373
374 /** Optional IBI Payload Size */
375 uint8_t ibi_len;
376 } __packed;
377
378 /**
379 * @brief The active controller part of payload for DEFTGTS CCC.
380 *
381 * This is used by DEFTGTS (Define List of Targets) CCC to describe
382 * the active controller on the I3C bus.
383 */
384 struct i3c_ccc_deftgts_active_controller {
385 /** Dynamic Address of Active Controller */
386 uint8_t addr;
387
388 /** Device Characteristic Register of Active Controller */
389 uint8_t dcr;
390
391 /** Bus Characteristic Register of Active Controller */
392 uint8_t bcr;
393
394 /** Static Address of Active Controller */
395 uint8_t static_addr;
396 };
397
398 /**
399 * @brief The target device part of payload for DEFTGTS CCC.
400 *
401 * This is used by DEFTGTS (Define List of Targets) CCC to describe
402 * the existing target devices on the I3C bus.
403 */
404 struct i3c_ccc_deftgts_target {
405 /** Dynamic Address of a target device, or a group address */
406 uint8_t addr;
407
408 union {
409 /**
410 * Device Characteristic Register of a I3C target device
411 * or a group.
412 */
413 uint8_t dcr;
414
415 /** Legacy Virtual Register for legacy I2C device. */
416 uint8_t lvr;
417 };
418
419 /** Bus Characteristic Register of a target device or a group */
420 uint8_t bcr;
421
422 /** Static Address of a target device or a group */
423 uint8_t static_addr;
424 };
425
426 /**
427 * @brief Payload for DEFTGTS CCC (Define List of Targets).
428 *
429 * @note @p i3c_ccc_deftgts_target is an array of targets, where
430 * the number of elements is dependent on the number of I3C targets
431 * on the bus. Please have enough space for both read and write of
432 * this CCC.
433 */
434 struct i3c_ccc_deftgts {
435 /** Data describing the active controller */
436 struct i3c_ccc_deftgts_active_controller active_controller;
437
438 /** Data describing the target(s) on the bus */
439 struct i3c_ccc_deftgts_target targets[];
440 } __packed;
441
442 /**
443 * @brief Payload for a single device address.
444 *
445 * This is used for:
446 * - SETDASA (Set Dynamic Address from Static Address)
447 * - SETNEWDA (Set New Dynamic Address)
448 * - SETGRPA (Set Group Address)
449 * - GETACCCR (Get Accept Controller Role)
450 *
451 * Note that the target address is encoded within
452 * struct i3c_ccc_target_payload instead of being encoded in
453 * this payload.
454 */
455 struct i3c_ccc_address {
456 /**
457 * - For SETDASA, Static Address to be assigned as
458 * Dynamic Address.
459 * - For SETNEWDA, new Dynamic Address to be assigned.
460 * - For SETGRPA, new Group Address to be set.
461 * - For GETACCCR, the correct address of Secondary
462 * Controller.
463 *
464 * @note For SETDATA, SETNEWDA and SETGRAP,
465 * the address is left-shift by 1, and bit[0] is always 0.
466 *
467 * @note Fpr SET GETACCCR, the address is left-shift by 1,
468 * and bit[0] is the calculated odd parity bit.
469 */
470 uint8_t addr;
471 } __packed;
472
473 /**
474 * @brief Payload for GETPID CCC (Get Provisioned ID).
475 */
476 struct i3c_ccc_getpid {
477 /**
478 * 48-bit Provisioned ID.
479 *
480 * @note Data is big-endian where first byte is MSB.
481 */
482 uint8_t pid[6];
483 } __packed;
484
485 /**
486 * @brief Payload for GETBCR CCC (Get Bus Characteristics Register).
487 */
488 struct i3c_ccc_getbcr {
489 /** Bus Characteristics Register */
490 uint8_t bcr;
491 } __packed;
492
493 /**
494 * @brief Payload for GETDCR CCC (Get Device Characteristics Register).
495 */
496 struct i3c_ccc_getdcr {
497 /** Device Characteristics Register */
498 uint8_t dcr;
499 } __packed;
500
501
502 /**
503 * @brief Indicate which format of GETSTATUS to use.
504 */
505 enum i3c_ccc_getstatus_fmt {
506 /** GETSTATUS Format 1 */
507 GETSTATUS_FORMAT_1,
508
509 /** GETSTATUS Format 2 */
510 GETSTATUS_FORMAT_2,
511 };
512
513 /**
514 * @brief Defining byte values for GETSTATUS Format 2.
515 */
516 enum i3c_ccc_getstatus_defbyte {
517 /** Target status. */
518 GETSTATUS_FORMAT_2_TGTSTAT = 0x00U,
519
520 /** PRECR - Alternate status format describing Controller-capable device. */
521 GETSTATUS_FORMAT_2_PRECR = 0x91U,
522
523 /** Invalid defining byte. */
524 GETSTATUS_FORMAT_2_INVALID = 0x100U
525 };
526
527 /**
528 * @brief Payload for GETSTATUS CCC (Get Device Status).
529 */
530 union i3c_ccc_getstatus {
531 struct {
532 /**
533 * Device Status
534 * - Bit[15:8]: Reserved.
535 * - Bit[7:6]: Activity Mode.
536 * - Bit[5]: Protocol Error.
537 * - Bit[4]: Reserved.
538 * - Bit[3:0]: Number of Pending Interrupts.
539 *
540 * @note For drivers and help functions, the raw data coming
541 * back from target device is in big endian. This needs to be
542 * translated back to CPU endianness before passing back to
543 * function caller.
544 */
545 uint16_t status;
546 } fmt1;
547
548 union {
549 /**
550 * Defining Byte 0x00: TGTSTAT
551 *
552 * @see i3c_ccc_getstatus::fmt1::status
553 */
554 uint16_t tgtstat;
555
556 /**
557 * Defining Byte 0x91: PRECR
558 * - Bit[15:8]: Vendor Reserved
559 * - Bit[7:2]: Reserved
560 * - Bit[1]: Handoff Delay NACK
561 * - Bit[0]: Deep Sleep Detected
562 *
563 * @note For drivers and help functions, the raw data coming
564 * back from target device is in big endian. This needs to be
565 * translated back to CPU endianness before passing back to
566 * function caller.
567 */
568 uint16_t precr;
569
570 uint16_t raw_u16;
571 } fmt2;
572 } __packed;
573
574 /** GETSTATUS Format 1 - Protocol Error bit. */
575 #define I3C_CCC_GETSTATUS_PROTOCOL_ERR BIT(5)
576
577 /** GETSTATUS Format 1 - Activity Mode bit shift value. */
578 #define I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT 6
579
580 /** GETSTATUS Format 1 - Activity Mode bitmask. */
581 #define I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK \
582 (0x03U << I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT)
583
584 /**
585 * @brief GETSTATUS Format 1 - Activity Mode
586 *
587 * Obtain Activity Mode from GETSTATUS Format 1 value obtained via
588 * GETSTATUS.
589 *
590 * @param status GETSTATUS Format 1 value
591 */
592 #define I3C_CCC_GETSTATUS_ACTIVITY_MODE(status) \
593 (((status) & I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK) \
594 >> I3C_CCC_GETSTATUS_ACTIVITY_MODE_SHIFT)
595
596 /** GETSTATUS Format 1 - Number of Pending Interrupts bit shift value. */
597 #define I3C_CCC_GETSTATUS_NUM_INT_SHIFT 0
598
599 /** GETSTATUS Format 1 - Number of Pending Interrupts bitmask. */
600 #define I3C_CCC_GETSTATUS_NUM_INT_MASK \
601 (0x0FU << I3C_CCC_GETSTATUS_NUM_INT_SHIFT)
602
603 /**
604 * @brief GETSTATUS Format 1 - Number of Pending Interrupts
605 *
606 * Obtain Number of Pending Interrupts from GETSTATUS Format 1 value
607 * obtained via GETSTATUS.
608 *
609 * @param status GETSTATUS Format 1 value
610 */
611 #define I3C_CCC_GETSTATUS_NUM_INT(status) \
612 (((status) & I3C_CCC_GETSTATUS_NUM_INT_MASK) \
613 >> I3C_CCC_GETSTATUS_NUM_INT_SHIFT)
614
615 /** GETSTATUS Format 2 - PERCR - Deep Sleep Detected bit. */
616 #define I3C_CCC_GETSTATUS_PRECR_DEEP_SLEEP_DETECTED BIT(0)
617
618 /** GETSTATUS Format 2 - PERCR - Handoff Delay NACK. */
619 #define I3C_CCC_GETSTATUS_PRECR_HANDOFF_DELAY_NACK BIT(1)
620
621 /**
622 * @brief One Bridged Target for SETBRGTGT payload.
623 */
624 struct i3c_ccc_setbrgtgt_tgt {
625 /**
626 * Dynamic address of the bridged target.
627 *
628 * @note The address is left-shift by 1, and bit[0]
629 * is always 0.
630 */
631 uint8_t addr;
632
633 /**
634 * 16-bit ID for the bridged target.
635 *
636 * @note For drivers and help functions, the raw data coming
637 * back from target device is in big endian. This needs to be
638 * translated back to CPU endianness before passing back to
639 * function caller.
640 */
641 uint16_t id;
642 } __packed;
643
644 /**
645 * @brief Payload for SETBRGTGT CCC (Set Bridge Targets).
646 *
647 * Note that the bridge target address is encoded within
648 * struct i3c_ccc_target_payload instead of being encoded in
649 * this payload.
650 */
651 struct i3c_ccc_setbrgtgt {
652 /** Number of bridged targets */
653 uint8_t count;
654
655 /** Array of bridged targets */
656 struct i3c_ccc_setbrgtgt_tgt targets[];
657 } __packed;
658
659 /**
660 * @brief Payload for GETMXDS CCC (Get Max Data Speed).
661 *
662 * @note This is only for GETMXDS Format 1 and Format 2.
663 */
664 union i3c_ccc_getmxds {
665 struct {
666 /** maxWr */
667 uint8_t maxwr;
668
669 /** maxRd */
670 uint8_t maxrd;
671 } fmt1;
672
673 struct {
674 /** maxWr */
675 uint8_t maxwr;
676
677 /** maxRd */
678 uint8_t maxrd;
679
680 /**
681 * Maximum Read Turnaround Time in microsecond.
682 *
683 * This is in little-endian where first byte is LSB.
684 */
685 uint8_t maxrdturn[3];
686 } fmt2;
687
688 struct {
689 /**
690 * Defining Byte 0x00: WRRDTURN
691 *
692 * @see i3c_ccc_getmxds::fmt2
693 */
694 uint8_t wrrdturn;
695
696 /**
697 * Defining Byte 0x91: CRHDLY
698 * - Bit[2]: Set Bus Actibity State
699 * - Bit[1:0]: Controller Handoff Activity State
700 */
701 uint8_t crhdly1;
702 } fmt3;
703 } __packed;
704
705 /** Get Max Data Speed (GETMXDS) - Default Max Sustained Data Rate. */
706 #define I3C_CCC_GETMXDS_MAX_SDR_FSCL_MAX 0
707
708 /** Get Max Data Speed (GETMXDS) - 8MHz Max Sustained Data Rate. */
709 #define I3C_CCC_GETMXDS_MAX_SDR_FSCL_8MHZ 1
710
711 /** Get Max Data Speed (GETMXDS) - 6MHz Max Sustained Data Rate. */
712 #define I3C_CCC_GETMXDS_MAX_SDR_FSCL_6MHZ 2
713
714 /** Get Max Data Speed (GETMXDS) - 4MHz Max Sustained Data Rate. */
715 #define I3C_CCC_GETMXDS_MAX_SDR_FSCL_4MHZ 3
716
717 /** Get Max Data Speed (GETMXDS) - 2MHz Max Sustained Data Rate. */
718 #define I3C_CCC_GETMXDS_MAX_SDR_FSCL_2MHZ 4
719
720 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 8ns. */
721 #define I3C_CCC_GETMXDS_TSCO_8NS 0
722
723 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 9ns. */
724 #define I3C_CCC_GETMXDS_TSCO_9NS 1
725
726 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 10ns. */
727 #define I3C_CCC_GETMXDS_TSCO_10NS 2
728
729 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 11ns. */
730 #define I3C_CCC_GETMXDS_TSCO_11NS 3
731
732 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround <= 12ns. */
733 #define I3C_CCC_GETMXDS_TSCO_12NS 4
734
735 /** Get Max Data Speed (GETMXDS) - Clock to Data Turnaround > 12ns. */
736 #define I3C_CCC_GETMXDS_TSCO_GT_12NS 7
737
738 /** Get Max Data Speed (GETMXDS) - maxWr - Optional Defining Byte Support. */
739 #define I3C_CCC_GETMXDS_MAXWR_DEFINING_BYTE_SUPPORT BIT(3)
740
741 /** Get Max Data Speed (GETMXDS) - Max Sustained Data Rate bit shift value. */
742 #define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT 0
743
744 /** Get Max Data Speed (GETMXDS) - Max Sustained Data Rate bitmask. */
745 #define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK \
746 (0x07U << I3C_CCC_GET_MXDS_MAXWR_MAX_SDR_FSCL_SHIFT)
747
748 /**
749 * @brief Get Max Data Speed (GETMXDS) - maxWr - Max Sustained Data Rate
750 *
751 * Obtain Max Sustained Data Rate value from GETMXDS maxWr value
752 * obtained via GETMXDS.
753 *
754 * @param maxwr GETMXDS maxWr value.
755 */
756 #define I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL(maxwr) \
757 (((maxwr) & \
758 I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_MASK) \
759 >> I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL_SHIFT)
760
761 /** Get Max Data Speed (GETMXDS) - maxRd - Write-to-Read Permits Stop Between. */
762 #define I3C_CCC_GETMXDS_MAXRD_W2R_PERMITS_STOP_BETWEEN BIT(6)
763
764 /** Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround bit shift value. */
765 #define I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT 3
766
767 /** Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround bitmask. */
768 #define I3C_CCC_GETMXDS_MAXRD_TSCO_MASK \
769 (0x07U << I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT)
770
771 /**
772 * @brief Get Max Data Speed (GETMXDS) - maxRd - Clock to Data Turnaround
773 *
774 * Obtain Clock to Data Turnaround value from GETMXDS maxRd value
775 * obtained via GETMXDS.
776 *
777 * @param maxrd GETMXDS maxRd value.
778 */
779 #define I3C_CCC_GETMXDS_MAXRD_TSCO(maxrd) \
780 (((maxrd) & I3C_CCC_GETMXDS_MAXRD_TSCO_MASK) \
781 >> I3C_CCC_GETMXDS_MAXRD_TSCO_SHIFT)
782
783 /** Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate bit shift value. */
784 #define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT 0
785
786 /** Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate bitmask. */
787 #define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK \
788 (0x07U << I3C_CCC_GET_MXDS_MAXRD_MAX_SDR_FSCL_SHIFT)
789
790 /**
791 * @brief Get Max Data Speed (GETMXDS) - maxRd - Max Sustained Data Rate
792 *
793 * Obtain Max Sustained Data Rate value from GETMXDS maxRd value
794 * obtained via GETMXDS.
795 *
796 * @param maxrd GETMXDS maxRd value.
797 */
798 #define I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL(maxrd) \
799 (((maxrd) & \
800 I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_MASK) \
801 >> I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL_SHIFT)
802
803 /** Get Max Data Speed (GETMXDS) - CRDHLY1 - Set Bus Activity State bit shift value. */
804 #define I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE BIT(2)
805
806 /** Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State bit shift value. */
807 #define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_SHIFT 0
808
809 /** Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State bitmask. */
810 #define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK \
811 (0x03U << I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE_SHIFT)
812
813 /**
814 * @brief Get Max Data Speed (GETMXDS) - CRDHLY1 - Controller Handoff Activity State
815 *
816 * Obtain Controller Handoff Activity State value from GETMXDS value
817 * obtained via GETMXDS.
818 *
819 * @param crhdly1 GETMXDS value.
820 */
821 #define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE(crhdly1) \
822 (((crhdly1) & \
823 I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE_MASK) \
824 >> I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE_SHIFT)
825
826 /**
827 * @brief Payload for GETCAPS CCC (Get Optional Feature Capabilities).
828 *
829 * @note Only support GETCAPS Format 1.
830 */
831 struct i3c_ccc_getcaps {
832 /**
833 * GETCAP[1-4] bytes.
834 */
835 uint8_t getcaps[4];
836 } __packed;
837
838 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR-DDR mode bit. */
839 #define I3C_CCC_GETCAPS1_HDR_DDR BIT(0)
840
841 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR-BT mode bit. */
842 #define I3C_CCC_GETCAPS1_HDR_BT BIT(3)
843
844 /**
845 * @brief Get Optional Feature Capabilities (GETCAPS) - HDR Mode
846 *
847 * Get the bit corresponding to HDR mode.
848 *
849 * @param x HDR mode
850 */
851 #define I3C_CCC_GETCAPS1_HDR_MODE(x) BIT(x)
852
853 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 0. */
854 #define I3C_CCC_GETCAPS1_HDR_MODE0 BIT(0)
855
856 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 1. */
857 #define I3C_CCC_GETCAPS1_HDR_MODE1 BIT(1)
858
859 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 2. */
860 #define I3C_CCC_GETCAPS1_HDR_MODE2 BIT(2)
861
862 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 3. */
863 #define I3C_CCC_GETCAPS1_HDR_MODE3 BIT(3)
864
865 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 4. */
866 #define I3C_CCC_GETCAPS1_HDR_MODE4 BIT(4)
867
868 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 5. */
869 #define I3C_CCC_GETCAPS1_HDR_MODE5 BIT(5)
870
871 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 6. */
872 #define I3C_CCC_GETCAPS1_HDR_MODE6 BIT(6)
873
874 /** Get Optional Feature Capabilities (GETCAPS) Format 1 - HDR Mode 7. */
875 #define I3C_CCC_GETCAPS1_HDR_MODE7 BIT(7)
876
877 /** Get Optional Feature Capabilities (GETCAPS) Format 2 - HDR-DDR Write Abort bit. */
878 #define I3C_CCC_GETCAPS2_HDRDDR_WRITE_ABORT BIT(6)
879
880 /** Get Optional Feature Capabilities (GETCAPS) Format 2 - HDR-DDR Abort CRC bit. */
881 #define I3C_CCC_GETCAPS2_HDRDDR_ABORT_CRC BIT(7)
882
883 /**
884 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 -
885 * Group Address Capabilities bit shift value.
886 */
887 #define I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT 4
888
889 /**
890 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 -
891 * Group Address Capabilities bitmask.
892 */
893 #define I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK \
894 (0x03U << I3C_CCC_GETCAPS2_GRPADDR_CAP_SHIFT)
895
896 /**
897 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 - Group Address Capabilities.
898 *
899 * Obtain Group Address Capabilities value from GETCAPS Format 2 value
900 * obtained via GETCAPS.
901 *
902 * @param getcaps2 GETCAPS2 value.
903 */
904 #define I3C_CCC_GETCAPS2_GRPADDR_CAP(getcaps2) \
905 (((getcaps2) & \
906 I3C_CCC_GETCAPS2_GRPADDR_CAP_MASK) \
907 >> I3C_CCC_GETCAPS_GRPADDR_CAP_SHIFT)
908
909 /**
910 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 -
911 * I3C 1.x Specification Version bit shift value.
912 */
913 #define I3C_CCC_GETCAPS2_SPEC_VER_SHIFT 0
914
915 /**
916 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 -
917 * I3C 1.x Specification Version bitmask.
918 */
919 #define I3C_CCC_GETCAPS2_SPEC_VER_MASK \
920 (0x0FU << I3C_CCC_GETCAPS2_SPEC_VER_SHIFT)
921
922 /**
923 * @brief Get Optional Feature Capabilities (GETCAPS) Format 2 -
924 * I3C 1.x Specification Version.
925 *
926 * Obtain I3C 1.x Specification Version value from GETCAPS Format 2 value
927 * obtained via GETCAPS.
928 *
929 * @param getcaps2 GETCAPS2 value.
930 */
931 #define I3C_CCC_GETCAPS2_SPEC_VER(getcaps2) \
932 (((getcaps2) & \
933 I3C_CCC_GETCAPS2_SPEC_VER_MASK) \
934 >> I3C_CCC_GETCAPS_SPEC_VER_SHIFT)
935
936 /**
937 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
938 * Multi-Lane Data Transfer Support bit.
939 */
940 #define I3C_CCC_GETCAPS3_MLANE_SUPPORT BIT(0)
941
942 /**
943 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
944 * Device to Device Transfer (D2DXFER) Support bit.
945 */
946 #define I3C_CCC_GETCAPS3_D2DXFER_SUPPORT BIT(1)
947
948 /**
949 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
950 * Device to Device Transfer (D2DXFER) IBI Capable bit.
951 */
952 #define I3C_CCC_GETCAPS3_D2DXFER_IBI_CAPABLE BIT(2)
953
954 /**
955 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
956 * Defining Byte Support in GETCAPS bit.
957 */
958 #define I3C_CCC_GETCAPS3_GETCAPS_DEFINING_BYTE_SUPPORT BIT(3)
959
960 /**
961 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
962 * Defining Byte Support in GETSTATUS bit.
963 */
964 #define I3C_CCC_GETCAPS3_GETSTATUS_DEFINING_BYTE_SUPPORT BIT(4)
965
966 /**
967 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
968 * HDR-BT CRC-32 Support bit.
969 */
970 #define I3C_CCC_GETCAPS3_HDRBT_CRC32_SUPPORT BIT(5)
971
972 /**
973 * @brief Get Optional Feature Capabilities (GETCAPS) Format 3 -
974 * IBI MDB Support for Pending Read Notification bit.
975 */
976 #define I3C_CCC_GETCAPS3_IBI_MDR_PENDING_READ_NOTIFICATION BIT(6)
977
978 /**
979 * @brief Enum for I3C Reset Action (RSTACT) Defining Byte Values.
980 */
981 enum i3c_ccc_rstact_defining_byte {
982 /** No Reset on Target Reset Pattern. */
983 I3C_CCC_RSTACT_NO_RESET = 0x00U,
984
985 /** Reset the I3C Peripheral Only. */
986 I3C_CCC_RSTACT_PERIPHERAL_ONLY = 0x01U,
987
988 /** Reset the Whole Target. */
989 I3C_CCC_RSTACT_RESET_WHOLE_TARGET = 0x02U,
990
991 /** Debug Network Adapter Reset. */
992 I3C_CCC_RSTACT_DEBUG_NETWORK_ADAPTER = 0x03U,
993
994 /** Virtual Target Detect. */
995 I3C_CCC_RSTACT_VIRTUAL_TARGET_DETECT = 0x04U,
996 };
997
998 /**
999 * @brief Test if I3C CCC payload is for broadcast.
1000 *
1001 * This tests if the CCC payload is for broadcast.
1002 *
1003 * @param[in] payload Pointer to the CCC payload.
1004 *
1005 * @retval true if payload target is broadcast
1006 * @retval false if payload target is direct
1007 */
i3c_ccc_is_payload_broadcast(const struct i3c_ccc_payload * payload)1008 static inline bool i3c_ccc_is_payload_broadcast(const struct i3c_ccc_payload *payload)
1009 {
1010 return (payload->ccc.id <= I3C_CCC_BROADCAST_MAX_ID);
1011 }
1012
1013 /**
1014 * @brief Get BCR from a target
1015 *
1016 * Helper function to get BCR (Bus Characteristic Register) from
1017 * target device.
1018 *
1019 * @param[in] target Pointer to the target device descriptor.
1020 * @param[out] bcr Pointer to the BCR payload structure.
1021 *
1022 * @return @see i3c_do_ccc
1023 */
1024 int i3c_ccc_do_getbcr(struct i3c_device_desc *target,
1025 struct i3c_ccc_getbcr *bcr);
1026
1027 /**
1028 * @brief Get DCR from a target
1029 *
1030 * Helper function to get DCR (Device Characteristic Register) from
1031 * target device.
1032 *
1033 * @param[in] target Pointer to the target device descriptor.
1034 * @param[out] dcr Pointer to the DCR payload structure.
1035 *
1036 * @return @see i3c_do_ccc
1037 */
1038 int i3c_ccc_do_getdcr(struct i3c_device_desc *target,
1039 struct i3c_ccc_getdcr *dcr);
1040
1041 /**
1042 * @brief Get PID from a target
1043 *
1044 * Helper function to get PID (Provisioned ID) from
1045 * target device.
1046 *
1047 * @param[in] target Pointer to the target device descriptor.
1048 * @param[out] pid Pointer to the PID payload structure.
1049 *
1050 * @return @see i3c_do_ccc
1051 */
1052 int i3c_ccc_do_getpid(struct i3c_device_desc *target,
1053 struct i3c_ccc_getpid *pid);
1054
1055 /**
1056 * @brief Broadcast RSTACT to reset I3C Peripheral.
1057 *
1058 * Helper function to broadcast Target Reset Action (RSTACT) to
1059 * all connected targets to Reset the I3C Peripheral Only (0x01).
1060 *
1061 * @param[in] controller Pointer to the controller device driver instance.
1062 * @param[in] action What reset action to perform.
1063 *
1064 * @return @see i3c_do_ccc
1065 */
1066 int i3c_ccc_do_rstact_all(const struct device *controller,
1067 enum i3c_ccc_rstact_defining_byte action);
1068
1069 /**
1070 * @brief Broadcast RSTDAA to reset dynamic addresses for all targets.
1071 *
1072 * Helper function to reset dynamic addresses of all connected targets.
1073 *
1074 * @param[in] controller Pointer to the controller device driver instance.
1075 *
1076 * @return @see i3c_do_ccc
1077 */
1078 int i3c_ccc_do_rstdaa_all(const struct device *controller);
1079
1080 /**
1081 * @brief Set Dynamic Address from Static Address for a target
1082 *
1083 * Helper function to do SETDASA (Set Dynamic Address from Static Address)
1084 * for a particular target.
1085 *
1086 * Note this does not update @p target with the new dynamic address.
1087 *
1088 * @param[in] target Pointer to the target device descriptor where
1089 * the device is configured with a static address.
1090 *
1091 * @return @see i3c_do_ccc
1092 */
1093 int i3c_ccc_do_setdasa(const struct i3c_device_desc *target);
1094
1095 /**
1096 * @brief Set New Dynamic Address for a target
1097 *
1098 * Helper function to do SETNEWDA(Set New Dynamic Address) for a particular target.
1099 *
1100 * Note this does not update @p target with the new dynamic address.
1101 *
1102 * @param[in] target Pointer to the target device descriptor where
1103 * the device is configured with a static address.
1104 * @param[in] new_da Pointer to the new_da struct.
1105 *
1106 * @return @see i3c_do_ccc
1107 */
1108 int i3c_ccc_do_setnewda(const struct i3c_device_desc *target,
1109 struct i3c_ccc_address new_da);
1110
1111 /**
1112 * @brief Broadcast ENEC/DISEC to enable/disable target events.
1113 *
1114 * Helper function to broadcast Target Events Command to enable or
1115 * disable target events (ENEC/DISEC).
1116 *
1117 * @param[in] controller Pointer to the controller device driver instance.
1118 * @param[in] enable ENEC if true, DISEC if false.
1119 * @param[in] events Pointer to the event struct.
1120 *
1121 * @return @see i3c_do_ccc
1122 */
1123 int i3c_ccc_do_events_all_set(const struct device *controller,
1124 bool enable, struct i3c_ccc_events *events);
1125
1126 /**
1127 * @brief Direct CCC ENEC/DISEC to enable/disable target events.
1128 *
1129 * Helper function to send Target Events Command to enable or
1130 * disable target events (ENEC/DISEC) on a single target.
1131 *
1132 * @param[in] target Pointer to the target device descriptor.
1133 * @param[in] enable ENEC if true, DISEC if false.
1134 * @param[in] events Pointer to the event struct.
1135 *
1136 * @return @see i3c_do_ccc
1137 */
1138 int i3c_ccc_do_events_set(struct i3c_device_desc *target,
1139 bool enable, struct i3c_ccc_events *events);
1140
1141 /**
1142 * @brief Broadcast SETMWL to Set Maximum Write Length.
1143 *
1144 * Helper function to do SETMWL (Set Maximum Write Length) to
1145 * all connected targets.
1146 *
1147 * @param[in] controller Pointer to the controller device driver instance.
1148 * @param[in] mwl Pointer to SETMWL payload.
1149 *
1150 * @return @see i3c_do_ccc
1151 */
1152 int i3c_ccc_do_setmwl_all(const struct device *controller,
1153 const struct i3c_ccc_mwl *mwl);
1154
1155 /**
1156 * @brief Single target SETMWL to Set Maximum Write Length.
1157 *
1158 * Helper function to do SETMWL (Set Maximum Write Length) to
1159 * one target.
1160 *
1161 * @param[in] target Pointer to the target device descriptor.
1162 * @param[in] mwl Pointer to SETMWL payload.
1163 *
1164 * @return @see i3c_do_ccc
1165 */
1166 int i3c_ccc_do_setmwl(const struct i3c_device_desc *target,
1167 const struct i3c_ccc_mwl *mwl);
1168
1169 /**
1170 * @brief Single target GETMWL to Get Maximum Write Length.
1171 *
1172 * Helper function to do GETMWL (Get Maximum Write Length) of
1173 * one target.
1174 *
1175 * @param[in] target Pointer to the target device descriptor.
1176 * @param[out] mwl Pointer to GETMWL payload.
1177 *
1178 * @return @see i3c_do_ccc
1179 */
1180 int i3c_ccc_do_getmwl(const struct i3c_device_desc *target,
1181 struct i3c_ccc_mwl *mwl);
1182
1183 /**
1184 * @brief Broadcast SETMRL to Set Maximum Read Length.
1185 *
1186 * Helper function to do SETMRL (Set Maximum Read Length) to
1187 * all connected targets.
1188 *
1189 * @param[in] controller Pointer to the controller device driver instance.
1190 * @param[in] mrl Pointer to SETMRL payload.
1191 * @param[in] has_ibi_size True if also sending the optional IBI payload
1192 * size. False if not sending.
1193 *
1194 * @return @see i3c_do_ccc
1195 */
1196 int i3c_ccc_do_setmrl_all(const struct device *controller,
1197 const struct i3c_ccc_mrl *mrl,
1198 bool has_ibi_size);
1199
1200 /**
1201 * @brief Single target SETMRL to Set Maximum Read Length.
1202 *
1203 * Helper function to do SETMRL (Set Maximum Read Length) to
1204 * one target.
1205 *
1206 * Note this uses the BCR of the target to determine whether
1207 * to send the optional IBI payload size.
1208 *
1209 * @param[in] target Pointer to the target device descriptor.
1210 * @param[in] mrl Pointer to SETMRL payload.
1211 *
1212 * @return @see i3c_do_ccc
1213 */
1214 int i3c_ccc_do_setmrl(const struct i3c_device_desc *target,
1215 const struct i3c_ccc_mrl *mrl);
1216
1217 /**
1218 * @brief Single target GETMRL to Get Maximum Read Length.
1219 *
1220 * Helper function to do GETMRL (Get Maximum Read Length) of
1221 * one target.
1222 *
1223 * Note this uses the BCR of the target to determine whether
1224 * to send the optional IBI payload size.
1225 *
1226 * @param[in] target Pointer to the target device descriptor.
1227 * @param[out] mrl Pointer to GETMRL payload.
1228 *
1229 * @return @see i3c_do_ccc
1230 */
1231 int i3c_ccc_do_getmrl(const struct i3c_device_desc *target,
1232 struct i3c_ccc_mrl *mrl);
1233
1234 /**
1235 * @brief Single target GETSTATUS to Get Target Status.
1236 *
1237 * Helper function to do GETSTATUS (Get Target Status) of
1238 * one target.
1239 *
1240 * Note this uses the BCR of the target to determine whether
1241 * to send the optional IBI payload size.
1242 *
1243 * @param[in] target Pointer to the target device descriptor.
1244 * @param[out] status Pointer to GETSTATUS payload.
1245 * @param[in] fmt Which GETSTATUS to use.
1246 * @param[in] defbyte Defining Byte if using format 2.
1247 *
1248 * @return @see i3c_do_ccc
1249 */
1250 int i3c_ccc_do_getstatus(const struct i3c_device_desc *target,
1251 union i3c_ccc_getstatus *status,
1252 enum i3c_ccc_getstatus_fmt fmt,
1253 enum i3c_ccc_getstatus_defbyte defbyte);
1254
1255 /**
1256 * @brief Single target GETSTATUS to Get Target Status (Format 1).
1257 *
1258 * Helper function to do GETSTATUS (Get Target Status, format 1) of
1259 * one target.
1260 *
1261 * @param[in] target Pointer to the target device descriptor.
1262 * @param[out] status Pointer to GETSTATUS payload.
1263 *
1264 * @return @see i3c_do_ccc
1265 */
i3c_ccc_do_getstatus_fmt1(const struct i3c_device_desc * target,union i3c_ccc_getstatus * status)1266 static inline int i3c_ccc_do_getstatus_fmt1(const struct i3c_device_desc *target,
1267 union i3c_ccc_getstatus *status)
1268 {
1269 return i3c_ccc_do_getstatus(target, status,
1270 GETSTATUS_FORMAT_1,
1271 GETSTATUS_FORMAT_2_INVALID);
1272 }
1273
1274 /**
1275 * @brief Single target GETSTATUS to Get Target Status (Format 2).
1276 *
1277 * Helper function to do GETSTATUS (Get Target Status, format 2) of
1278 * one target.
1279 *
1280 * @param[in] target Pointer to the target device descriptor.
1281 * @param[out] status Pointer to GETSTATUS payload.
1282 * @param[in] defbyte Defining Byte for GETSTATUS format 2.
1283 *
1284 * @return @see i3c_do_ccc
1285 */
i3c_ccc_do_getstatus_fmt2(const struct i3c_device_desc * target,union i3c_ccc_getstatus * status,enum i3c_ccc_getstatus_defbyte defbyte)1286 static inline int i3c_ccc_do_getstatus_fmt2(const struct i3c_device_desc *target,
1287 union i3c_ccc_getstatus *status,
1288 enum i3c_ccc_getstatus_defbyte defbyte)
1289 {
1290 return i3c_ccc_do_getstatus(target, status,
1291 GETSTATUS_FORMAT_2, defbyte);
1292 }
1293
1294
1295 #ifdef __cplusplus
1296 }
1297 #endif
1298
1299 /**
1300 * @}
1301 */
1302
1303 #endif /* ZEPHYR_INCLUDE_DRIVERS_I3C_CCC_H_ */
1304
