1 /**************************************************************************//** 2 * @file i2s_reg.h 3 * @version V1.00 4 * @brief I2S register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __I2S_REG_H__ 10 #define __I2S_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- I2S Interface Controller -------------------------*/ 19 /** 20 @addtogroup I2S I2S Interface Controller(I2S) 21 Memory Mapped Structure for I2S Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var I2S_T::CTL0 31 * Offset: 0x00 I2S Control Register 0 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |I2SEN |I2S Controller Enable Control 36 * | | |0 = I2S controller Disabled. 37 * | | |1 = I2S controller Enabled. 38 * |[1] |TXEN |Transmit Enable Control 39 * | | |0 = Data transmission Disabled. 40 * | | |1 = Data transmission Enabled. 41 * |[2] |RXEN |Receive Enable Control 42 * | | |0 = Data receiving Disabled. 43 * | | |1 = Data receiving Enabled. 44 * |[3] |MUTE |Transmit Mute Enable Control 45 * | | |0 = Transmit data is shifted from buffer. 46 * | | |1 = Send zero on transmit channel. 47 * |[5:4] |DATWIDTH |Data Width 48 * | | |This bit field is used to define the bit-width of data word in each audio channel 49 * | | |00 = The bit-width of data word is 8-bit. 50 * | | |01 = The bit-width of data word is 16-bit. 51 * | | |10 = The bit-width of data word is 24-bit. 52 * | | |11 = The bit-width of data word is 32-bit. 53 * |[6] |MONO |Monaural Data Control 54 * | | |0 = Data is stereo format. 55 * | | |1 = Data is monaural format. 56 * | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected. 57 * |[7] |ORDER |Stereo Data Order in FIFO 58 * | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte 59 * | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries. 60 * | | |0 = Even channel data at high byte in 8-bit/16-bit data width. 61 * | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries. 62 * | | |1 = Even channel data at low byte. 63 * | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries. 64 * |[8] |SLAVE |Slave Mode Enable Control 65 * | | |0 = Master mode. 66 * | | |1 = Slave mode. 67 * | | |Note: I2S can operate as master or slave 68 * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip 69 * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. 70 * |[15] |MCLKEN |Master Clock Enable Control 71 * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices. 72 * | | |0 = Master clock Disabled. 73 * | | |1 = Master clock Enabled. 74 * |[18] |TXFBCLR |Transmit FIFO Buffer Clear 75 * | | |0 = No Effect. 76 * | | |1 = Clear TX FIFO. 77 * | | |Note 1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. 78 * | | |Note 2: This bit is clear by hardware automatically, read it return zero. 79 * |[19] |RXFBCLR |Receive FIFO Buffer Clear 80 * | | |0 = No Effect. 81 * | | |1 = Clear RX FIFO. 82 * | | |Note 1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty. 83 * | | |Note 2: This bit is cleared by hardware automatically, read it return zero. 84 * |[20] |TXPDMAEN |Transmit PDMA Enable Control 85 * | | |0 = Transmit PDMA function Disabled. 86 * | | |1 = Transmit PDMA function Enabled. 87 * |[21] |RXPDMAEN |Receive PDMA Enable Control 88 * | | |0 = Receiver PDMA function Disabled. 89 * | | |1 = Receiver PDMA function Enabled. 90 * |[23] |RXLCH |Receive Left Channel Enable Control 91 * | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1. 92 * | | |0 = Receives channel1 data in MONO mode. 93 * | | |1 = Receives channel0 data in MONO mode. 94 * |[26:24] |FORMAT |Data Format Selection 95 * | | |000 = I2S standard data format. 96 * | | |001 = I2S with MSB justified. 97 * | | |010 = I2S with LSB justified. 98 * | | |011 = Reserved. 99 * | | |100 = PCM standard data format. 100 * | | |101 = PCM with MSB justified. 101 * | | |110 = PCM with LSB justified. 102 * | | |111 = Reserved. 103 * |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection 104 * | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol. 105 * | | |0 = One BCLK period. 106 * | | |1 = One channel period. 107 * | | |Note: This bit is only available in master mode. 108 * |[29:28] |CHWIDTH |Channel Width 109 * | | |This bit fields are used to define the length of audio channel 110 * | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH. 111 * | | |00 = The bit-width of each audio channel is 8-bit. 112 * | | |01 = The bit-width of each audio channel is 16-bit. 113 * | | |10 = The bit-width of each audio channel is 24-bit. 114 * | | |11 = The bit-width of each audio channel is 32-bit. 115 * |[31:30] |TDMCHNUM |TDM Channel Number 116 * | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1). 117 * | | |00 = 2 channels in audio frame. 118 * | | |01 = 4 channels in audio frame. 119 * | | |10 = 6 channels in audio frame. 120 * | | |11 = 8 channels in audio frame. 121 * @var I2S_T::CLKDIV 122 * Offset: 0x04 I2S Clock Divider Register 123 * --------------------------------------------------------------------------------------------------- 124 * |Bits |Field |Descriptions 125 * | :----: | :----: | :---- | 126 * |[5:0] |MCLKDIV |Master Clock Divider 127 * | | |If chip external crystal frequency is (2 x MCLKDIV) x 256fs then software can program these bits to generate 256fs clock frequency to audio codec chip 128 * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input. 129 * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1. 130 * | | |F_MCLK = F_I2SCLK/(2 x MCLKDIV) (When MCLKDIV is >= 1 ). 131 * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ). 132 * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK. 133 * |[16:8] |BCLKDIV |Bit Clock Divider 134 * | | |The I2S controller will generate bit clock in Master mode 135 * | | |Software can program these bit fields to generate sampling rate clock frequency. 136 * | | |F_BCLK= F_I2SCLK / (2 x (BCLKDIV + 1)). 137 * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK. 138 * @var I2S_T::IEN 139 * Offset: 0x08 I2S Interrupt Enable Register 140 * --------------------------------------------------------------------------------------------------- 141 * |Bits |Field |Descriptions 142 * | :----: | :----: | :---- | 143 * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control 144 * | | |0 = Interrupt Disabled. 145 * | | |1 = Interrupt Enabled. 146 * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. 147 * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control 148 * | | |0 = Interrupt Disabled. 149 * | | |1 = Interrupt Enabled. 150 * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1. 151 * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control 152 * | | |0 = Interrupt Disabled. 153 * | | |1 = Interrupt Enabled. 154 * | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1 155 * | | |If RXTHIEN bit is enabled, interrupt occur. 156 * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control 157 * | | |0 = Interrupt Disabled. 158 * | | |1 = Interrupt Enabled. 159 * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. 160 * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control 161 * | | |0 = Interrupt Disabled. 162 * | | |1 = Interrupt Enabled. 163 * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1. 164 * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control 165 * | | |0 = Interrupt Disabled. 166 * | | |1 = Interrupt Enabled. 167 * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]). 168 * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control 169 * | | |0 = Interrupt Disabled. 170 * | | |1 = Interrupt Enabled. 171 * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross. 172 * | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. 173 * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control 174 * | | |0 = Interrupt Disabled. 175 * | | |1 = Interrupt Enabled. 176 * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross. 177 * | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. 178 * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control 179 * | | |0 = Interrupt Disabled. 180 * | | |1 = Interrupt Enabled. 181 * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross. 182 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 183 * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control 184 * | | |0 = Interrupt Disabled. 185 * | | |1 = Interrupt Enabled. 186 * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross. 187 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 188 * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control 189 * | | |0 = Interrupt Disabled. 190 * | | |1 = Interrupt Enabled. 191 * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross. 192 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 193 * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control 194 * | | |0 = Interrupt Disabled. 195 * | | |1 = Interrupt Enabled. 196 * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross. 197 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 198 * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control 199 * | | |0 = Interrupt Disabled. 200 * | | |1 = Interrupt Enabled. 201 * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross. 202 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 203 * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control 204 * | | |0 = Interrupt Disabled. 205 * | | |1 = Interrupt Enabled. 206 * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross. 207 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 208 * @var I2S_T::STATUS0 209 * Offset: 0x0C I2S Status Register 0 210 * --------------------------------------------------------------------------------------------------- 211 * |Bits |Field |Descriptions 212 * | :----: | :----: | :---- | 213 * |[0] |I2SINT |I2S Interrupt Flag (Read Only) 214 * | | |0 = No I2S interrupt. 215 * | | |1 = I2S interrupt. 216 * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits. 217 * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only) 218 * | | |0 = No receive interrupt. 219 * | | |1 = Receive interrupt. 220 * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only) 221 * | | |0 = No transmit interrupt. 222 * | | |1 = Transmit interrupt. 223 * |[5:3] |DATACH |Transmission Data Channel (Read Only) 224 * | | |This bit fields are used to indicate which audio channel is current transmit data belong. 225 * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode). 226 * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode). 227 * | | |010 = channel2 (available while 4-channel TDM PCM mode). 228 * | | |011 = channel3 (available while 4-channel TDM PCM mode). 229 * | | |100 = channel4 (available while 6-channel TDM PCM mode). 230 * | | |101 = channel5 (available while 6-channel TDM PCM mode). 231 * | | |110 = channel6 (available while 8-channel TDM PCM mode). 232 * | | |111 = channel7 (available while 8-channel TDM PCM mode). 233 * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag 234 * | | |0 = No underflow occur. 235 * | | |1 = Underflow occur. 236 * | | |Note 1: When receive FIFO is empty, and software reads the receive FIFO again 237 * | | |This bit will be set to 1, and it indicates underflow situation occurs. 238 * | | |Note 2: Write 1 to clear this bit to zero 239 * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag 240 * | | |0 = No overflow occur. 241 * | | |1 = Overflow occur. 242 * | | |Note 1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. 243 * | | |Note 2: Write 1 to clear this bit to 0. 244 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) 245 * | | |0 = Data word(s) in FIFO is not higher than threshold level. 246 * | | |1 = Data word(s) in FIFO is higher than threshold level. 247 * | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1 248 * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. 249 * |[11] |RXFULL |Receive FIFO Full (Read Only) 250 * | | |0 = Not full. 251 * | | |1 = Full. 252 * | | |Note: This bit reflects data words number in receive FIFO is 16. 253 * |[12] |RXEMPTY |Receive FIFO Empty (Read Only) 254 * | | |0 = Not empty. 255 * | | |1 = Empty. 256 * | | |Note: This bit reflects data words number in receive FIFO is 0. 257 * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag 258 * | | |0 = No underflow. 259 * | | |1 = Underflow. 260 * | | |Note 1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. 261 * | | |Note 2: Write 1 to clear this bit to 0. 262 * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag 263 * | | |0 = No overflow. 264 * | | |1 = Overflow. 265 * | | |Note 1: Write data to transmit FIFO when it is full and this bit set to 1. 266 * | | |Note 2: Write 1 to clear this bit to 0. 267 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) 268 * | | |0 = Data word(s) in FIFO is higher than threshold level. 269 * | | |1 = Data word(s) in FIFO is equal or lower than threshold level. 270 * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1 271 * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. 272 * |[19] |TXFULL |Transmit FIFO Full (Read Only) 273 * | | |0 = Not full. 274 * | | |1 = Full. 275 * | | |Note: This bit reflects data words number in transmit FIFO is 16. 276 * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only) 277 * | | |0 = Not empty. 278 * | | |1 = Empty. 279 * | | |Note: This bit reflects data words number in transmit FIFO is 0. 280 * |[21] |TXBUSY |Transmit Busy (Read Only) 281 * | | |0 = Transmit shift buffer is empty. 282 * | | |1 = Transmit shift buffer is busy. 283 * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out 284 * | | |And set to 1 when 1st data is load to shift buffer 285 * @var I2S_T::TXFIFO 286 * Offset: 0x10 I2S Transmit FIFO Register 287 * --------------------------------------------------------------------------------------------------- 288 * |Bits |Field |Descriptions 289 * | :----: | :----: | :---- | 290 * |[31:0] |TXFIFO |Transmit FIFO Bits 291 * | | |I2S contains 16 words (16x32 bit) data buffer for data transmit 292 * | | |Write data to this register to prepare data for transmit 293 * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). 294 * @var I2S_T::RXFIFO 295 * Offset: 0x14 I2S Receive FIFO Register 296 * --------------------------------------------------------------------------------------------------- 297 * |Bits |Field |Descriptions 298 * | :----: | :----: | :---- | 299 * |[31:0] |RXFIFO |Receive FIFO Bits 300 * | | |I2S contains 16 words (16x32 bit) data buffer for data receive 301 * | | |Read this register to get data in FIFO 302 * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). 303 * @var I2S_T::CTL1 304 * Offset: 0x20 I2S Control Register 1 305 * --------------------------------------------------------------------------------------------------- 306 * |Bits |Field |Descriptions 307 * | :----: | :----: | :---- | 308 * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control 309 * | | |0 = channel0 zero-cross detect Disabled. 310 * | | |1 = channel0 zero-cross detect Enabled. 311 * | | |Note 1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. 312 * | | |Note 2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. 313 * | | |Note 3: If CH0ZCIF Flag is set to 1, the channel0 will be mute. 314 * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control 315 * | | |0 = channel1 zero-cross detect Disabled. 316 * | | |1 = channel1 zero-cross detect Enabled. 317 * | | |Note 1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. 318 * | | |Note 2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. 319 * | | |Note 3: If CH1ZCIF Flag is set to 1, the channel1 will be mute. 320 * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control 321 * | | |0 = channel2 zero-cross detect Disabled. 322 * | | |1 = channel2 zero-cross detect Enabled. 323 * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 324 * | | |Note 2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1. 325 * | | |Note 3: If CH2ZCIF Flag is set to 1, the channel2 will be mute. 326 * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control 327 * | | |0 = channel3 zero-cross detect Disabled. 328 * | | |1 = channel3 zero-cross detect Enabled. 329 * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 330 * | | |Note 2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1. 331 * | | |Note 3: If CH3ZCIF Flag is set to 1, the channel3 will be mute. 332 * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control 333 * | | |0 = channel4 zero-cross detect Disabled. 334 * | | |1 = channel4 zero-cross detect Enabled. 335 * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 336 * | | |Note 2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1. 337 * | | |Note 3: If CH4ZCIF Flag is set to 1, the channel4 will be mute. 338 * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control 339 * | | |0 = channel5 zero-cross detect Disabled. 340 * | | |1 = channel5 zero-cross detect Enabled. 341 * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 342 * | | |Note 2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1. 343 * | | |Note 3: If CH5ZCIF Flag is set to 1, the channel5 will be mute. 344 * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control 345 * | | |0 = channel6 zero-cross detect Disabled. 346 * | | |1 = channel6 zero-cross detect Enabled. 347 * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 348 * | | |Note 2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1. 349 * | | |Note 3: If CH6ZCIF Flag is set to 1, the channel6 will be mute. 350 * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control 351 * | | |0 = channel7 zero-cross detect Disabled. 352 * | | |1 = channel7 zero-cross detect Enabled. 353 * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 354 * | | |Note 2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1. 355 * | | |Note 3: If CH7ZCIF Flag is set to 1, the channel7 will be mute. 356 * |[11:8] |TXTH |Transmit FIFO Threshold Level 357 * | | |0000 = 0 data word in transmit FIFO. 358 * | | |0001 = 1 data word in transmit FIFO. 359 * | | |0010 = 2 data words in transmit FIFO. 360 * | | |... 361 * | | |1110 = 14 data words in transmit FIFO. 362 * | | |1111 = 15 data words in transmit FIFO. 363 * | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. 364 * |[19:16] |RXTH |Receive FIFO Threshold Level 365 * | | |0000 = 1 data word in receive FIFO. 366 * | | |0001 = 2 data words in receive FIFO. 367 * | | |0010 = 3 data words in receive FIFO. 368 * | | |... 369 * | | |1110 = 15 data words in receive FIFO. 370 * | | |1111 = 16 data words in receive FIFO. 371 * | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. 372 * |[24] |PBWIDTH |Peripheral Bus Data Width Selection 373 * | | |This bit is used to choice the available data width of APB bus 374 * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode 375 * | | |0 = 32 bits data width. 376 * | | |1 = 16 bits data width. 377 * | | |Note 1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available. 378 * | | |Note 2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations. 379 * | | |Note 3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations. 380 * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus 381 * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access 382 * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries. 383 * | | |0 = Low 16-bit read/write access first. 384 * | | |1 = High 16-bit read/write access first. 385 * | | |Note: This bit is available while PBWIDTH = 1. 386 * @var I2S_T::STATUS1 387 * Offset: 0x24 I2S Status Register 1 388 * --------------------------------------------------------------------------------------------------- 389 * |Bits |Field |Descriptions 390 * | :----: | :----: | :---- | 391 * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag 392 * | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero. 393 * | | |0 = No zero-cross in channel0. 394 * | | |1 = Channel0 zero-cross is detected. 395 * | | |Note 1: Write 1 to clear this bit to 0. 396 * | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. 397 * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag 398 * | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero. 399 * | | |0 = No zero-cross in channel1. 400 * | | |1 = Channel1 zero-cross is detected. 401 * | | |Note 1: Write 1 to clear this bit to 0. 402 * | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. 403 * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag 404 * | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero. 405 * | | |0 = No zero-cross in channel2. 406 * | | |1 = Channel2 zero-cross is detected. 407 * | | |Note 1: Write 1 to clear this bit to 0. 408 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 409 * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag 410 * | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero. 411 * | | |0 = No zero-cross in channel3. 412 * | | |1 = Channel3 zero-cross is detected. 413 * | | |Note 1: Write 1 to clear this bit to 0. 414 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 415 * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag 416 * | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero. 417 * | | |0 = No zero-cross in channel4. 418 * | | |1 = Channel4 zero-cross is detected. 419 * | | |Note 1: Write 1 to clear this bit to 0. 420 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 421 * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag 422 * | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero. 423 * | | |0 = No zero-cross in channel5. 424 * | | |1 = Channel5 zero-cross is detected. 425 * | | |Note 1: Write 1 to clear this bit to 0. 426 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 427 * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag 428 * | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero. 429 * | | |0 = No zero-cross in channel6. 430 * | | |1 = Channel6 zero-cross is detected. 431 * | | |Note 1: Write 1 to clear this bit to 0. 432 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 433 * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag 434 * | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero. 435 * | | |0 = No zero-cross in channel7. 436 * | | |1 = Channel7 zero-cross is detected. 437 * | | |Note 1: Write 1 to clear this bit to 0. 438 * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. 439 * |[12:8] |TXCNT |Transmit FIFO Level (Read Only) 440 * | | |These bits indicate the number of available entries in transmit FIFO. 441 * | | |00000 = No data. 442 * | | |00001 = 1 word in transmit FIFO. 443 * | | |00010 = 2 words in transmit FIFO. 444 * | | |... 445 * | | |01110 = 14 words in transmit FIFO. 446 * | | |01111 = 15 words in transmit FIFO. 447 * | | |10000 = 16 words in transmit FIFO. 448 * | | |Others are reserved. 449 * |[20:16] |RXCNT |Receive FIFO Level (Read Only) 450 * | | |These bits indicate the number of available entries in receive FIFO. 451 * | | |00000 = No data. 452 * | | |00001 = 1 word in receive FIFO. 453 * | | |00010 = 2 words in receive FIFO. 454 * | | |... 455 * | | |01110 = 14 words in receive FIFO. 456 * | | |01111 = 15 words in receive FIFO. 457 * | | |10000 = 16 words in receive FIFO. 458 * | | |Others are reserved. 459 */ 460 __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */ 461 __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */ 462 __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */ 463 __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */ 464 __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */ 465 __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */ 466 __I uint32_t RESERVE0[2]; 467 __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */ 468 __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */ 469 470 } I2S_T; 471 472 /** 473 @addtogroup I2S_CONST I2S Bit Field Definition 474 Constant Definitions for I2S Controller 475 @{ 476 */ 477 478 #define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */ 479 #define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */ 480 481 #define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */ 482 #define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */ 483 484 #define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */ 485 #define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */ 486 487 #define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */ 488 #define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */ 489 490 #define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */ 491 #define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */ 492 493 #define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */ 494 #define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */ 495 496 #define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */ 497 #define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */ 498 499 #define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */ 500 #define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */ 501 502 #define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */ 503 #define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */ 504 505 #define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */ 506 #define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */ 507 508 #define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */ 509 #define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */ 510 511 #define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */ 512 #define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */ 513 514 #define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */ 515 #define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */ 516 517 #define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */ 518 #define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */ 519 520 #define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */ 521 #define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */ 522 523 #define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */ 524 #define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */ 525 526 #define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */ 527 #define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */ 528 529 #define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */ 530 #define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */ 531 532 #define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */ 533 #define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */ 534 535 #define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */ 536 #define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */ 537 538 #define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */ 539 #define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */ 540 541 #define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */ 542 #define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */ 543 544 #define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */ 545 #define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */ 546 547 #define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */ 548 #define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */ 549 550 #define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */ 551 #define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */ 552 553 #define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */ 554 #define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */ 555 556 #define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */ 557 #define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */ 558 559 #define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */ 560 #define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */ 561 562 #define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */ 563 #define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */ 564 565 #define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */ 566 #define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */ 567 568 #define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */ 569 #define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */ 570 571 #define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */ 572 #define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */ 573 574 #define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */ 575 #define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */ 576 577 #define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */ 578 #define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */ 579 580 #define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */ 581 #define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */ 582 583 #define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */ 584 #define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */ 585 586 #define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */ 587 #define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */ 588 589 #define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */ 590 #define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */ 591 592 #define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */ 593 #define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */ 594 595 #define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */ 596 #define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */ 597 598 #define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */ 599 #define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */ 600 601 #define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */ 602 #define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */ 603 604 #define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */ 605 #define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */ 606 607 #define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */ 608 #define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */ 609 610 #define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */ 611 #define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */ 612 613 #define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */ 614 #define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */ 615 616 #define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */ 617 #define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */ 618 619 #define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */ 620 #define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */ 621 622 #define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */ 623 #define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */ 624 625 #define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */ 626 #define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */ 627 628 #define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */ 629 #define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */ 630 631 #define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */ 632 #define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */ 633 634 #define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */ 635 #define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */ 636 637 #define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */ 638 #define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */ 639 640 #define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */ 641 #define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */ 642 643 #define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */ 644 #define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */ 645 646 #define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */ 647 #define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */ 648 649 #define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */ 650 #define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */ 651 652 #define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */ 653 #define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */ 654 655 #define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */ 656 #define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */ 657 658 #define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */ 659 #define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */ 660 661 #define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */ 662 #define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */ 663 664 #define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */ 665 #define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */ 666 667 #define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */ 668 #define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */ 669 670 #define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */ 671 #define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */ 672 673 #define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */ 674 #define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */ 675 676 #define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */ 677 #define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */ 678 679 #define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */ 680 #define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */ 681 682 #define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */ 683 #define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */ 684 685 #define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */ 686 #define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */ 687 688 #define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */ 689 #define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */ 690 691 #define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */ 692 #define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */ 693 694 #define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */ 695 #define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */ 696 697 /**@}*/ /* I2S_CONST */ 698 /**@}*/ /* end of I2S register group */ 699 /**@}*/ /* end of REGISTER group */ 700 701 #endif /* __I2S_REG_H__ */ 702
