1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 #define I2C_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) 15 /* I2C_MST_I2C0_CTRL : R/W; bitpos: [24:0]; default: 0;*/ 16 /* description: .*/ 17 #define I2C_MST_I2C0_CTRL 0x01FFFFFFU 18 #define I2C_MST_I2C0_CTRL_M (I2C_MST_I2C0_CTRL_V << I2C_MST_I2C0_CTRL_S) 19 #define I2C_MST_I2C0_CTRL_V 0x01FFFFFFU 20 #define I2C_MST_I2C0_CTRL_S 0 21 /* I2C_MST_I2C0_BUSY : RO; bitpos: [25]; default: 0;*/ 22 /* description: .*/ 23 #define I2C_MST_I2C0_BUSY (BIT(25)) 24 #define I2C_MST_I2C0_BUSY_M (I2C_MST_I2C0_BUSY_V << I2C_MST_I2C0_BUSY_S) 25 #define I2C_MST_I2C0_BUSY_V 0x00000001U 26 #define I2C_MST_I2C0_BUSY_S 25 27 28 #define I2C_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) 29 /* I2C_MST_I2C1_CTRL : R/W; bitpos: [24:0]; default: 0;*/ 30 /* description: .*/ 31 #define I2C_MST_I2C1_CTRL 0x01FFFFFFU 32 #define I2C_MST_I2C1_CTRL_M (I2C_MST_I2C1_CTRL_V << I2C_MST_I2C1_CTRL_S) 33 #define I2C_MST_I2C1_CTRL_V 0x01FFFFFFU 34 #define I2C_MST_I2C1_CTRL_S 0 35 /* I2C_MST_I2C1_BUSY : RO; bitpos: [25]; default: 0;*/ 36 /* description: .*/ 37 #define I2C_MST_I2C1_BUSY (BIT(25)) 38 #define I2C_MST_I2C1_BUSY_M (I2C_MST_I2C1_BUSY_V << I2C_MST_I2C1_BUSY_S) 39 #define I2C_MST_I2C1_BUSY_V 0x00000001U 40 #define I2C_MST_I2C1_BUSY_S 25 41 42 #define I2C_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) 43 /* I2C_MST_I2C0_CONF : R/W; bitpos: [23:0]; default: 0;*/ 44 /* description: .*/ 45 #define I2C_MST_I2C0_CONF 0x00FFFFFFU 46 #define I2C_MST_I2C0_CONF_M (I2C_MST_I2C0_CONF_V << I2C_MST_I2C0_CONF_S) 47 #define I2C_MST_I2C0_CONF_V 0x00FFFFFFU 48 #define I2C_MST_I2C0_CONF_S 0 49 /* I2C_MST_I2C0_STATUS : RO; bitpos: [31:24]; default: 0;*/ 50 /* description: .*/ 51 #define I2C_MST_I2C0_STATUS 0x000000FFU 52 #define I2C_MST_I2C0_STATUS_M (I2C_MST_I2C0_STATUS_V << I2C_MST_I2C0_STATUS_S) 53 #define I2C_MST_I2C0_STATUS_V 0x000000FFU 54 #define I2C_MST_I2C0_STATUS_S 24 55 56 #define I2C_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xc) 57 /* I2C_MST_I2C1_CONF : R/W; bitpos: [23:0]; default: 0;*/ 58 /* description: .*/ 59 #define I2C_MST_I2C1_CONF 0x00FFFFFFU 60 #define I2C_MST_I2C1_CONF_M (I2C_MST_I2C1_CONF_V << I2C_MST_I2C1_CONF_S) 61 #define I2C_MST_I2C1_CONF_V 0x00FFFFFFU 62 #define I2C_MST_I2C1_CONF_S 0 63 /* I2C_MST_I2C1_STATUS : RO; bitpos: [31:24]; default: 0;*/ 64 /* description: .*/ 65 #define I2C_MST_I2C1_STATUS 0x000000FFU 66 #define I2C_MST_I2C1_STATUS_M (I2C_MST_I2C1_STATUS_V << I2C_MST_I2C1_STATUS_S) 67 #define I2C_MST_I2C1_STATUS_V 0x000000FFU 68 #define I2C_MST_I2C1_STATUS_S 24 69 70 #define I2C_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) 71 /* I2C_MST_BURST_CTRL : R/W; bitpos: [31:0]; default: 0;*/ 72 /* description: .*/ 73 #define I2C_MST_BURST_CTRL 0xFFFFFFFFU 74 #define I2C_MST_BURST_CTRL_M (I2C_MST_BURST_CTRL_V << I2C_MST_BURST_CTRL_S) 75 #define I2C_MST_BURST_CTRL_V 0xFFFFFFFFU 76 #define I2C_MST_BURST_CTRL_S 0 77 78 #define I2C_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) 79 /* I2C_MST_I2C_MST_BURST_DONE : RO; bitpos: [0]; default: 0;*/ 80 /* description: .*/ 81 #define I2C_MST_I2C_MST_BURST_DONE (BIT(0)) 82 #define I2C_MST_I2C_MST_BURST_DONE_M (I2C_MST_I2C_MST_BURST_DONE_V << I2C_MST_I2C_MST_BURST_DONE_S) 83 #define I2C_MST_I2C_MST_BURST_DONE_V 0x00000001U 84 #define I2C_MST_I2C_MST_BURST_DONE_S 0 85 /* I2C_MST_I2C_MST0_BURST_ERR_FLAG : RO; bitpos: [1]; default: 0;*/ 86 /* description: .*/ 87 #define I2C_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1)) 88 #define I2C_MST_I2C_MST0_BURST_ERR_FLAG_M (I2C_MST_I2C_MST0_BURST_ERR_FLAG_V << I2C_MST_I2C_MST0_BURST_ERR_FLAG_S) 89 #define I2C_MST_I2C_MST0_BURST_ERR_FLAG_V 0x00000001U 90 #define I2C_MST_I2C_MST0_BURST_ERR_FLAG_S 1 91 /* I2C_MST_I2C_MST1_BURST_ERR_FLAG : RO; bitpos: [2]; default: 0;*/ 92 /* description: .*/ 93 #define I2C_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2)) 94 #define I2C_MST_I2C_MST1_BURST_ERR_FLAG_M (I2C_MST_I2C_MST1_BURST_ERR_FLAG_V << I2C_MST_I2C_MST1_BURST_ERR_FLAG_S) 95 #define I2C_MST_I2C_MST1_BURST_ERR_FLAG_V 0x00000001U 96 #define I2C_MST_I2C_MST1_BURST_ERR_FLAG_S 2 97 /* I2C_MST_BURST_TIMEOUT_CNT : RO; bitpos: [19:3]; default: 0;*/ 98 /* description: .*/ 99 #define I2C_MST_BURST_TIMEOUT_CNT 0x0001FFFFU 100 #define I2C_MST_BURST_TIMEOUT_CNT_M (I2C_MST_BURST_TIMEOUT_CNT_V << I2C_MST_BURST_TIMEOUT_CNT_S) 101 #define I2C_MST_BURST_TIMEOUT_CNT_V 0x0001FFFFU 102 #define I2C_MST_BURST_TIMEOUT_CNT_S 3 103 104 #define I2C_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) 105 /* I2C_MST_ANA_CONF0 : R/W; bitpos: [23:0]; default: 0;*/ 106 /* description: .*/ 107 #define I2C_MST_ANA_CONF0 0x00FFFFFFU 108 #define I2C_MST_ANA_CONF0_M (I2C_MST_ANA_CONF0_V << I2C_MST_ANA_CONF0_S) 109 #define I2C_MST_ANA_CONF0_V 0x00FFFFFFU 110 #define I2C_MST_ANA_CONF0_S 0 111 /* I2C_MST_ANA_STATUS0 : RO; bitpos: [31:24]; default: 0;*/ 112 /* description: .*/ 113 #define I2C_MST_ANA_STATUS0 0x000000FFU 114 #define I2C_MST_ANA_STATUS0_M (I2C_MST_ANA_STATUS0_V << I2C_MST_ANA_STATUS0_S) 115 #define I2C_MST_ANA_STATUS0_V 0x000000FFU 116 #define I2C_MST_ANA_STATUS0_S 24 117 118 #define I2C_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1c) 119 /* I2C_MST_ANA_CONF1 : R/W; bitpos: [23:0]; default: 0;*/ 120 /* description: .*/ 121 #define I2C_MST_ANA_CONF1 0x00FFFFFFU 122 #define I2C_MST_ANA_CONF1_M (I2C_MST_ANA_CONF1_V << I2C_MST_ANA_CONF1_S) 123 #define I2C_MST_ANA_CONF1_V 0x00FFFFFFU 124 #define I2C_MST_ANA_CONF1_S 0 125 /* I2C_MST_ANA_STATUS1 : RO; bitpos: [31:24]; default: 0;*/ 126 /* description: .*/ 127 #define I2C_MST_ANA_STATUS1 0x000000FFU 128 #define I2C_MST_ANA_STATUS1_M (I2C_MST_ANA_STATUS1_V << I2C_MST_ANA_STATUS1_S) 129 #define I2C_MST_ANA_STATUS1_V 0x000000FFU 130 #define I2C_MST_ANA_STATUS1_S 24 131 132 #define I2C_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) 133 /* I2C_MST_ANA_CONF2 : R/W; bitpos: [23:0]; default: 0;*/ 134 /* description: .*/ 135 #define I2C_MST_ANA_CONF2 0x00FFFFFFU 136 #define I2C_MST_ANA_CONF2_M (I2C_MST_ANA_CONF2_V << I2C_MST_ANA_CONF2_S) 137 #define I2C_MST_ANA_CONF2_V 0x00FFFFFFU 138 #define I2C_MST_ANA_CONF2_S 0 139 /* I2C_MST_ANA_STATUS2 : RO; bitpos: [31:24]; default: 0;*/ 140 /* description: .*/ 141 #define I2C_MST_ANA_STATUS2 0x000000FFU 142 #define I2C_MST_ANA_STATUS2_M (I2C_MST_ANA_STATUS2_V << I2C_MST_ANA_STATUS2_S) 143 #define I2C_MST_ANA_STATUS2_V 0x000000FFU 144 #define I2C_MST_ANA_STATUS2_S 24 145 146 #define I2C_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) 147 /* I2C_MST_I2C0_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ 148 /* description: .*/ 149 #define I2C_MST_I2C0_SCL_PULSE_DUR 0x0000003FU 150 #define I2C_MST_I2C0_SCL_PULSE_DUR_M (I2C_MST_I2C0_SCL_PULSE_DUR_V << I2C_MST_I2C0_SCL_PULSE_DUR_S) 151 #define I2C_MST_I2C0_SCL_PULSE_DUR_V 0x0000003FU 152 #define I2C_MST_I2C0_SCL_PULSE_DUR_S 0 153 /* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ 154 /* description: .*/ 155 #define I2C_MST_I2C0_SDA_SIDE_GUARD 0x0000001FU 156 #define I2C_MST_I2C0_SDA_SIDE_GUARD_M (I2C_MST_I2C0_SDA_SIDE_GUARD_V << I2C_MST_I2C0_SDA_SIDE_GUARD_S) 157 #define I2C_MST_I2C0_SDA_SIDE_GUARD_V 0x0000001FU 158 #define I2C_MST_I2C0_SDA_SIDE_GUARD_S 6 159 160 #define I2C_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) 161 /* I2C_MST_I2C1_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ 162 /* description: .*/ 163 #define I2C_MST_I2C1_SCL_PULSE_DUR 0x0000003FU 164 #define I2C_MST_I2C1_SCL_PULSE_DUR_M (I2C_MST_I2C1_SCL_PULSE_DUR_V << I2C_MST_I2C1_SCL_PULSE_DUR_S) 165 #define I2C_MST_I2C1_SCL_PULSE_DUR_V 0x0000003FU 166 #define I2C_MST_I2C1_SCL_PULSE_DUR_S 0 167 /* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ 168 /* description: .*/ 169 #define I2C_MST_I2C1_SDA_SIDE_GUARD 0x0000001FU 170 #define I2C_MST_I2C1_SDA_SIDE_GUARD_M (I2C_MST_I2C1_SDA_SIDE_GUARD_V << I2C_MST_I2C1_SDA_SIDE_GUARD_S) 171 #define I2C_MST_I2C1_SDA_SIDE_GUARD_V 0x0000001FU 172 #define I2C_MST_I2C1_SDA_SIDE_GUARD_S 6 173 174 #define I2C_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2c) 175 /* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W; bitpos: [5:0]; default: 2;*/ 176 /* description: .*/ 177 #define I2C_MST_HW_I2C_SCL_PULSE_DUR 0x0000003FU 178 #define I2C_MST_HW_I2C_SCL_PULSE_DUR_M (I2C_MST_HW_I2C_SCL_PULSE_DUR_V << I2C_MST_HW_I2C_SCL_PULSE_DUR_S) 179 #define I2C_MST_HW_I2C_SCL_PULSE_DUR_V 0x0000003FU 180 #define I2C_MST_HW_I2C_SCL_PULSE_DUR_S 0 181 /* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W; bitpos: [10:6]; default: 1;*/ 182 /* description: .*/ 183 #define I2C_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001FU 184 #define I2C_MST_HW_I2C_SDA_SIDE_GUARD_M (I2C_MST_HW_I2C_SDA_SIDE_GUARD_V << I2C_MST_HW_I2C_SDA_SIDE_GUARD_S) 185 #define I2C_MST_HW_I2C_SDA_SIDE_GUARD_V 0x0000001FU 186 #define I2C_MST_HW_I2C_SDA_SIDE_GUARD_S 6 187 /* I2C_MST_ARBITER_DIS : R/W; bitpos: [11]; default: 0;*/ 188 /* description: .*/ 189 #define I2C_MST_ARBITER_DIS (BIT(11)) 190 #define I2C_MST_ARBITER_DIS_M (I2C_MST_ARBITER_DIS_V << I2C_MST_ARBITER_DIS_S) 191 #define I2C_MST_ARBITER_DIS_V 0x00000001U 192 #define I2C_MST_ARBITER_DIS_S 11 193 194 #define I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) 195 /* I2C_MST_NOUSE : R/W; bitpos: [31:0]; default: 0;*/ 196 /* description: .*/ 197 #define I2C_MST_NOUSE 0xFFFFFFFFU 198 #define I2C_MST_NOUSE_M (I2C_MST_NOUSE_V << I2C_MST_NOUSE_S) 199 #define I2C_MST_NOUSE_V 0xFFFFFFFFU 200 #define I2C_MST_NOUSE_S 0 201 202 #define I2C_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) 203 /* I2C_MST_DATE : R/W; bitpos: [27:0]; default: 35656448;*/ 204 /* description: .*/ 205 #define I2C_MST_DATE 0x0FFFFFFFU 206 #define I2C_MST_DATE_M (I2C_MST_DATE_V << I2C_MST_DATE_S) 207 #define I2C_MST_DATE_V 0x0FFFFFFFU 208 #define I2C_MST_DATE_S 0 209 /* I2C_MST_CLK_EN : R/W; bitpos: [28]; default: 0;*/ 210 /* description: .*/ 211 #define I2C_MST_CLK_EN (BIT(28)) 212 #define I2C_MST_CLK_EN_M (I2C_MST_CLK_EN_V << I2C_MST_CLK_EN_S) 213 #define I2C_MST_CLK_EN_V 0x00000001U 214 #define I2C_MST_CLK_EN_S 28 215 216 #ifdef __cplusplus 217 } 218 #endif 219
