1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_I2C_H__ 35 #define __HW_I2C_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the I2C register offsets. 40 // 41 //***************************************************************************** 42 #define I2C_O_MSA 0x00000000 43 #define I2C_O_MCS 0x00000004 44 #define I2C_O_MDR 0x00000008 45 #define I2C_O_MTPR 0x0000000C 46 #define I2C_O_MIMR 0x00000010 47 #define I2C_O_MRIS 0x00000014 48 #define I2C_O_MMIS 0x00000018 49 #define I2C_O_MICR 0x0000001C 50 #define I2C_O_MCR 0x00000020 51 #define I2C_O_MCLKOCNT 0x00000024 52 #define I2C_O_MBMON 0x0000002C 53 #define I2C_O_MBLEN 0x00000030 54 #define I2C_O_MBCNT 0x00000034 55 #define I2C_O_SOAR 0x00000800 56 #define I2C_O_SCSR 0x00000804 57 #define I2C_O_SDR 0x00000808 58 #define I2C_O_SIMR 0x0000080C 59 #define I2C_O_SRIS 0x00000810 60 #define I2C_O_SMIS 0x00000814 61 #define I2C_O_SICR 0x00000818 62 #define I2C_O_SOAR2 0x0000081C 63 #define I2C_O_SACKCTL 0x00000820 64 #define I2C_O_FIFODATA 0x00000F00 65 #define I2C_O_FIFOCTL 0x00000F04 66 #define I2C_O_FIFOSTATUS 0x00000F08 67 #define I2C_O_OBSMUXSEL0 0x00000F80 68 #define I2C_O_OBSMUXSEL1 0x00000F84 69 #define I2C_O_MUXROUTE 0x00000F88 70 #define I2C_O_PV 0x00000FB0 71 #define I2C_O_PP 0x00000FC0 72 #define I2C_O_PC 0x00000FC4 73 #define I2C_O_CC 0x00000FC8 74 75 76 77 //****************************************************************************** 78 // 79 // The following are defines for the bit fields in the I2C_O_MSA register. 80 // 81 //****************************************************************************** 82 #define I2C_MSA_SA_M 0x000000FE // I2C Slave Address 83 #define I2C_MSA_SA_S 1 84 #define I2C_MSA_RS 0x00000001 // Receive not send 85 //****************************************************************************** 86 // 87 // The following are defines for the bit fields in the I2C_O_MCS register. 88 // 89 //****************************************************************************** 90 #define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status 91 #define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status 92 #define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error 93 #define I2C_MCS_BUSBSY 0x00000040 // Bus Busy 94 #define I2C_MCS_IDLE 0x00000020 // I2C Idle 95 #define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost 96 #define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable 97 #define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address 98 #define I2C_MCS_ERROR 0x00000002 // Error 99 #define I2C_MCS_BUSY 0x00000001 // I2C Busy 100 //****************************************************************************** 101 // 102 // The following are defines for the bit fields in the I2C_O_MDR register. 103 // 104 //****************************************************************************** 105 #define I2C_MDR_DATA_M 0x000000FF // Data Transferred 106 #define I2C_MDR_DATA_S 0 107 //****************************************************************************** 108 // 109 // The following are defines for the bit fields in the I2C_O_MTPR register. 110 // 111 //****************************************************************************** 112 #define I2C_MTPR_HS 0x00000080 // High-Speed Enable 113 #define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period 114 #define I2C_MTPR_TPR_S 0 115 //****************************************************************************** 116 // 117 // The following are defines for the bit fields in the I2C_O_MIMR register. 118 // 119 //****************************************************************************** 120 #define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask 121 #define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt 122 // Mask 123 #define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt 124 // Mask 125 #define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt 126 // Mask 127 #define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask 128 #define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask 129 #define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask 130 #define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask 131 #define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask 132 #define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask 133 #define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask 134 #define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask 135 //****************************************************************************** 136 // 137 // The following are defines for the bit fields in the I2C_O_MRIS register. 138 // 139 //****************************************************************************** 140 #define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt 141 // Status 142 #define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw 143 // Interrupt Status 144 #define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw 145 // Interrupt Status 146 #define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt 147 // Status 148 #define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt 149 // Status 150 #define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt 151 // Status 152 #define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt 153 // Status 154 #define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt 155 // Status 156 #define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt 157 // Status 158 #define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status 159 #define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt 160 // Status 161 #define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status 162 //****************************************************************************** 163 // 164 // The following are defines for the bit fields in the I2C_O_MMIS register. 165 // 166 //****************************************************************************** 167 #define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask 168 #define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt 169 // Mask 170 #define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt 171 // Mask 172 #define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask 173 #define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask 174 #define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask 175 #define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask 176 #define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask 177 #define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status 178 #define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status 179 #define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt 180 // Status 181 #define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status 182 //****************************************************************************** 183 // 184 // The following are defines for the bit fields in the I2C_O_MICR register. 185 // 186 //****************************************************************************** 187 #define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt 188 // Clear 189 #define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt 190 // Clear 191 #define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt 192 // Clear 193 #define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt 194 // Clear 195 #define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear 196 #define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear 197 #define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear 198 #define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt 199 // Clear 200 #define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear 201 #define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear 202 #define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear 203 #define I2C_MICR_IC 0x00000001 // Master Interrupt Clear 204 //****************************************************************************** 205 // 206 // The following are defines for the bit fields in the I2C_O_MCR register. 207 // 208 //****************************************************************************** 209 #define I2C_MCR_MMD 0x00000040 // Multi-master Disable 210 #define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable 211 #define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable 212 #define I2C_MCR_LPBK 0x00000001 // I2C Loopback 213 //****************************************************************************** 214 // 215 // The following are defines for the bit fields in the I2C_O_MCLKOCNT register. 216 // 217 //****************************************************************************** 218 #define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count 219 #define I2C_MCLKOCNT_CNTL_S 0 220 //****************************************************************************** 221 // 222 // The following are defines for the bit fields in the I2C_O_MBMON register. 223 // 224 //****************************************************************************** 225 #define I2C_MBMON_SDA 0x00000002 // I2C SDA Status 226 #define I2C_MBMON_SCL 0x00000001 // I2C SCL Status 227 //****************************************************************************** 228 // 229 // The following are defines for the bit fields in the I2C_O_MBLEN register. 230 // 231 //****************************************************************************** 232 #define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length 233 #define I2C_MBLEN_CNTL_S 0 234 //****************************************************************************** 235 // 236 // The following are defines for the bit fields in the I2C_O_MBCNT register. 237 // 238 //****************************************************************************** 239 #define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count 240 #define I2C_MBCNT_CNTL_S 0 241 //****************************************************************************** 242 // 243 // The following are defines for the bit fields in the I2C_O_SOAR register. 244 // 245 //****************************************************************************** 246 #define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address 247 #define I2C_SOAR_OAR_S 0 248 //****************************************************************************** 249 // 250 // The following are defines for the bit fields in the I2C_O_SCSR register. 251 // 252 //****************************************************************************** 253 #define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status 254 #define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status 255 #define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write 256 #define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status 257 #define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched 258 #define I2C_SCSR_FBR 0x00000004 // First Byte Received 259 #define I2C_SCSR_TREQ 0x00000002 // Transmit Request 260 #define I2C_SCSR_DA 0x00000001 // Device Active 261 //****************************************************************************** 262 // 263 // The following are defines for the bit fields in the I2C_O_SDR register. 264 // 265 //****************************************************************************** 266 #define I2C_SDR_DATA_M 0x000000FF // Data for Transfer 267 #define I2C_SDR_DATA_S 0 268 //****************************************************************************** 269 // 270 // The following are defines for the bit fields in the I2C_O_SIMR register. 271 // 272 //****************************************************************************** 273 #define I2C_SIMR_IM 0x00000100 // Interrupt Mask 274 #define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt 275 // Mask 276 #define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt 277 // Mask 278 #define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt 279 // Mask 280 #define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask 281 #define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask 282 #define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask 283 #define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask 284 #define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask 285 //****************************************************************************** 286 // 287 // The following are defines for the bit fields in the I2C_O_SRIS register. 288 // 289 //****************************************************************************** 290 #define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status 291 #define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw 292 // Interrupt Status 293 #define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw 294 // Interrupt Status 295 #define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt 296 // Status 297 #define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt 298 // Status 299 #define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status 300 #define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt 301 // Status 302 #define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt 303 // Status 304 #define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status 305 //****************************************************************************** 306 // 307 // The following are defines for the bit fields in the I2C_O_SMIS register. 308 // 309 //****************************************************************************** 310 #define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask 311 #define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt 312 // Mask 313 #define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt 314 // Mask 315 #define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt 316 // Mask 317 #define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt 318 // Status 319 #define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt 320 // Status 321 #define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt 322 // Status 323 #define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt 324 // Status 325 #define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status 326 //****************************************************************************** 327 // 328 // The following are defines for the bit fields in the I2C_O_SICR register. 329 // 330 //****************************************************************************** 331 #define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask 332 #define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt 333 // Mask 334 #define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask 335 #define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask 336 #define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear 337 #define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear 338 #define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear 339 #define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear 340 #define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear 341 //****************************************************************************** 342 // 343 // The following are defines for the bit fields in the I2C_O_SOAR2 register. 344 // 345 //****************************************************************************** 346 #define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable 347 #define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 348 #define I2C_SOAR2_OAR2_S 0 349 //****************************************************************************** 350 // 351 // The following are defines for the bit fields in the I2C_O_SACKCTL register. 352 // 353 //****************************************************************************** 354 #define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value 355 #define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable 356 //****************************************************************************** 357 // 358 // The following are defines for the bit fields in the I2C_O_FIFODATA register. 359 // 360 //****************************************************************************** 361 #define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte 362 #define I2C_FIFODATA_DATA_S 0 363 //****************************************************************************** 364 // 365 // The following are defines for the bit fields in the I2C_O_FIFOCTL register. 366 // 367 //****************************************************************************** 368 #define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment 369 #define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush 370 #define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable 371 #define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger 372 #define I2C_FIFOCTL_RXTRIG_S 16 373 #define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment 374 #define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush 375 #define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable 376 #define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger 377 #define I2C_FIFOCTL_TXTRIG_S 0 378 //****************************************************************************** 379 // 380 // The following are defines for the bit fields in the I2C_O_FIFOSTATUS register. 381 // 382 //****************************************************************************** 383 #define I2C_FIFOSTATUS_RXABVTRIG \ 384 0x00040000 // RX FIFO Above Trigger Level 385 386 #define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full 387 #define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty 388 #define I2C_FIFOSTATUS_TXBLWTRIG \ 389 0x00000004 // TX FIFO Below Trigger Level 390 391 #define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full 392 #define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty 393 //****************************************************************************** 394 // 395 // The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register. 396 // 397 //****************************************************************************** 398 #define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3 399 #define I2C_OBSMUXSEL0_LN3_S 24 400 #define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2 401 #define I2C_OBSMUXSEL0_LN2_S 16 402 #define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1 403 #define I2C_OBSMUXSEL0_LN1_S 8 404 #define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0 405 #define I2C_OBSMUXSEL0_LN0_S 0 406 //****************************************************************************** 407 // 408 // The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register. 409 // 410 //****************************************************************************** 411 #define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7 412 #define I2C_OBSMUXSEL1_LN7_S 24 413 #define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6 414 #define I2C_OBSMUXSEL1_LN6_S 16 415 #define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5 416 #define I2C_OBSMUXSEL1_LN5_S 8 417 #define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4 418 #define I2C_OBSMUXSEL1_LN4_S 0 419 //****************************************************************************** 420 // 421 // The following are defines for the bit fields in the I2C_O_MUXROUTE register. 422 // 423 //****************************************************************************** 424 #define I2C_MUXROUTE_LN7ROUTE_M \ 425 0x70000000 // Lane 7 output is routed to the 426 // lane pointed to by the offset in 427 // this bit field 428 429 #define I2C_MUXROUTE_LN7ROUTE_S 28 430 #define I2C_MUXROUTE_LN6ROUTE_M \ 431 0x07000000 // Lane 6 output is routed to the 432 // lane pointed to by the offset in 433 // this bit field 434 435 #define I2C_MUXROUTE_LN6ROUTE_S 24 436 #define I2C_MUXROUTE_LN5ROUTE_M \ 437 0x00700000 // Lane 5 output is routed to the 438 // lane pointed to by the offset in 439 // this bit field 440 441 #define I2C_MUXROUTE_LN5ROUTE_S 20 442 #define I2C_MUXROUTE_LN4ROUTE_M \ 443 0x00070000 // Lane 4 output is routed to the 444 // lane pointed to by the offset in 445 // this bit field 446 447 #define I2C_MUXROUTE_LN4ROUTE_S 16 448 #define I2C_MUXROUTE_LN3ROUTE_M \ 449 0x00007000 // Lane 3 output is routed to the 450 // lane pointed to by the offset in 451 // this bit field 452 453 #define I2C_MUXROUTE_LN3ROUTE_S 12 454 #define I2C_MUXROUTE_LN2ROUTE_M \ 455 0x00000700 // Lane 2 output is routed to the 456 // lane pointed to by the offset in 457 // this bit field 458 459 #define I2C_MUXROUTE_LN2ROUTE_S 8 460 #define I2C_MUXROUTE_LN1ROUTE_M \ 461 0x00000070 // Lane 1 output is routed to the 462 // lane pointed to by the offset in 463 // this bit field 464 465 #define I2C_MUXROUTE_LN1ROUTE_S 4 466 #define I2C_MUXROUTE_LN0ROUTE_M \ 467 0x00000007 // Lane 0 output is routed to the 468 // lane pointed to by the offset in 469 // this bit field 470 471 #define I2C_MUXROUTE_LN0ROUTE_S 0 472 //****************************************************************************** 473 // 474 // The following are defines for the bit fields in the I2C_O_PV register. 475 // 476 //****************************************************************************** 477 #define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision 478 #define I2C_PV_MAJOR_S 8 479 #define I2C_PV_MINOR_M 0x000000FF // Minor Revision 480 #define I2C_PV_MINOR_S 0 481 //****************************************************************************** 482 // 483 // The following are defines for the bit fields in the I2C_O_PP register. 484 // 485 //****************************************************************************** 486 #define I2C_PP_HS 0x00000001 // High-Speed Capable 487 //****************************************************************************** 488 // 489 // The following are defines for the bit fields in the I2C_O_PC register. 490 // 491 //****************************************************************************** 492 #define I2C_PC_HS 0x00000001 // High-Speed Capable 493 //****************************************************************************** 494 // 495 // The following are defines for the bit fields in the I2C_O_CC register. 496 // 497 //****************************************************************************** 498 499 500 501 #endif // __HW_I2C_H__ 502
