1 /****************************************************************************//**
2 * @file i2c.h
3 * @version V1.00
4 * @brief M460 series I2C driver header file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __I2C_H__
10 #define __I2C_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup I2C_Driver I2C Driver
23 @{
24 */
25
26 /** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
27 @{
28 */
29
30 /*---------------------------------------------------------------------------------------------------------*/
31 /* I2C_CTL constant definitions. */
32 /*---------------------------------------------------------------------------------------------------------*/
33 #define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits \hideinitializer */
34 #define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits \hideinitializer */
35 #define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits \hideinitializer */
36 #define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits \hideinitializer */
37 #define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit \hideinitializer */
38 #define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits \hideinitializer */
39 #define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit \hideinitializer */
40 #define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit \hideinitializer */
41 #define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit \hideinitializer */
42
43 /*---------------------------------------------------------------------------------------------------------*/
44 /* I2C GCMode constant definitions. */
45 /*---------------------------------------------------------------------------------------------------------*/
46 #define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode \hideinitializer */
47 #define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode \hideinitializer */
48
49 /*---------------------------------------------------------------------------------------------------------*/
50 /* I2C SMBUS constant definitions. */
51 /*---------------------------------------------------------------------------------------------------------*/
52 #define I2C_SMBH_ENABLE 1 /*!< Enable SMBus Host Mode enable \hideinitializer */
53 #define I2C_SMBD_ENABLE 0 /*!< Enable SMBus Device Mode enable \hideinitializer */
54 #define I2C_PECTX_ENABLE 1 /*!< Enable SMBus Packet Error Check Transmit function \hideinitializer */
55 #define I2C_PECTX_DISABLE 0 /*!< Disable SMBus Packet Error Check Transmit function \hideinitializer */
56
57 /*---------------------------------------------------------------------------------------------------------*/
58 /* I2C Define Error Code */
59 /*---------------------------------------------------------------------------------------------------------*/
60 #define I2C_TIMEOUT SystemCoreClock /*!< I2C time-out counter (1 second time-out) \hideinitializer */
61 #define I2C_OK ( 0L) /*!< I2C operation OK \hideinitializer */
62 #define I2C_ERR_FAIL (-1L) /*!< I2C operation failed \hideinitializer */
63 #define I2C_ERR_TIMEOUT (-2L) /*!< I2C operation abort due to timeout error \hideinitializer */
64
65 /*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
66
67 extern int32_t g_I2C_i32ErrCode;
68
69 /** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
70 @{
71 */
72 /**
73 * @brief The macro is used to set I2C bus condition at One Time
74 *
75 * @param[in] i2c Specify I2C port
76 * @param[in] u8Ctrl A byte writes to I2C control register
77 *
78 * @return None
79 *
80 * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
81 * \hideinitializer
82 */
83 #define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3c) | (u8Ctrl))
84
85 /**
86 * @brief The macro is used to set START condition of I2C Bus
87 *
88 * @param[in] i2c Specify I2C port
89 *
90 * @return None
91 *
92 * @details Set the I2C bus START condition in I2C_CTL register.
93 * \hideinitializer
94 */
95 #define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 & ~I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk)
96
97 /**
98 * @brief The macro is used to wait I2C bus status get ready
99 *
100 * @param[in] i2c Specify I2C port
101 *
102 * @return None
103 *
104 * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
105 * \hideinitializer
106 */
107 #define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk))
108
109 /**
110 * @brief The macro is used to Read I2C Bus Data Register
111 *
112 * @param[in] i2c Specify I2C port
113 *
114 * @return A byte of I2C data register
115 *
116 * @details I2C controller read data from bus and save it in I2CDAT register.
117 * \hideinitializer
118 */
119 #define I2C_GET_DATA(i2c) ((i2c)->DAT)
120
121 /**
122 * @brief Write a Data to I2C Data Register
123 *
124 * @param[in] i2c Specify I2C port
125 * @param[in] u8Data A byte that writes to data register
126 *
127 * @return None
128 *
129 * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
130 * \hideinitializer
131 */
132 #define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
133
134 /**
135 * @brief Get I2C Bus status code
136 *
137 * @param[in] i2c Specify I2C port
138 *
139 * @return I2C status code
140 *
141 * @details To get this status code to monitor I2C bus event.
142 * \hideinitializer
143 */
144 #define I2C_GET_STATUS(i2c) ((i2c)->STATUS0)
145
146 /**
147 * @brief Get Time-out flag from I2C Bus
148 *
149 * @param[in] i2c Specify I2C port
150 *
151 * @retval 0 I2C Bus time-out is not happened
152 * @retval 1 I2C Bus time-out is happened
153 *
154 * @details When I2C bus occurs time-out event, the time-out flag will be set.
155 * \hideinitializer
156 */
157 #define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
158
159 /**
160 * @brief To get wake-up flag from I2C Bus
161 *
162 * @param[in] i2c Specify I2C port
163 *
164 * @retval 0 Chip is not woken-up from power-down mode
165 * @retval 1 Chip is woken-up from power-down mode
166 *
167 * @details I2C bus occurs wake-up event, wake-up flag will be set.
168 * \hideinitializer
169 */
170 #define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
171
172 /**
173 * @brief To clear wake-up flag
174 *
175 * @param[in] i2c Specify I2C port
176 *
177 * @return None
178 *
179 * @details If wake-up flag is set, use this macro to clear it.
180 * \hideinitializer
181 */
182 #define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
183
184 /**
185 * @brief To get SMBus Status
186 *
187 * @param[in] i2c Specify I2C port
188 *
189 * @return SMBus status
190 *
191 * @details To get the Bus Management status of I2C_BUSSTS register
192 * \hideinitializer
193 *
194 */
195 #define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
196
197 /**
198 * @brief Get SMBus CRC value
199 *
200 * @param[in] i2c Specify I2C port
201 *
202 * @return Packet error check byte value
203 *
204 * @details The CRC check value after a transmission or a reception by count by using CRC8
205 * \hideinitializer
206 */
207 #define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
208
209 /**
210 * @brief Set SMBus Bytes number of Transmission or reception
211 *
212 * @param[in] i2c Specify I2C port
213 * @param[in] u32PktSize Transmit / Receive bytes
214 *
215 * @return None
216 *
217 * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
218 * \hideinitializer
219 */
220 #define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
221
222 /**
223 * @brief Enable SMBus Alert function
224 *
225 * @param[in] i2c Specify I2C port
226 *
227 * @return None
228 *
229 * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
230 * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
231 * \hideinitializer
232 */
233 #define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
234
235 /**
236 * @brief Disable SMBus Alert pin function
237 *
238 * @param[in] i2c Specify I2C port
239 *
240 * @return None
241 *
242 * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
243 * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
244 * \hideinitializer
245 */
246 #define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
247
248 /**
249 * @brief Set SMBus SUSCON pin is output mode
250 *
251 * @param[in] i2c Specify I2C port
252 *
253 * @return None
254 *
255 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
256 *
257 * \hideinitializer
258 */
259 #define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
260
261 /**
262 * @brief Set SMBus SUSCON pin is input mode
263 *
264 * @param[in] i2c Specify I2C port
265 *
266 * @return None
267 *
268 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
269 *
270 * \hideinitializer
271 */
272 #define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
273
274 /**
275 * @brief Set SMBus SUSCON pin output high state
276 *
277 * @param[in] i2c Specify I2C port
278 *
279 * @return None
280 *
281 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
282 * \hideinitializer
283 */
284 #define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
285
286
287 /**
288 * @brief Set SMBus SUSCON pin output low state
289 *
290 * @param[in] i2c Specify I2C port
291 *
292 * @return None
293 *
294 * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
295 * \hideinitializer
296 */
297 #define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
298
299 /**
300 * @brief Enable SMBus Acknowledge control by manual
301 *
302 * @param[in] i2c Specify I2C port
303 *
304 * @return None
305 *
306 * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
307 * \hideinitializer
308 */
309 #define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
310
311 /**
312 * @brief Disable SMBus Acknowledge control by manual
313 *
314 * @param[in] i2c Specify I2C port
315 *
316 * @return None
317 *
318 * @details Disable acknowledge response control by user.
319 * \hideinitializer
320 */
321 #define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
322
323 /**
324 * @brief Enable SMBus Acknowledge manual interrupt
325 *
326 * @param[in] i2c Specify I2C port
327 *
328 * @return None
329 *
330 * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
331 * \hideinitializer
332 */
333 #define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
334
335 /**
336 * @brief Disable SMBus Acknowledge manual interrupt
337 *
338 * @param[in] i2c Specify I2C port
339 *
340 * @return None
341 *
342 * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
343 * \hideinitializer
344 */
345 #define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
346
347 /**
348 * @brief Enable SMBus PEC clear at REPEAT START
349 *
350 * @param[in] i2c Specify I2C port
351 *
352 * @return None
353 *
354 * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.
355 * \hideinitializer
356 */
357 #define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
358
359 /**
360 * @brief Disable SMBus PEC clear at Repeat START
361 *
362 * @param[in] i2c Specify I2C port
363 *
364 * @return None
365 *
366 * @details This function is used to disable the condition of Repeat START can clear the PEC calculation.
367 * \hideinitializer
368 */
369 #define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
370
371 /**
372 * @brief Enable RX PDMA function.
373 * @param[in] i2c The pointer of the specified I2C module.
374 * @return None.
375 * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
376 * \hideinitializer
377 */
378 #define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
379
380 /**
381 * @brief Enable TX PDMA function.
382 * @param[in] i2c The pointer of the specified I2C module.
383 * @return None.
384 * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
385 * \hideinitializer
386 */
387 #define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
388
389 /**
390 * @brief Disable RX PDMA transfer.
391 * @param[in] i2c The pointer of the specified I2C module.
392 * @return None.
393 * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
394 * \hideinitializer
395 */
396 #define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
397
398 /**
399 * @brief Disable TX PDMA transfer.
400 * @param[in] i2c The pointer of the specified I2C module.
401 * @return None.
402 * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
403 * \hideinitializer
404 */
405 #define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
406
407 /**
408 * @brief Enable PDMA stretch function.
409 * @param[in] i2c The pointer of the specified I2C module.
410 * @return None.
411 * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
412 * \hideinitializer
413 */
414 #define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
415
416 /**
417 * @brief Disable PDMA stretch function.
418 * @param[in] i2c The pointer of the specified I2C module.
419 * @return None.
420 * @details I2C will send STOP after PDMA transfers done automatically.
421 * \hideinitializer
422 */
423 #define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
424
425 /**
426 * @brief Reset PDMA function.
427 * @param[in] i2c The pointer of the specified I2C module.
428 * @return None.
429 * @details I2C PDMA engine will be reset after this function is called.
430 * \hideinitializer
431 */
432 #define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
433
434 /*---------------------------------------------------------------------------------------------------------*/
435 /* inline functions */
436 /*---------------------------------------------------------------------------------------------------------*/
437
438 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
439 __STATIC_INLINE void I2C_STOP(I2C_T *i2c);
440
441 /**
442 * @brief The macro is used to set STOP condition of I2C Bus
443 *
444 * @param[in] i2c Specify I2C port
445 *
446 * @return None
447 *
448 * @details Set the I2C bus STOP condition in I2C_CTL register.
449 */
I2C_STOP(I2C_T * i2c)450 __STATIC_INLINE void I2C_STOP(I2C_T *i2c)
451 {
452 uint32_t u32TimeOutCount = I2C_TIMEOUT;
453
454 (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk);
455 while(i2c->CTL0 & I2C_CTL0_STO_Msk)
456 {
457 if(--u32TimeOutCount == 0) break;
458 }
459 }
460
461 void I2C_ClearTimeoutFlag(I2C_T *i2c);
462 void I2C_Close(I2C_T *i2c);
463 void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
464 void I2C_DisableInt(I2C_T *i2c);
465 void I2C_EnableInt(I2C_T *i2c);
466 uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
467 uint32_t I2C_GetIntFlag(I2C_T *i2c);
468 uint32_t I2C_GetStatus(I2C_T *i2c);
469 uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
470 uint8_t I2C_GetData(I2C_T *i2c);
471 void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode);
472 void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask);
473 uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
474 void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
475 void I2C_DisableTimeout(I2C_T *i2c);
476 void I2C_EnableWakeup(I2C_T *i2c);
477 void I2C_DisableWakeup(I2C_T *i2c);
478 void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
479 void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag);
480 uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data);
481 uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen);
482 uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data);
483 uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen);
484 uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data);
485 uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen);
486 uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
487 uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen);
488 uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
489 uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen);
490 uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
491 uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen);
492 uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
493 void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
494 void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
495 void I2C_SMBusClose(I2C_T *i2c);
496 void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
497 uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
498 void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
499 void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
500 void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
501
502 /*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
503
504 /*@}*/ /* end of group I2C_Driver */
505
506 /*@}*/ /* end of group Standard_Driver */
507
508 #ifdef __cplusplus
509 }
510 #endif
511
512 #endif
513
514 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
515
