1 /* dw_i2c.h - header for Design Ware I2C operations */ 2 3 /* 4 * Copyright (c) 2015 Intel Corporation 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 #ifndef ZEPHYR_DRIVERS_I2C_I2C_DW_H_ 9 #define ZEPHYR_DRIVERS_I2C_I2C_DW_H_ 10 11 #include <zephyr/drivers/i2c.h> 12 #include <stdbool.h> 13 14 #define DT_DRV_COMPAT snps_designware_i2c 15 16 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) 17 BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "DW I2C in DT needs CONFIG_PCIE"); 18 #include <zephyr/drivers/pcie/pcie.h> 19 #endif 20 21 #if defined(CONFIG_RESET) 22 #include <zephyr/drivers/reset.h> 23 #endif 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 #define I2C_DW_MAGIC_KEY 0x44570140 30 31 typedef void (*i2c_isr_cb_t)(const struct device *port); 32 33 #define IC_ACTIVITY (1 << 0) 34 #define IC_ENABLE_BIT (1 << 0) 35 36 /* dev->state values from IC_DATA_CMD Data transfer mode settings (bit 8) */ 37 #define I2C_DW_STATE_READY (0) 38 #define I2C_DW_CMD_SEND (1 << 0) 39 #define I2C_DW_CMD_RECV (1 << 1) 40 #define I2C_DW_CMD_ERROR (1 << 2) 41 #define I2C_DW_BUSY (1 << 3) 42 43 #define DW_ENABLE_TX_INT_I2C_MASTER \ 44 (DW_INTR_STAT_TX_OVER | DW_INTR_STAT_TX_EMPTY | DW_INTR_STAT_TX_ABRT | \ 45 DW_INTR_STAT_STOP_DET) 46 #define DW_ENABLE_RX_INT_I2C_MASTER \ 47 (DW_INTR_STAT_RX_UNDER | DW_INTR_STAT_RX_OVER | DW_INTR_STAT_RX_FULL | \ 48 DW_INTR_STAT_STOP_DET) 49 50 #define DW_ENABLE_TX_INT_I2C_SLAVE \ 51 (DW_INTR_STAT_RD_REQ | DW_INTR_STAT_TX_ABRT | DW_INTR_STAT_STOP_DET) 52 #define DW_ENABLE_RX_INT_I2C_SLAVE (DW_INTR_STAT_RX_FULL | DW_INTR_STAT_STOP_DET) 53 54 #define DW_DISABLE_ALL_I2C_INT 0x00000000 55 56 /* IC_CON Low count and high count default values */ 57 /* TODO verify values for high speed */ 58 #define I2C_STD_HCNT (CONFIG_I2C_DW_CLOCK_SPEED * 4) 59 #define I2C_STD_LCNT (CONFIG_I2C_DW_CLOCK_SPEED * 5) 60 #define I2C_FS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8) 61 #define I2C_FS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8) 62 #define I2C_FSP_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 2) / 8) 63 #define I2C_FSP_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 2) / 8) 64 #define I2C_HS_HCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 6) / 8) 65 #define I2C_HS_LCNT ((CONFIG_I2C_DW_CLOCK_SPEED * 7) / 8) 66 67 /* 68 * DesignWare speed values don't directly translate from the Zephyr speed 69 * selections in include/i2c.h so here we do a little translation 70 */ 71 #define I2C_DW_SPEED_STANDARD 0x1 72 #define I2C_DW_SPEED_FAST 0x2 73 #define I2C_DW_SPEED_FAST_PLUS 0x2 74 #define I2C_DW_SPEED_HIGH 0x3 75 76 /* 77 * These values have been randomly selected. It would be good to test different 78 * watermark levels for performance capabilities 79 */ 80 #define I2C_DW_TX_WATERMARK 2 81 #define I2C_DW_RX_WATERMARK 7 82 83 struct i2c_dw_rom_config { 84 DEVICE_MMIO_ROM; 85 i2c_isr_cb_t config_func; 86 uint32_t bitrate; 87 int16_t lcnt_offset; 88 int16_t hcnt_offset; 89 90 #if defined(CONFIG_PINCTRL) 91 const struct pinctrl_dev_config *pcfg; 92 #endif 93 #if defined(CONFIG_RESET) 94 const struct reset_dt_spec reset; 95 #endif 96 97 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) 98 struct pcie_dev *pcie; 99 #endif /* I2C_DW_PCIE_ENABLED */ 100 101 #ifdef CONFIG_I2C_DW_LPSS_DMA 102 const struct device *dma_dev; 103 #endif 104 }; 105 106 struct i2c_dw_dev_config { 107 DEVICE_MMIO_RAM; 108 struct k_sem device_sync_sem; 109 struct k_mutex bus_mutex; 110 uint32_t app_config; 111 112 uint8_t *xfr_buf; 113 uint32_t xfr_len; 114 uint32_t rx_pending; 115 116 uint16_t hcnt; 117 uint16_t lcnt; 118 119 volatile uint8_t state; /* last direction of transfer */ 120 uint8_t request_bytes; 121 uint8_t xfr_flags; 122 bool support_hs_mode; 123 #ifdef CONFIG_I2C_DW_LPSS_DMA 124 uintptr_t phy_addr; 125 uintptr_t base_addr; 126 /* For dma transfer */ 127 bool xfr_status; 128 #endif 129 130 struct i2c_target_config *slave_cfg; 131 }; 132 133 #define Z_REG_READ(__sz) sys_read##__sz 134 #define Z_REG_WRITE(__sz) sys_write##__sz 135 #define Z_REG_SET_BIT sys_set_bit 136 #define Z_REG_CLEAR_BIT sys_clear_bit 137 #define Z_REG_TEST_BIT sys_test_bit 138 139 #define DEFINE_MM_REG_READ(__reg, __off, __sz) \ 140 static inline uint32_t read_##__reg(uint32_t addr) \ 141 { \ 142 return Z_REG_READ(__sz)(addr + __off); \ 143 } 144 #define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \ 145 static inline void write_##__reg(uint32_t data, uint32_t addr) \ 146 { \ 147 Z_REG_WRITE(__sz)(data, addr + __off); \ 148 } 149 150 #define DEFINE_SET_BIT_OP(__reg_bit, __reg_off, __bit) \ 151 static inline void set_bit_##__reg_bit(uint32_t addr) \ 152 { \ 153 Z_REG_SET_BIT(addr + __reg_off, __bit); \ 154 } 155 156 #define DEFINE_CLEAR_BIT_OP(__reg_bit, __reg_off, __bit) \ 157 static inline void clear_bit_##__reg_bit(uint32_t addr) \ 158 { \ 159 Z_REG_CLEAR_BIT(addr + __reg_off, __bit); \ 160 } 161 162 #define DEFINE_TEST_BIT_OP(__reg_bit, __reg_off, __bit) \ 163 static inline int test_bit_##__reg_bit(uint32_t addr) \ 164 { \ 165 return Z_REG_TEST_BIT(addr + __reg_off, __bit); \ 166 } 167 168 #ifdef __cplusplus 169 } 170 #endif 171 172 #endif /* ZEPHYR_DRIVERS_I2C_I2C_DW_H_ */ 173
