1 /**************************************************************************//** 2 * @file i2c_reg.h 3 * @version V1.00 4 * @brief I2C register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __I2C_REG_H__ 10 #define __I2C_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup I2C Inter-IC Bus Controller(I2C) 23 Memory Mapped Structure for I2C Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var I2C_T::CTL0 32 * Offset: 0x00 I2C Control Register 0 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[2] |AA |Assert Acknowledge Control 37 * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter 38 * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line 39 * |[3] |SI |I2C Interrupt Flag 40 * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware 41 * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested 42 * | | |SI must be cleared by software 43 * | | |Clear SI by writing 1 to this bit. 44 * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. 45 * |[4] |STO |I2C STOP Control 46 * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected 47 * | | |This bit will be cleared by hardware automatically. 48 * |[5] |STA |I2C START Control 49 * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 50 * |[6] |I2CEN |I2C Controller Enable Bit 51 * | | |Set to enable I2C serial function controller 52 * | | |When I2CEN=1 the I2C serial function enable 53 * | | |The multi-function pin function must set to SDA, and SCL of I2C function first. 54 * | | |0 = I2C controller Disabled. 55 * | | |1 = I2C controller Enabled. 56 * |[7] |INTEN |Enable Interrupt 57 * | | |0 = I2C interrupt Disabled. 58 * | | |1 = I2C interrupt Enabled. 59 * @var I2C_T::ADDR0 60 * Offset: 0x04 I2C Slave Address Register0 61 * --------------------------------------------------------------------------------------------------- 62 * |Bits |Field |Descriptions 63 * | :----: | :----: | :---- | 64 * |[0] |GC |General Call Function 65 * | | |0 = General Call Function Disabled. 66 * | | |1 = General Call Function Enabled. 67 * |[10:1] |ADDR |I2C Address 68 * | | |The content of this register is irrelevant when I2C is in Master mode 69 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 70 * | | |The I2C hardware will react if either of the address is matched. 71 * | | |Note: When software set 10'h000, the address can not be used. 72 * @var I2C_T::DAT 73 * Offset: 0x08 I2C Data Register 74 * --------------------------------------------------------------------------------------------------- 75 * |Bits |Field |Descriptions 76 * | :----: | :----: | :---- | 77 * |[7:0] |DAT |I2C Data 78 * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. 79 * @var I2C_T::STATUS0 80 * Offset: 0x0C I2C Status Register 0 81 * --------------------------------------------------------------------------------------------------- 82 * |Bits |Field |Descriptions 83 * | :----: | :----: | :---- | 84 * |[7:0] |STATUS |I2C Status 85 * | | |The three least significant bits are always 0 86 * | | |The five most significant bits contain the status code 87 * | | |There are 28 possible status codes 88 * | | |When the content of I2C_STATUS is F8H, no serial interrupt is requested 89 * | | |Others I2C_STATUS values correspond to defined I2C states 90 * | | |When each of these states is entered, a status interrupt is requested (SI = 1) 91 * | | |A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software 92 * | | |In addition, states 00H stands for a Bus Error 93 * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame 94 * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. 95 * @var I2C_T::CLKDIV 96 * Offset: 0x10 I2C Clock Divided Register 97 * --------------------------------------------------------------------------------------------------- 98 * |Bits |Field |Descriptions 99 * | :----: | :----: | :---- | 100 * |[9:0] |DIVIDER |I2C Clock Divided 101 * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)). 102 * | | |Note: The minimum value of I2C_CLKDIV is 4. 103 * @var I2C_T::TOCTL 104 * Offset: 0x14 I2C Time-out Control Register 105 * --------------------------------------------------------------------------------------------------- 106 * |Bits |Field |Descriptions 107 * | :----: | :----: | :---- | 108 * |[0] |TOIF |Time-out Flag 109 * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. 110 * | | |Note: Software can write 1 to clear this bit. 111 * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4 112 * | | |When Enabled, The time-out period is extend 4 times. 113 * | | |0 = Time-out period is extend 4 times Disabled. 114 * | | |1 = Time-out period is extend 4 times Enabled. 115 * |[2] |TOCEN |Time-out Counter Enable Bit 116 * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear 117 * | | |Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared. 118 * | | |0 = Time-out counter Disabled. 119 * | | |1 = Time-out counter Enabled. 120 * @var I2C_T::ADDR1 121 * Offset: 0x18 I2C Slave Address Register1 122 * --------------------------------------------------------------------------------------------------- 123 * |Bits |Field |Descriptions 124 * | :----: | :----: | :---- | 125 * |[0] |GC |General Call Function 126 * | | |0 = General Call Function Disabled. 127 * | | |1 = General Call Function Enabled. 128 * |[10:1] |ADDR |I2C Address 129 * | | |The content of this register is irrelevant when I2C is in Master mode 130 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 131 * | | |The I2C hardware will react if either of the address is matched. 132 * | | |Note: When software set 10'h000, the address can not be used. 133 * @var I2C_T::ADDR2 134 * Offset: 0x1C I2C Slave Address Register2 135 * --------------------------------------------------------------------------------------------------- 136 * |Bits |Field |Descriptions 137 * | :----: | :----: | :---- | 138 * |[0] |GC |General Call Function 139 * | | |0 = General Call Function Disabled. 140 * | | |1 = General Call Function Enabled. 141 * |[10:1] |ADDR |I2C Address 142 * | | |The content of this register is irrelevant when I2C is in Master mode 143 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 144 * | | |The I2C hardware will react if either of the address is matched. 145 * | | |Note: When software set 10'h000, the address can not be used. 146 * @var I2C_T::ADDR3 147 * Offset: 0x20 I2C Slave Address Register3 148 * --------------------------------------------------------------------------------------------------- 149 * |Bits |Field |Descriptions 150 * | :----: | :----: | :---- | 151 * |[0] |GC |General Call Function 152 * | | |0 = General Call Function Disabled. 153 * | | |1 = General Call Function Enabled. 154 * |[10:1] |ADDR |I2C Address 155 * | | |The content of this register is irrelevant when I2C is in Master mode 156 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address 157 * | | |The I2C hardware will react if either of the address is matched. 158 * | | |Note: When software set 10'h000, the address can not be used. 159 * @var I2C_T::ADDRMSK0 160 * Offset: 0x24 I2C Slave Address Mask Register0 161 * --------------------------------------------------------------------------------------------------- 162 * |Bits |Field |Descriptions 163 * | :----: | :----: | :---- | 164 * |[10:1] |ADDRMSK |I2C Address Mask 165 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 166 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 167 * | | |I2C bus controllers support multiple address recognition with four address mask register 168 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 169 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 170 * | | |Note: The wake-up function can not use address mask. 171 * @var I2C_T::ADDRMSK1 172 * Offset: 0x28 I2C Slave Address Mask Register1 173 * --------------------------------------------------------------------------------------------------- 174 * |Bits |Field |Descriptions 175 * | :----: | :----: | :---- | 176 * |[10:1] |ADDRMSK |I2C Address Mask 177 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 178 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 179 * | | |I2C bus controllers support multiple address recognition with four address mask register 180 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 181 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 182 * | | |Note: The wake-up function can not use address mask. 183 * @var I2C_T::ADDRMSK2 184 * Offset: 0x2C I2C Slave Address Mask Register2 185 * --------------------------------------------------------------------------------------------------- 186 * |Bits |Field |Descriptions 187 * | :----: | :----: | :---- | 188 * |[10:1] |ADDRMSK |I2C Address Mask 189 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 190 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 191 * | | |I2C bus controllers support multiple address recognition with four address mask register 192 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 193 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 194 * | | |Note: The wake-up function can not use address mask. 195 * @var I2C_T::ADDRMSK3 196 * Offset: 0x30 I2C Slave Address Mask Register3 197 * --------------------------------------------------------------------------------------------------- 198 * |Bits |Field |Descriptions 199 * | :----: | :----: | :---- | 200 * |[10:1] |ADDRMSK |I2C Address Mask 201 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 202 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 203 * | | |I2C bus controllers support multiple address recognition with four address mask register 204 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 205 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 206 * | | |Note: The wake-up function can not use address mask. 207 * @var I2C_T::WKCTL 208 * Offset: 0x3C I2C Wake-up Control Register 209 * --------------------------------------------------------------------------------------------------- 210 * |Bits |Field |Descriptions 211 * | :----: | :----: | :---- | 212 * |[0] |WKEN |I2C Wake-up Enable Bit 213 * | | |0 = I2C wake-up function Disabled. 214 * | | |1 = I2C wake-up function Enabled. 215 * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit 216 * | | |0 = I2C hold bus after wake-up. 217 * | | |1 = I2C don't hold bus after wake-up. 218 * | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received 219 * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. 220 * @var I2C_T::WKSTS 221 * Offset: 0x40 I2C Wake-up Status Register 222 * --------------------------------------------------------------------------------------------------- 223 * |Bits |Field |Descriptions 224 * | :----: | :----: | :---- | 225 * |[0] |WKIF |I2C Wake-up Flag 226 * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1 227 * | | |Software can write 1 to clear this bit. 228 * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done 229 * | | |0 = The ACK bit cycle of address match frame isn't done. 230 * | | |1 = The ACK bit cycle of address match frame is done in power-down. 231 * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit. 232 * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame 233 * | | |0 = Write command be record on the address match wakeup frame. 234 * | | |1 = Read command be record on the address match wakeup frame. 235 * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit. 236 * @var I2C_T::CTL1 237 * Offset: 0x44 I2C Control Register 1 238 * --------------------------------------------------------------------------------------------------- 239 * |Bits |Field |Descriptions 240 * | :----: | :----: | :---- | 241 * |[0] |TXPDMAEN |PDMA Transmit Channel Available 242 * | | |0 = Transmit PDMA function disable. 243 * | | |1 = Transmit PDMA function enable. 244 * |[1] |RXPDMAEN |PDMA Receive Channel Available 245 * | | |0 = Receive PDMA function disable. 246 * | | |1 = Receive PDMA function enable. 247 * |[2] |PDMARST |PDMA Reset 248 * | | |0 = No effect. 249 * | | |1 = Reset the I2C request to PDMA. 250 * |[8] |PDMASTR |PDMA Stretch Bit 251 * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX) 252 * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared 253 * | | |(only master TX) 254 * |[9] |ADDR10EN |Address 10-bit Function Enable 255 * | | |0 = Address match 10-bit function is disabled. 256 * | | |1 = Address match 10-bit function is enabled. 257 * @var I2C_T::STATUS1 258 * Offset: 0x48 I2C Status Register 1 259 * --------------------------------------------------------------------------------------------------- 260 * |Bits |Field |Descriptions 261 * | :----: | :----: | :---- | 262 * |[0] |ADMAT0 |I2C Address 0 Match Status Register 263 * | | |When address 0 is matched, hardware will inform which address used 264 * | | |This bit will set to 1, and software can write 1 to clear this bit. 265 * |[1] |ADMAT1 |I2C Address 1 Match Status Register 266 * | | |When address 1 is matched, hardware will inform which address used 267 * | | |This bit will set to 1, and software can write 1 to clear this bit. 268 * |[2] |ADMAT2 |I2C Address 2 Match Status Register 269 * | | |When address 2 is matched, hardware will inform which address used 270 * | | |This bit will set to 1, and software can write 1 to clear this bit. 271 * |[3] |ADMAT3 |I2C Address 3 Match Status Register 272 * | | |When address 3 is matched, hardware will inform which address used 273 * | | |This bit will set to 1, and software can write 1 to clear this bit. 274 * |[8] |ONBUSY |On Bus Busy 275 * | | |Indicates that a communication is in progress on the bus 276 * | | |It is set by hardware when a START condition is detected 277 * | | |It is cleared by hardware when a STOP condition is detected. 278 * | | |0 = The bus is IDLE (both SCLK and SDA High). 279 * | | |1 = The bus is busy. 280 * | | |Note:This bit is read only. 281 * @var I2C_T::TMCTL 282 * Offset: 0x4C I2C Timing Configure Control Register 283 * --------------------------------------------------------------------------------------------------- 284 * |Bits |Field |Descriptions 285 * | :----: | :----: | :---- | 286 * |[8:0] |STCTL |Setup Time Configure Control Register 287 * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. 288 * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK. 289 * | | |Note: Setup time setting should not make SCL output less than three PCLKs. 290 * |[24:16] |HTCTL |Hold Time Configure Control Register 291 * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. 292 * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK. 293 * @var I2C_T::BUSCTL 294 * Offset: 0x50 I2C Bus Management Control Register 295 * --------------------------------------------------------------------------------------------------- 296 * |Bits |Field |Descriptions 297 * | :----: | :----: | :---- | 298 * |[0] |ACKMEN |Acknowledge Control by Manual 299 * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. 300 * | | |0 = Slave byte control Disabled. 301 * | | |1 = Slave byte control Enabled 302 * | | |The 9th bit can response the ACK or NACK according the received data by user 303 * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse. 304 * | | |Note: If the BMDEN=1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition. 305 * |[1] |PECEN |Packet Error Checking Calculation Enable Bit 306 * | | |0 = Packet Error Checking Calculation Disabled. 307 * | | |1 = Packet Error Checking Calculation Enabled. 308 * | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation. 309 * |[2] |BMDEN |Bus Management Device Default Address Enable Bit 310 * | | |0 = Device default address Disable 311 * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed 312 * | | |1 = Device default address Enabled 313 * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed. 314 * |[3] |BMHEN |Bus Management Host Enable Bit 315 * | | |0 = Host function Disabled. 316 * | | |1 = Host function Enabled. 317 * |[4] |ALERTEN |Bus Management Alert Enable Bit 318 * | | |Device Mode (BMHEN=0). 319 * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. 320 * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. 321 * | | |Host Mode (BMHEN=1). 322 * | | |0 = BM_ALERT pin not supported. 323 * | | |1 = BM_ALERT pin supported. 324 * |[5] |SCTLOSTS |Suspend/Control Data Output Status 325 * | | |0 = The output of SUSCON pin is low. 326 * | | |1 = The output of SUSCON pin is high. 327 * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit 328 * | | |0 = The SUSCON pin in input. 329 * | | |1 = The output enable is active on the SUSCON pin. 330 * |[7] |BUSEN |BUS Enable Bit 331 * | | |0 = The system management function is Disabled. 332 * | | |1 = The system management function is Enable. 333 * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. 334 * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception 335 * | | |0 = No PEC transfer. 336 * | | |1 = PEC transmission is requested. 337 * | | |Note: This bit has no effect in slave mode when ACKMEN=0. 338 * |[9] |TIDLE |Timer Check in Idle State 339 * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle 340 * | | |This bit is used to define which condition is enabled. 341 * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active. 342 * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle. 343 * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. 344 * |[10] |PECCLR |PEC Clear at Repeat Start 345 * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected 346 * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. 347 * | | |0 = The PEC calculation is cleared by "Repeat Start" function is Disabled. 348 * | | |1 = The PEC calculation is cleared by "Repeat Start"" function is Enabled. 349 * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt 350 * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1. 351 * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN=1 and ACKMEN=1. 352 * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit 353 * | | |0 = Indicates the byte count done interrupt is Disabled. 354 * | | |1 = Indicates the byte count done interrupt is Enabled. 355 * | | |Note: This bit is used in PECEN=1. 356 * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit 357 * | | |0 = Indicates the PEC transfer done interrupt is Disabled. 358 * | | |1 = Indicates the PEC transfer done interrupt is Enabled. 359 * | | |Note: This bit is used in PECEN=1. 360 * @var I2C_T::BUSTCTL 361 * Offset: 0x54 I2C Bus Management Timer Control Register 362 * --------------------------------------------------------------------------------------------------- 363 * |Bits |Field |Descriptions 364 * | :----: | :----: | :---- | 365 * |[0] |BUSTOEN |Bus Time Out Enable Bit 366 * | | |0 = Indicates the bus clock low time-out detection is Disabled. 367 * | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than TTime-out (in BIDLE=0) or high more than TTime-out(in BIDLE =1) 368 * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit 369 * | | |0 = Indicates the cumulative clock low time-out detection is Disabled. 370 * | | |1 = Indicates the cumulative clock low time-out detection is Enabled. 371 * | | |For Master, it calculates the period from START to ACK 372 * | | |For Slave, it calculates the period from START to STOP 373 * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit 374 * | | |BUSY =1. 375 * | | |0 = Indicates the SCLK low time-out interrupt is Disabled. 376 * | | |1 = Indicates the SCLK low time-out interrupt is Enabled. 377 * | | |BUSY =0. 378 * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled. 379 * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled. 380 * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit 381 * | | |0 = Indicates the clock time out interrupt is Disabled. 382 * | | |1 = Indicates the clock time out interrupt is Enabled. 383 * |[4] |TORSTEN |Time Out Reset Enable Bit 384 * | | |0 = Indicates the I2C state machine reset is Disable. 385 * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high) 386 * @var I2C_T::BUSSTS 387 * Offset: 0x58 I2C Bus Management Status Register 388 * --------------------------------------------------------------------------------------------------- 389 * |Bits |Field |Descriptions 390 * | :----: | :----: | :---- | 391 * |[0] |BUSY |Bus Busy 392 * | | |Indicates that a communication is in progress on the bus 393 * | | |It is set by hardware when a START condition is detected 394 * | | |It is cleared by hardware when a STOP condition is detected 395 * | | |0 = The bus is IDLE (both SCLK and SDA High). 396 * | | |1 = The bus is busy. 397 * |[1] |BCDONE |Byte Count Transmission/Receive Done 398 * | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set. 399 * | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set. 400 * | | |Note: Software can write 1 to clear this bit. 401 * |[2] |PECERR |PEC Error in Reception 402 * | | |0 = Indicates the PEC value equal the received PEC data packet. 403 * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet. 404 * | | |Note: Software can write 1 to clear this bit. 405 * |[3] |ALERT |SMBus Alert Status 406 * | | |Device Mode (BMHEN =0). 407 * | | |0 = Indicates SMBALERT pin state is low. 408 * | | |1 = Indicates SMBALERT pin state is high. 409 * | | |Host Mode (BMHEN =1). 410 * | | |0 = No SMBALERT event. 411 * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1. 412 * | | |Note: 413 * | | |1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system 414 * | | |2. Software can write 1 to clear this bit. 415 * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status 416 * | | |0 = The input status of SUSCON pin is 0. 417 * | | |1 = The input status of SUSCON pin is 1. 418 * |[5] |BUSTO |Bus Time-out Status 419 * | | |0 = Indicates that there is no any time-out or external clock time-out. 420 * | | |1 = Indicates that a time-out or external clock time-out occurred. 421 * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. 422 * | | |Note: Software can write 1 to clear this bit. 423 * |[6] |CLKTO |Clock Low Cumulate Time-out Status 424 * | | |0 = Indicates that the cumulative clock low is no any time-out. 425 * | | |1 = Indicates that the cumulative clock low time-out occurred. 426 * | | |Note: Software can write 1 to clear this bit. 427 * |[7] |PECDONE |PEC Byte Transmission/Receive Done 428 * | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set. 429 * | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set. 430 * | | |Note: Software can write 1 to clear this bit. 431 * @var I2C_T::PKTSIZE 432 * Offset: 0x5C I2C Packet Error Checking Byte Number Register 433 * --------------------------------------------------------------------------------------------------- 434 * |Bits |Field |Descriptions 435 * | :----: | :----: | :---- | 436 * |[8:0] |PLDSIZE |Transfer Byte Number 437 * | | |The transmission or receive byte number in one transaction when the PECEN is set 438 * | | |The maximum transaction or receive byte is 256 Bytes. 439 * | | |Notice: The byte number counting includes address, command code, and data frame. 440 * @var I2C_T::PKTCRC 441 * Offset: 0x60 I2C Packet Error Checking Byte Value Register 442 * --------------------------------------------------------------------------------------------------- 443 * |Bits |Field |Descriptions 444 * | :----: | :----: | :---- | 445 * |[7:0] |PECCRC |Packet Error Checking Byte Value 446 * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1 447 * | | |It is read only. 448 * @var I2C_T::BUSTOUT 449 * Offset: 0x64 I2C Bus Management Timer Register 450 * --------------------------------------------------------------------------------------------------- 451 * |Bits |Field |Descriptions 452 * | :----: | :----: | :---- | 453 * |[7:0] |BUSTO |Bus Management Time-out Value 454 * | | |Indicate the bus time-out value in bus is IDLE or SCLK low. 455 * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. 456 * @var I2C_T::CLKTOUT 457 * Offset: 0x68 I2C Bus Management Clock Low Timer Register 458 * --------------------------------------------------------------------------------------------------- 459 * |Bits |Field |Descriptions 460 * | :----: | :----: | :---- | 461 * |[7:0] |CLKTO |Bus Clock Low Timer 462 * | | |The field is used to configure the cumulative clock extension time-out. 463 * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. 464 */ 465 __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */ 466 __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */ 467 __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */ 468 __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */ 469 __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */ 470 __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */ 471 __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */ 472 __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */ 473 __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */ 474 __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */ 475 __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */ 476 __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */ 477 __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */ 478 /// @cond HIDDEN_SYMBOLS 479 __I uint32_t RESERVE0[2]; 480 /// @endcond //HIDDEN_SYMBOLS 481 __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */ 482 __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */ 483 __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */ 484 __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */ 485 __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */ 486 __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */ 487 __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */ 488 __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */ 489 __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */ 490 __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */ 491 __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */ 492 __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */ 493 494 } I2C_T; 495 496 /** 497 @addtogroup I2C_CONST I2C Bit Field Definition 498 Constant Definitions for I2C Controller 499 @{ */ 500 501 #define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL: AA Position */ 502 #define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL: AA Mask */ 503 504 #define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL: SI Position */ 505 #define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL: SI Mask */ 506 507 #define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL: STO Position */ 508 #define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL: STO Mask */ 509 510 #define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL: STA Position */ 511 #define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL: STA Mask */ 512 513 #define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL: I2CEN Position */ 514 #define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL: I2CEN Mask */ 515 516 #define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL: INTEN Position */ 517 #define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL: INTEN Mask */ 518 519 #define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */ 520 #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */ 521 522 #define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */ 523 #define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */ 524 525 #define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */ 526 #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */ 527 528 #define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS: STATUS Position */ 529 #define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos) /*!< I2C_T::STATUS: STATUS Mask */ 530 531 #define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */ 532 #define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */ 533 534 #define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */ 535 #define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */ 536 537 #define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */ 538 #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */ 539 540 #define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */ 541 #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */ 542 543 #define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */ 544 #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */ 545 546 #define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */ 547 #define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */ 548 549 #define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */ 550 #define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */ 551 552 #define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */ 553 #define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */ 554 555 #define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */ 556 #define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */ 557 558 #define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */ 559 #define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */ 560 561 #define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */ 562 #define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */ 563 564 #define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */ 565 #define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */ 566 567 #define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */ 568 #define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */ 569 570 #define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */ 571 #define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */ 572 573 #define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */ 574 #define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */ 575 576 #define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */ 577 #define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */ 578 579 #define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */ 580 #define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */ 581 582 #define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */ 583 #define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */ 584 585 #define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */ 586 #define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */ 587 588 #define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */ 589 #define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */ 590 591 #define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */ 592 #define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */ 593 594 #define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */ 595 #define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */ 596 597 #define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */ 598 #define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */ 599 600 #define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */ 601 #define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */ 602 603 #define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */ 604 #define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */ 605 606 #define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */ 607 #define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */ 608 609 #define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */ 610 #define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */ 611 612 #define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */ 613 #define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */ 614 615 #define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */ 616 #define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */ 617 618 #define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */ 619 #define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */ 620 621 #define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */ 622 #define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */ 623 624 #define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */ 625 #define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */ 626 627 #define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */ 628 #define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */ 629 630 #define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */ 631 #define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */ 632 633 #define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */ 634 #define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */ 635 636 #define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */ 637 #define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */ 638 639 #define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */ 640 #define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */ 641 642 #define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */ 643 #define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */ 644 645 #define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */ 646 #define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */ 647 648 #define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */ 649 #define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */ 650 651 #define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */ 652 #define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */ 653 654 #define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */ 655 #define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */ 656 657 #define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */ 658 #define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */ 659 660 #define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */ 661 #define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */ 662 663 #define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */ 664 #define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */ 665 666 #define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */ 667 #define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */ 668 669 #define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */ 670 #define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */ 671 672 #define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */ 673 #define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */ 674 675 #define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */ 676 #define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */ 677 678 #define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */ 679 #define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */ 680 681 #define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */ 682 #define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */ 683 684 #define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */ 685 #define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */ 686 687 #define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */ 688 #define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */ 689 690 #define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */ 691 #define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */ 692 693 #define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */ 694 #define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */ 695 696 #define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */ 697 #define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */ 698 699 #define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */ 700 #define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */ 701 702 #define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */ 703 #define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */ 704 705 #define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */ 706 #define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */ 707 708 #define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */ 709 #define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */ 710 711 #define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */ 712 #define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */ 713 714 #define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */ 715 #define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */ 716 717 /**@}*/ /* I2C_CONST */ 718 /**@}*/ /* end of I2C register group */ 719 /**@}*/ /* end of REGISTER group */ 720 721 #if defined ( __CC_ARM ) 722 #pragma no_anon_unions 723 #endif 724 725 #endif /* __I2C_REG_H__ */ 726
