1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #include <stdint.h> 10 #include "soc/soc.h" 11 12 #ifdef __cplusplus 13 extern "C" { 14 #endif 15 16 #define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0) 17 /* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ 18 /*description: .*/ 19 #define I2C_ANA_MST_I2C0_BUSY (BIT(25)) 20 #define I2C_ANA_MST_I2C0_BUSY_M (BIT(25)) 21 #define I2C_ANA_MST_I2C0_BUSY_V 0x1 22 #define I2C_ANA_MST_I2C0_BUSY_S 25 23 /* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 24 /*description: .*/ 25 #define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF 26 #define I2C_ANA_MST_I2C0_CTRL_M ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S)) 27 #define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF 28 #define I2C_ANA_MST_I2C0_CTRL_S 0 29 30 #define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4) 31 /* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */ 32 /*description: .*/ 33 #define I2C_ANA_MST_I2C1_BUSY (BIT(25)) 34 #define I2C_ANA_MST_I2C1_BUSY_M (BIT(25)) 35 #define I2C_ANA_MST_I2C1_BUSY_V 0x1 36 #define I2C_ANA_MST_I2C1_BUSY_S 25 37 /* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */ 38 /*description: .*/ 39 #define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF 40 #define I2C_ANA_MST_I2C1_CTRL_M ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S)) 41 #define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF 42 #define I2C_ANA_MST_I2C1_CTRL_S 0 43 44 #define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8) 45 /* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ 46 /*description: .*/ 47 #define I2C_ANA_MST_I2C0_STATUS 0x000000FF 48 #define I2C_ANA_MST_I2C0_STATUS_M ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S)) 49 #define I2C_ANA_MST_I2C0_STATUS_V 0xFF 50 #define I2C_ANA_MST_I2C0_STATUS_S 24 51 /* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ 52 /*description: .*/ 53 #define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF 54 #define I2C_ANA_MST_I2C0_CONF_M ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S)) 55 #define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF 56 #define I2C_ANA_MST_I2C0_CONF_S 0 57 58 #define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC) 59 /* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */ 60 /*description: .*/ 61 #define I2C_ANA_MST_I2C1_STATUS 0x000000FF 62 #define I2C_ANA_MST_I2C1_STATUS_M ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S)) 63 #define I2C_ANA_MST_I2C1_STATUS_V 0xFF 64 #define I2C_ANA_MST_I2C1_STATUS_S 24 65 /* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ 66 /*description: .*/ 67 #define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF 68 #define I2C_ANA_MST_I2C1_CONF_M ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S)) 69 #define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF 70 #define I2C_ANA_MST_I2C1_CONF_S 0 71 72 #define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10) 73 /* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 74 /*description: .*/ 75 #define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF 76 #define I2C_ANA_MST_BURST_CTRL_M ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S)) 77 #define I2C_ANA_MST_BURST_CTRL_V 0xFFFFFFFF 78 #define I2C_ANA_MST_BURST_CTRL_S 0 79 80 #define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14) 81 /* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */ 82 /*description: .*/ 83 #define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF 84 #define I2C_ANA_MST_BURST_TIMEOUT_CNT_M ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S)) 85 #define I2C_ANA_MST_BURST_TIMEOUT_CNT_V 0xFFF 86 #define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20 87 /* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */ 88 /*description: .*/ 89 #define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2)) 90 #define I2C_ANA_MST1_BURST_ERR_FLAG_M (BIT(2)) 91 #define I2C_ANA_MST1_BURST_ERR_FLAG_V 0x1 92 #define I2C_ANA_MST1_BURST_ERR_FLAG_S 2 93 /* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */ 94 /*description: .*/ 95 #define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1)) 96 #define I2C_ANA_MST0_BURST_ERR_FLAG_M (BIT(1)) 97 #define I2C_ANA_MST0_BURST_ERR_FLAG_V 0x1 98 #define I2C_ANA_MST0_BURST_ERR_FLAG_S 1 99 /* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */ 100 /*description: .*/ 101 #define I2C_ANA_MST_BURST_DONE (BIT(0)) 102 #define I2C_ANA_MST_BURST_DONE_M (BIT(0)) 103 #define I2C_ANA_MST_BURST_DONE_V 0x1 104 #define I2C_ANA_MST_BURST_DONE_S 0 105 106 #define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) 107 /* I2C_ANA_MST_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ 108 /*description: .*/ 109 #define I2C_ANA_MST_ANA_STATUS0 0x000000FF 110 #define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S)) 111 #define I2C_ANA_MST_ANA_STATUS0_V 0xFF 112 #define I2C_ANA_MST_ANA_STATUS0_S 24 113 /* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */ 114 /*description: .*/ 115 #define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF 116 #define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S)) 117 #define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF 118 #define I2C_ANA_MST_ANA_CONF0_S 0 119 120 #define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C) 121 /* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ 122 /*description: .*/ 123 #define I2C_ANA_MST_ANA_STATUS1 0x000000FF 124 #define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S)) 125 #define I2C_ANA_MST_ANA_STATUS1_V 0xFF 126 #define I2C_ANA_MST_ANA_STATUS1_S 24 127 /* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ 128 /*description: .*/ 129 #define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF 130 #define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S)) 131 #define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF 132 #define I2C_ANA_MST_ANA_CONF1_S 0 133 134 #define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) 135 /* I2C_ANA_MST_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ 136 /*description: .*/ 137 #define I2C_ANA_MST_ANA_STATUS2 0x000000FF 138 #define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S)) 139 #define I2C_ANA_MST_ANA_STATUS2_V 0xFF 140 #define I2C_ANA_MST_ANA_STATUS2_S 24 141 /* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */ 142 /*description: .*/ 143 #define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF 144 #define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S)) 145 #define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF 146 #define I2C_ANA_MST_ANA_CONF2_S 0 147 148 #define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24) 149 /* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ 150 /*description: .*/ 151 #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F 152 #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S)) 153 #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F 154 #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6 155 /* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ 156 /*description: .*/ 157 #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F 158 #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S)) 159 #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F 160 #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0 161 162 #define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28) 163 /* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ 164 /*description: .*/ 165 #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F 166 #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S)) 167 #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F 168 #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6 169 /* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ 170 /*description: .*/ 171 #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F 172 #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S)) 173 #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F 174 #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0 175 176 #define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C) 177 /* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */ 178 /*description: .*/ 179 #define I2C_ANA_MST_ARBITER_DIS (BIT(11)) 180 #define I2C_ANA_MST_ARBITER_DIS_M (BIT(11)) 181 #define I2C_ANA_MST_ARBITER_DIS_V 0x1 182 #define I2C_ANA_MST_ARBITER_DIS_S 11 183 /* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */ 184 /*description: .*/ 185 #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F 186 #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S)) 187 #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F 188 #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6 189 /* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */ 190 /*description: .*/ 191 #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F 192 #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S)) 193 #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F 194 #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0 195 196 #define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30) 197 /* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 198 /*description: .*/ 199 #define I2C_ANA_MST_NOUSE 0xFFFFFFFF 200 #define I2C_ANA_MST_NOUSE_M ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S)) 201 #define I2C_ANA_MST_NOUSE_V 0xFFFFFFFF 202 #define I2C_ANA_MST_NOUSE_S 0 203 204 #define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x34) 205 /* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ 206 /*description: .*/ 207 #define I2C_ANA_MST_CLK_EN (BIT(28)) 208 #define I2C_ANA_MST_CLK_EN_M (BIT(28)) 209 #define I2C_ANA_MST_CLK_EN_V 0x1 210 #define I2C_ANA_MST_CLK_EN_S 28 211 /* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */ 212 /*description: .*/ 213 #define I2C_ANA_MST_DATE 0x0FFFFFFF 214 #define I2C_ANA_MST_DATE_M ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S)) 215 #define I2C_ANA_MST_DATE_V 0xFFFFFFF 216 #define I2C_ANA_MST_DATE_S 0 217 218 #ifdef __cplusplus 219 } 220 #endif 221
