1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #include "fsl_i2c.h"
9
10 /*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13
14 /* Component ID definition, used by tools. */
15 #ifndef FSL_COMPONENT_ID
16 #define FSL_COMPONENT_ID "platform.drivers.i2c"
17 #endif
18
19 /*! @brief i2c transfer state. */
20 enum _i2c_transfer_states
21 {
22 kIdleState = 0x0U, /*!< I2C bus idle. */
23 kCheckAddressState = 0x1U, /*!< 7-bit address check state. */
24 kSendCommandState = 0x2U, /*!< Send command byte phase. */
25 kSendDataState = 0x3U, /*!< Send data transfer phase. */
26 kReceiveDataBeginState = 0x4U, /*!< Receive data transfer phase begin. */
27 kReceiveDataState = 0x5U, /*!< Receive data transfer phase. */
28 };
29
30 /*! @brief Typedef for interrupt handler. */
31 typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle);
32
33 /*! @brief static variable to keep current configured baudrate. */
34 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
35 static uint32_t g_baudrate = 100000;
36 #endif
37
38 /*******************************************************************************
39 * Prototypes
40 ******************************************************************************/
41
42 /*!
43 * @brief Set SCL/SDA hold time, this API receives SCL stop hold time, calculate the
44 * closest SCL divider and MULT value for the SDA hold time, SCL start and SCL stop
45 * hold time. To reduce the ROM size, SDA/SCL hold value mapping table is not provided,
46 * assume SCL divider = SCL stop hold value *2 to get the closest SCL divider value and MULT
47 * value, then the related SDA hold time, SCL start and SCL stop hold time is used.
48 *
49 * @param base I2C peripheral base address.
50 * @param sourceClock_Hz I2C functional clock frequency in Hertz.
51 * @param sclStopHoldTime_ns SCL stop hold time in ns.
52 */
53 static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz);
54
55 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
56 /*!
57 * @brief I2C master manually ack byte.
58 *
59 * @param base I2C peripheral base address.
60 */
61 static void I2C_MasterAckByte(I2C_Type *base);
62 #endif
63
64 /*!
65 * @brief Set up master transfer, send slave address and decide the initial
66 * transfer state.
67 *
68 * @param base I2C peripheral base address.
69 * @param handle pointer to i2c_master_handle_t structure which stores the transfer state.
70 * @param xfer pointer to i2c_master_transfer_t structure.
71 */
72 static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer);
73
74 /*!
75 * @brief Check and clear status operation.
76 *
77 * @param base I2C peripheral base address.
78 * @param status current i2c hardware status.
79 * @retval kStatus_Success No error found.
80 * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
81 * @retval kStatus_I2C_Nak Received Nak error.
82 */
83 static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status);
84
85 /*!
86 * @brief Master run transfer state machine to perform a byte of transfer.
87 *
88 * @param base I2C peripheral base address.
89 * @param handle pointer to i2c_master_handle_t structure which stores the transfer state
90 * @param isDone input param to get whether the thing is done, true is done
91 * @retval kStatus_Success No error found.
92 * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
93 * @retval kStatus_I2C_Nak Received Nak error.
94 * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
95 */
96 static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone);
97
98 /*!
99 * @brief I2C common interrupt handler.
100 *
101 * @param base I2C peripheral base address.
102 * @param handle pointer to i2c_master_handle_t structure which stores the transfer state
103 */
104 static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle);
105
106 /*******************************************************************************
107 * Variables
108 ******************************************************************************/
109
110 /*! @brief Pointers to i2c handles for each instance. */
111 static void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT];
112
113 /*! @brief SCL clock divider used to calculate baudrate. */
114 static const uint16_t s_i2cDividerTable[] = {
115 20, 22, 24, 26, 28, 30, 34, 40, 28, 32, 36, 40, 44, 48, 56, 68,
116 48, 56, 64, 72, 80, 88, 104, 128, 80, 96, 112, 128, 144, 160, 192, 240,
117 160, 192, 224, 256, 288, 320, 384, 480, 320, 384, 448, 512, 576, 640, 768, 960,
118 640, 768, 896, 1024, 1152, 1280, 1536, 1920, 1280, 1536, 1792, 2048, 2304, 2560, 3072, 3840};
119
120 /*! @brief Pointers to i2c IRQ number for each instance. */
121 static const IRQn_Type s_i2cIrqs[] = I2C_IRQS;
122
123 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
124 /*! @brief Pointers to i2c clocks for each instance. */
125 static const clock_ip_name_t s_i2cClocks[] = I2C_CLOCKS;
126 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
127
128 /*! @brief Pointer to master IRQ handler for each instance. */
129 static i2c_isr_t s_i2cMasterIsr;
130
131 /*! @brief Pointer to slave IRQ handler for each instance. */
132 static i2c_isr_t s_i2cSlaveIsr;
133
134 /*! @brief Pointers to i2c bases for each instance. */
135 static I2C_Type *const s_i2cBases[] = I2C_BASE_PTRS;
136 /*******************************************************************************
137 * Codes
138 ******************************************************************************/
139
140 /*!
141 * brief Get instance number for I2C module.
142 *
143 * param base I2C peripheral base address.
144 */
I2C_GetInstance(I2C_Type * base)145 uint32_t I2C_GetInstance(I2C_Type *base)
146 {
147 uint32_t instance;
148
149 /* Find the instance index from base address mappings. */
150 for (instance = 0; instance < ARRAY_SIZE(s_i2cBases); instance++)
151 {
152 if (s_i2cBases[instance] == base)
153 {
154 break;
155 }
156 }
157
158 assert(instance < ARRAY_SIZE(s_i2cBases));
159
160 return instance;
161 }
162
I2C_SetHoldTime(I2C_Type * base,uint32_t sclStopHoldTime_ns,uint32_t sourceClock_Hz)163 static void I2C_SetHoldTime(I2C_Type *base, uint32_t sclStopHoldTime_ns, uint32_t sourceClock_Hz)
164 {
165 uint32_t multiplier;
166 uint32_t computedSclHoldTime;
167 uint32_t absError;
168 uint32_t bestError = UINT32_MAX;
169 uint32_t bestMult = 0u;
170 uint32_t bestIcr = 0u;
171 uint32_t u32flag = 1u;
172 uint8_t mult;
173 uint8_t i;
174
175 /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register,
176 * and ranges from 0-2. It selects the multiplier factor for the divider. */
177 /* SDA hold time = bus period (s) * mul * SDA hold value. */
178 /* SCL start hold time = bus period (s) * mul * SCL start hold value. */
179 /* SCL stop hold time = bus period (s) * mul * SCL stop hold value. */
180
181 for (mult = 0u; mult <= 2u; ++mult)
182 {
183 if (bestError == 0u)
184 {
185 break;
186 }
187
188 multiplier = u32flag << mult;
189
190 /* Scan table to find best match. */
191 for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(s_i2cDividerTable[0]); ++i)
192 {
193 /* Assume SCL hold(stop) value = s_i2cDividerTable[i]/2. */
194 computedSclHoldTime = ((multiplier * s_i2cDividerTable[i]) * 500000U) / (sourceClock_Hz / 1000U);
195 absError = sclStopHoldTime_ns > computedSclHoldTime ? (sclStopHoldTime_ns - computedSclHoldTime) :
196 (computedSclHoldTime - sclStopHoldTime_ns);
197
198 if (absError < bestError)
199 {
200 bestMult = mult;
201 bestIcr = i;
202 bestError = absError;
203
204 /* If the error is 0, then we can stop searching because we won't find a better match. */
205 if (absError == 0u)
206 {
207 break;
208 }
209 }
210 }
211 }
212
213 /* Set frequency register based on best settings. */
214 base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr);
215 }
216
217 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
I2C_MasterAckByte(I2C_Type * base)218 static void I2C_MasterAckByte(I2C_Type *base)
219 {
220 /* Clear the TXAK flag. */
221 base->C1 &= ~(uint8_t)I2C_C1_TXAK_MASK;
222
223 /* Delay at least one bit time */
224 SDK_DelayAtLeastUs(1000000 / g_baudrate, SystemCoreClock);
225
226 /* Do dummy read. */
227 (void)base->D;
228 }
229 #endif
230
I2C_InitTransferStateMachine(I2C_Type * base,i2c_master_handle_t * handle,i2c_master_transfer_t * xfer)231 static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
232 {
233 status_t result = kStatus_Success;
234 i2c_direction_t direction = xfer->direction;
235
236 /* Initialize the handle transfer information. */
237 handle->transfer = *xfer;
238
239 /* Save total transfer size. */
240 handle->transferSize = xfer->dataSize;
241
242 /* Initial transfer state. */
243 if (handle->transfer.subaddressSize > 0u)
244 {
245 if (xfer->direction == kI2C_Read)
246 {
247 direction = kI2C_Write;
248 }
249 }
250
251 handle->state = (uint8_t)kCheckAddressState;
252
253 /* Clear all status before transfer. */
254 I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags);
255
256 /* Handle no start option. */
257 if (0U != (handle->transfer.flags & (uint32_t)kI2C_TransferNoStartFlag))
258 {
259 /* No need to send start flag, directly go to send command or data */
260 if (handle->transfer.subaddressSize > 0u)
261 {
262 handle->state = (uint8_t)kSendCommandState;
263 }
264 else
265 {
266 if (direction == kI2C_Write)
267 {
268 /* Next state, send data. */
269 handle->state = (uint8_t)kSendDataState;
270 }
271 else
272 {
273 /* Only support write with no stop signal. */
274 return kStatus_InvalidArgument;
275 }
276 }
277
278 /* Wait for TCF bit and manually trigger tx interrupt. */
279 #if I2C_RETRY_TIMES != 0U
280 uint32_t waitTimes = I2C_RETRY_TIMES;
281 while ((0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) && (0U != waitTimes))
282 {
283 waitTimes--;
284 }
285 if (0U == waitTimes)
286 {
287 return kStatus_I2C_Timeout;
288 }
289 #else
290 while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag))
291 {
292 }
293 #endif
294 I2C_MasterTransferHandleIRQ(base, handle);
295 }
296 /* If repeated start is requested, send repeated start. */
297 else if (0U != (handle->transfer.flags & (uint32_t)kI2C_TransferRepeatedStartFlag))
298 {
299 result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, direction);
300 }
301 else /* For normal transfer, send start. */
302 {
303 result = I2C_MasterStart(base, handle->transfer.slaveAddress, direction);
304 }
305
306 return result;
307 }
308
I2C_CheckAndClearError(I2C_Type * base,uint32_t status)309 static status_t I2C_CheckAndClearError(I2C_Type *base, uint32_t status)
310 {
311 status_t result = kStatus_Success;
312
313 /* Check arbitration lost. */
314 if (0U != (status & (uint32_t)kI2C_ArbitrationLostFlag))
315 {
316 /* Clear arbitration lost flag. */
317 base->S = (uint8_t)kI2C_ArbitrationLostFlag;
318 result = kStatus_I2C_ArbitrationLost;
319 }
320 /* Check NAK */
321 else if (0U != (status & (uint32_t)kI2C_ReceiveNakFlag))
322 {
323 result = kStatus_I2C_Nak;
324 }
325 else
326 {
327 /* Add this to fix MISRA C2012 rule15.7 issue: Empty else without comment. */
328 }
329
330 return result;
331 }
332
I2C_MasterTransferRunStateMachine(I2C_Type * base,i2c_master_handle_t * handle,bool * isDone)333 static status_t I2C_MasterTransferRunStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone)
334 {
335 status_t result = kStatus_Success;
336 uint32_t statusFlags = base->S;
337 *isDone = false;
338 uint32_t tmpDataSize = handle->transfer.dataSize;
339 bool ignoreNak = ((handle->state == (uint8_t)kSendDataState) && (tmpDataSize == 0U)) ||
340 ((handle->state == (uint8_t)kReceiveDataState) && (tmpDataSize == 1U));
341 uint8_t tmpdata;
342
343 /* Check & clear error flags. */
344 result = I2C_CheckAndClearError(base, statusFlags);
345
346 /* Ignore Nak when it's appeared for last byte. */
347 if ((result == kStatus_I2C_Nak) && ignoreNak)
348 {
349 result = kStatus_Success;
350 }
351
352 /* Handle Check address state to check the slave address is Acked in slave
353 probe application. */
354 if (handle->state == (uint8_t)kCheckAddressState)
355 {
356 if (0U != (statusFlags & (uint8_t)kI2C_ReceiveNakFlag))
357 {
358 result = kStatus_I2C_Addr_Nak;
359 }
360 else
361 {
362 if (handle->transfer.subaddressSize > 0U)
363 {
364 handle->state = (uint8_t)kSendCommandState;
365 }
366 else
367 {
368 if (handle->transfer.direction == kI2C_Write)
369 {
370 /* Next state, send data. */
371 handle->state = (uint8_t)kSendDataState;
372 }
373 else
374 {
375 /* Next state, receive data begin. */
376 handle->state = (uint8_t)kReceiveDataBeginState;
377 }
378 }
379 }
380 }
381
382 if (kStatus_Success != result)
383 {
384 return result;
385 }
386
387 /* Run state machine. */
388 switch (handle->state)
389 {
390 /* Send I2C command. */
391 case (uint8_t)kSendCommandState:
392 if (0U != (handle->transfer.subaddressSize))
393 {
394 handle->transfer.subaddressSize--;
395 base->D = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize));
396 }
397 else
398 {
399 if (handle->transfer.direction == kI2C_Write)
400 {
401 /* Send first byte of data. */
402 if (handle->transfer.dataSize > 0U)
403 {
404 /* Next state, send data. */
405 handle->state = (uint8_t)kSendDataState;
406 base->D = *handle->transfer.data;
407 handle->transfer.data++;
408 handle->transfer.dataSize--;
409 }
410 else
411 {
412 *isDone = true;
413 }
414 }
415 else
416 {
417 /* Send repeated start and slave address. */
418 result = I2C_MasterRepeatedStart(base, handle->transfer.slaveAddress, kI2C_Read);
419
420 /* Next state, receive data begin. */
421 handle->state = (uint8_t)kReceiveDataBeginState;
422 }
423 }
424 break;
425
426 /* Send I2C data. */
427 case (uint8_t)kSendDataState:
428 /* Send one byte of data. */
429 if (handle->transfer.dataSize > 0U)
430 {
431 base->D = *handle->transfer.data;
432 handle->transfer.data++;
433 handle->transfer.dataSize--;
434 }
435 else
436 {
437 *isDone = true;
438 }
439 break;
440
441 /* Start I2C data receive. */
442 case (uint8_t)kReceiveDataBeginState:
443
444 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
445 base->SMB |= I2C_SMB_FACK_MASK;
446 #endif
447
448 base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
449
450 /* Read dummy to release the bus. */
451 (void)base->D;
452
453 if (handle->transfer.dataSize == 1U)
454 {
455 /* Issue NACK on read. */
456 base->C1 |= I2C_C1_TXAK_MASK;
457 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
458 base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK;
459 #endif
460 }
461
462 /* Next state, receive data. */
463 handle->state = (uint8_t)kReceiveDataState;
464 break;
465
466 /* Receive I2C data. */
467 case (uint8_t)kReceiveDataState:
468 /* Receive one byte of data. */
469 if (0U != (handle->transfer.dataSize--))
470 {
471 if (handle->transfer.dataSize == 0U)
472 {
473 *isDone = true;
474
475 /* Send stop if kI2C_TransferNoStop is not asserted. */
476 if (0U == (handle->transfer.flags & (uint32_t)kI2C_TransferNoStopFlag))
477 {
478 result = I2C_MasterStop(base);
479 }
480 else
481 {
482 base->C1 |= I2C_C1_TX_MASK;
483 }
484 }
485
486 /* Read the data byte into the transfer buffer. */
487 tmpdata = base->D;
488 *handle->transfer.data = tmpdata;
489 handle->transfer.data++;
490
491 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
492 if (handle->transfer.dataSize != 0U)
493 {
494 I2C_MasterAckByte(base);
495 }
496 #endif
497 if (handle->transfer.dataSize == 1U)
498 {
499 /* Issue NACK on read. */
500 base->C1 |= I2C_C1_TXAK_MASK;
501 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
502 base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK;
503 #endif
504 }
505 }
506
507 break;
508
509 default:
510 /* Add this to fix MISRA C2012 rule 16.4 issue: Empty default. */
511 assert(false);
512 break;
513 }
514
515 return result;
516 }
517
I2C_TransferCommonIRQHandler(I2C_Type * base,void * handle)518 static void I2C_TransferCommonIRQHandler(I2C_Type *base, void *handle)
519 {
520 uint8_t tmpS = base->S;
521 uint8_t tmpC1 = base->C1;
522
523 /* Check if master interrupt. */
524 if ((0U != (tmpC1 & I2C_C1_MST_MASK)) || (0U != (tmpS & (uint8_t)kI2C_ArbitrationLostFlag)))
525 {
526 s_i2cMasterIsr(base, handle);
527 }
528 else
529 {
530 s_i2cSlaveIsr(base, handle);
531 }
532 SDK_ISR_EXIT_BARRIER;
533 }
534
535 /*!
536 * brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
537 * and configure the I2C with master configuration.
538 *
539 * note This API should be called at the beginning of the application.
540 * Otherwise, any operation to the I2C module can cause a hard fault
541 * because the clock is not enabled. The configuration structure can be custom filled
542 * or it can be set with default values by using the I2C_MasterGetDefaultConfig().
543 * After calling this API, the master is ready to transfer.
544 * This is an example.
545 * code
546 * i2c_master_config_t config = {
547 * .enableMaster = true,
548 * .enableStopHold = false,
549 * .highDrive = false,
550 * .baudRate_Bps = 100000,
551 * .glitchFilterWidth = 0
552 * };
553 * I2C_MasterInit(I2C0, &config, 12000000U);
554 * endcode
555 *
556 * param base I2C base pointer
557 * param masterConfig A pointer to the master configuration structure
558 * param srcClock_Hz I2C peripheral clock frequency in Hz
559 */
I2C_MasterInit(I2C_Type * base,const i2c_master_config_t * masterConfig,uint32_t srcClock_Hz)560 void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
561 {
562 assert(NULL != masterConfig);
563 assert(0U != srcClock_Hz);
564
565 /* Temporary register for filter read. */
566 uint8_t fltReg;
567 #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
568 uint8_t s2Reg;
569 #endif
570 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
571 /* Enable I2C clock. */
572 CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
573 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
574
575 /* Reset the module. */
576 base->A1 = 0;
577 base->F = 0;
578 base->C1 = 0;
579 base->S = 0xFFU;
580 base->C2 = 0;
581 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
582 base->FLT = 0x50U;
583 #elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
584 base->FLT = 0x40U;
585 #endif
586 base->RA = 0;
587
588 /* Disable I2C prior to configuring it. */
589 base->C1 &= ~(uint8_t)(I2C_C1_IICEN_MASK);
590
591 /* Clear all flags. */
592 I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags);
593
594 /* Configure baud rate. */
595 I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz);
596
597 /* Read out the FLT register. */
598 fltReg = base->FLT;
599
600 #if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
601 /* Configure the stop / hold enable. */
602 fltReg &= ~(uint8_t)(I2C_FLT_SHEN_MASK);
603 fltReg |= I2C_FLT_SHEN(masterConfig->enableStopHold);
604 #endif
605
606 /* Configure the glitch filter value. */
607 fltReg &= ~(uint8_t)(I2C_FLT_FLT_MASK);
608 fltReg |= I2C_FLT_FLT(masterConfig->glitchFilterWidth);
609
610 /* Write the register value back to the filter register. */
611 base->FLT = fltReg;
612
613 /* Enable the I2C peripheral based on the configuration. */
614 base->C1 = I2C_C1_IICEN(masterConfig->enableMaster);
615
616 /* Enable/Disable double buffering. */
617 #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
618 s2Reg = (uint8_t)(base->S2 & (~I2C_S2_DFEN_MASK));
619 base->S2 = s2Reg | I2C_S2_DFEN(masterConfig->enableDoubleBuffering);
620 #endif
621 }
622
623 /*!
624 * brief De-initializes the I2C master peripheral. Call this API to gate the I2C clock.
625 * The I2C master module can't work unless the I2C_MasterInit is called.
626 * param base I2C base pointer
627 */
I2C_MasterDeinit(I2C_Type * base)628 void I2C_MasterDeinit(I2C_Type *base)
629 {
630 /* Disable I2C module. */
631 I2C_Enable(base, false);
632
633 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
634 /* Disable I2C clock. */
635 CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
636 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
637 }
638
639 /*!
640 * brief Sets the I2C master configuration structure to default values.
641 *
642 * The purpose of this API is to get the configuration structure initialized for use in the I2C_MasterConfigure().
643 * Use the initialized structure unchanged in the I2C_MasterConfigure() or modify
644 * the structure before calling the I2C_MasterConfigure().
645 * This is an example.
646 * code
647 * i2c_master_config_t config;
648 * I2C_MasterGetDefaultConfig(&config);
649 * endcode
650 * param masterConfig A pointer to the master configuration structure.
651 */
I2C_MasterGetDefaultConfig(i2c_master_config_t * masterConfig)652 void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
653 {
654 assert(NULL != masterConfig);
655
656 /* Initializes the configure structure to zero. */
657 (void)memset(masterConfig, 0, sizeof(*masterConfig));
658
659 /* Default baud rate at 100kbps. */
660 masterConfig->baudRate_Bps = 100000U;
661
662 /* Default stop hold enable is disabled. */
663 #if defined(FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF) && FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
664 masterConfig->enableStopHold = false;
665 #endif
666
667 /* Default glitch filter value is no filter. */
668 masterConfig->glitchFilterWidth = 0U;
669
670 /* Default enable double buffering. */
671 #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
672 masterConfig->enableDoubleBuffering = true;
673 #endif
674
675 /* Enable the I2C peripheral. */
676 masterConfig->enableMaster = true;
677 }
678
679 /*!
680 * brief Enables I2C interrupt requests.
681 *
682 * param base I2C base pointer
683 * param mask interrupt source
684 * The parameter can be combination of the following source if defined:
685 * arg kI2C_GlobalInterruptEnable
686 * arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
687 * arg kI2C_SdaTimeoutInterruptEnable
688 */
I2C_EnableInterrupts(I2C_Type * base,uint32_t mask)689 void I2C_EnableInterrupts(I2C_Type *base, uint32_t mask)
690 {
691 #ifdef I2C_HAS_STOP_DETECT
692 uint8_t fltReg;
693 #endif
694
695 if (0U != (mask & (uint32_t)kI2C_GlobalInterruptEnable))
696 {
697 base->C1 |= I2C_C1_IICIE_MASK;
698 }
699
700 #if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
701 if (0U != (mask & (uint32_t)kI2C_StopDetectInterruptEnable))
702 {
703 fltReg = base->FLT;
704
705 /* Keep STOPF flag. */
706 fltReg &= ~I2C_FLT_STOPF_MASK;
707
708 /* Stop detect enable. */
709 fltReg |= I2C_FLT_STOPIE_MASK;
710 base->FLT = fltReg;
711 }
712 #endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
713
714 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
715 if (0U != (mask & (uint32_t)kI2C_StartStopDetectInterruptEnable))
716 {
717 fltReg = base->FLT;
718
719 /* Keep STARTF and STOPF flags. */
720 fltReg &= ~(uint8_t)(I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
721
722 /* Start and stop detect enable. */
723 fltReg |= I2C_FLT_SSIE_MASK;
724 base->FLT = fltReg;
725 }
726 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
727 }
728
729 /*!
730 * brief Disables I2C interrupt requests.
731 *
732 * param base I2C base pointer
733 * param mask interrupt source
734 * The parameter can be combination of the following source if defined:
735 * arg kI2C_GlobalInterruptEnable
736 * arg kI2C_StopDetectInterruptEnable/kI2C_StartDetectInterruptEnable
737 * arg kI2C_SdaTimeoutInterruptEnable
738 */
I2C_DisableInterrupts(I2C_Type * base,uint32_t mask)739 void I2C_DisableInterrupts(I2C_Type *base, uint32_t mask)
740 {
741 if (0U != (mask & (uint32_t)kI2C_GlobalInterruptEnable))
742 {
743 base->C1 &= ~(uint8_t)I2C_C1_IICIE_MASK;
744 }
745
746 #if defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
747 if (0U != (mask & (uint32_t)kI2C_StopDetectInterruptEnable))
748 {
749 base->FLT &= ~(I2C_FLT_STOPIE_MASK | I2C_FLT_STOPF_MASK);
750 }
751 #endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */
752
753 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
754 if (0U != (mask & (uint32_t)kI2C_StartStopDetectInterruptEnable))
755 {
756 base->FLT &= ~(uint8_t)(I2C_FLT_SSIE_MASK | I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK);
757 }
758 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
759 }
760
761 /*!
762 * brief Sets the I2C master transfer baud rate.
763 *
764 * param base I2C base pointer
765 * param baudRate_Bps the baud rate value in bps
766 * param srcClock_Hz Source clock
767 */
I2C_MasterSetBaudRate(I2C_Type * base,uint32_t baudRate_Bps,uint32_t srcClock_Hz)768 void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
769 {
770 uint32_t multiplier;
771 uint32_t computedRate;
772 uint32_t absError;
773 uint32_t bestError = UINT32_MAX;
774 uint32_t bestMult = 0u;
775 uint32_t bestIcr = 0u;
776 uint32_t u32flag = 1u;
777 uint8_t mult;
778 uint8_t i;
779
780 /* Search for the settings with the lowest error. Mult is the MULT field of the I2C_F register,
781 * and ranges from 0-2. It selects the multiplier factor for the divider. */
782 for (mult = 0u; mult <= 2u; ++mult)
783 {
784 if (bestError == 0u)
785 {
786 break;
787 }
788
789 multiplier = u32flag << mult;
790
791 /* Scan table to find best match. */
792 for (i = 0u; i < sizeof(s_i2cDividerTable) / sizeof(uint16_t); ++i)
793 {
794 computedRate = srcClock_Hz / (multiplier * s_i2cDividerTable[i]);
795 absError = baudRate_Bps > computedRate ? (baudRate_Bps - computedRate) : (computedRate - baudRate_Bps);
796
797 if (absError < bestError)
798 {
799 bestMult = mult;
800 bestIcr = i;
801 bestError = absError;
802
803 /* If the error is 0, then we can stop searching because we won't find a better match. */
804 if (absError == 0u)
805 {
806 break;
807 }
808 }
809 }
810 }
811
812 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
813 g_baudrate = baudRate_Bps;
814 #endif
815 /* Set frequency register based on best settings. */
816 base->F = I2C_F_MULT(bestMult) | I2C_F_ICR(bestIcr);
817 }
818
819 /*!
820 * brief Sends a START on the I2C bus.
821 *
822 * This function is used to initiate a new master mode transfer by sending the START signal.
823 * The slave address is sent following the I2C START signal.
824 *
825 * param base I2C peripheral base pointer
826 * param address 7-bit slave device address.
827 * param direction Master transfer directions(transmit/receive).
828 * retval kStatus_Success Successfully send the start signal.
829 * retval kStatus_I2C_Busy Current bus is busy.
830 */
I2C_MasterStart(I2C_Type * base,uint8_t address,i2c_direction_t direction)831 status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
832 {
833 status_t result = kStatus_Success;
834 uint32_t statusFlags = I2C_MasterGetStatusFlags(base);
835
836 /* Return an error if the bus is already in use. */
837 if (0U != (statusFlags & (uint32_t)kI2C_BusBusyFlag))
838 {
839 result = kStatus_I2C_Busy;
840 }
841 else
842 {
843 /* Send the START signal. */
844 base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK;
845
846 #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
847 #if I2C_RETRY_TIMES != 0U
848 uint32_t waitTimes = I2C_RETRY_TIMES;
849 while ((0U == (base->S2 & I2C_S2_EMPTY_MASK)) && (0U != waitTimes))
850 {
851 waitTimes--;
852 }
853 if (0U == waitTimes)
854 {
855 return kStatus_I2C_Timeout;
856 }
857 #else
858 while (0U == (base->S2 & I2C_S2_EMPTY_MASK))
859 {
860 }
861 #endif
862 #endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */
863
864 base->D = (uint8_t)(((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U));
865 }
866
867 return result;
868 }
869
870 /*!
871 * brief Sends a REPEATED START on the I2C bus.
872 *
873 * param base I2C peripheral base pointer
874 * param address 7-bit slave device address.
875 * param direction Master transfer directions(transmit/receive).
876 * retval kStatus_Success Successfully send the start signal.
877 * retval kStatus_I2C_Busy Current bus is busy but not occupied by current I2C master.
878 */
I2C_MasterRepeatedStart(I2C_Type * base,uint8_t address,i2c_direction_t direction)879 status_t I2C_MasterRepeatedStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
880 {
881 status_t result = kStatus_Success;
882 uint8_t savedMult;
883 uint32_t statusFlags = I2C_MasterGetStatusFlags(base);
884 uint8_t timeDelay = 6;
885
886 /* Return an error if the bus is already in use, but not by us. */
887 if ((0U == (base->C1 & I2C_C1_MST_MASK)) && (0U != (statusFlags & (uint32_t)kI2C_BusBusyFlag)))
888 {
889 result = kStatus_I2C_Busy;
890 }
891 else
892 {
893 savedMult = base->F;
894 base->F = savedMult & (~(uint8_t)I2C_F_MULT_MASK);
895
896 /* We are already in a transfer, so send a repeated start. */
897 base->C1 |= I2C_C1_RSTA_MASK | I2C_C1_TX_MASK;
898
899 /* Restore the multiplier factor. */
900 base->F = savedMult;
901
902 /* Add some delay to wait the Re-Start signal. */
903 while (0U != (timeDelay--))
904 {
905 __NOP();
906 }
907
908 #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
909 #if I2C_RETRY_TIMES != 0U
910 uint32_t waitTimes = I2C_RETRY_TIMES;
911 while ((0U == (base->S2 & I2C_S2_EMPTY_MASK)) && (0U != waitTimes))
912 {
913 waitTimes--;
914 }
915 if (0U == waitTimes)
916 {
917 return kStatus_I2C_Timeout;
918 }
919 #else
920 while (0U == (base->S2 & I2C_S2_EMPTY_MASK))
921 {
922 }
923 #endif
924 #endif /* FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING */
925
926 base->D = (uint8_t)(((uint32_t)address) << 1U | ((direction == kI2C_Read) ? 1U : 0U));
927 }
928
929 return result;
930 }
931
932 /*!
933 * brief Sends a STOP signal on the I2C bus.
934 *
935 * retval kStatus_Success Successfully send the stop signal.
936 * retval kStatus_I2C_Timeout Send stop signal failed, timeout.
937 */
I2C_MasterStop(I2C_Type * base)938 status_t I2C_MasterStop(I2C_Type *base)
939 {
940 status_t result = kStatus_Success;
941
942 /* Issue the STOP command on the bus. */
943 base->C1 &= ~(uint8_t)(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
944
945 #if I2C_RETRY_TIMES != 0U
946 uint32_t waitTimes = I2C_RETRY_TIMES;
947 /* Wait until bus not busy. */
948 while ((0U != (base->S & (uint8_t)kI2C_BusBusyFlag)) && (0U != waitTimes))
949 {
950 waitTimes--;
951 }
952
953 if (0U == waitTimes)
954 {
955 result = kStatus_I2C_Timeout;
956 }
957 #else
958 /* Wait until data transfer complete. */
959 while (0U != (base->S & (uint8_t)kI2C_BusBusyFlag))
960 {
961 }
962 #endif
963
964 return result;
965 }
966
967 /*!
968 * brief Gets the I2C status flags.
969 *
970 * param base I2C base pointer
971 * return status flag, use status flag to AND #_i2c_flags to get the related status.
972 */
I2C_MasterGetStatusFlags(I2C_Type * base)973 uint32_t I2C_MasterGetStatusFlags(I2C_Type *base)
974 {
975 uint32_t statusFlags = base->S;
976
977 #ifdef I2C_HAS_STOP_DETECT
978 /* Look up the STOPF bit from the filter register. */
979 if (0U != (base->FLT & I2C_FLT_STOPF_MASK))
980 {
981 statusFlags |= (uint32_t)kI2C_StopDetectFlag;
982 }
983 #endif
984
985 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
986 /* Look up the STARTF bit from the filter register. */
987 if (0U != (base->FLT & I2C_FLT_STARTF_MASK))
988 {
989 statusFlags |= (uint32_t)kI2C_StartDetectFlag;
990 }
991 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
992
993 return statusFlags;
994 }
995
996 /*!
997 * brief Performs a polling send transaction on the I2C bus.
998 *
999 * param base The I2C peripheral base pointer.
1000 * param txBuff The pointer to the data to be transferred.
1001 * param txSize The length in bytes of the data to be transferred.
1002 * param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag
1003 * to issue a stop and kI2C_TransferNoStop to not send a stop.
1004 * retval kStatus_Success Successfully complete the data transmission.
1005 * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
1006 * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
1007 */
I2C_MasterWriteBlocking(I2C_Type * base,const uint8_t * txBuff,size_t txSize,uint32_t flags)1008 status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize, uint32_t flags)
1009 {
1010 status_t result = kStatus_Success;
1011 uint8_t statusFlags = 0;
1012
1013 #if I2C_RETRY_TIMES != 0U
1014 uint32_t waitTimes = I2C_RETRY_TIMES;
1015 /* Wait until the data register is ready for transmit. */
1016 while ((0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) && (0U != waitTimes))
1017 {
1018 waitTimes--;
1019 }
1020 if (0U == waitTimes)
1021 {
1022 return kStatus_I2C_Timeout;
1023 }
1024 #else
1025 /* Wait until the data register is ready for transmit. */
1026 while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag))
1027 {
1028 }
1029 #endif
1030
1031 /* Clear the IICIF flag. */
1032 base->S = (uint8_t)kI2C_IntPendingFlag;
1033
1034 /* Setup the I2C peripheral to transmit data. */
1035 base->C1 |= I2C_C1_TX_MASK;
1036
1037 while (0U != (txSize--))
1038 {
1039 /* Send a byte of data. */
1040 base->D = *txBuff++;
1041
1042 #if I2C_RETRY_TIMES != 0U
1043 waitTimes = I2C_RETRY_TIMES;
1044 /* Wait until data transfer complete. */
1045 while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
1046 {
1047 waitTimes--;
1048 }
1049 if (0U == waitTimes)
1050 {
1051 return kStatus_I2C_Timeout;
1052 }
1053 #else
1054 /* Wait until data transfer complete. */
1055 while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
1056 {
1057 }
1058 #endif
1059 statusFlags = base->S;
1060
1061 /* Clear the IICIF flag. */
1062 base->S = (uint8_t)kI2C_IntPendingFlag;
1063
1064 /* Check if arbitration lost or no acknowledgement (NAK), return failure status. */
1065 if (0U != (statusFlags & (uint8_t)kI2C_ArbitrationLostFlag))
1066 {
1067 base->S = (uint8_t)kI2C_ArbitrationLostFlag;
1068 result = kStatus_I2C_ArbitrationLost;
1069 }
1070
1071 if ((0U != (statusFlags & (uint8_t)kI2C_ReceiveNakFlag)) && (0U != txSize))
1072 {
1073 base->S = (uint8_t)kI2C_ReceiveNakFlag;
1074 result = kStatus_I2C_Nak;
1075 }
1076
1077 if (result != kStatus_Success)
1078 {
1079 /* Breaking out of the send loop. */
1080 break;
1081 }
1082 }
1083
1084 if (((result == kStatus_Success) && (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag))) ||
1085 (result == kStatus_I2C_Nak))
1086 {
1087 /* Clear the IICIF flag. */
1088 base->S = (uint8_t)kI2C_IntPendingFlag;
1089
1090 /* Send stop. */
1091 result = I2C_MasterStop(base);
1092 }
1093
1094 return result;
1095 }
1096
1097 /*!
1098 * brief Performs a polling receive transaction on the I2C bus.
1099 *
1100 * note The I2C_MasterReadBlocking function stops the bus before reading the final byte.
1101 * Without stopping the bus prior for the final read, the bus issues another read, resulting
1102 * in garbage data being read into the data register.
1103 *
1104 * param base I2C peripheral base pointer.
1105 * param rxBuff The pointer to the data to store the received data.
1106 * param rxSize The length in bytes of the data to be received.
1107 * param flags Transfer control flag to decide whether need to send a stop, use kI2C_TransferDefaultFlag
1108 * to issue a stop and kI2C_TransferNoStop to not send a stop.
1109 * retval kStatus_Success Successfully complete the data transmission.
1110 * retval kStatus_I2C_Timeout Send stop signal failed, timeout.
1111 */
I2C_MasterReadBlocking(I2C_Type * base,uint8_t * rxBuff,size_t rxSize,uint32_t flags)1112 status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize, uint32_t flags)
1113 {
1114 status_t result = kStatus_Success;
1115
1116 #if I2C_RETRY_TIMES != 0U
1117 uint32_t waitTimes = I2C_RETRY_TIMES;
1118 /* Wait until the data register is ready for transmit. */
1119 while ((0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) && (0U != waitTimes))
1120 {
1121 waitTimes--;
1122 }
1123 if (0U == waitTimes)
1124 {
1125 return kStatus_I2C_Timeout;
1126 }
1127 #else
1128 /* Wait until the data register is ready for transmit. */
1129 while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag))
1130 {
1131 }
1132 #endif
1133
1134 /* Clear the IICIF flag. */
1135 base->S = (uint8_t)kI2C_IntPendingFlag;
1136
1137 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
1138 base->SMB |= I2C_SMB_FACK_MASK;
1139 #endif
1140
1141 /* Setup the I2C peripheral to receive data. */
1142 base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
1143
1144 /* Do dummy read. */
1145 (void)base->D;
1146
1147 if (rxSize == 1U)
1148 {
1149 /* Issue NACK on read. */
1150 base->C1 |= I2C_C1_TXAK_MASK;
1151 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
1152 base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK;
1153 #endif
1154 }
1155
1156 while (0U != (rxSize--))
1157 {
1158 #if I2C_RETRY_TIMES != 0U
1159 waitTimes = I2C_RETRY_TIMES;
1160 /* Wait until data transfer complete. */
1161 while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
1162 {
1163 waitTimes--;
1164 }
1165 if (0U == waitTimes)
1166 {
1167 return kStatus_I2C_Timeout;
1168 }
1169 #else
1170 /* Wait until data transfer complete. */
1171 while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
1172 {
1173 }
1174 #endif
1175
1176 if (rxSize == 0U)
1177 {
1178 if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag))
1179 {
1180 /* Issue STOP command before reading last byte. */
1181 result = I2C_MasterStop(base);
1182 }
1183 else
1184 {
1185 /* Change direction to Tx to avoid extra clocks. */
1186 base->C1 |= I2C_C1_TX_MASK;
1187 }
1188 }
1189
1190 /* Clear the IICIF flag. */
1191 base->S = (uint8_t)kI2C_IntPendingFlag;
1192
1193 /* Read from the data register. */
1194 *rxBuff++ = base->D;
1195
1196 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
1197 if (rxSize != 0U)
1198 {
1199 I2C_MasterAckByte(base);
1200 }
1201 #endif
1202
1203 if (rxSize == 1U)
1204 {
1205 base->C1 |= I2C_C1_TXAK_MASK;
1206 #if defined(I2C_MASTER_FACK_CONTROL) && I2C_MASTER_FACK_CONTROL
1207 /* Issue NACK on read. */
1208 base->SMB &= ~(uint8_t)I2C_SMB_FACK_MASK;
1209 #endif
1210 }
1211 }
1212
1213 return result;
1214 }
1215
1216 /*!
1217 * brief Performs a master polling transfer on the I2C bus.
1218 *
1219 * note The API does not return until the transfer succeeds or fails due
1220 * to arbitration lost or receiving a NAK.
1221 *
1222 * param base I2C peripheral base address.
1223 * param xfer Pointer to the transfer structure.
1224 * retval kStatus_Success Successfully complete the data transmission.
1225 * retval kStatus_I2C_Busy Previous transmission still not finished.
1226 * retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
1227 * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
1228 * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
1229 */
I2C_MasterTransferBlocking(I2C_Type * base,i2c_master_transfer_t * xfer)1230 status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer)
1231 {
1232 assert(NULL != xfer);
1233
1234 i2c_direction_t direction = xfer->direction;
1235 status_t result = kStatus_Success;
1236
1237 /* Clear all status before transfer. */
1238 I2C_MasterClearStatusFlags(base, (uint32_t)kClearFlags);
1239
1240 #if I2C_RETRY_TIMES != 0U
1241 uint32_t waitTimes = I2C_RETRY_TIMES;
1242 /* Wait until the data register is ready for transmit. */
1243 while ((0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag)) && (0U != waitTimes))
1244 {
1245 waitTimes--;
1246 }
1247 if (0U == waitTimes)
1248 {
1249 return kStatus_I2C_Timeout;
1250 }
1251 #else
1252 /* Wait until the data register is ready for transmit. */
1253 while (0U == (base->S & (uint8_t)kI2C_TransferCompleteFlag))
1254 {
1255 }
1256 #endif
1257
1258 /* Change to send write address when it's a read operation with command. */
1259 if ((xfer->subaddressSize > 0U) && (xfer->direction == kI2C_Read))
1260 {
1261 direction = kI2C_Write;
1262 }
1263
1264 /* Handle no start option, only support write with no start signal. */
1265 if (0U != (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag))
1266 {
1267 if (direction == kI2C_Read)
1268 {
1269 return kStatus_InvalidArgument;
1270 }
1271 }
1272 /* If repeated start is requested, send repeated start. */
1273 else if (0U != (xfer->flags & (uint32_t)kI2C_TransferRepeatedStartFlag))
1274 {
1275 result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, direction);
1276 }
1277 else /* For normal transfer, send start. */
1278 {
1279 result = I2C_MasterStart(base, xfer->slaveAddress, direction);
1280 }
1281
1282 if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag))
1283 {
1284 /* Return if error. */
1285 if (kStatus_Success != result)
1286 {
1287 return result;
1288 }
1289
1290 #if I2C_RETRY_TIMES != 0U
1291 waitTimes = I2C_RETRY_TIMES;
1292 /* Wait until data transfer complete. */
1293 while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
1294 {
1295 waitTimes--;
1296 }
1297 if (0U == waitTimes)
1298 {
1299 return kStatus_I2C_Timeout;
1300 }
1301 #else
1302 /* Wait until data transfer complete. */
1303 while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
1304 {
1305 }
1306 #endif
1307 /* Check if there's transfer error. */
1308 result = I2C_CheckAndClearError(base, base->S);
1309
1310 /* Return if error. */
1311 if (kStatus_Success != result)
1312 {
1313 if (result == kStatus_I2C_Nak)
1314 {
1315 result = kStatus_I2C_Addr_Nak;
1316
1317 (void)I2C_MasterStop(base);
1318 }
1319
1320 return result;
1321 }
1322 }
1323
1324 /* Send subaddress. */
1325 if (0U != (xfer->subaddressSize))
1326 {
1327 do
1328 {
1329 /* Clear interrupt pending flag. */
1330 base->S = (uint8_t)kI2C_IntPendingFlag;
1331
1332 xfer->subaddressSize--;
1333 base->D = (uint8_t)((xfer->subaddress) >> (8U * xfer->subaddressSize));
1334
1335 #if I2C_RETRY_TIMES != 0U
1336 waitTimes = I2C_RETRY_TIMES;
1337 /* Wait until data transfer complete. */
1338 while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
1339 {
1340 waitTimes--;
1341 }
1342 if (0U == waitTimes)
1343 {
1344 return kStatus_I2C_Timeout;
1345 }
1346 #else
1347 /* Wait until data transfer complete. */
1348 while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
1349 {
1350 }
1351 #endif
1352
1353 /* Check if there's transfer error. */
1354 result = I2C_CheckAndClearError(base, base->S);
1355
1356 if (0 != result)
1357 {
1358 if (result == kStatus_I2C_Nak)
1359 {
1360 (void)I2C_MasterStop(base);
1361 }
1362
1363 return result;
1364 }
1365
1366 } while (xfer->subaddressSize > 0u);
1367
1368 if (xfer->direction == kI2C_Read)
1369 {
1370 /* Clear pending flag. */
1371 base->S = (uint8_t)kI2C_IntPendingFlag;
1372
1373 /* Send repeated start and slave address. */
1374 result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, kI2C_Read);
1375
1376 /* Return if error. */
1377 if (kStatus_Success != result)
1378 {
1379 return result;
1380 }
1381
1382 #if I2C_RETRY_TIMES != 0U
1383 waitTimes = I2C_RETRY_TIMES;
1384 /* Wait until data transfer complete. */
1385 while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
1386 {
1387 waitTimes--;
1388 }
1389 if (0U == waitTimes)
1390 {
1391 return kStatus_I2C_Timeout;
1392 }
1393 #else
1394 /* Wait until data transfer complete. */
1395 while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
1396 {
1397 }
1398 #endif
1399
1400 /* Check if there's transfer error. */
1401 result = I2C_CheckAndClearError(base, base->S);
1402
1403 if (kStatus_Success != result)
1404 {
1405 if (result == kStatus_I2C_Nak)
1406 {
1407 result = kStatus_I2C_Addr_Nak;
1408
1409 (void)I2C_MasterStop(base);
1410 }
1411
1412 return result;
1413 }
1414 }
1415 }
1416
1417 /* Transmit data. */
1418 if (xfer->direction == kI2C_Write)
1419 {
1420 if (xfer->dataSize > 0U)
1421 {
1422 uint8_t *tmpData = xfer->data;
1423 size_t tmpDataSize = xfer->dataSize;
1424 uint32_t tmpFlags = xfer->flags;
1425 /* Send Data. */
1426 result = I2C_MasterWriteBlocking(base, tmpData, tmpDataSize, tmpFlags);
1427 }
1428 else if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStopFlag))
1429 {
1430 /* Send stop. */
1431 result = I2C_MasterStop(base);
1432 }
1433 else
1434 {
1435 /* Add this to fix MISRA C2012 rule15.7 issue: Empty else without comment. */
1436 }
1437 }
1438
1439 /* Receive Data. */
1440 if ((xfer->dataSize > 0u) && (xfer->direction == kI2C_Read))
1441 {
1442 uint8_t *tmpData = xfer->data;
1443 size_t tmpDataSize = xfer->dataSize;
1444 uint32_t tmpFlags = xfer->flags;
1445
1446 result = I2C_MasterReadBlocking(base, tmpData, tmpDataSize, tmpFlags);
1447 }
1448
1449 return result;
1450 }
1451
1452 /*!
1453 * brief Initializes the I2C handle which is used in transactional functions.
1454 *
1455 * param base I2C base pointer.
1456 * param handle pointer to i2c_master_handle_t structure to store the transfer state.
1457 * param callback pointer to user callback function.
1458 * param userData user parameter passed to the callback function.
1459 */
I2C_MasterTransferCreateHandle(I2C_Type * base,i2c_master_handle_t * handle,i2c_master_transfer_callback_t callback,void * userData)1460 void I2C_MasterTransferCreateHandle(I2C_Type *base,
1461 i2c_master_handle_t *handle,
1462 i2c_master_transfer_callback_t callback,
1463 void *userData)
1464 {
1465 assert(NULL != handle);
1466
1467 uint32_t instance = I2C_GetInstance(base);
1468
1469 /* Zero handle. */
1470 (void)memset(handle, 0, sizeof(*handle));
1471
1472 /* Set callback and userData. */
1473 handle->completionCallback = callback;
1474 handle->userData = userData;
1475
1476 /* Save the context in global variables to support the double weak mechanism. */
1477 s_i2cHandle[instance] = handle;
1478
1479 /* Save master interrupt handler. */
1480 s_i2cMasterIsr = I2C_MasterTransferHandleIRQ;
1481
1482 /* Enable NVIC interrupt. */
1483 (void)EnableIRQ(s_i2cIrqs[instance]);
1484 }
1485
1486 /*!
1487 * brief Performs a master interrupt non-blocking transfer on the I2C bus.
1488 *
1489 * note Calling the API returns immediately after transfer initiates. The user needs
1490 * to call I2C_MasterGetTransferCount to poll the transfer status to check whether
1491 * the transfer is finished. If the return status is not kStatus_I2C_Busy, the transfer
1492 * is finished.
1493 *
1494 * param base I2C base pointer.
1495 * param handle pointer to i2c_master_handle_t structure which stores the transfer state.
1496 * param xfer pointer to i2c_master_transfer_t structure.
1497 * retval kStatus_Success Successfully start the data transmission.
1498 * retval kStatus_I2C_Busy Previous transmission still not finished.
1499 * retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
1500 */
I2C_MasterTransferNonBlocking(I2C_Type * base,i2c_master_handle_t * handle,i2c_master_transfer_t * xfer)1501 status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer)
1502 {
1503 assert(NULL != handle);
1504 assert(NULL != xfer);
1505
1506 status_t result = kStatus_Success;
1507
1508 /* Check if the I2C bus is idle - if not return busy status. */
1509 if (handle->state != (uint8_t)kIdleState)
1510 {
1511 result = kStatus_I2C_Busy;
1512 }
1513 else
1514 {
1515 /* Start up the master transfer state machine. */
1516 result = I2C_InitTransferStateMachine(base, handle, xfer);
1517
1518 if (result == kStatus_Success)
1519 {
1520 /* Enable the I2C interrupts. */
1521 I2C_EnableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable);
1522 }
1523 }
1524
1525 return result;
1526 }
1527
1528 /*!
1529 * brief Aborts an interrupt non-blocking transfer early.
1530 *
1531 * note This API can be called at any time when an interrupt non-blocking transfer initiates
1532 * to abort the transfer early.
1533 *
1534 * param base I2C base pointer.
1535 * param handle pointer to i2c_master_handle_t structure which stores the transfer state
1536 * retval kStatus_I2C_Timeout Timeout during polling flag.
1537 * retval kStatus_Success Successfully abort the transfer.
1538 */
I2C_MasterTransferAbort(I2C_Type * base,i2c_master_handle_t * handle)1539 status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
1540 {
1541 assert(NULL != handle);
1542
1543 #if I2C_RETRY_TIMES != 0U
1544 uint32_t waitTimes = I2C_RETRY_TIMES;
1545 #endif
1546
1547 /* Disable interrupt. */
1548 I2C_DisableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable);
1549
1550 /* Reset the state to idle. */
1551 handle->state = (uint8_t)kIdleState;
1552
1553 /* If the bus is already in use, but not by us */
1554 if (0U == (base->C1 & I2C_C1_MST_MASK))
1555 {
1556 return kStatus_I2C_Busy;
1557 }
1558
1559 /* Send STOP signal. */
1560 if (handle->transfer.direction == kI2C_Read)
1561 {
1562 base->C1 |= I2C_C1_TXAK_MASK;
1563
1564 #if I2C_RETRY_TIMES != 0U
1565 /* Wait until data transfer complete. */
1566 while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
1567 {
1568 waitTimes--;
1569 }
1570 if (0U == waitTimes)
1571 {
1572 return kStatus_I2C_Timeout;
1573 }
1574 #else
1575 /* Wait until data transfer complete. */
1576 while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
1577 {
1578 }
1579 #endif
1580 base->S = (uint8_t)kI2C_IntPendingFlag;
1581
1582 base->C1 &= ~(uint8_t)(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
1583 (void)base->D;
1584 }
1585 else
1586 {
1587 #if I2C_RETRY_TIMES != 0U
1588 /* Wait until data transfer complete. */
1589 while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
1590 {
1591 waitTimes--;
1592 }
1593 if (0U == waitTimes)
1594 {
1595 return kStatus_I2C_Timeout;
1596 }
1597 #else
1598 /* Wait until data transfer complete. */
1599 while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
1600 {
1601 }
1602 #endif
1603 base->S = (uint8_t)kI2C_IntPendingFlag;
1604 base->C1 &= ~(uint8_t)(I2C_C1_MST_MASK | I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
1605 }
1606
1607 return kStatus_Success;
1608 }
1609
1610 /*!
1611 * brief Gets the master transfer status during a interrupt non-blocking transfer.
1612 *
1613 * param base I2C base pointer.
1614 * param handle pointer to i2c_master_handle_t structure which stores the transfer state.
1615 * param count Number of bytes transferred so far by the non-blocking transaction.
1616 * retval kStatus_InvalidArgument count is Invalid.
1617 * retval kStatus_Success Successfully return the count.
1618 */
I2C_MasterTransferGetCount(I2C_Type * base,i2c_master_handle_t * handle,size_t * count)1619 status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
1620 {
1621 assert(NULL != handle);
1622
1623 if (NULL == count)
1624 {
1625 return kStatus_InvalidArgument;
1626 }
1627
1628 *count = handle->transferSize - handle->transfer.dataSize;
1629
1630 return kStatus_Success;
1631 }
1632
1633 /*!
1634 * brief Master interrupt handler.
1635 *
1636 * param base I2C base pointer.
1637 * param i2cHandle pointer to i2c_master_handle_t structure.
1638 */
I2C_MasterTransferHandleIRQ(I2C_Type * base,void * i2cHandle)1639 void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
1640 {
1641 assert(NULL != i2cHandle);
1642
1643 i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle;
1644 status_t result = kStatus_Success;
1645 bool isDone;
1646
1647 /* Clear the interrupt flag. */
1648 base->S = (uint8_t)kI2C_IntPendingFlag;
1649
1650 /* Check transfer complete flag. */
1651 result = I2C_MasterTransferRunStateMachine(base, handle, &isDone);
1652
1653 if ((true == isDone) || (0 != result))
1654 {
1655 /* Send stop command if transfer done or received Nak. */
1656 if ((0U == (handle->transfer.flags & (uint32_t)kI2C_TransferNoStopFlag)) || (result == kStatus_I2C_Nak) ||
1657 (result == kStatus_I2C_Addr_Nak))
1658 {
1659 /* Ensure stop command is a need. */
1660 if (0U != (base->C1 & I2C_C1_MST_MASK))
1661 {
1662 if (I2C_MasterStop(base) != kStatus_Success)
1663 {
1664 result = kStatus_I2C_Timeout;
1665 }
1666 }
1667 }
1668
1669 /* Restore handle to idle state. */
1670 handle->state = (uint8_t)kIdleState;
1671
1672 /* Disable interrupt. */
1673 I2C_DisableInterrupts(base, (uint32_t)kI2C_GlobalInterruptEnable);
1674
1675 /* Call the callback function after the function has completed. */
1676 if (NULL != (handle->completionCallback))
1677 {
1678 handle->completionCallback(base, handle, result, handle->userData);
1679 }
1680 }
1681 }
1682
1683 /*!
1684 * brief Initializes the I2C peripheral. Call this API to ungate the I2C clock
1685 * and initialize the I2C with the slave configuration.
1686 *
1687 * note This API should be called at the beginning of the application.
1688 * Otherwise, any operation to the I2C module can cause a hard fault
1689 * because the clock is not enabled. The configuration structure can partly be set
1690 * with default values by I2C_SlaveGetDefaultConfig() or it can be custom filled by the user.
1691 * This is an example.
1692 * code
1693 * i2c_slave_config_t config = {
1694 * .enableSlave = true,
1695 * .enableGeneralCall = false,
1696 * .addressingMode = kI2C_Address7bit,
1697 * .slaveAddress = 0x1DU,
1698 * .enableWakeUp = false,
1699 * .enablehighDrive = false,
1700 * .enableBaudRateCtl = false,
1701 * .sclStopHoldTime_ns = 4000
1702 * };
1703 * I2C_SlaveInit(I2C0, &config, 12000000U);
1704 * endcode
1705 *
1706 * param base I2C base pointer
1707 * param slaveConfig A pointer to the slave configuration structure
1708 * param srcClock_Hz I2C peripheral clock frequency in Hz
1709 */
I2C_SlaveInit(I2C_Type * base,const i2c_slave_config_t * slaveConfig,uint32_t srcClock_Hz)1710 void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, uint32_t srcClock_Hz)
1711 {
1712 assert(NULL != slaveConfig);
1713
1714 uint8_t tmpReg;
1715
1716 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1717 CLOCK_EnableClock(s_i2cClocks[I2C_GetInstance(base)]);
1718 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1719
1720 /* Reset the module. */
1721 base->A1 = 0;
1722 base->F = 0;
1723 base->C1 = 0;
1724 base->S = 0xFFU;
1725 base->C2 = 0;
1726 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
1727 base->FLT = 0x50U;
1728 #elif defined(FSL_FEATURE_I2C_HAS_STOP_DETECT) && FSL_FEATURE_I2C_HAS_STOP_DETECT
1729 base->FLT = 0x40U;
1730 #endif
1731 base->RA = 0;
1732
1733 /* Configure addressing mode. */
1734 switch (slaveConfig->addressingMode)
1735 {
1736 case kI2C_Address7bit:
1737 base->A1 = (uint8_t)(((uint32_t)(slaveConfig->slaveAddress)) << 1U);
1738 break;
1739
1740 case kI2C_RangeMatch:
1741 assert(slaveConfig->slaveAddress < slaveConfig->upperAddress);
1742 base->A1 = (uint8_t)(((uint32_t)(slaveConfig->slaveAddress)) << 1U);
1743 base->RA = (uint8_t)(((uint32_t)(slaveConfig->upperAddress)) << 1U);
1744 base->C2 |= I2C_C2_RMEN_MASK;
1745 break;
1746
1747 default:
1748 /* All the cases have been listed above, the default clause should not be reached. */
1749 assert(false);
1750 break;
1751 }
1752
1753 /* Configure low power wake up feature. */
1754 tmpReg = base->C1;
1755 tmpReg &= ~(uint8_t)I2C_C1_WUEN_MASK;
1756 base->C1 = tmpReg | I2C_C1_WUEN(slaveConfig->enableWakeUp) | I2C_C1_IICEN(slaveConfig->enableSlave);
1757
1758 /* Configure general call & baud rate control. */
1759 tmpReg = base->C2;
1760 tmpReg &= ~(uint8_t)(I2C_C2_SBRC_MASK | I2C_C2_GCAEN_MASK);
1761 tmpReg |= I2C_C2_SBRC(slaveConfig->enableBaudRateCtl) | I2C_C2_GCAEN(slaveConfig->enableGeneralCall);
1762 base->C2 = tmpReg;
1763
1764 /* Enable/Disable double buffering. */
1765 #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
1766 tmpReg = (uint8_t)(base->S2 & (~I2C_S2_DFEN_MASK));
1767 base->S2 = tmpReg | I2C_S2_DFEN(slaveConfig->enableDoubleBuffering);
1768 #endif
1769
1770 /* Set hold time. */
1771 I2C_SetHoldTime(base, slaveConfig->sclStopHoldTime_ns, srcClock_Hz);
1772 }
1773
1774 /*!
1775 * brief De-initializes the I2C slave peripheral. Calling this API gates the I2C clock.
1776 * The I2C slave module can't work unless the I2C_SlaveInit is called to enable the clock.
1777 * param base I2C base pointer
1778 */
I2C_SlaveDeinit(I2C_Type * base)1779 void I2C_SlaveDeinit(I2C_Type *base)
1780 {
1781 /* Disable I2C module. */
1782 I2C_Enable(base, false);
1783
1784 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1785 /* Disable I2C clock. */
1786 CLOCK_DisableClock(s_i2cClocks[I2C_GetInstance(base)]);
1787 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1788 }
1789
1790 /*!
1791 * brief Sets the I2C slave configuration structure to default values.
1792 *
1793 * The purpose of this API is to get the configuration structure initialized for use in the I2C_SlaveConfigure().
1794 * Modify fields of the structure before calling the I2C_SlaveConfigure().
1795 * This is an example.
1796 * code
1797 * i2c_slave_config_t config;
1798 * I2C_SlaveGetDefaultConfig(&config);
1799 * endcode
1800 * param slaveConfig A pointer to the slave configuration structure.
1801 */
I2C_SlaveGetDefaultConfig(i2c_slave_config_t * slaveConfig)1802 void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
1803 {
1804 assert(NULL != slaveConfig);
1805
1806 /* Initializes the configure structure to zero. */
1807 (void)memset(slaveConfig, 0, sizeof(*slaveConfig));
1808
1809 /* By default slave is addressed with 7-bit address. */
1810 slaveConfig->addressingMode = kI2C_Address7bit;
1811
1812 /* General call mode is disabled by default. */
1813 slaveConfig->enableGeneralCall = false;
1814
1815 /* Slave address match waking up MCU from low power mode is disabled. */
1816 slaveConfig->enableWakeUp = false;
1817
1818 /* Independent slave mode baud rate at maximum frequency is disabled. */
1819 slaveConfig->enableBaudRateCtl = false;
1820
1821 /* Default enable double buffering. */
1822 #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE
1823 slaveConfig->enableDoubleBuffering = true;
1824 #endif
1825
1826 /* Set default SCL stop hold time to 4us which is minimum requirement in I2C spec. */
1827 slaveConfig->sclStopHoldTime_ns = 4000;
1828
1829 /* Enable the I2C peripheral. */
1830 slaveConfig->enableSlave = true;
1831 }
1832
1833 /*!
1834 * brief Performs a polling send transaction on the I2C bus.
1835 *
1836 * param base The I2C peripheral base pointer.
1837 * param txBuff The pointer to the data to be transferred.
1838 * param txSize The length in bytes of the data to be transferred.
1839 * retval kStatus_Success Successfully complete the data transmission.
1840 * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
1841 * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer.
1842 */
I2C_SlaveWriteBlocking(I2C_Type * base,const uint8_t * txBuff,size_t txSize)1843 status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t txSize)
1844 {
1845 status_t result = kStatus_Success;
1846
1847 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
1848 /* Check start flag. */
1849 while (0U == (base->FLT & I2C_FLT_STARTF_MASK))
1850 {
1851 }
1852 /* Clear STARTF flag. */
1853 base->FLT |= I2C_FLT_STARTF_MASK;
1854 /* Clear the IICIF flag. */
1855 base->S = (uint8_t)kI2C_IntPendingFlag;
1856 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
1857
1858 #if I2C_RETRY_TIMES != 0U
1859 uint32_t waitTimes = I2C_RETRY_TIMES;
1860 /* Wait until data transfer complete. */
1861 while ((0U == (base->S & (uint8_t)kI2C_AddressMatchFlag)) && (0U != waitTimes))
1862 {
1863 waitTimes--;
1864 }
1865 if (0U == waitTimes)
1866 {
1867 return kStatus_I2C_Timeout;
1868 }
1869 #else
1870 /* Wait for address match flag. */
1871 while (0U == (base->S & (uint8_t)kI2C_AddressMatchFlag))
1872 {
1873 }
1874 #endif
1875 /* Read dummy to release bus. */
1876 (void)base->D;
1877
1878 result = I2C_MasterWriteBlocking(base, txBuff, txSize, (uint32_t)kI2C_TransferNoStopFlag);
1879
1880 /* Switch to receive mode. */
1881 base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
1882
1883 /* Read dummy to release bus. */
1884 (void)base->D;
1885
1886 return result;
1887 }
1888
1889 /*!
1890 * brief Performs a polling receive transaction on the I2C bus.
1891 *
1892 * param base I2C peripheral base pointer.
1893 * param rxBuff The pointer to the data to store the received data.
1894 * param rxSize The length in bytes of the data to be received.
1895 * retval kStatus_Success Successfully complete data receive.
1896 * retval kStatus_I2C_Timeout Wait status flag timeout.
1897 */
I2C_SlaveReadBlocking(I2C_Type * base,uint8_t * rxBuff,size_t rxSize)1898 status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize)
1899 {
1900 status_t result = kStatus_Success;
1901
1902 /* Wait until address match. */
1903 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
1904 /* Check start flag. */
1905 while (0U == (base->FLT & I2C_FLT_STARTF_MASK))
1906 {
1907 }
1908 /* Clear STARTF flag. */
1909 base->FLT |= I2C_FLT_STARTF_MASK;
1910 /* Clear the IICIF flag. */
1911 base->S = (uint8_t)kI2C_IntPendingFlag;
1912 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
1913
1914 #if I2C_RETRY_TIMES != 0U
1915 uint32_t waitTimes = I2C_RETRY_TIMES;
1916 /* Wait for address match and int pending flag. */
1917 while ((0U == (base->S & (uint8_t)kI2C_AddressMatchFlag)) && (0U != waitTimes))
1918 {
1919 waitTimes--;
1920 }
1921 if (0U == waitTimes)
1922 {
1923 return kStatus_I2C_Timeout;
1924 }
1925
1926 waitTimes = I2C_RETRY_TIMES;
1927 while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
1928 {
1929 waitTimes--;
1930 }
1931 if (0U == waitTimes)
1932 {
1933 return kStatus_I2C_Timeout;
1934 }
1935 #else
1936 /* Wait for address match and int pending flag. */
1937 while (0U == (base->S & (uint8_t)kI2C_AddressMatchFlag))
1938 {
1939 }
1940 while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
1941 {
1942 }
1943 #endif
1944
1945 /* Read dummy to release bus. */
1946 (void)base->D;
1947
1948 /* Clear the IICIF flag. */
1949 base->S = (uint8_t)kI2C_IntPendingFlag;
1950
1951 /* Setup the I2C peripheral to receive data. */
1952 base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK);
1953
1954 while (0U != (rxSize--))
1955 {
1956 #if I2C_RETRY_TIMES != 0U
1957 waitTimes = I2C_RETRY_TIMES;
1958 /* Wait until data transfer complete. */
1959 while ((0U == (base->S & (uint8_t)kI2C_IntPendingFlag)) && (0U != waitTimes))
1960 {
1961 waitTimes--;
1962 }
1963 if (0U == waitTimes)
1964 {
1965 return kStatus_I2C_Timeout;
1966 }
1967 #else
1968 /* Wait until data transfer complete. */
1969 while (0U == (base->S & (uint8_t)kI2C_IntPendingFlag))
1970 {
1971 }
1972 #endif
1973 /* Clear the IICIF flag. */
1974 base->S = (uint8_t)kI2C_IntPendingFlag;
1975
1976 /* Read from the data register. */
1977 *rxBuff++ = base->D;
1978 }
1979
1980 return result;
1981 }
1982
1983 /*!
1984 * brief Initializes the I2C handle which is used in transactional functions.
1985 *
1986 * param base I2C base pointer.
1987 * param handle pointer to i2c_slave_handle_t structure to store the transfer state.
1988 * param callback pointer to user callback function.
1989 * param userData user parameter passed to the callback function.
1990 */
I2C_SlaveTransferCreateHandle(I2C_Type * base,i2c_slave_handle_t * handle,i2c_slave_transfer_callback_t callback,void * userData)1991 void I2C_SlaveTransferCreateHandle(I2C_Type *base,
1992 i2c_slave_handle_t *handle,
1993 i2c_slave_transfer_callback_t callback,
1994 void *userData)
1995 {
1996 assert(NULL != handle);
1997
1998 uint32_t instance = I2C_GetInstance(base);
1999
2000 /* Zero handle. */
2001 (void)memset(handle, 0, sizeof(*handle));
2002
2003 /* Set callback and userData. */
2004 handle->callback = callback;
2005 handle->userData = userData;
2006
2007 /* Save the context in global variables to support the double weak mechanism. */
2008 s_i2cHandle[instance] = handle;
2009
2010 /* Save slave interrupt handler. */
2011 s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ;
2012
2013 /* Enable NVIC interrupt. */
2014 (void)EnableIRQ(s_i2cIrqs[instance]);
2015 }
2016
2017 /*!
2018 * brief Starts accepting slave transfers.
2019 *
2020 * Call this API after calling the I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing
2021 * transactions driven by an I2C master. The slave monitors the I2C bus and passes events to the
2022 * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked
2023 * from the interrupt context.
2024 *
2025 * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to
2026 * the OR'd combination of #i2c_slave_transfer_event_t enumerators for the events you wish to receive.
2027 * The #kI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need
2028 * to be included in the mask. Alternatively, pass 0 to get a default set of only the transmit and
2029 * receive events that are always enabled. In addition, the #kI2C_SlaveAllEvents constant is provided as
2030 * a convenient way to enable all events.
2031 *
2032 * param base The I2C peripheral base address.
2033 * param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state.
2034 * param eventMask Bit mask formed by OR'ing together #i2c_slave_transfer_event_t enumerators to specify
2035 * which events to send to the callback. Other accepted values are 0 to get a default set of
2036 * only the transmit and receive events, and #kI2C_SlaveAllEvents to enable all events.
2037 *
2038 * retval #kStatus_Success Slave transfers were successfully started.
2039 * retval #kStatus_I2C_Busy Slave transfers have already been started on this handle.
2040 */
I2C_SlaveTransferNonBlocking(I2C_Type * base,i2c_slave_handle_t * handle,uint32_t eventMask)2041 status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint32_t eventMask)
2042 {
2043 assert(NULL != handle);
2044
2045 /* Check if the I2C bus is idle - if not return busy status. */
2046 if (true == handle->isBusy)
2047 {
2048 return kStatus_I2C_Busy;
2049 }
2050 else
2051 {
2052 /* Disable LPI2C IRQ sources while we configure stuff. */
2053 I2C_DisableInterrupts(base, (uint32_t)kIrqFlags);
2054
2055 /* Clear transfer in handle. */
2056 (void)memset(&handle->transfer, 0, sizeof(handle->transfer));
2057
2058 /* Record that we're busy. */
2059 handle->isBusy = true;
2060
2061 /* Set up event mask. tx and rx are always enabled. */
2062 handle->eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent |
2063 (uint32_t)kI2C_SlaveGenaralcallEvent;
2064
2065 /* Clear all flags. */
2066 I2C_SlaveClearStatusFlags(base, (uint32_t)kClearFlags);
2067
2068 /* Enable I2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */
2069 I2C_EnableInterrupts(base, (uint32_t)kIrqFlags);
2070 }
2071
2072 return kStatus_Success;
2073 }
2074
2075 /*!
2076 * brief Aborts the slave transfer.
2077 *
2078 * note This API can be called at any time to stop slave for handling the bus events.
2079 *
2080 * param base I2C base pointer.
2081 * param handle pointer to i2c_slave_handle_t structure which stores the transfer state.
2082 */
I2C_SlaveTransferAbort(I2C_Type * base,i2c_slave_handle_t * handle)2083 void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle)
2084 {
2085 assert(NULL != handle);
2086
2087 if (true == handle->isBusy)
2088 {
2089 /* Disable interrupts. */
2090 I2C_DisableInterrupts(base, (uint32_t)kIrqFlags);
2091
2092 /* Reset transfer info. */
2093 (void)memset(&handle->transfer, 0, sizeof(handle->transfer));
2094
2095 /* Reset the state to idle. */
2096 handle->isBusy = false;
2097 }
2098 }
2099
2100 /*!
2101 * brief Gets the slave transfer remaining bytes during a interrupt non-blocking transfer.
2102 *
2103 * param base I2C base pointer.
2104 * param handle pointer to i2c_slave_handle_t structure.
2105 * param count Number of bytes transferred so far by the non-blocking transaction.
2106 * retval kStatus_InvalidArgument count is Invalid.
2107 * retval kStatus_Success Successfully return the count.
2108 */
I2C_SlaveTransferGetCount(I2C_Type * base,i2c_slave_handle_t * handle,size_t * count)2109 status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)
2110 {
2111 assert(NULL != handle);
2112
2113 if (NULL == count)
2114 {
2115 return kStatus_InvalidArgument;
2116 }
2117
2118 /* Catch when there is not an active transfer. */
2119 if (false == handle->isBusy)
2120 {
2121 *count = 0;
2122 return kStatus_NoTransferInProgress;
2123 }
2124
2125 /* For an active transfer, just return the count from the handle. */
2126 *count = handle->transfer.transferredCount;
2127
2128 return kStatus_Success;
2129 }
2130
2131 /*!
2132 * brief Slave interrupt handler.
2133 *
2134 * param base I2C base pointer.
2135 * param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state
2136 */
I2C_SlaveTransferHandleIRQ(I2C_Type * base,void * i2cHandle)2137 void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
2138 {
2139 assert(NULL != i2cHandle);
2140
2141 uint16_t status;
2142 bool doTransmit = false;
2143 i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle;
2144 i2c_slave_transfer_t *xfer;
2145 size_t tmpDataSize = 0;
2146
2147 status = (uint16_t)I2C_SlaveGetStatusFlags(base);
2148 xfer = &(handle->transfer);
2149
2150 #ifdef I2C_HAS_STOP_DETECT
2151 /* Check stop flag. */
2152 if (0U != (status & (uint16_t)kI2C_StopDetectFlag))
2153 {
2154 I2C_MasterClearStatusFlags(base, (uint32_t)kI2C_StopDetectFlag);
2155
2156 /* Clear the interrupt flag. */
2157 base->S = (uint8_t)kI2C_IntPendingFlag;
2158
2159 /* Call slave callback if this is the STOP of the transfer. */
2160 if (true == handle->isBusy)
2161 {
2162 xfer->event = kI2C_SlaveCompletionEvent;
2163 xfer->completionStatus = kStatus_Success;
2164 handle->isBusy = false;
2165
2166 if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback))
2167 {
2168 handle->callback(base, xfer, handle->userData);
2169 }
2170 }
2171
2172 if (0U == (status & (uint16_t)kI2C_AddressMatchFlag))
2173 {
2174 return;
2175 }
2176 }
2177 #endif /* I2C_HAS_STOP_DETECT */
2178
2179 #if defined(FSL_FEATURE_I2C_HAS_START_STOP_DETECT) && FSL_FEATURE_I2C_HAS_START_STOP_DETECT
2180 /* Check start flag. */
2181 if (0U != (status & (uint16_t)kI2C_StartDetectFlag))
2182 {
2183 I2C_MasterClearStatusFlags(base, (uint32_t)kI2C_StartDetectFlag);
2184
2185 /* Clear the interrupt flag. */
2186 base->S = (uint8_t)kI2C_IntPendingFlag;
2187
2188 xfer->event = kI2C_SlaveStartEvent;
2189
2190 if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback))
2191 {
2192 handle->callback(base, xfer, handle->userData);
2193 }
2194
2195 if (0U == (status & (uint16_t)kI2C_AddressMatchFlag))
2196 {
2197 return;
2198 }
2199 }
2200 #endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */
2201
2202 /* Clear the interrupt flag. */
2203 base->S = (uint8_t)kI2C_IntPendingFlag;
2204
2205 /* Check NAK */
2206 if (0U != (status & (uint16_t)kI2C_ReceiveNakFlag))
2207 {
2208 /* Set receive mode. */
2209 base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
2210
2211 /* Read dummy. */
2212 (void)base->D;
2213
2214 if (handle->transfer.dataSize != 0u)
2215 {
2216 xfer->event = kI2C_SlaveCompletionEvent;
2217 xfer->completionStatus = kStatus_I2C_Nak;
2218 handle->isBusy = false;
2219
2220 if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback))
2221 {
2222 handle->callback(base, xfer, handle->userData);
2223 }
2224 }
2225 else
2226 {
2227 #ifndef I2C_HAS_STOP_DETECT
2228 xfer->event = kI2C_SlaveCompletionEvent;
2229 xfer->completionStatus = kStatus_Success;
2230 handle->isBusy = false;
2231
2232 if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback))
2233 {
2234 handle->callback(base, xfer, handle->userData);
2235 }
2236 #endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
2237 }
2238 }
2239 /* Check address match. */
2240 else if (0U != (status & (uint16_t)kI2C_AddressMatchFlag))
2241 {
2242 handle->isBusy = true;
2243 xfer->event = kI2C_SlaveAddressMatchEvent;
2244
2245 /* Slave transmit, master reading from slave. */
2246 if (0U != (status & (uint16_t)kI2C_TransferDirectionFlag))
2247 {
2248 /* Change direction to send data. */
2249 base->C1 |= I2C_C1_TX_MASK;
2250
2251 doTransmit = true;
2252 }
2253 else
2254 {
2255 /* Slave receive, master writing to slave. */
2256 base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
2257
2258 /* Read dummy to release the bus and check the address master issued. */
2259 if (base->D == 0u)
2260 {
2261 xfer->event = kI2C_SlaveGenaralcallEvent;
2262 }
2263 }
2264
2265 if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback))
2266 {
2267 handle->callback(base, xfer, handle->userData);
2268 }
2269 }
2270 /* Check transfer complete flag. */
2271 else if (0U != (status & (uint16_t)kI2C_TransferCompleteFlag))
2272 {
2273 /* Slave transmit, master reading from slave. */
2274 if (0U != (status & (uint16_t)kI2C_TransferDirectionFlag))
2275 {
2276 doTransmit = true;
2277 }
2278 else
2279 {
2280 tmpDataSize = xfer->dataSize;
2281 /* If we're out of data, invoke callback to get more. */
2282 if ((NULL == xfer->data) || (0U == tmpDataSize))
2283 {
2284 xfer->event = kI2C_SlaveReceiveEvent;
2285
2286 if (NULL != handle->callback)
2287 {
2288 handle->callback(base, xfer, handle->userData);
2289 }
2290
2291 /* Clear the transferred count now that we have a new buffer. */
2292 xfer->transferredCount = 0;
2293 }
2294
2295 /* Slave receive, master writing to slave. */
2296 uint8_t data = base->D;
2297
2298 if (0U != (handle->transfer.dataSize))
2299 {
2300 /* Receive data. */
2301 *handle->transfer.data++ = data;
2302 handle->transfer.dataSize--;
2303 xfer->transferredCount++;
2304 if (0U == handle->transfer.dataSize)
2305 {
2306 #ifndef I2C_HAS_STOP_DETECT
2307 xfer->event = kI2C_SlaveCompletionEvent;
2308 xfer->completionStatus = kStatus_Success;
2309 handle->isBusy = false;
2310
2311 /* Proceed receive complete event. */
2312 if (((handle->eventMask & (uint32_t)xfer->event) != 0U) && (handle->callback != NULL))
2313 {
2314 handle->callback(base, xfer, handle->userData);
2315 }
2316 #endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
2317 }
2318 }
2319 }
2320 }
2321 else
2322 {
2323 /* Read dummy to release bus. */
2324 (void)base->D;
2325 }
2326
2327 /* Send data if there is the need. */
2328 if (doTransmit)
2329 {
2330 tmpDataSize = xfer->dataSize;
2331 /* If we're out of data, invoke callback to get more. */
2332 if ((NULL == xfer->data) || (0U == tmpDataSize))
2333 {
2334 xfer->event = kI2C_SlaveTransmitEvent;
2335
2336 if (NULL != handle->callback)
2337 {
2338 handle->callback(base, xfer, handle->userData);
2339 }
2340
2341 /* Clear the transferred count now that we have a new buffer. */
2342 xfer->transferredCount = 0;
2343 }
2344
2345 if (0U != (handle->transfer.dataSize))
2346 {
2347 /* Send data. */
2348 base->D = *handle->transfer.data++;
2349 handle->transfer.dataSize--;
2350 xfer->transferredCount++;
2351 }
2352 else
2353 {
2354 /* Switch to receive mode. */
2355 base->C1 &= ~(uint8_t)(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
2356
2357 /* Read dummy to release bus. */
2358 (void)base->D;
2359
2360 #ifndef I2C_HAS_STOP_DETECT
2361 xfer->event = kI2C_SlaveCompletionEvent;
2362 xfer->completionStatus = kStatus_Success;
2363 handle->isBusy = false;
2364
2365 /* Proceed txdone event. */
2366 if (((handle->eventMask & (uint32_t)xfer->event) != 0U) && (handle->callback != NULL))
2367 {
2368 handle->callback(base, xfer, handle->userData);
2369 }
2370 #endif /* !FSL_FEATURE_I2C_HAS_START_STOP_DETECT or !FSL_FEATURE_I2C_HAS_STOP_DETECT */
2371 }
2372 }
2373 }
2374
2375 #if defined(FSL_FEATURE_I2C_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_I2C_HAS_SHARED_IRQ0_IRQ1
2376 void I2C0_I2C1_DriverIRQHandler(void);
I2C0_I2C1_DriverIRQHandler(void)2377 void I2C0_I2C1_DriverIRQHandler(void)
2378 {
2379 for (uint32_t instance = 0U; instance < 2U; instance++)
2380 {
2381 if (s_i2cHandle[instance] != NULL)
2382 {
2383 I2C_TransferCommonIRQHandler(s_i2cBases[instance], s_i2cHandle[instance]);
2384 }
2385 }
2386 }
2387 #else
2388 #if defined(I2C0)
2389 void I2C0_DriverIRQHandler(void);
I2C0_DriverIRQHandler(void)2390 void I2C0_DriverIRQHandler(void)
2391 {
2392 I2C_TransferCommonIRQHandler(I2C0, s_i2cHandle[0]);
2393 }
2394 #endif
2395
2396 #if defined(I2C1)
2397 void I2C1_DriverIRQHandler(void);
I2C1_DriverIRQHandler(void)2398 void I2C1_DriverIRQHandler(void)
2399 {
2400 I2C_TransferCommonIRQHandler(I2C1, s_i2cHandle[1]);
2401 }
2402 #endif
2403 #endif
2404
2405 #if defined(I2C2)
2406 void I2C2_DriverIRQHandler(void);
I2C2_DriverIRQHandler(void)2407 void I2C2_DriverIRQHandler(void)
2408 {
2409 I2C_TransferCommonIRQHandler(I2C2, s_i2cHandle[2]);
2410 }
2411 #endif
2412
2413 #if defined(I2C3)
2414 void I2C3_DriverIRQHandler(void);
I2C3_DriverIRQHandler(void)2415 void I2C3_DriverIRQHandler(void)
2416 {
2417 I2C_TransferCommonIRQHandler(I2C3, s_i2cHandle[3]);
2418 }
2419 #endif
2420
