1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup GMAC_DRIVER GMAC Driver
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Gmac_Ip_Hw_Access.h"
25 #include "OsIf.h"
26
27 /*==================================================================================================
28 * SOURCE FILE VERSION INFORMATION
29 ==================================================================================================*/
30 #define GMAC_IP_HW_ACCESS_VENDOR_ID_C 43
31 #define GMAC_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_C 4
32 #define GMAC_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_C 7
33 #define GMAC_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION_C 0
34 #define GMAC_IP_HW_ACCESS_SW_MAJOR_VERSION_C 3
35 #define GMAC_IP_HW_ACCESS_SW_MINOR_VERSION_C 0
36 #define GMAC_IP_HW_ACCESS_SW_PATCH_VERSION_C 0
37
38 /*==================================================================================================
39 * FILE VERSION CHECKS
40 ==================================================================================================*/
41 /* Checks against Gmac_Ip_Hw_Access.h */
42 #if (GMAC_IP_HW_ACCESS_VENDOR_ID_C != GMAC_IP_HW_ACCESS_VENDOR_ID)
43 #error "Gmac_Ip_Hw_Access.c and Gmac_Ip_Hw_Access.h have different vendor ids"
44 #endif
45 #if ((GMAC_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_C != GMAC_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION) || \
46 (GMAC_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_C != GMAC_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION) || \
47 (GMAC_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION_C != GMAC_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION))
48 #error "AUTOSAR Version Numbers of Gmac_Ip_Hw_Access.c and Gmac_Ip_Hw_Access.h are different"
49 #endif
50 #if ((GMAC_IP_HW_ACCESS_SW_MAJOR_VERSION_C != GMAC_IP_HW_ACCESS_SW_MAJOR_VERSION) || \
51 (GMAC_IP_HW_ACCESS_SW_MINOR_VERSION_C != GMAC_IP_HW_ACCESS_SW_MINOR_VERSION) || \
52 (GMAC_IP_HW_ACCESS_SW_PATCH_VERSION_C != GMAC_IP_HW_ACCESS_SW_PATCH_VERSION))
53 #error "Software Version Numbers of Gmac_Ip_Hw_Access.c and Gmac_Ip_Hw_Access.h are different"
54 #endif
55
56 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
57 /* Checks against OsIf.h */
58 #if (( GMAC_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION_C != OSIF_AR_RELEASE_MAJOR_VERSION) || \
59 ( GMAC_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION_C != OSIF_AR_RELEASE_MINOR_VERSION))
60 #error "AUTOSAR Version Numbers of Gmac_Ip_Hw_Access.c and OsIf.h are different"
61 #endif
62 #endif
63
64 /*******************************************************************************
65 * Definitions
66 ******************************************************************************/
67
68 #define GMAC_CRC32_BITS_31_28_MASK (0xF0000000U)
69 #define GMAC_CRC32_BITS_31_28_SHIFT 28U
70
71 #define GMAC_HASH_TABLE_REG_MASK 0xE0U
72 #define GMAC_HASH_TABLE_BIT_MASK 0x1FU
73 #define GMAC_HASH_TABLE_GET_REG_SHIFT 5U
74
75 #define GMAC_HASH_TABLE_REG_IDX(revCrc32) ((((uint32)(revCrc32) >> FEATURE_GMAC_HASH_TABLE_MSB_SHIFT) & (((uint32)FEATURE_GMAC_HASH_TABLE_SZ - 1U) & GMAC_HASH_TABLE_REG_MASK)) >> GMAC_HASH_TABLE_GET_REG_SHIFT)
76 #define GMAC_HASH_TABLE_BIT_IDX(revCrc32) (((uint32)(revCrc32) >> FEATURE_GMAC_HASH_TABLE_MSB_SHIFT) & (((uint32)FEATURE_GMAC_HASH_TABLE_SZ - 1U) & GMAC_HASH_TABLE_BIT_MASK))
77
78 #define GMAC_RX_INTERRUPTS (GMAC_DMA_CH0_STATUS_REB_MASK | GMAC_DMA_CH0_STATUS_ERI_MASK | GMAC_DMA_CH0_STATUS_RWT_MASK | GMAC_DMA_CH0_STATUS_RPS_MASK \
79 | GMAC_DMA_CH0_STATUS_RBU_MASK | GMAC_DMA_CH0_STATUS_RI_MASK)
80 #define GMAC_TX_INTERRUPTS (GMAC_DMA_CH0_STATUS_TEB_MASK | GMAC_DMA_CH0_STATUS_ETI_MASK | GMAC_DMA_CH0_STATUS_TBU_MASK | GMAC_DMA_CH0_STATUS_TPS_MASK \
81 | GMAC_DMA_CH0_STATUS_TI_MASK)
82
83 #define FEATURE_GMAC_HASH_TABLE_DIM (FEATURE_GMAC_HASH_TABLE_SZ / 32U)
84
85 /*******************************************************************************
86 * Variables
87 ******************************************************************************/
88 #define ETH_43_GMAC_START_SEC_CONST_UNSPECIFIED
89 #include "Eth_43_GMAC_MemMap.h"
90
91
92 GMAC_Type * const Gmac_apxBases[FEATURE_GMAC_NUM_INSTANCES] = IP_GMAC_BASE_PTRS;
93
94 Gmac_Ip_ChannelType * const Gmac_apxChBases[FEATURE_GMAC_NUM_INSTANCES][FEATURE_GMAC_NUM_CHANNELS] = DEV_REG_GMAC_CH_BASE;
95
96 Gmac_Ip_QueueType * const Gmac_apxQueueBases[FEATURE_GMAC_NUM_INSTANCES][FEATURE_GMAC_NUM_QUEUES] = DEV_REG_GMAC_QUEUE_BASE;
97
98
99 #define ETH_43_GMAC_STOP_SEC_CONST_UNSPECIFIED
100 #include "Eth_43_GMAC_MemMap.h"
101
102 /*******************************************************************************
103 * Private Functions
104 ******************************************************************************/
105 #define ETH_43_GMAC_START_SEC_CODE
106 #include "Eth_43_GMAC_MemMap.h"
107
108 /*FUNCTION**********************************************************************
109 *
110 * Function Name : REV_BITS_32
111 * Description : Performs bitwise reversal on a 32 bit value.
112 *
113 *END**************************************************************************/
REV_BITS_32(uint32 value)114 static inline uint32 REV_BITS_32(uint32 value)
115 {
116 uint32 v;
117
118 v = value;
119 v = (((v & (0xAAAAAAAAU)) >> 1U) | ((v & (0x55555555U)) << 1U));
120 v = (((v & (0xCCCCCCCCU)) >> 2U) | ((v & (0x33333333U)) << 2U));
121 v = (((v & (0xF0F0F0F0U)) >> 4U) | ((v & (0x0F0F0F0FU)) << 4U));
122 v = (((v & (0xFF00FF00U)) >> 8U) | ((v & (0x00FF00FFU)) << 8U));
123 return ((v >> 16U) | (v << 16U));
124 }
125
126 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC)
127 static void GMAC_IrqFSMHandler( \
128 const uint8 Instance, \
129 uint32 ErrorStatusFlags, \
130 uint32 ErrorEnFlags \
131 );
132 static void GMAC_IrqFSMDPPHandler( \
133 const uint8 Instance, \
134 uint32 ErrorStatusFlags, \
135 uint32 ErrorEnFlags \
136 );
137 static void GMAC_IrqECCHandler( \
138 const uint8 Instance, \
139 uint32 ErrorStatusFlags, \
140 uint32 ErrorEnFlags \
141 );
142
143 #define GMAC_ECC_CTL_MASK (GMAC_MTL_ECC_CONTROL_MTXEE_MASK | \
144 GMAC_MTL_ECC_CONTROL_MRXEE_MASK | \
145 GMAC_MTL_ECC_CONTROL_MESTEE_MASK)
146
147 #define GMAC_ECC_STS_MASK (GMAC_MTL_ECC_INTERRUPT_STATUS_EUES_MASK | GMAC_MTL_ECC_INTERRUPT_STATUS_EAMS_MASK | \
148 GMAC_MTL_ECC_INTERRUPT_STATUS_RXUES_MASK | GMAC_MTL_ECC_INTERRUPT_STATUS_RXAMS_MASK | \
149 GMAC_MTL_ECC_INTERRUPT_STATUS_TXUES_MASK | GMAC_MTL_ECC_INTERRUPT_STATUS_TXAMS_MASK)
150
151
152 #define GMAC_CSR_TIMEOUT_CTL_MASK (GMAC_MAC_FSM_CONTROL_TMOUTEN_MASK)
153
154 #define GMAC_CSR_TIMEOUT_STS_MASK (GMAC_SAF_ERR_MASTER_INTERFACE_TIMEOUT)
155
156
157 #define GMAC_FSM_TIMEOUT_CTL_MASK (GMAC_MAC_FSM_CONTROL_TMOUTEN_MASK)
158
159 #define GMAC_FSM_TIMEOUT_STS_MASK (GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES_MASK | \
160 GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES_MASK | \
161 GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES_MASK | \
162 GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES_MASK)
163
164
165 #define GMAC_FSM_SPP_CTL_MASK (GMAC_MAC_FSM_CONTROL_PRTYEN_MASK)
166
167 #define GMAC_FSM_SPP_STS_MASK (GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES_MASK)
168
169
170 #define GMAC_DPP_CTL_MASK (GMAC_MTL_DPP_CONTROL_EDPP_MASK)
171
172 #define GMAC_DPP_STS_MASK (GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES_MASK | \
173 GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES_MASK | \
174 GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES_MASK | \
175 GMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES_MASK)
176 #if FEATURE_GMAC_ASP_ALL
GMAC_IrqFSMHandler(const uint8 Instance,uint32 ErrorStatusFlags,uint32 ErrorEnFlags)177 static void GMAC_IrqFSMHandler( \
178 const uint8 Instance, \
179 uint32 ErrorStatusFlags, \
180 uint32 ErrorEnFlags \
181 )
182 {
183 if (((ErrorStatusFlags & GMAC_FSM_SPP_STS_MASK) != 0U) && ((ErrorEnFlags & GMAC_FSM_SPP_CTL_MASK) != 0U))
184 {
185 Gmac_apxState[Instance]->SafetyCallback(Instance, GMAC_SAF_ERR_FSM_STATE_PARITY);
186 }
187 else if (((ErrorStatusFlags & GMAC_FSM_TIMEOUT_STS_MASK) != 0U) && ((ErrorEnFlags & GMAC_FSM_TIMEOUT_CTL_MASK) != 0U))
188 {
189 Gmac_apxState[Instance]->SafetyCallback(Instance, GMAC_SAF_ERR_FSM_TIMEOUT);
190 }
191 else if (((ErrorStatusFlags & (uint32)GMAC_CSR_TIMEOUT_STS_MASK) != 0U) && ((ErrorEnFlags & GMAC_CSR_TIMEOUT_CTL_MASK) != 0U))
192 {
193 Gmac_apxState[Instance]->SafetyCallback(Instance, GMAC_SAF_ERR_MASTER_INTERFACE_TIMEOUT);
194 }
195 else if (ErrorStatusFlags == 0U)
196 {
197 Gmac_apxState[Instance]->SafetyCallback(Instance, GMAC_SAF_ERR_CSR_EMPTY_DATA);
198 }
199 else
200 {
201 /* Do nothing */
202 }
203 }
204
GMAC_IrqFSMDPPHandler(const uint8 Instance,uint32 ErrorStatusFlags,uint32 ErrorEnFlags)205 static void GMAC_IrqFSMDPPHandler( \
206 const uint8 Instance, \
207 uint32 ErrorStatusFlags, \
208 uint32 ErrorEnFlags \
209 )
210 {
211 const GMAC_Type *Base = Gmac_apxBases[Instance];
212
213 /* Check if driver is initialized */
214 if (Gmac_apxState[Instance] != NULL_PTR)
215 {
216 /* Callback function. */
217 if (Gmac_apxState[Instance]->SafetyCallback != NULL_PTR)
218 {
219 if (((ErrorStatusFlags & GMAC_DPP_STS_MASK) != 0U) && ((ErrorEnFlags & GMAC_DPP_CTL_MASK) != 0U))
220 {
221 Gmac_apxState[Instance]->SafetyCallback(Instance, GMAC_SAF_ERR_DATA_PATH_PARITY);
222 }
223 else
224 {
225 GMAC_IrqFSMHandler(Instance, ErrorStatusFlags, Base->MAC_FSM_CONTROL);
226 }
227 }
228 }
229 }
230 #endif
GMAC_IrqECCHandler(const uint8 Instance,uint32 ErrorStatusFlags,uint32 ErrorEnFlags)231 static void GMAC_IrqECCHandler( \
232 const uint8 Instance, \
233 uint32 ErrorStatusFlags, \
234 uint32 ErrorEnFlags \
235 )
236 {
237 /* Check if driver is initialized */
238 if (Gmac_apxState[Instance] != NULL_PTR)
239 {
240 /* Check if IRQ is spurious */
241 if (((ErrorStatusFlags & GMAC_ECC_STS_MASK) != 0U) && ((ErrorEnFlags & GMAC_ECC_CTL_MASK) != 0U))
242 {
243 /* Callback function. */
244 if (Gmac_apxState[Instance]->SafetyCallback != NULL_PTR)
245 {
246 Gmac_apxState[Instance]->SafetyCallback(Instance, GMAC_SAF_ERR_ECC);
247 }
248 }
249 }
250 }
251 #endif
252
GMAC_MACIRQHandler(uint8 Instance)253 static void GMAC_MACIRQHandler(uint8 Instance)
254 {
255 const GMAC_Type *Base = Gmac_apxBases[Instance];
256 uint32 Flags;
257
258 if ((Base->DMA_INTERRUPT_STATUS & GMAC_DMA_INTERRUPT_STATUS_MACIS_MASK) != 0U)
259 {
260 /* Clear the interrupt events. */
261 Flags = Base->MAC_INTERRUPT_STATUS;
262
263 /* Callback function. */
264 if (Gmac_apxState[Instance]->Callback != NULL_PTR)
265 {
266 Gmac_apxState[Instance]->Callback(Instance);
267 }
268
269 #if FEATURE_GMAC_RGMII_EN || FEATURE_GMAC_SMII_EN
270 if ((Flags & GMAC_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK) != 0U)
271 {
272 (void)Base->MAC_PHYIF_CONTROL_STATUS;
273 }
274 #endif
275 if ((Flags & GMAC_MAC_INTERRUPT_STATUS_FPEIS_MASK) != 0U)
276 {
277 (void)Base->MAC_FPE_CTRL_STS;
278 }
279 if (((Flags & GMAC_MAC_INTERRUPT_STATUS_RXSTSIS_MASK) != 0U) ||
280 ((Flags & GMAC_MAC_INTERRUPT_STATUS_TXSTSIS_MASK) != 0U))
281 {
282 (void)Base->MAC_RX_TX_STATUS;
283 }
284 }
285 }
286 /*******************************************************************************
287 * Code
288 ******************************************************************************/
289
290 /*FUNCTION**********************************************************************
291 *
292 * Function Name : GMAC_StartTimeout
293 * Description : Checks for timeout condition
294 *
295 *END**************************************************************************/
GMAC_StartTimeOut(uint32 * StartTimeOut,uint32 * ElapsedTimeOut,uint32 * TimeoutTicksOut,uint32 TimeoutUs)296 void GMAC_StartTimeOut(uint32 *StartTimeOut,
297 uint32 *ElapsedTimeOut,
298 uint32 *TimeoutTicksOut,
299 uint32 TimeoutUs)
300 {
301 *StartTimeOut = OsIf_GetCounter(GMAC_TIMEOUT_TYPE);
302 *ElapsedTimeOut = 0U;
303 *TimeoutTicksOut = OsIf_MicrosToTicks(TimeoutUs, GMAC_TIMEOUT_TYPE);
304 }
305
306 /*FUNCTION**********************************************************************
307 *
308 * Function Name : GMAC_TimeoutExpired
309 * Description : Checks for timeout expiration condition
310 *
311 *END**************************************************************************/
GMAC_TimeoutExpired(uint32 * StartTimeInOut,uint32 * ElapsedTimeInOut,uint32 TimeoutTicks)312 boolean GMAC_TimeoutExpired(uint32 *StartTimeInOut,
313 uint32 *ElapsedTimeInOut,
314 uint32 TimeoutTicks)
315 {
316 boolean RetVal = FALSE;
317 *ElapsedTimeInOut += OsIf_GetElapsed(StartTimeInOut, GMAC_TIMEOUT_TYPE);
318
319 if(*ElapsedTimeInOut >= TimeoutTicks)
320 {
321 RetVal = TRUE;
322 }
323
324 return RetVal;
325 }
326
327 /*FUNCTION**********************************************************************
328 *
329 * Function Name : GMAC_WriteManagementFrame
330 * Description : Writes a MII management frame.
331 *
332 *END**************************************************************************/
GMAC_WriteManagementFrame(GMAC_Type * Base,const Gmac_Ip_ManagementInfo * ManageInfo,uint32 TimeoutUs)333 Gmac_Ip_StatusType GMAC_WriteManagementFrame(GMAC_Type * Base,
334 const Gmac_Ip_ManagementInfo *ManageInfo,
335 uint32 TimeoutUs)
336 {
337 Gmac_Ip_StatusType Status = GMAC_STATUS_TIMEOUT;
338 uint32 StartTime;
339 uint32 ElapsedTime;
340 uint32 TimeoutTicks;
341
342 Base->MAC_MDIO_ADDRESS &= ~(GMAC_MAC_MDIO_ADDRESS_PA_MASK |
343 GMAC_MAC_MDIO_ADDRESS_RDA_MASK |
344 GMAC_MAC_MDIO_ADDRESS_GOC_0_MASK |
345 GMAC_MAC_MDIO_ADDRESS_GOC_1_MASK |
346 GMAC_MAC_MDIO_ADDRESS_C45E_MASK);
347 Base->MAC_MDIO_DATA = GMAC_MAC_MDIO_DATA_RA(ManageInfo->SupportedClause45 ? ManageInfo->PhysReg : 0UL) |
348 GMAC_MAC_MDIO_DATA_GD(ManageInfo->FrameData);
349 Base->MAC_MDIO_ADDRESS |= (ManageInfo->SupportedClause45 ? GMAC_MAC_MDIO_ADDRESS_C45E_MASK : 0UL) |
350 GMAC_MAC_MDIO_ADDRESS_GOC_1(ManageInfo->OpFrameType) |
351 GMAC_MAC_MDIO_ADDRESS_GOC_0_MASK |
352 GMAC_MAC_MDIO_ADDRESS_PA(ManageInfo->PhysAddr) |
353 GMAC_MAC_MDIO_ADDRESS_RDA(ManageInfo->SupportedClause45 ? (uint32)ManageInfo->MmdAddr : (uint32)ManageInfo->PhysReg) |
354 GMAC_MAC_MDIO_ADDRESS_GB_MASK;
355 /* Add fault label for testing */
356 #ifdef MCAL_ENABLE_FAULT_INJECTION
357 MCAL_FAULT_INJECTION_POINT(ETH_MDIO_TIMEOUT);
358 #endif
359
360 /* Wait for completion */
361 GMAC_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, TimeoutUs);
362 do
363 {
364 if ((Base->MAC_MDIO_ADDRESS & GMAC_MAC_MDIO_ADDRESS_GB_MASK) == 0U)
365 {
366 Status = GMAC_STATUS_SUCCESS;
367 break;
368 }
369 }
370 while (!GMAC_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
371
372 return Status;
373 }
374
375 /*FUNCTION**********************************************************************
376 *
377 * Function Name : GMAC_CommonIRQHandler
378 * Description : Handler for GMAC common interrupt.
379 * This handler invokes the installed callback (if available) and clears the
380 * interrupt flags.
381 *
382 *END**************************************************************************/
GMAC_CommonIRQHandler(uint8 Instance)383 void GMAC_CommonIRQHandler(uint8 Instance)
384 {
385 const GMAC_Type *Base = Gmac_apxBases[Instance];
386 uint8 i;
387 uint32 Flags;
388
389 GMAC_MACIRQHandler(Instance);
390
391 for (i = 0; i < FEATURE_GMAC_NUM_CHANNELS; i++)
392 {
393 if ((Base->DMA_INTERRUPT_STATUS & (1UL << (uint32)i)) != 0U)
394 {
395 Gmac_Ip_ChannelType *ChBase = Gmac_apxChBases[Instance][i];
396 Flags = ChBase->DMA_STATUS;
397
398 /* Callback function. */
399 if (((Flags & GMAC_RX_INTERRUPTS) != 0U) &&
400 (Gmac_apxState[Instance]->RxChCallback[i] != NULL_PTR))
401 {
402 Gmac_apxState[Instance]->RxChCallback[i](Instance, i);
403 }
404
405 /* Callback function. */
406 if (((Flags & GMAC_TX_INTERRUPTS) != 0U) &&
407 (Gmac_apxState[Instance]->TxChCallback[i] != NULL_PTR))
408 {
409 Gmac_apxState[Instance]->TxChCallback[i](Instance, i);
410 }
411
412 /* Clear the interrupt event. */
413 ChBase->DMA_STATUS = Flags;
414 (void)ChBase->DMA_STATUS;
415 }
416 }
417 }
418
419
420 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC)
421 /*FUNCTION**********************************************************************
422 *
423 * Function Name : Gmac_SafetyIRQHandler
424 * Description : Handler for GMAC safety interrupt.
425 * This handler invokes the installed callback (if available) and clears the
426 * interrupt flags.
427 *
428 *END**************************************************************************/
429
GMAC_SafetyIRQHandler(uint8 Instance)430 void GMAC_SafetyIRQHandler(uint8 Instance)
431 {
432 GMAC_Type *Base = Gmac_apxBases[Instance];
433 uint32 SafetyStatusFlags;
434 uint32 ErrorStatusFlags;
435
436 SafetyStatusFlags = Base->DMA_SAFETY_INTERRUPT_STATUS;
437 if ((SafetyStatusFlags & GMAC_DMA_SAFETY_INTERRUPT_STATUS_MSUIS_MASK) != 0U)
438 {
439 ErrorStatusFlags = Base->MTL_ECC_INTERRUPT_STATUS;
440
441 /* Clear the ECC interrupt event(s) */
442 Base->MTL_ECC_INTERRUPT_STATUS = ErrorStatusFlags;
443
444 GMAC_IrqECCHandler(Instance, ErrorStatusFlags, Base->MTL_ECC_CONTROL);
445
446 }
447 #if FEATURE_GMAC_ASP_ALL
448 else if ((SafetyStatusFlags & GMAC_DMA_SAFETY_INTERRUPT_STATUS_MCSIS_MASK) != 0U)
449 {
450 ErrorStatusFlags = Base->MAC_DPP_FSM_INTERRUPT_STATUS;
451
452 GMAC_IrqFSMDPPHandler(Instance, ErrorStatusFlags, Base->MTL_DPP_CONTROL);
453 }
454 else
455 {
456 /*Do nothing*/
457 }
458 #endif
459 }
460 #endif /* #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC) */
461
462 /*FUNCTION**********************************************************************
463 *
464 * Function Name : GMAC_RxIRQHandler
465 * Description : Handler for GMAC receive interrupt.
466 * This handler invokes the installed callback (if available) and clears the
467 * interrupt flags.
468 *
469 *END**************************************************************************/
470 /* implements GMAC_RxIRQHandler_Activity */
GMAC_RxIRQHandler(uint8 Instance,uint8 Channel)471 void GMAC_RxIRQHandler(uint8 Instance,
472 uint8 Channel)
473 {
474 Gmac_Ip_ChannelType *ChBase = Gmac_apxChBases[Instance][Channel];
475 uint32 StatusFlags = ChBase->DMA_STATUS;
476 uint32 IrqEnFlags = ChBase->DMA_INTERRUPT_ENABLE;
477
478 /* Check if driver is initialized */
479 if (Gmac_apxState[Instance] != NULL_PTR)
480 {
481 /* Check if IRQ is spurious */
482 if (((IrqEnFlags & GMAC_DMA_CH0_INTERRUPT_ENABLE_RIE_MASK) != 0U) &&
483 ((StatusFlags & GMAC_DMA_CH0_STATUS_RI_MASK) != 0U))
484 {
485 /* Clear the interrupt event. */
486 ChBase->DMA_STATUS = GMAC_DMA_CH0_STATUS_RI_MASK;
487
488 /* Callback function. */
489 if (Gmac_apxState[Instance]->RxChCallback[Channel] != NULL_PTR)
490 {
491 Gmac_apxState[Instance]->RxChCallback[Channel](Instance, Channel);
492 }
493 }
494 }
495 else
496 {
497 /* Clear the interrupt event. */
498 ChBase->DMA_STATUS = GMAC_DMA_CH0_STATUS_RI_MASK;
499 }
500 }
501
502 /*FUNCTION**********************************************************************
503 *
504 * Function Name : GMAC_TxIRQHandler
505 * Description : Handler for GMAC transmit interrupt.
506 * This handler invokes the installed callback (if available) and clears the
507 * interrupt flags.
508 *
509 *END**************************************************************************/
510 /* implements GMAC_TxIRQHandler_Activity */
GMAC_TxIRQHandler(uint8 Instance,uint8 Channel)511 void GMAC_TxIRQHandler(uint8 Instance,
512 uint8 Channel)
513 {
514 Gmac_Ip_ChannelType *ChBase = Gmac_apxChBases[Instance][Channel];
515 uint32 StatusFlags = ChBase->DMA_STATUS;
516 uint32 IrqEnFlags = ChBase->DMA_INTERRUPT_ENABLE;
517
518 /* Check if driver is initialized */
519 if (Gmac_apxState[Instance] != NULL_PTR)
520 {
521 /* Check if IRQ is spurious */
522 if (((IrqEnFlags & GMAC_DMA_CH0_INTERRUPT_ENABLE_TIE_MASK) != 0U) &&
523 ((StatusFlags & GMAC_DMA_CH0_STATUS_TI_MASK) != 0U))
524 {
525 /* Clear the interrupt event. */
526 ChBase->DMA_STATUS = GMAC_DMA_CH0_STATUS_TI_MASK;
527
528 /* Callback function. */
529 if (Gmac_apxState[Instance]->TxChCallback[Channel] != NULL_PTR)
530 {
531 Gmac_apxState[Instance]->TxChCallback[Channel](Instance, Channel);
532 }
533 }
534 }
535 else
536 {
537 /* Clear the interrupt event. */
538 ChBase->DMA_STATUS = GMAC_DMA_CH0_STATUS_TI_MASK;
539 }
540 }
541
542 /*FUNCTION**********************************************************************
543 *
544 * Function Name : GMAC_AddToHashTable
545 * Description : Adds an entry to the hash table filter.
546 * This functions adds an entry to the hash table filter based on the CRC of a
547 * hardware address.
548 *
549 *END**************************************************************************/
GMAC_AddToHashTable(const GMAC_Type * Base,uint32 Crc)550 void GMAC_AddToHashTable(const GMAC_Type * Base,
551 uint32 Crc)
552 {
553 uint32 Index;
554 uint32 Hash_bit;
555 volatile uint32 HashBaseAddr = (uint32)&Base->MAC_HASH_TABLE_REG0;
556 volatile uint32 (*Hash_table)[FEATURE_GMAC_HASH_TABLE_DIM] = (volatile uint32 (*)[FEATURE_GMAC_HASH_TABLE_DIM])HashBaseAddr;
557
558 Index = GMAC_HASH_TABLE_REG_IDX(REV_BITS_32(Crc));
559 Hash_bit = (uint32)1U << GMAC_HASH_TABLE_BIT_IDX(REV_BITS_32(Crc));
560
561 (*Hash_table)[Index % FEATURE_GMAC_HASH_TABLE_DIM] |= Hash_bit;
562 }
563
564 /*FUNCTION**********************************************************************
565 *
566 * Function Name : GMAC_RemoveFromHashTable
567 * Description : Removes an entry from the hash table filter.
568 * This functions removes an entry from the hash table filter based on the CRC
569 * of a hardware address.
570 *
571 *END**************************************************************************/
GMAC_RemoveFromHashTable(const GMAC_Type * Base,uint32 Crc)572 void GMAC_RemoveFromHashTable(const GMAC_Type * Base,
573 uint32 Crc)
574 {
575 uint32 Index;
576 uint32 Hash_bit;
577 volatile uint32 HashBaseAddr = (uint32)&Base->MAC_HASH_TABLE_REG0;
578 volatile uint32 (*Hash_table)[FEATURE_GMAC_HASH_TABLE_DIM] = (volatile uint32 (*)[FEATURE_GMAC_HASH_TABLE_DIM])HashBaseAddr;
579
580 Index = GMAC_HASH_TABLE_REG_IDX(REV_BITS_32(Crc));
581 Hash_bit = (uint32)1U << GMAC_HASH_TABLE_BIT_IDX(REV_BITS_32(Crc));
582
583 (*Hash_table)[Index % FEATURE_GMAC_HASH_TABLE_DIM] &= ~Hash_bit;
584 }
585
586 /*FUNCTION**********************************************************************
587 *
588 * Function Name : GMAC_AddVlanToHashTable
589 * Description : Adds a VLAN tag to the VLAN hash table filter.
590 *
591 *END**************************************************************************/
GMAC_AddVlanToHashTable(GMAC_Type * Base,uint32 Crc)592 void GMAC_AddVlanToHashTable(GMAC_Type * Base,
593 uint32 Crc)
594 {
595 uint32 Index;
596
597 Index = (REV_BITS_32(Crc) & GMAC_CRC32_BITS_31_28_MASK) >>
598 GMAC_CRC32_BITS_31_28_SHIFT;
599
600 if (GMAC_MAC_VLAN_TAG_DATA_ETV_MASK != (Base->MAC_VLAN_TAG_DATA_REG & GMAC_MAC_VLAN_TAG_DATA_ETV_MASK))
601 {
602 Index = Index - 1UL;
603 }
604
605 Base->MAC_VLAN_HASH_TABLE |= ((uint32)1U << Index);
606 }
607 /*FUNCTION**********************************************************************
608 *
609 * Function Name : GMAC_RemoveVlanFromHashTable
610 * Description : Removes a VLAN tag from the VLAN has0x00 0x64h table filter.
611 *
612 *END**************************************************************************/
GMAC_RemoveVlanFromHashTable(GMAC_Type * Base,uint32 Crc)613 void GMAC_RemoveVlanFromHashTable(GMAC_Type * Base,
614 uint32 Crc)
615 {
616 uint32 Index;
617
618 Index = (REV_BITS_32(Crc) & GMAC_CRC32_BITS_31_28_MASK) >>
619 GMAC_CRC32_BITS_31_28_SHIFT;
620
621 if (GMAC_MAC_VLAN_TAG_DATA_ETV_MASK != (Base->MAC_VLAN_TAG_DATA_REG & GMAC_MAC_VLAN_TAG_DATA_ETV_MASK))
622 {
623 Index = Index - 1UL;
624 }
625
626 Base->MAC_VLAN_HASH_TABLE &= ~((uint32)1U << Index);
627 }
628 /*FUNCTION**********************************************************************
629 *
630 * Function Name : GMAC_GetPowerState
631 * Description : Gets the current power state
632 *
633 *END**************************************************************************/
GMAC_GetPowerState(const GMAC_Type * Base)634 Gmac_Ip_PowerStateType GMAC_GetPowerState(const GMAC_Type * Base)
635 {
636 Gmac_Ip_PowerStateType PowerState = GMAC_PSTATE_RESET;
637
638 /* The order is important to enforce RESET > SLEEP > ACTIVE > INACTIVE priority */
639 if ((Base->DMA_MODE & GMAC_DMA_MODE_SWR_MASK) != 0U)
640 {
641 PowerState = GMAC_PSTATE_RESET;
642 }
643 #if FEATURE_GMAC_PMT_EN
644 else if ((Base->MAC_PMT_CONTROL_STATUS & GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK) != 0U)
645 {
646 PowerState = GMAC_PSTATE_SLEEP;
647 }
648 #endif
649 else if ((Base->MAC_CONFIGURATION & (GMAC_MAC_CONFIGURATION_RE_MASK | GMAC_MAC_CONFIGURATION_TE_MASK)) != 0U)
650 {
651 PowerState = GMAC_PSTATE_ACTIVE;
652 }
653 else if ((Base->MAC_CONFIGURATION & (GMAC_MAC_CONFIGURATION_RE_MASK | GMAC_MAC_CONFIGURATION_TE_MASK)) == 0U)
654 {
655 PowerState = GMAC_PSTATE_INACTIVE;
656 }
657 else
658 {
659 /* Should not get here. */
660 }
661
662 return PowerState;
663 }
664
665 /*FUNCTION**********************************************************************
666 *
667 * Function Name : GMAC_SetPowerState
668 * Description : Sets the power state
669 *
670 *END**************************************************************************/
GMAC_SetPowerState(GMAC_Type * Base,Gmac_Ip_PowerStateType PowerState)671 void GMAC_SetPowerState(GMAC_Type * Base, Gmac_Ip_PowerStateType PowerState)
672 {
673 switch (PowerState)
674 {
675 case GMAC_PSTATE_INACTIVE:
676 {
677 #if FEATURE_GMAC_PMT_EN
678 Base->MAC_PMT_CONTROL_STATUS &= ~GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK;
679 #endif
680 Base->MAC_CONFIGURATION &= ~(GMAC_MAC_CONFIGURATION_RE_MASK | GMAC_MAC_CONFIGURATION_TE_MASK);
681 break;
682 }
683
684 case GMAC_PSTATE_ACTIVE:
685 {
686 #if FEATURE_GMAC_PMT_EN
687 Base->MAC_PMT_CONTROL_STATUS &= ~GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK;
688 #endif
689 Base->MAC_CONFIGURATION |= (GMAC_MAC_CONFIGURATION_RE_MASK | GMAC_MAC_CONFIGURATION_TE_MASK);
690 break;
691 }
692
693 #if FEATURE_GMAC_PMT_EN
694 case GMAC_PSTATE_SLEEP:
695 {
696 Base->MAC_PMT_CONTROL_STATUS |= (GMAC_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK | GMAC_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK);
697 Base->MAC_PMT_CONTROL_STATUS |= GMAC_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK;
698 Base->MAC_PMT_CONTROL_STATUS |= GMAC_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK;
699 break;
700 }
701 #endif
702
703 case GMAC_PSTATE_RESET:
704 {
705 Base->DMA_MODE |= GMAC_DMA_MODE_SWR_MASK;
706 break;
707 }
708
709 default:
710 {
711 /* Should not get here. */
712 break;
713 }
714 }
715 }
716
717 /*FUNCTION**********************************************************************
718 *
719 * Function Name : GMAC_SetSpeed
720 * Description : Sets the MII speed
721 *
722 *END**************************************************************************/
GMAC_SetSpeed(GMAC_Type * Base,Gmac_Ip_SpeedType Speed)723 void GMAC_SetSpeed(GMAC_Type * Base, Gmac_Ip_SpeedType Speed)
724 {
725 if (Speed == GMAC_SPEED_1G)
726 {
727 Base->MAC_CONFIGURATION &= ~(GMAC_MAC_CONFIGURATION_PS_MASK |
728 GMAC_MAC_CONFIGURATION_FES_MASK);
729 }
730 else if (Speed == GMAC_SPEED_100M) /* The enum GMAC_SPEED_100M will work for both GMAC_SPEED_100M and GMAC_SPEED_200M because they are equal. */
731 {
732 Base->MAC_CONFIGURATION |= GMAC_MAC_CONFIGURATION_PS_MASK |
733 GMAC_MAC_CONFIGURATION_FES_MASK;
734 }
735 else if (Speed == GMAC_SPEED_10M)
736 {
737 Base->MAC_CONFIGURATION |= GMAC_MAC_CONFIGURATION_PS_MASK;
738 Base->MAC_CONFIGURATION &= ~GMAC_MAC_CONFIGURATION_FES_MASK;
739 }
740 #if FEATURE_GMAC_SGMII_EN
741 else if (Speed == GMAC_SPEED_2500M)
742 {
743 Base->MAC_CONFIGURATION &= ~GMAC_MAC_CONFIGURATION_PS_MASK;
744 Base->MAC_CONFIGURATION |= GMAC_MAC_CONFIGURATION_FES_MASK;
745 }
746 #endif
747 else
748 {
749 /* Should not get here. */
750 }
751 }
752
753 /*FUNCTION**********************************************************************
754 *
755 * Function Name : GMAC_SetSchedAlg
756 * Description : Sets the Tx scheduling algorithm
757 *
758 *END**************************************************************************/
GMAC_SetSchedAlg(GMAC_Type * Base,Gmac_Ip_TxSchedAlgoType SchedAlgo)759 void GMAC_SetSchedAlg(GMAC_Type * Base, Gmac_Ip_TxSchedAlgoType SchedAlgo)
760 {
761 if (SchedAlgo == GMAC_SCHED_ALGO_WRR)
762 {
763 Base->MTL_OPERATION_MODE &= ~GMAC_MTL_OPERATION_MODE_SCHALG_MASK;
764 }
765 else if (SchedAlgo == GMAC_SCHED_ALGO_SP)
766 {
767 Base->MTL_OPERATION_MODE |= GMAC_MTL_OPERATION_MODE_SCHALG_MASK;
768 }
769 else
770 {
771 /* Should not get here. */
772 }
773 }
774
775 /*FUNCTION**********************************************************************
776 *
777 * Function Name : GMAC_SetTxQueueQuantumWeight
778 * Description : Sets the weight or idle slope credit for a specific Tx Queue
779 *
780 *END**************************************************************************/
GMAC_SetTxQueueQuantumWeight(Gmac_Ip_QueueType * QueueBase,uint32 Weight)781 void GMAC_SetTxQueueQuantumWeight(Gmac_Ip_QueueType * QueueBase,
782 uint32 Weight)
783 {
784 QueueBase->MTL_TXQ_QUANTUM_WEIGHT = Weight;
785 }
786
787 /*FUNCTION**********************************************************************
788 *
789 * Function Name : GMAC_SetTxQueueCreditBasedShaper
790 * Description : Sets the send slope, high credit and low credit for a specific Tx Queue
791 *
792 *END**************************************************************************/
GMAC_SetTxQueueCreditBasedShaper(Gmac_Ip_QueueType * QueueBase,uint32 SendSlopeCredit,uint32 HighCredit,sint32 LowCredit)793 void GMAC_SetTxQueueCreditBasedShaper(Gmac_Ip_QueueType * QueueBase,
794 uint32 SendSlopeCredit,
795 uint32 HighCredit,
796 sint32 LowCredit)
797 {
798 QueueBase->MTL_TXQ_SENDSLOPECREDIT = SendSlopeCredit;
799 QueueBase->MTL_TXQ_HICREDIT = HighCredit;
800 QueueBase->MTL_TXQ_LOCREDIT = (uint32)LowCredit;
801 }
802
803 /*FUNCTION**********************************************************************
804 *
805 * Function Name : GMAC_SetTxQueueOperationMode
806 * Description : Sets the operation mode for a Tx Queue
807 *
808 *END**************************************************************************/
GMAC_SetTxQueueOperationMode(Gmac_Ip_QueueType * QueueBase,Gmac_Ip_OperationModeType QueueMode,uint32 QueueSize)809 void GMAC_SetTxQueueOperationMode(Gmac_Ip_QueueType * QueueBase,
810 Gmac_Ip_OperationModeType QueueMode,
811 uint32 QueueSize)
812 {
813 uint32 BlockNum;
814 BlockNum = QueueSize / FEATURE_GMAC_MTL_TX_FIFO_BLOCK_SIZE;
815 BlockNum = (BlockNum == 0U)? 0U : (BlockNum - 1UL);
816
817 QueueBase->MTL_TXQ_OPERATION_MODE = GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN((uint32)QueueMode) |
818 GMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK |
819 (((uint32)(BlockNum <<
820 GMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT)) &
821 GMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK);
822 }
823
824 /*FUNCTION**********************************************************************
825 *
826 * Function Name : GMAC_SetTxStoreAndForward
827 * Description : Enable store and forward for a specific Tx Queue.
828 *
829 *END**************************************************************************/
GMAC_SetTxStoreAndForward(Gmac_Ip_QueueType * QueueBase)830 void GMAC_SetTxStoreAndForward(Gmac_Ip_QueueType * QueueBase)
831 {
832 QueueBase->MTL_TXQ_OPERATION_MODE |= GMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK;
833 }
834
835 /*FUNCTION**********************************************************************
836 *
837 * Function Name : GMAC_SetTxThreshold
838 * Description : Sets the Tx threshold value.
839 *
840 *END**************************************************************************/
GMAC_SetTxThreshold(Gmac_Ip_QueueType * QueueBase,Gmac_Ip_TxThresholdType ThresholdValue)841 void GMAC_SetTxThreshold(Gmac_Ip_QueueType * QueueBase,
842 Gmac_Ip_TxThresholdType ThresholdValue)
843 {
844 QueueBase->MTL_TXQ_OPERATION_MODE &= ~(GMAC_MTL_TXQ0_OPERATION_MODE_TSF_MASK |
845 GMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK);
846 QueueBase->MTL_TXQ_OPERATION_MODE |= GMAC_MTL_TXQ0_OPERATION_MODE_TTC((uint32)ThresholdValue);
847 }
848
849 /*FUNCTION**********************************************************************
850 *
851 * Function Name : GMAC_EnableRxQueue
852 * Description : Enables the given Rx Queue for generic traffic with the given VLAN priorities.
853 *
854 *END**************************************************************************/
GMAC_EnableRxQueue(GMAC_Type * Base,uint8 PriorityMask,uint8 QueueNum)855 void GMAC_EnableRxQueue(GMAC_Type * Base,
856 uint8 PriorityMask,
857 uint8 QueueNum)
858 {
859 /* Set Rx Queue's VLAN Priorities */
860 #if FEATURE_GMAC_NUM_QUEUES > 4
861 if (QueueNum < 4U)
862 {
863 #endif
864 Base->MAC_RXQ_CTRL2 |= (uint32)((uint32)PriorityMask << (uint32)((uint32)QueueNum * GMAC_MAC_RXQ_CTRL2_PSRQ0_WIDTH));
865 #if FEATURE_GMAC_NUM_QUEUES > 4
866 }
867 else
868 {
869 Base->MAC_RXQ_CTRL3 |= (uint32)((uint32)PriorityMask << (uint32)(((uint32)QueueNum - 4U) * GMAC_MAC_RXQ_CTRL2_PSRQ0_WIDTH));
870 }
871 #endif
872
873 /* Enable the Rx Queue */
874 Base->MAC_RXQ_CTRL0 |= (uint32)((uint32)GMAC_OP_MODE_DCB_GEN << (uint32)((uint32)QueueNum * GMAC_MAC_RXQ_CTRL0_RXQ0EN_WIDTH));
875 }
876
877 /*FUNCTION**********************************************************************
878 *
879 * Function Name : GMAC_SetRxQueueOperationMode
880 * Description : Sets the operation mode for an Rx queue
881 *
882 *END**************************************************************************/
GMAC_SetRxQueueOperationMode(Gmac_Ip_QueueType * QueueBase,uint32 QueueSize)883 void GMAC_SetRxQueueOperationMode(Gmac_Ip_QueueType * QueueBase,
884 uint32 QueueSize)
885 {
886 uint32 BlockNum;
887 BlockNum = QueueSize / FEATURE_GMAC_MTL_RX_FIFO_BLOCK_SIZE;
888 BlockNum = (BlockNum == 0U)? 0U : (BlockNum - 1UL);
889
890 QueueBase->MTL_RXQ_OPERATION_MODE = (((uint32)(BlockNum <<
891 GMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT)) &
892 GMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK);
893 }
894
895 /*FUNCTION**********************************************************************
896 *
897 * Function Name : GMAC_SetRxQueuesDmaChMap
898 * Description : Sets the DMA channel mapping for Rx queues
899 *
900 *END**************************************************************************/
GMAC_SetRxQueuesDmaChMap(GMAC_Type * Base,uint8 QueuesNum)901 void GMAC_SetRxQueuesDmaChMap(GMAC_Type * Base,
902 uint8 QueuesNum)
903 {
904 if (QueuesNum > 0U)
905 {
906 Base->MTL_RXQ_DMA_MAP0 |= GMAC_MTL_RXQ_DMA_MAP0_Q0DDMACH(0U) |
907 GMAC_MTL_RXQ_DMA_MAP0_Q0MDMACH(0U);
908 }
909 #if FEATURE_GMAC_NUM_CHANNELS > 1U
910 if (QueuesNum > 1U)
911 {
912 Base->MTL_RXQ_DMA_MAP0 |= GMAC_MTL_RXQ_DMA_MAP0_Q1DDMACH(0U) |
913 GMAC_MTL_RXQ_DMA_MAP0_Q1MDMACH(1U);
914 }
915 #endif
916 #if FEATURE_GMAC_NUM_CHANNELS > 2U
917 if (QueuesNum > 2U)
918 {
919 Base->MTL_RXQ_DMA_MAP0 |= GMAC_MTL_RXQ_DMA_MAP0_Q2DDMACH(0U) |
920 GMAC_MTL_RXQ_DMA_MAP0_Q2MDMACH(2U);
921 }
922 #endif
923 #if FEATURE_GMAC_NUM_CHANNELS > 3U
924 if (QueuesNum > 3U)
925 {
926 Base->MTL_RXQ_DMA_MAP0 |= GMAC_MTL_RXQ_DMA_MAP0_Q3DDMACH(0U) |
927 GMAC_MTL_RXQ_DMA_MAP0_Q3MDMACH(3U);
928 }
929 #endif
930 #if FEATURE_GMAC_NUM_CHANNELS > 4U
931 if (QueuesNum > 4U)
932 {
933 Base->MTL_RXQ_DMA_MAP1 |= GMAC_MTL_RXQ_DMA_MAP1_Q4DDMACH(0U) |
934 GMAC_MTL_RXQ_DMA_MAP1_Q4MDMACH(4U);
935 }
936 #endif
937 }
938
939 /*FUNCTION**********************************************************************
940 *
941 * Function Name : GMAC_SetVlanTagInvMatch
942 * Description : Sets VLAN Tag inverse match.
943 *
944 *END**************************************************************************/
GMAC_SetVlanTagInvMatch(GMAC_Type * Base,boolean Enable)945 void GMAC_SetVlanTagInvMatch(GMAC_Type * Base, boolean Enable)
946 {
947 if (Enable)
948 {
949 Base->MAC_VLAN_TAG_CTRL_REG |= GMAC_MAC_VLAN_TAG_CTRL_VTIM_MASK;
950 }
951 else
952 {
953 Base->MAC_VLAN_TAG_CTRL_REG &= ~GMAC_MAC_VLAN_TAG_CTRL_VTIM_MASK;
954 }
955 }
956 /*FUNCTION**********************************************************************
957 *
958 * Function Name : GMAC_SetVlanTagDataRxMatch
959 * Description : Sets MAC_VLAN_Tag_Data register with Rx matching relevant
960 * data.
961 *
962 *END**************************************************************************/
GMAC_SetVlanTagDataRxMatch(GMAC_Type * Base,boolean EnInnerVlanMatch,boolean EnSvlanMatch,boolean DisVlanTypeMatch,boolean En12bitMatch)963 void GMAC_SetVlanTagDataRxMatch(GMAC_Type * Base,
964 boolean EnInnerVlanMatch,
965 boolean EnSvlanMatch,
966 boolean DisVlanTypeMatch,
967 boolean En12bitMatch)
968 {
969 if (EnInnerVlanMatch)
970 {
971 Base->MAC_VLAN_TAG_DATA_REG |= GMAC_MAC_VLAN_TAG_DATA_ERIVLT_MASK;
972 }
973 else
974 {
975 Base->MAC_VLAN_TAG_DATA_REG &= ~GMAC_MAC_VLAN_TAG_DATA_ERIVLT_MASK;
976 }
977
978 if (EnSvlanMatch)
979 {
980 Base->MAC_VLAN_TAG_DATA_REG |= GMAC_MAC_VLAN_TAG_DATA_ERSVLM_MASK;
981 }
982 else
983 {
984 Base->MAC_VLAN_TAG_DATA_REG &= ~GMAC_MAC_VLAN_TAG_DATA_ERSVLM_MASK;
985 }
986
987 if (DisVlanTypeMatch)
988 {
989 Base->MAC_VLAN_TAG_DATA_REG |= GMAC_MAC_VLAN_TAG_DATA_DOVLTC_MASK;
990 }
991 else
992 {
993 Base->MAC_VLAN_TAG_DATA_REG &= ~GMAC_MAC_VLAN_TAG_DATA_DOVLTC_MASK;
994 }
995
996 if (En12bitMatch)
997 {
998 Base->MAC_VLAN_TAG_DATA_REG |= GMAC_MAC_VLAN_TAG_DATA_ETV_MASK;
999 }
1000 else
1001 {
1002 Base->MAC_VLAN_TAG_DATA_REG &= ~GMAC_MAC_VLAN_TAG_DATA_ETV_MASK;
1003 }
1004
1005 Base->MAC_VLAN_TAG_DATA_REG |= GMAC_MAC_VLAN_TAG_DATA_VEN_MASK;
1006 }
1007 #if (FEATURE_GMAC_VLAN_RX_FILTERS_NUM > 0U)
1008 /*FUNCTION**********************************************************************
1009 *
1010 * Function Name : GMAC_ReadVlanTagRxFilter
1011 * Description : Read a VLAN Tag Rx filter.
1012 *
1013 *END**************************************************************************/
GMAC_ReadVlanTagRxFilter(GMAC_Type * Base,uint8 FilterIdx,uint16 * VlanTag)1014 Gmac_Ip_StatusType GMAC_ReadVlanTagRxFilter(GMAC_Type * Base,
1015 uint8 FilterIdx,
1016 uint16 * VlanTag)
1017 {
1018 Gmac_Ip_StatusType Status = GMAC_STATUS_TIMEOUT;
1019 uint32 StartTime;
1020 uint32 ElapsedTime;
1021 uint32 TimeoutTicks;
1022
1023 /* Clear filter offset. */
1024 Base->MAC_VLAN_TAG_CTRL_REG &= ~GMAC_MAC_VLAN_TAG_CTRL_OFS_MASK;
1025 /* Set filter offset and enable write operation. */
1026 Base->MAC_VLAN_TAG_CTRL_REG |= ((uint32)(((uint32)FilterIdx) <<
1027 GMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) |
1028 GMAC_MAC_VLAN_TAG_CTRL_CT_MASK;
1029 /* Set busy bit. */
1030 Base->MAC_VLAN_TAG_CTRL_REG |= GMAC_MAC_VLAN_TAG_CTRL_OB_MASK;
1031
1032 #ifdef MCAL_ENABLE_FAULT_INJECTION
1033 MCAL_FAULT_INJECTION_POINT(ETH_READ_VLAN_TAG_RX_FILTER_TIMEOUT);
1034 #endif
1035
1036 GMAC_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, GMAC_TIMEOUT_VALUE_US);
1037 do
1038 {
1039 if ((Base->MAC_VLAN_TAG_CTRL_REG & GMAC_MAC_VLAN_TAG_CTRL_OB_MASK) == 0U)
1040 {
1041 Status = GMAC_STATUS_SUCCESS;
1042 break;
1043 }
1044 }
1045 while (!GMAC_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
1046
1047 if (Status == GMAC_STATUS_SUCCESS)
1048 {
1049 /* Read the VLAN tag. */
1050 *VlanTag = (uint16)(Base->MAC_VLAN_TAG_DATA_REG &
1051 GMAC_MAC_VLAN_TAG_DATA_VID_MASK);
1052 }
1053
1054 return Status;
1055 }
1056 #endif
1057
1058 #define ETH_43_GMAC_STOP_SEC_CODE
1059 #include "Eth_43_GMAC_MemMap.h"
1060
1061
1062 #ifdef __cplusplus
1063 }
1064 #endif
1065 /** @} */
1066
