1 /** 2 ****************************************************************************** 3 * @file hts221_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * hts221_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef HTS221_REGS_H 23 #define HTS221_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup HTS221 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 115 typedef struct 116 { 117 /** Component mandatory fields **/ 118 stmdev_write_ptr write_reg; 119 stmdev_read_ptr read_reg; 120 /** Customizable optional pointer **/ 121 void *handle; 122 } stmdev_ctx_t; 123 124 /** 125 * @} 126 * 127 */ 128 129 #endif /* MEMS_SHARED_TYPES */ 130 131 #ifndef MEMS_UCF_SHARED_TYPES 132 #define MEMS_UCF_SHARED_TYPES 133 134 /** @defgroup Generic address-data structure definition 135 * @brief This structure is useful to load a predefined configuration 136 * of a sensor. 137 * You can create a sensor configuration by your own or using 138 * Unico / Unicleo tools available on STMicroelectronics 139 * web site. 140 * 141 * @{ 142 * 143 */ 144 145 typedef struct 146 { 147 uint8_t address; 148 uint8_t data; 149 } ucf_line_t; 150 151 /** 152 * @} 153 * 154 */ 155 156 #endif /* MEMS_UCF_SHARED_TYPES */ 157 158 /** 159 * @} 160 * 161 */ 162 163 /** @defgroup HTS221_Infos 164 * @{ 165 * 166 */ 167 168 /** I2C Device Address 8 bit format **/ 169 #define HTS221_I2C_ADDRESS 0xBFU 170 171 /** Device Identification (Who am I) **/ 172 #define HTS221_ID 0xBCU 173 174 /** 175 * @} 176 * 177 */ 178 179 #define HTS221_WHO_AM_I 0x0FU 180 #define HTS221_AV_CONF 0x10U 181 typedef struct 182 { 183 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 184 uint8_t avgh : 3; 185 uint8_t avgt : 3; 186 uint8_t not_used_01 : 2; 187 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 188 uint8_t not_used_01 : 2; 189 uint8_t avgt : 3; 190 uint8_t avgh : 3; 191 #endif /* DRV_BYTE_ORDER */ 192 } hts221_av_conf_t; 193 194 #define HTS221_CTRL_REG1 0x20U 195 typedef struct 196 { 197 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 198 uint8_t odr : 2; 199 uint8_t bdu : 1; 200 uint8_t not_used_01 : 4; 201 uint8_t pd : 1; 202 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 203 uint8_t pd : 1; 204 uint8_t not_used_01 : 4; 205 uint8_t bdu : 1; 206 uint8_t odr : 2; 207 #endif /* DRV_BYTE_ORDER */ 208 } hts221_ctrl_reg1_t; 209 210 #define HTS221_CTRL_REG2 0x21U 211 typedef struct 212 { 213 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 214 uint8_t one_shot : 1; 215 uint8_t heater : 1; 216 uint8_t not_used_01 : 5; 217 uint8_t boot : 1; 218 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 219 uint8_t boot : 1; 220 uint8_t not_used_01 : 5; 221 uint8_t heater : 1; 222 uint8_t one_shot : 1; 223 #endif /* DRV_BYTE_ORDER */ 224 } hts221_ctrl_reg2_t; 225 226 #define HTS221_CTRL_REG3 0x22U 227 typedef struct 228 { 229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 230 uint8_t not_used_01 : 2; 231 uint8_t drdy : 1; 232 uint8_t not_used_02 : 3; 233 uint8_t pp_od : 1; 234 uint8_t drdy_h_l : 1; 235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 236 uint8_t drdy_h_l : 1; 237 uint8_t pp_od : 1; 238 uint8_t not_used_02 : 3; 239 uint8_t drdy : 1; 240 uint8_t not_used_01 : 2; 241 #endif /* DRV_BYTE_ORDER */ 242 } hts221_ctrl_reg3_t; 243 244 #define HTS221_STATUS_REG 0x27U 245 typedef struct 246 { 247 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 248 uint8_t t_da : 1; 249 uint8_t h_da : 1; 250 uint8_t not_used_01 : 6; 251 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 252 uint8_t not_used_01 : 6; 253 uint8_t h_da : 1; 254 uint8_t t_da : 1; 255 #endif /* DRV_BYTE_ORDER */ 256 } hts221_status_reg_t; 257 258 #define HTS221_HUMIDITY_OUT_L 0x28U 259 #define HTS221_HUMIDITY_OUT_H 0x29U 260 #define HTS221_TEMP_OUT_L 0x2AU 261 #define HTS221_TEMP_OUT_H 0x2BU 262 #define HTS221_H0_RH_X2 0x30U 263 #define HTS221_H1_RH_X2 0x31U 264 #define HTS221_T0_DEGC_X8 0x32U 265 #define HTS221_T1_DEGC_X8 0x33U 266 #define HTS221_T1_T0_MSB 0x35U 267 typedef struct 268 { 269 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 270 uint8_t t0_msb : 2; 271 uint8_t t1_msb : 2; 272 uint8_t not_used_01 : 4; 273 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 274 uint8_t not_used_01 : 4; 275 uint8_t t1_msb : 2; 276 uint8_t t0_msb : 2; 277 #endif /* DRV_BYTE_ORDER */ 278 } hts221_t1_t0_msb_t; 279 280 #define HTS221_H0_T0_OUT_L 0x36U 281 #define HTS221_H0_T0_OUT_H 0x37U 282 #define HTS221_H1_T0_OUT_L 0x3AU 283 #define HTS221_H1_T0_OUT_H 0x3BU 284 #define HTS221_T0_OUT_L 0x3CU 285 #define HTS221_T0_OUT_H 0x3DU 286 #define HTS221_T1_OUT_L 0x3EU 287 #define HTS221_T1_OUT_H 0x3FU 288 289 /** 290 * @defgroup HTS221_Register_Union 291 * @brief This union group all the registers having a bit-field 292 * description. 293 * This union is useful but it's not needed by the driver. 294 * 295 * REMOVING this union you are compliant with: 296 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 297 * 298 * @{ 299 * 300 */ 301 typedef union 302 { 303 hts221_av_conf_t av_conf; 304 hts221_ctrl_reg1_t ctrl_reg1; 305 hts221_ctrl_reg2_t ctrl_reg2; 306 hts221_ctrl_reg3_t ctrl_reg3; 307 hts221_status_reg_t status_reg; 308 hts221_t1_t0_msb_t t1_t0_msb; 309 bitwise_t bitwise; 310 uint8_t byte; 311 } hts221_reg_t; 312 313 /** 314 * @} 315 * 316 */ 317 318 int32_t hts221_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data, 319 uint16_t len); 320 int32_t hts221_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 321 uint8_t *data, 322 uint16_t len); 323 324 typedef enum 325 { 326 HTS221_H_AVG_4 = 0, 327 HTS221_H_AVG_8 = 1, 328 HTS221_H_AVG_16 = 2, 329 HTS221_H_AVG_32 = 3, 330 HTS221_H_AVG_64 = 4, 331 HTS221_H_AVG_128 = 5, 332 HTS221_H_AVG_256 = 6, 333 HTS221_H_AVG_512 = 7, 334 HTS221_H_AVG_ND = 8, 335 } hts221_avgh_t; 336 int32_t hts221_humidity_avg_set(stmdev_ctx_t *ctx, hts221_avgh_t val); 337 int32_t hts221_humidity_avg_get(stmdev_ctx_t *ctx, 338 hts221_avgh_t *val); 339 340 typedef enum 341 { 342 HTS221_T_AVG_2 = 0, 343 HTS221_T_AVG_4 = 1, 344 HTS221_T_AVG_8 = 2, 345 HTS221_T_AVG_16 = 3, 346 HTS221_T_AVG_32 = 4, 347 HTS221_T_AVG_64 = 5, 348 HTS221_T_AVG_128 = 6, 349 HTS221_T_AVG_256 = 7, 350 HTS221_T_AVG_ND = 8, 351 } hts221_avgt_t; 352 int32_t hts221_temperature_avg_set(stmdev_ctx_t *ctx, 353 hts221_avgt_t val); 354 int32_t hts221_temperature_avg_get(stmdev_ctx_t *ctx, 355 hts221_avgt_t *val); 356 357 typedef enum 358 { 359 HTS221_ONE_SHOT = 0, 360 HTS221_ODR_1Hz = 1, 361 HTS221_ODR_7Hz = 2, 362 HTS221_ODR_12Hz5 = 3, 363 HTS221_ODR_ND = 4, 364 } hts221_odr_t; 365 int32_t hts221_data_rate_set(stmdev_ctx_t *ctx, hts221_odr_t val); 366 int32_t hts221_data_rate_get(stmdev_ctx_t *ctx, hts221_odr_t *val); 367 368 int32_t hts221_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); 369 int32_t hts221_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); 370 371 int32_t hts221_one_shoot_trigger_set(stmdev_ctx_t *ctx, uint8_t val); 372 int32_t hts221_one_shoot_trigger_get(stmdev_ctx_t *ctx, uint8_t *val); 373 374 int32_t hts221_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 375 376 int32_t hts221_hum_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); 377 378 int32_t hts221_humidity_raw_get(stmdev_ctx_t *ctx, int16_t *val); 379 380 int32_t hts221_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val); 381 382 int32_t hts221_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); 383 384 int32_t hts221_power_on_set(stmdev_ctx_t *ctx, uint8_t val); 385 386 int32_t hts221_power_on_get(stmdev_ctx_t *ctx, uint8_t *val); 387 388 int32_t hts221_heater_set(stmdev_ctx_t *ctx, uint8_t val); 389 int32_t hts221_heater_get(stmdev_ctx_t *ctx, uint8_t *val); 390 391 int32_t hts221_boot_set(stmdev_ctx_t *ctx, uint8_t val); 392 int32_t hts221_boot_get(stmdev_ctx_t *ctx, uint8_t *val); 393 394 int32_t hts221_status_get(stmdev_ctx_t *ctx, 395 hts221_status_reg_t *val); 396 397 int32_t hts221_drdy_on_int_set(stmdev_ctx_t *ctx, uint8_t val); 398 int32_t hts221_drdy_on_int_get(stmdev_ctx_t *ctx, uint8_t *val); 399 400 typedef enum 401 { 402 HTS221_PUSH_PULL = 0, 403 HTS221_OPEN_DRAIN = 1, 404 HTS221_PIN_MODE_ND = 2, 405 } hts221_pp_od_t; 406 int32_t hts221_pin_mode_set(stmdev_ctx_t *ctx, hts221_pp_od_t val); 407 int32_t hts221_pin_mode_get(stmdev_ctx_t *ctx, hts221_pp_od_t *val); 408 409 typedef enum 410 { 411 HTS221_ACTIVE_HIGH = 0, 412 HTS221_ACTIVE_LOW = 1, 413 HTS221_ACTIVE_ND = 2, 414 } hts221_drdy_h_l_t; 415 int32_t hts221_int_polarity_set(stmdev_ctx_t *ctx, 416 hts221_drdy_h_l_t val); 417 int32_t hts221_int_polarity_get(stmdev_ctx_t *ctx, 418 hts221_drdy_h_l_t *val); 419 420 int32_t hts221_hum_rh_point_0_get(stmdev_ctx_t *ctx, float_t *val); 421 int32_t hts221_hum_rh_point_1_get(stmdev_ctx_t *ctx, float_t *val); 422 423 int32_t hts221_temp_deg_point_0_get(stmdev_ctx_t *ctx, float_t *val); 424 int32_t hts221_temp_deg_point_1_get(stmdev_ctx_t *ctx, float_t *val); 425 426 int32_t hts221_hum_adc_point_0_get(stmdev_ctx_t *ctx, float_t *val); 427 int32_t hts221_hum_adc_point_1_get(stmdev_ctx_t *ctx, float_t *val); 428 429 int32_t hts221_temp_adc_point_0_get(stmdev_ctx_t *ctx, float_t *val); 430 int32_t hts221_temp_adc_point_1_get(stmdev_ctx_t *ctx, float_t *val); 431 432 /** 433 * @} 434 * 435 */ 436 437 #ifdef __cplusplus 438 } 439 #endif 440 441 #endif /*HTS221_REGS_H */ 442 443 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 444
