1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18
19 /********************************************************************************************************
20 * @file spi.h
21 *
22 * @brief This is the header file for B91
23 *
24 * @author Driver Group
25 *
26 *******************************************************************************************************/
27 #ifndef SPI_H
28 #define SPI_H
29
30 #include "reg_include/register_b91.h"
31 #include "gpio.h"
32 #include "dma.h"
33 /** @page SPI
34 *
35 * Introduction
36 * ===============
37 * B91 supports two spi
38 *
39 * API Reference
40 * ===============
41 * Header File: spi.h
42 */
43
44 typedef enum{
45 SPI_RXFIFO_OR_INT_EN =BIT(0),
46 SPI_TXFIFO_UR_INT_EN =BIT(1),
47 SPI_RXFIFO_INT_EN =BIT(2),
48 SPI_TXFIFO_INT_EN =BIT(3),
49 SPI_END_INT_EN =BIT(4),
50 SPI_SLV_CMD_EN =BIT(5),
51 }spi_irq_mask;
52
53 typedef enum{
54 SPI_RXF_OR_INT =BIT(2),
55 SPI_TXF_UR_INT =BIT(3),
56 SPI_RXF_INT =BIT(4),
57 SPI_TXF_INT =BIT(5),
58 SPI_END_INT =BIT(6),
59 SPI_SLV_CMD_INT =BIT(7),
60 }spi_irq_status_e;
61
62 typedef enum{
63 PSPI_MODULE = 0,
64 HSPI_MODULE = 1 ,
65 }spi_sel_e;
66
67 /**
68 * @brief Define the work mode.
69 */
70 typedef enum{
71 SPI_MODE0 = 0,
72 /**
73 * change enum SPI_MODE1 value to 1 from 2,
74 * enum SPI_MODE2 value to 2 from 1,
75 * changed by chaofan.20210113.
76 */
77 SPI_MODE1,
78 SPI_MODE2,
79 SPI_MODE3,
80 } spi_mode_type_e;
81
82 /**
83 * @brief Define the mode for SPI io mode.
84 */
85 typedef enum{
86 SPI_SINGLE_MODE = 0,
87 SPI_DUAL_MODE = 1 ,
88 HSPI_QUAD_MODE = 2,
89 SPI_3_LINE_MODE = 3
90 } spi_io_mode_e;
91
92 typedef enum{
93 SPI_NOMAL = 0,
94 SPI_3LINE = 3,
95 } spi_nomal_3line_mode_e;
96
97 typedef enum{
98 PSPI_SINGLE = 0,
99 PSPI_DUAL = 1,
100 PSPI_3LINE = 3
101 } pspi_single_dual_mode_e;
102
103 typedef enum{
104 HSPI_SINGLE = 0,
105 HSPI_DUAL = 1,
106 HSPI_QUAD = 2,
107 HSPI_3LINE = 3
108 } hspi_single_dual_quad_mode_e;
109
110
111 /**
112 * @brief Define the SPI command & translate mode.
113 */
114 typedef enum{
115 SPI_MODE_WRITE_AND_READ = 0,//write and read at the same.must enbale CmdEn
116 SPI_MODE_WRITE_ONLY,//write
117 SPI_MODE_READ_ONLY,// read must enbale CmdEn
118 SPI_MODE_WRITE_READ,//write_ read
119 SPI_MODE_READ_WRITE,//read_write
120 SPI_MODE_WRITE_DUMMY_READ,//write_dummy_read
121 SPI_MODE_READ_DUMMY_WRITE,//read_ dummy_write must enbale CmdEn
122 SPI_MODE_NONE_DATA,//must enbale CmdEn
123 SPI_MODE_DUMMY_WRITE,//dummy_write
124 SPI_MODE_DUMMY_READ,//dummy_read
125 SPI_MODE_RESERVED,
126 }spi_tans_mode_e;
127
128 typedef enum{
129 SPI_MODE_WR_WRITE_ONLY = 1,//write
130 SPI_MODE_WR_DUMMY_WRITE = 8,//dummy_write
131 }spi_wr_tans_mode_e;
132
133 typedef enum{
134 SPI_MODE_RD_READ_ONLY = 2,//must enbale CmdEn
135 SPI_MODE_RD_DUMMY_READ = 9,//dummy_read
136 }spi_rd_tans_mode_e;
137
138 typedef enum{
139 SPI_MODE_WR_RD = 3,//must enbale CmdEn
140 SPI_MODE_WR_DUMMY_RD = 5,//write_dummy_read
141 }spi_wr_rd_tans_mode_e;
142
143 typedef struct{
144 hspi_single_dual_quad_mode_e hspi_io_mode;//set spi interface mode
145 unsigned char hspi_dummy_cnt;//set dummy cnt if tans_mode have dummy .
146 unsigned char hspi_cmd_en;//enable cmd phase
147 unsigned char hspi_addr_en;//enable address phase
148 unsigned char hspi_addr_len;//enable address phase
149 unsigned char hspi_cmd_fmt_en;//if cmd_en enable cmd fmt will follow the interface (dual/quad)
150 unsigned char hspi_addr_fmt_en;//if addr_en enable addr fmt will follow the interface (dual/quad)
151 }hspi_config_t;
152
153 typedef struct{
154 pspi_single_dual_mode_e pspi_io_mode;//set spi interface mode
155 unsigned char pspi_dummy_cnt;//set dummy cnt if tans_mode have dummy .
156 _Bool pspi_cmd_en;//enable cmd phase
157 }pspi_config_t;
158
159
160 typedef enum{
161 SPI_SLAVE_WRITE_DATA_CMD = 0x00,
162 SPI_SLAVE_WRITE_DATA_DUAL_CMD = FLD_SPI_CMD_DATA_DUAL,
163 SPI_SLAVE_WRITE_ADDR_DUAL_CMD = FLD_SPI_CMD_ADDR_DUAL,
164
165 SPI_SLAVE_WRITE_DATA_DUAL_4CYC_CMD = FLD_SPI_CMD_DATA_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
166 SPI_SLAVE_WRITE_ADDR_DUAL_4CYC_CMD = FLD_SPI_CMD_ADDR_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
167 SPI_SLAVE_WRITE_DATA_AND_ADDR_DUL_4CYC_CMD = FLD_SPI_CMD_ADDR_DUAL | FLD_SPI_CMD_DATA_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
168 }spi_slave_write_cmd_e;
169
170 typedef enum{
171 SPI_SLAVE_READ_DATA_CMD = FLD_SPI_CMD_RD_EN,
172 SPI_SLAVE_READ_DATA_DUAL_CMD = FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_DATA_DUAL,
173 SPI_SLAVE_READ_ADDR_DUAL_CMD = FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_ADDR_DUAL,
174
175 SPI_SLAVE_READ_DATA_DUAL_4CYC_CMD = FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_DATA_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
176 SPI_SLAVE_READ_ADDR_DUAL_4CYC_CMD = FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_ADDR_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
177
178 SPI_SLAVE_READ_DATA_AND_ADDR_DUL_4CYC_CMD = FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_ADDR_DUAL | FLD_SPI_CMD_DATA_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
179
180 }spi_slave_read_cmd_e;
181
182 typedef enum{
183 SPI_READ_STATUS_SINGLE_CMD = 0x05,
184 SPI_READ_STATUS_DUAL_CMD = 0x15,
185 HSPI_READ_STATUS_QUAD_CMD = 0x25,
186 SPI_READ_DATA_SINGLE_CMD = 0x0B,
187 SPI_READ_DATA_DUAL_CMD = 0x0C,
188 HSPI_READ_DATA_QUAD_CMD = 0x0E,
189 SPI_WRITE_DATA_SINGLE_CMD = 0x51,
190 SPI_WRITE_DATA_DUAL_CMD = 0x52,
191 HSPI_WRITE_DATA_QUAD_CMD = 0x54,
192 }pspi_hspi_cmd_e;
193 /**
194 * @brief Define APS1604M-3SQR QSPI PSRAM CMD.
195 */
196 typedef enum{
197 PSRAM_READ_CMD = 0x03,
198 PSRAM_FAST_READ_CMD = 0x0B,
199 PSRAM_FAST_READ_QUAD_CMD = 0xEB,
200
201 PSRAM_WRITE_CMD = 0x02,
202 PSRAM_QUAD_WRITE_CMD = 0x38,//
203 PSRAM_WRAPPED_READ_CMD = 0x8B,
204 PSRAM_WRAPPED_WRITE_CMD = 0x82,
205
206 PSRAM_MODE_RG_READ_CMD = 0xB5,
207 PSRAM_MODE_RG_WRITE_CMD = 0xB1,
208
209 PSRAM_ENTER_QUAD_MODE_CMD = 0x35,
210 PSRAM_EXIT_QUAD_MODE_CMD = 0xF5,
211
212 PSRAM_REST_ENABLE_CMD = 0x66,
213 PSRAM_REST_CMD = 0x99,
214 PSRAM_BURST_LENGTH_TOGGLE_CMD = 0xC0,
215 PSRAM_READ_ID_CMD = 0x95,
216
217 }spi_xip_cmd_e;
218
219 /**
220 * @brief Define panel 2data_lane_mode
221 */
222 typedef enum{
223 HSPI_2DATA_LANE_CLOSE = 0x00,
224 HSPI_2DATA_LANE_RGB565 = 0x01,
225 HSPI_2DATA_LANE_RGB666 = 0x03,
226 HSPI_2DATA_LANE_RGB888 = 0x07,
227 }hspi_panel_2data_lane_mode_e;
228
229 /**
230 * @brief Define the SPI io.
231 */
232 typedef enum{
233 HSPI_CLK_PB4 = GPIO_PB4,
234 HSPI_CLK_PA2 = GPIO_PA2,
235 }hspi_clk_pin_def_e;
236
237 typedef enum{
238 HSPI_CSN_PB6 = GPIO_PB6,
239 HSPI_CSN_PA1 = GPIO_PA1,
240 }hspi_csn_pin_def_e;
241
242 typedef enum{
243 HSPI_MOSI_IO0_PB3 = GPIO_PB3,
244 HSPI_MOSI_IO0_PA4 = GPIO_PA4,
245 }hspi_mosi_io0_pin_def_e;
246
247 typedef enum{
248 HSPI_MISO_IO1_PB2 = GPIO_PB2,
249 HSPI_MISO_IO1_PA3 = GPIO_PA3,
250 }hspi_miso_io1_pin_def_e;
251
252 typedef enum{
253 HSPI_WP_IO2_PB1 = GPIO_PB1,
254 }hspi_wp_io2_pin_def_e;
255
256 typedef enum{
257 HSPI_HOLD_IO3_PB0 = GPIO_PB0,
258 }hspi_hold_io3_pin_def_e;
259
260 typedef enum{
261 HSPI_CLK_PB4_PIN = GPIO_PB4,
262 HSPI_CLK_PA2_PIN = GPIO_PA2,
263
264 HSPI_CSN_PB6_PIN = GPIO_PB6,
265 HSPI_CSN_PA1_PIN = GPIO_PA1,
266
267 HSPI_MOSI_IO0_PB3_PIN = GPIO_PB3,
268 HSPI_MOSI_IO0_PA4_PIN = GPIO_PA4,
269
270 HSPI_MISO_IO1_PB2_PIN = GPIO_PB2,
271 HSPI_MISO_IO1_PA3_PIN = GPIO_PA3,
272
273 HSPI_WP_IO2_PB1_PIN = GPIO_PB1,
274 HSPI_HOLD_IO3_PB0_PIN = GPIO_PB0,
275 HSPI_NONE_PIN = 0xfff,
276 }hspi_pin_def_e;
277
278 typedef struct{
279 hspi_clk_pin_def_e hspi_clk_pin;
280 hspi_csn_pin_def_e hspi_csn_pin;
281 hspi_mosi_io0_pin_def_e hspi_mosi_io0_pin;
282 hspi_miso_io1_pin_def_e hspi_miso_io1_pin;
283 hspi_wp_io2_pin_def_e hspi_wp_io2_pin;
284 hspi_hold_io3_pin_def_e hspi_hold_io3_pin;
285 }hspi_pin_config_t;
286
287
288 typedef enum{
289 PSPI_CLK_PC5 = GPIO_PC5,
290 PSPI_CLK_PB5 = GPIO_PB5,
291 PSPI_CLK_PD1 = GPIO_PD1,
292 }pspi_clk_pin_def_e;
293
294 typedef enum{
295 PSPI_CSN_PC4 = GPIO_PC4,
296 PSPI_CSN_PC0 = GPIO_PC0,
297 PSPI_CSN_PD0 = GPIO_PD0,
298 }pspi_csn_pin_def_e;
299
300 typedef enum{
301 PSPI_MOSI_IO0_PC7 = GPIO_PC7,
302 PSPI_MOSI_IO0_PB7 = GPIO_PB7,
303 PSPI_MOSI_IO0_PD3 = GPIO_PD3,
304 }pspi_mosi_io0_pin_def_e;
305
306 typedef enum{
307 PSPI_MISO_IO1_PC6 = GPIO_PC6,
308 PSPI_MISO_IO1_PB6 = GPIO_PB6,
309 PSPI_MISO_IO1_PD2 = GPIO_PD2,
310 }pspi_miso_io1_pin_def_e;
311
312 typedef enum{
313 PSPI_CLK_PC5_PIN = GPIO_PC5,
314 PSPI_CLK_PB5_PIN = GPIO_PB5,
315 PSPI_CLK_PD1_PIN = GPIO_PD1,
316
317 PSPI_CSN_PC4_PIN = GPIO_PC4,
318 PSPI_CSN_PC0_PIN = GPIO_PC0,
319 PSPI_CSN_PD0_PIN = GPIO_PD0,
320
321 PSPI_MOSI_IO0_PC7_PIN = GPIO_PC7,
322 PSPI_MOSI_IO0_PB7_PIN = GPIO_PB7,
323 PSPI_MOSI_IO0_PD3_PIN = GPIO_PD3,
324
325 PSPI_MISO_IO1_PC6_PIN = GPIO_PC6,
326 PSPI_MISO_IO1_PB6_PIN = GPIO_PB6,
327 PSPI_MISO_IO1_PD2_PIN = GPIO_PD2,
328 PSPI_NONE_PIN = 0xfff,
329 }pspi_pin_def_e;
330
331 typedef struct{
332 pspi_clk_pin_def_e pspi_clk_pin;
333 pspi_csn_pin_def_e pspi_csn_pin;
334 pspi_mosi_io0_pin_def_e pspi_mosi_io0_pin;
335 pspi_miso_io1_pin_def_e pspi_miso_io1_pin;
336 }pspi_pin_config_t;
337
338
339 /**
340 * @brief This function reset HSPI module.
341 * @return none
342 */
hspi_reset(void)343 static inline void hspi_reset(void)
344 {
345 reg_rst0 &= (~FLD_RST0_HSPI);
346 reg_rst0 |= FLD_RST0_HSPI;
347 }
348 /**
349 * @brief This function reset PSPI module.
350 * @return none
351 */
pspi_reset(void)352 static inline void pspi_reset(void)
353 {
354 reg_rst1 &= (~FLD_RST1_PSPI);
355 reg_rst1 |= FLD_RST1_PSPI;
356 }
357
358 /**
359 * @brief This function get tx_fifo number.
360 * @param[in] spi_sel - the spi module.
361 * @return ntx_fifo - number that wait to be sent.
362 */
spi_get_txfifo_num(spi_sel_e spi_sel)363 static inline unsigned char spi_get_txfifo_num(spi_sel_e spi_sel)
364 {
365 return (reg_spi_fifo_num(spi_sel) & FLD_SPI_TXF_NUM) >> 4;
366 }
367
368 /**
369 * @brief This function get rx_fifo number.
370 * @param[in] spi_sel - the spi module.
371 * @return rx_fifo - num that have been received.
372 */
spi_get_rxfifo_num(spi_sel_e spi_sel)373 static inline unsigned char spi_get_rxfifo_num(spi_sel_e spi_sel)
374 {
375 return reg_spi_fifo_num(spi_sel) & FLD_SPI_RXF_NUM;
376 }
377
378 /**
379 * @brief This function set SPI rx_cnt.
380 * @param[in] spi_sel - the spi module.
381 * @param[in] cnt - rx amount of data.
382 * @return none
383 */
spi_rx_cnt(spi_sel_e spi_sel,unsigned int cnt)384 static inline void spi_rx_cnt(spi_sel_e spi_sel, unsigned int cnt)
385 {
386 reg_spi_rx_cnt2(spi_sel) = ((cnt - 1) >> 16) & 0xff;
387 reg_spi_rx_cnt1(spi_sel) = ((cnt - 1) >> 8) & 0xff;
388 reg_spi_rx_cnt0(spi_sel) = (cnt - 1) & 0xff;
389
390 }
391
392 /**
393 * @brief This function set SPI tx_cnt.
394 * @param[in] spi_sel - the spi module.
395 * @param[in] cnt - tx amount of data.
396 * @return none
397 */
spi_tx_cnt(spi_sel_e spi_sel,unsigned int cnt)398 static inline void spi_tx_cnt(spi_sel_e spi_sel, unsigned int cnt)
399 {
400 reg_spi_tx_cnt2(spi_sel) = ((cnt - 1) >> 16) & 0xff;
401 reg_spi_tx_cnt1(spi_sel) = ((cnt - 1) >> 8) & 0xff;
402 reg_spi_tx_cnt0(spi_sel) = (cnt - 1) & 0xff;
403
404 }
405
406 /**
407 * @brief This function clear tx_fifo.
408 * @param[in] spi_sel - the spi module.
409 * @return none
410 */
spi_tx_fifo_clr(spi_sel_e spi_sel)411 static inline void spi_tx_fifo_clr(spi_sel_e spi_sel)
412 {
413 BM_SET(reg_spi_fifo_state(spi_sel), FLD_SPI_TXF_CLR);
414 }
415
416 /**
417 * @brief This function clear rx_fifo.
418 * @param[in] spi_sel - the spi module.
419 * @return none
420 */
spi_rx_fifo_clr(spi_sel_e spi_sel)421 static inline void spi_rx_fifo_clr(spi_sel_e spi_sel)
422 {
423 BM_SET(reg_spi_fifo_state(spi_sel), FLD_SPI_RXF_CLR);
424 }
425
426 /**
427 * @brief This function set hspi command content.
428 * @param[in] spi_sel - the spi module.
429 * @param[in] cmd - command content.
430 * @return none
431 */
spi_set_cmd(spi_sel_e spi_sel,unsigned char cmd)432 static inline void spi_set_cmd(spi_sel_e spi_sel, unsigned char cmd)
433 {
434 reg_spi_trans1(spi_sel) = cmd;
435 }
436
437 /**
438 * @brief This function servers to enable cmd which will sent a byte cmd.
439 * @param[in] spi_sel - the spi module.
440 * @return none
441 */
spi_cmd_en(spi_sel_e spi_sel)442 static inline void spi_cmd_en(spi_sel_e spi_sel)
443 {
444 BM_SET( reg_spi_mode2(spi_sel), FLD_SPI_CMD_EN);
445 }
446
447 /**
448 * @brief This function servers to disable cmd which will not sent cmd.
449 * @param[in] spi_sel - the spi module.
450 * @return none
451 */
spi_cmd_dis(spi_sel_e spi_sel)452 static inline void spi_cmd_dis(spi_sel_e spi_sel)
453 {
454
455 BM_CLR(reg_spi_mode2(spi_sel), FLD_SPI_CMD_EN);
456 }
457
458 /**
459 * @brief This function servers enable cmd format,the format of cmd phase is the same as the data phase(Dual/Quad).
460 * @return none
461 */
hspi_cmd_fmt_en()462 static inline void hspi_cmd_fmt_en()
463 {
464 BM_SET( reg_spi_mode2(HSPI_MODULE), FLD_HSPI_CMD_FMT);
465 }
466
467 /**
468 * @brief This function servers disable cmd format.
469 * @return none
470 */
hspi_cmd_fmt_dis()471 static inline void hspi_cmd_fmt_dis()
472 {
473 BM_CLR(reg_spi_mode2(HSPI_MODULE), FLD_HSPI_CMD_FMT);
474 }
475
476 /**
477 * @brief This function servers to enable hspi quad mode.
478 * @return none
479 */
hspi_quad_mode_en()480 static inline void hspi_quad_mode_en()
481 {
482 BM_SET(reg_spi_mode2(HSPI_MODULE), FLD_HSPI_QUAD);
483 }
484
485 /**
486 * @brief This function servers to disable hspi quad mode.
487 * @param[in] spi_sel - the spi module.
488 * @return none
489 */
hspi_quad_mode_dis(spi_sel_e spi_sel)490 static inline void hspi_quad_mode_dis(spi_sel_e spi_sel)
491 {
492 BM_CLR(reg_spi_mode2(spi_sel), FLD_HSPI_QUAD);
493 }
494
495 /**
496 * @brief This function servers to enable hspi dual mode.
497 * @param[in] spi_sel - the spi module.
498 * @return none
499 */
spi_dual_mode_en(spi_sel_e spi_sel)500 static inline void spi_dual_mode_en(spi_sel_e spi_sel)
501 {
502 BM_SET(reg_spi_mode0(spi_sel), FLD_SPI_DUAL);
503 }
504
505 /**
506 * @brief This function servers to disable hspi dual mode.
507 * @param[in] spi_sel - the spi module.
508 * @return none
509 */
spi_dual_mode_dis(spi_sel_e spi_sel)510 static inline void spi_dual_mode_dis(spi_sel_e spi_sel)
511 {
512 BM_CLR(reg_spi_mode0(spi_sel), FLD_SPI_DUAL);
513 }
514
515 /**
516 * @brief This function servers to enable hspi 3line mode.
517 * @param[in] spi_sel - the spi module.
518 * @return none
519 */
spi_3line_mode_en(spi_sel_e spi_sel)520 static inline void spi_3line_mode_en(spi_sel_e spi_sel)
521 {
522 BM_SET(reg_spi_mode0(spi_sel), FLD_SPI_3LINE);
523 }
524
525 /**
526 * @brief This function servers to disable hspi 3line mode..
527 * @param[in] spi_sel - the spi module.
528 * @return none
529 */
spi_3line_mode_dis(spi_sel_e spi_sel)530 static inline void spi_3line_mode_dis(spi_sel_e spi_sel)
531 {
532 BM_CLR(reg_spi_mode0(spi_sel), FLD_SPI_3LINE);
533 }
534
535 /**
536 * @brief This function to enable address format.the format of addr phase is the same as the data phase(Dual/Quad).
537 * @return none
538 */
hspi_addr_fmt_en(void)539 static inline void hspi_addr_fmt_en(void)
540 {
541 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_ADDR_FMT);
542
543 }
544
545 /**
546 * @brief This function to disable address format.
547 * @return none
548 */
hspi_addr_fmt_dis(void)549 static inline void hspi_addr_fmt_dis(void)
550 {
551 BM_CLR( reg_hspi_xip_ctrl, FLD_HSPI_ADDR_FMT);
552
553 }
554
555 /**
556 * @brief This function to determine whether the bus is busy.
557 * @param[in] spi_sel - the spi module.
558 * @return 1:Indicates that the bus is busy. 0:Indicates that the bus is free.
559 */
spi_is_busy(spi_sel_e spi_sel)560 static inline _Bool spi_is_busy(spi_sel_e spi_sel)
561 {
562 return reg_spi_status(spi_sel) & FLD_HSPI_BUSY;
563
564 }
565
566 /**
567 * @brief This function enable tx dma.
568 * @param[in] spi_sel - the spi module.
569 * @return none
570 */
spi_tx_dma_en(spi_sel_e spi_sel)571 static inline void spi_tx_dma_en(spi_sel_e spi_sel)
572 {
573 BM_SET(reg_spi_trans2(spi_sel), FLD_SPI_TX_DMA_EN);
574 }
575
576 /**
577 * @brief This function disable tx dma.
578 * @param[in] spi_sel - the spi module.
579 * @return none
580 */
spi_tx_dma_dis(spi_sel_e spi_sel)581 static inline void spi_tx_dma_dis(spi_sel_e spi_sel)
582 {
583 BM_CLR(reg_spi_trans2(spi_sel), FLD_SPI_TX_DMA_EN);
584 }
585
586 /**
587 * @brief This function enable rx dma.
588 * @param[in] spi_sel - the spi module.
589 * @return none
590 */
spi_rx_dma_en(spi_sel_e spi_sel)591 static inline void spi_rx_dma_en(spi_sel_e spi_sel)
592 {
593 BM_SET(reg_spi_trans2(spi_sel), FLD_SPI_RX_DMA_EN);
594 }
595
596 /**
597 * @brief This function disable rx dma.
598 * @param[in] spi_sel - the spi module.
599 * @return none
600 */
spi_rx_dma_dis(spi_sel_e spi_sel)601 static inline void spi_rx_dma_dis(spi_sel_e spi_sel)
602 {
603 BM_CLR(reg_spi_trans2(spi_sel), FLD_SPI_RX_DMA_EN);
604 }
605
606 /**
607 * @brief This function set xip write command content.
608 * @param[in] wr_cmd - write command content.
609 * @return none
610 */
hspi_xip_set_wr_cmd(unsigned char wr_cmd)611 static inline void hspi_xip_set_wr_cmd(unsigned char wr_cmd)
612 {
613 reg_hspi_xip_wr_cmd = wr_cmd;
614 }
615
616 /**
617 * @brief This function set xip read command content.
618 * @param[in] rd_cmd - read command content.
619 * @return none
620 */
hspi_xip_set_rd_cmd(unsigned char rd_cmd)621 static inline void hspi_xip_set_rd_cmd(unsigned char rd_cmd)
622 {
623
624 reg_hspi_xip_rd_cmd = rd_cmd;
625 }
626
627 /**
628 * @brief This function set xip address offset.
629 * @param[in] addr_offset - the offset of data.
630 * @return none
631 */
hspi_xip_addr_offset(unsigned int addr_offset)632 static inline void hspi_xip_addr_offset(unsigned int addr_offset)
633 {
634 reg_hspi_xip_addr_offset0 = addr_offset & 0xff;
635 reg_hspi_xip_addr_offset1 = (addr_offset >> 8) & 0xff;
636 reg_hspi_xip_addr_offset2 = (addr_offset >> 16) & 0xff;
637 reg_hspi_xip_addr_offset3 = (addr_offset >> 24) & 0xff;
638 }
639
640 /**
641 * @brief This function servers to set xip read transfer mode.
642 * @param[in] rd_mode - read mode in enum hspi_tans_mode_e.
643 * @return none
644 */
hspi_xip_read_transmode(unsigned char rd_mode)645 static inline void hspi_xip_read_transmode(unsigned char rd_mode)
646 {
647 reg_hspi_xip_trans_mode &= (~FLD_HSPI_XIP_RD_TRANS_MODE);
648 reg_hspi_xip_trans_mode |= (rd_mode & 0xf) << 4;
649 }
650
651 /**
652 * @brief This function servers to set xip write transfer mode.
653 * @param[in] wr_mode - write mode in enum hspi_tans_mode_e.
654 * @return none
655 */
hspi_xip_write_transmode(unsigned char wr_mode)656 static inline void hspi_xip_write_transmode(unsigned char wr_mode)
657 {
658 reg_hspi_xip_trans_mode &= (~FLD_HSPI_XIP_WR_TRANS_MODE);
659 reg_hspi_xip_trans_mode |= wr_mode & FLD_HSPI_XIP_WR_TRANS_MODE;
660 }
661
662 /**
663 * @brief This function enable address phase.
664 * @return none
665 */
hspi_addr_en(void)666 static inline void hspi_addr_en(void)
667 {
668 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_ADDR_EN);
669 }
670
671 /**
672 * @brief This function disable address phase.
673 * @return none
674 */
hspi_addr_dis(void)675 static inline void hspi_addr_dis(void)
676 {
677 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_ADDR_EN);
678 }
679
680 /**
681 * @brief This function servers to set hspi address length.
682 * @param[in] len The number of bytes of address, range is 1~4.
683 * @return none
684 */
hspi_set_addr_len(unsigned char len)685 static inline void hspi_set_addr_len(unsigned char len)
686 {
687 reg_hspi_xip_ctrl |= ((len - 1) & 0x3) << 2;
688 }
689
690 /**
691 * @brief This function servers to enable xip sequential mode.
692 * @return none
693 */
hspi_xip_seq_mode_en(void)694 static inline void hspi_xip_seq_mode_en(void)
695 {
696 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_XIP_MODE);
697 }
698
699 /**
700 * @brief This function servers to disable xip sequential mode.
701 * @return none
702 */
hspi_xip_seq_mode_dis(void)703 static inline void hspi_xip_seq_mode_dis(void)
704 {
705 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_XIP_MODE);
706 }
707
708 /**
709 * @brief This function servers to enable xip.
710 * @return none
711 */
hspi_xip_en(void)712 static inline void hspi_xip_en(void)
713 {
714 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_XIP_ENABLE);
715 }
716
717 /**
718 * @brief This function servers to disable xip.
719 * @return none
720 */
hspi_xip_dis(void)721 static inline void hspi_xip_dis(void)
722 {
723 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_XIP_ENABLE);
724 }
725
726 /**
727 * @brief This function servers to stop xip.
728 * @return none
729 */
hspi_xip_stop(void)730 static inline void hspi_xip_stop(void)
731 {
732 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_XIP_STOP);
733 }
734
735 /**
736 * @brief This function servers to enable xip timeout that set hight level.
737 * @return none
738 */
hspi_xip_timeout_mode_en(void)739 static inline void hspi_xip_timeout_mode_en(void)
740 {
741 BM_SET(reg_hspi_xip_ctrl, FLD_HSPI_XIP_TIMEOUT_MODE);
742 }
743
744 /**
745 * @brief This function servers to disable xip timeout.
746 * @return none
747 */
hspi_xip_timeout_mode_dis(void)748 static inline void hspi_xip_timeout_mode_dis(void)
749 {
750 BM_CLR(reg_hspi_xip_ctrl, FLD_HSPI_XIP_TIMEOUT_MODE);
751 }
752
753 /**
754 * @brief This function servers to set xip timeout cnt,when two data frame intervals exceed spi_clock_out_period*timeout_cnt,cs will set high level.
755 * @param[in] cnt - xip timeout cnt.
756 * @return none
757 */
hspi_xip_timeout_cnt(unsigned char cnt)758 static inline void hspi_xip_timeout_cnt(unsigned char cnt)
759 {
760 reg_hspi_xip_timeout_cnt = cnt & 0xff;
761 }
762
763 /**
764 * @brief This function servers to set page_size.
765 * @param[in] page_size_i - page boundary 2^page_size_i bytes.
766 * @return none
767 */
hspi_xip_page_size(unsigned char page_size_i)768 static inline void hspi_xip_page_size(unsigned char page_size_i)
769 {
770 reg_hspi_page_size = page_size_i;
771 }
772
773 /**
774 * @brief This function servers to reply master slave is ready .When slave is ready, slave ready reply a byte data:0x5a. indicating that slave is ready for data transmission.
775 * @param[in] spi_sel - the spi module.
776 * @return none
777 */
spi_slave_ready_en(spi_sel_e spi_sel)778 static inline void spi_slave_ready_en(spi_sel_e spi_sel)
779 {
780 BM_SET(reg_spi_status(spi_sel), FLD_HSPI_SLAVE_READY);
781 }
782
783 /**
784 * @brief This function servers to reply master slave is not ready.slave reply a byte data: 0x00.indicating that slave is not ready for data transmission.
785 * @param[in] spi_sel - the spi module.
786 * @return none
787 */
spi_slave_ready_dis(spi_sel_e spi_sel)788 static inline void spi_slave_ready_dis(spi_sel_e spi_sel)
789 {
790 BM_CLR(reg_spi_status(spi_sel), FLD_HSPI_SLAVE_READY);
791 }
792
793 /**
794 * @brief This function servers to read cmd from master for slave.
795 * @param[in] spi_sel - the spi module.
796 * @return cmd transferd by master.
797 */
spi_slave_get_cmd(spi_sel_e spi_sel)798 static inline unsigned char spi_slave_get_cmd(spi_sel_e spi_sel)
799 {
800 return reg_spi_trans1(spi_sel);
801 }
802
803 /**
804 * @brief The function of this API is to set the number of bytes to triggered the receive and transmit interrupt.
805 * Its default value is 4. recommend setting 4.
806 * @param[in] spi_sel - the spi module.
807 * @param[in] cnt - the interrupt trigger level.
808 * @return none
809 */
spi_rx_tx_irq_trig_cnt(spi_sel_e spi_sel,unsigned char cnt)810 static inline void spi_rx_tx_irq_trig_cnt(spi_sel_e spi_sel, unsigned char cnt)
811 {
812 BM_CLR(reg_spi_status(spi_sel), FLD_HSPI_FIFO_THRES);
813 reg_spi_status(spi_sel) |= ((cnt & 7) << 4);
814 }
815
816 /**
817 * @brief This function servers to get irq status.
818 * @param[in] spi_sel - the spi module.
819 * @param[in] status - the irq status.
820 * @return - the value of status is be set.
821 */
spi_get_irq_status(spi_sel_e spi_sel,spi_irq_status_e status)822 static inline unsigned char spi_get_irq_status(spi_sel_e spi_sel,spi_irq_status_e status )
823 {
824 return reg_spi_irq_state(spi_sel)&status;
825 }
826
827 /**
828 * @brief This function servers to clear irq status.
829 * @param[in] spi_sel - the spi module.
830 * @param[in] status - the irq status.
831 * @return none.
832 */
spi_clr_irq_status(spi_sel_e spi_sel,spi_irq_status_e status)833 static inline void spi_clr_irq_status(spi_sel_e spi_sel, spi_irq_status_e status)
834 {
835 reg_spi_irq_state(spi_sel) = status;
836 }
837
838 /**
839 * @brief This function servers to set irq mask.
840 * @param[in] spi_sel - the spi module.
841 * @param[in] mask - the irq mask.
842 * @return cmd - transferd by master.
843 */
spi_set_irq_mask(spi_sel_e spi_sel,spi_irq_mask mask)844 static inline void spi_set_irq_mask(spi_sel_e spi_sel, spi_irq_mask mask)
845 {
846 BM_SET(reg_spi_trans2(spi_sel), mask);
847 }
848
849 /**
850 * @brief This function servers to clear irq mask.
851 * @param[in] spi_sel - the spi module.
852 * @param[in] mask - the irq mask.
853 * @return cmd - transferd by master.
854 */
spi_clr_irq_mask(spi_sel_e spi_sel,spi_irq_mask mask)855 static inline void spi_clr_irq_mask(spi_sel_e spi_sel, spi_irq_mask mask)
856 {
857 BM_CLR(reg_spi_trans2(spi_sel), mask);
858 }
859
860 /**
861 * @brief This function enable 3line_dcx module which is use for panel(lcd oled..).
862 * @return none
863 */
hspi_3line_dcx_en(void)864 static inline void hspi_3line_dcx_en(void)
865 {
866 BM_SET(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX_EN);
867 }
868
869 /**
870 * @brief This function disable 3line_dcx module which is use for panel(lcd oled..).
871 * @return none
872 */
hspi_3line_dcx_dis(void)873 static inline void hspi_3line_dcx_dis(void)
874 {
875 BM_CLR(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX_EN);
876 }
877
878 /**
879 * @brief This function set 3line_dcx translate data.
880 * @return none
881 */
hspi_set_3line_dcx_data(void)882 static inline void hspi_set_3line_dcx_data(void)
883 {
884 BM_SET(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX);
885 }
886
887 /**
888 * @brief This function set 3line_dcx translate command.
889 * @return none
890 */
hspi_set_3line_dcx_cmd(void)891 static inline void hspi_set_3line_dcx_cmd(void)
892 {
893 BM_CLR(reg_hspi_panel_ctrl, FLD_HSPI_PANEL_3LINE_DCX);
894 }
895
896 /**
897 * @brief This function set 2data_lane mode for panel.
898 * @return none
899 */
hspi_set_panel_2data_lane_mode(hspi_panel_2data_lane_mode_e mode)900 static inline void hspi_set_panel_2data_lane_mode(hspi_panel_2data_lane_mode_e mode)
901 {
902 reg_hspi_panel_ctrl &= (~FLD_HSPI_PANEL_2DATA_LANE);
903 reg_hspi_panel_ctrl |= (mode & 0xf) << 2;
904 }
905
906 /**
907 * @brief This function selects pin for hspi master or slave.
908 * @return none
909 */
910 void spi_slave_set_pin(void);
911 /**
912 * @brief This function configures hspi pin.
913 * @param[in] config - the pointer of pin config struct.
914 * @return none
915 */
916 void hspi_set_pin(hspi_pin_config_t *config);
917
918 /**
919 * @brief This function configures pspi pin.
920 * @param[in] config - the pointer of pin config struct.
921 * @return none
922 */
923 void pspi_set_pin(pspi_pin_config_t *config);
924
925 /**
926 * @brief This function enable hspi csn pin.
927 * @param[in] pin - the csn pin.
928 * @return none
929 */
930 void hspi_cs_pin_en(hspi_csn_pin_def_e pin);
931
932 /**
933 * @brief This function disable hspi csn pin.
934 * @param[in] pin - the csn pin.
935 * @return none
936 */
937 void hspi_cs_pin_dis(hspi_csn_pin_def_e pin);
938
939 /**
940 * @brief This function enable pspi csn pin.
941 * @param[in] pin - the csn pin.
942 * @return none
943 */
944 void pspi_cs_pin_en(pspi_csn_pin_def_e pin);
945
946 /**
947 * @brief This function disable pspi csn pin.
948 * @param[in] pin - the csn pin.
949 * @return none
950 */
951 void pspi_cs_pin_dis(pspi_csn_pin_def_e pin);
952
953 /**
954 * @brief This function configures the clock and working mode for SPI interface.
955 * @param[in] spi_sel - the spi module.
956 * @param[in] div_clock - the division factor for SPI module.
957 * spi_clock_out = ahb_clock / ((div_clock+1)*2)
958 * @param[in] mode - the selected working mode of SPI module.
959 * bit5:CPHA-Clock Polarity ; bit6:CPOL:CPHA-Clock Phase
960 * MODE0: CPOL = 0, CPHA =0;
961 * MODE1: CPOL = 0, CPHA =1;
962 * MODE2: CPOL = 1, CPHA =0;
963 * MODE3: CPOL = 1, CPHA =1;
964 * @return none
965 */
966 void spi_master_init(spi_sel_e spi_sel, unsigned char div_clock, spi_mode_type_e mode);
967
968 /**
969 * @brief This function configures the clock and working mode for SPI interface.
970 * @param[in] spi_sel - the spi module.
971 * @param[in] mode - the selected working mode of SPI module.
972 * bit5:CPHA-Clock Polarity ; bit6:CPOL:CPHA-Clock Phase
973 * MODE0: CPOL = 0, CPHA =0;
974 * MODE1: CPOL = 0, CPHA =1;
975 * MODE2: CPOL = 1, CPHA =0;
976 * MODE3: CPOL = 1, CPHA =1;
977 * @return none
978 * @note spi_clock_in (spi_slave_clock frequency)/3
979 */
980 void spi_slave_init(spi_sel_e spi_sel, spi_mode_type_e mode);
981
982 /**
983 * @brief This function servers to set dummy cycle cnt.
984 * @param[in] spi_sel - the spi module.
985 * @param[in] dummy_cnt - the cnt of dummy clock.
986 * @return none
987 */
988 void spi_set_dummy_cnt(spi_sel_e spi_sel, unsigned char dummy_cnt);
989
990 /**
991 * @brief This function servers to set slave address hspi only.
992 * @param[in] addr - address of slave.
993 * @return none
994 */
995 void hspi_set_address(unsigned int addr);
996
997 /**
998 * @brief This function servers to set spi transfer mode.
999 * @param[in] spi_sel - the spi module.
1000 * @param[in] mode - transfer mode.
1001 * @return none
1002 */
1003 void spi_set_transmode(spi_sel_e spi_sel, spi_tans_mode_e mode);
1004
1005
1006 /**
1007 * @brief This function servers to set normal mode.
1008 * @param[in] spi_sel - the spi module.
1009 * @return none
1010 */
1011 void spi_set_normal_mode(spi_sel_e spi_sel);
1012
1013 /**
1014 * @brief This function servers to set dual mode.
1015 * @param[in] spi_sel - the spi module.
1016 * @return none
1017 */
1018 void spi_set_dual_mode(spi_sel_e spi_sel);
1019
1020 /**
1021 * @brief This function servers to set quad mode.
1022 * @return none
1023 */
1024 void hspi_set_quad_mode();
1025
1026 /**
1027 * @brief This function servers to set 3line mode.
1028 * @param[in] spi_sel - the spi module.
1029 * @return none
1030 */
1031 void spi_set_3line_mode(spi_sel_e spi_sel);
1032
1033 /**
1034 * @brief This function servers to set hspi io mode.
1035 * @param[in] spi_sel - the spi module.
1036 * @param[in] mode - single/dual/quad /3line.
1037 * @return none
1038 */
1039 void spi_set_io_mode(spi_sel_e spi_sel, spi_io_mode_e mode);
1040
1041 /**
1042 * @brief This function servers to config normal mode.
1043 * @param[in] spi_sel - the spi module.
1044 * @param[in] mode - nomal ,mode 3line.
1045 * @return none
1046 */
1047 void spi_master_config(spi_sel_e spi_sel, spi_nomal_3line_mode_e mode);
1048
1049 /**
1050 * @brief This function servers to config hspi special mode.
1051 * @param[in] config - the pointer of pin special config struct.
1052 * @return none
1053 */
1054 void hspi_master_config_plus(hspi_config_t *config);
1055
1056 /**
1057 * @brief This function servers to config pspi special mode.
1058 * @param[in] config - the pointer of pin special config struct.
1059 * @return none
1060 */
1061 void pspi_master_config_plus(pspi_config_t *config);
1062
1063 /**
1064 * @brief This function servers to write hspi fifo.
1065 * @param[in] spi_sel - the spi module.
1066 * @param[in] data - the pointer to the data for write.
1067 * @param[in] len - write length.
1068 * @return none
1069 */
1070 void spi_write(spi_sel_e spi_sel, unsigned char *data, unsigned int len);
1071
1072 /**
1073 * @brief This function servers to read hspi fifo.
1074 * @param[in] spi_sel - the spi module.
1075 * @param[in] data - the pointer to the data for read.
1076 * @param[in] len - write length.
1077 * @return none
1078 */
1079 void spi_read(spi_sel_e spi_sel, unsigned char *data, unsigned int len);
1080
1081 /**
1082 * @brief This function serves to normal write data in normal.
1083 * @param[in] spi_sel - the spi module.
1084 * @param[in] data - the pointer to the data for write.
1085 * @param[in] len - write length.
1086 * @return none
1087 */
1088 void spi_master_write(spi_sel_e spi_sel, unsigned char *data, unsigned int len);
1089
1090 /**
1091 * @brief This function serves to normal write and read data.
1092 * @param[in] spi_sel - the spi module.
1093 * @param[in] wr_data - the pointer to the data for write.
1094 * @param[in] wr_len - write length.
1095 * @param[in] rd_data - the pointer to the data for read.
1096 * @param[in] rd_len - read length.
1097 * @return none
1098 */
1099 void spi_master_write_read(spi_sel_e spi_sel, unsigned char *wr_data, unsigned int wr_len, unsigned char *rd_data, unsigned int rd_len);
1100
1101 /**
1102 * @brief This function serves to write and read data simultaneously
1103 * @param[in] spi_sel - the spi module.
1104 * @param[in] write_data - write data pointer.
1105 * @param[in] read_data - read data pointer.
1106 * @param[in] len - write/read length.
1107 * @return none
1108 */
1109 void spi_master_write_read_loopback(spi_sel_e spi_sel, unsigned char *write_data, unsigned char *read_data, unsigned int len);
1110
1111 /**
1112 * @brief This function serves to single/dual/quad write to the SPI slave.
1113 * @param[in] spi_sel - the spi module.
1114 * @param[in] cmd - cmd one byte will first write.
1115 * @param[in] addr - the address of slave.
1116 * @param[in] data - pointer to the data need to write.
1117 * @param[in] data_len - length in byte of the data need to write.
1118 * @param[in] wr_mode - write mode.dummy or not dummy.
1119 * @return none
1120 */
1121 void spi_master_write_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int addr, unsigned char *data, unsigned int data_len, spi_wr_tans_mode_e wr_mode);
1122
1123 /**
1124 * @brief This function serves to single/dual/quad read from the SPI slave.
1125 * @param[in] spi_sel - the spi module.
1126 * @param[in] cmd - cmd one byte will first write.
1127 * @param[in] addr - the address of slave.
1128 * @param[in] data - pointer to the data need to read.
1129 * @param[in] data_len - the length of data.
1130 * @param[in] rd_mode - read mode.dummy or not dummy.
1131 * @return none
1132 */
1133 void spi_master_read_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int addr, unsigned char *data, unsigned int data_len, spi_rd_tans_mode_e rd_mode);
1134
1135 /**
1136 * @brief This function serves to write address, then read data from the SPI slave.
1137 * @param[in] spi_sel - the spi module.
1138 * @param[in] cmd - cmd one byte will first write.
1139 * @param[in] addrs - pointer to the address of slave.
1140 * @param[in] addr_len - the length of address.
1141 * @param[in] data - the pointer to the data for read.
1142 * @param[in] data_len - read length.
1143 * @param[in] wr_mode - write mode.dummy or not dummy.
1144 * @return none
1145 */
1146 void spi_master_write_read_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned char *addrs, unsigned int addr_len, unsigned char *data, unsigned int data_len, spi_rd_tans_mode_e wr_mode);
1147
1148 /**
1149 * @brief This function serves to set tx_dam channel and config dma tx default.
1150 * @param[in] chn - dma channel.
1151 * @return none
1152 */
1153 void hspi_set_tx_dma_config(dma_chn_e chn);
1154
1155 /**
1156 * @brief This function serves to set rx_dam channel and config dma rx default.
1157 * @param[in] chn - dma channel.
1158 * @return none
1159 */
1160 void hspi_set_rx_dma_config(dma_chn_e chn);
1161
1162 /**
1163 * @brief This function serves to set tx_dam channel and config dma tx default.
1164 * @param[in] chn - dma channel.
1165 * @return none
1166 */
1167 void pspi_set_tx_dma_config(dma_chn_e chn);
1168
1169 /**
1170 * @brief This function serves to set rx_dam channel and config dma rx default.
1171 * @param[in] chn - dma channel.
1172 * @return none
1173 */
1174 void pspi_set_rx_dma_config(dma_chn_e chn);
1175
1176 /**
1177 * @brief this function set spi dma channel.
1178 * @param[in] spi_dma_chn - dma channel.
1179 * @param[in] src_addr - the address of source.
1180 * @param[in] dst_addr - the address of destination.
1181 * @param[in] len - the length of data.
1182 * */
1183 void spi_set_dma(dma_chn_e spi_dma_chn, unsigned int src_addr, unsigned int dst_addr, unsigned int len);
1184
1185
1186
1187
1188 /**
1189 * @brief this function set spi tx dma channel.
1190 * @param[in] spi_sel - the spi module.
1191 * @param[in] src_addr - the address of source.
1192 * @param[in] len - the length of data.
1193 * */
1194 _attribute_ram_code_sec_ void spi_set_tx_dma(spi_sel_e spi_sel, unsigned char* src_addr,unsigned int len);
1195
1196
1197 /**
1198 * @brief this function set spi rx dma channel.
1199 * @param[in] spi_sel - the spi module.
1200 * @param[in] dst_addr - the address of destination.
1201 * @param[in] len - the length of data.
1202 * */
1203 _attribute_ram_code_sec_ void spi_set_rx_dma(spi_sel_e spi_sel, unsigned char* dst_addr,unsigned int len);
1204 /**
1205 * @brief This function serves to normal write data by dma.
1206 * @param[in] spi_sel - the spi module.
1207 * @param[in] src_addr - the pointer to the data for write.
1208 * @param[in] len - write length.
1209 * @return none
1210 */
1211 void spi_master_write_dma(spi_sel_e spi_sel, unsigned char *src_addr, unsigned int len);
1212
1213 /**
1214 * @brief This function serves to normal write cmd and address, then read data by dma.
1215 * @param[in] spi_sel - the spi module.
1216 * @param[in] addr - the pointer to the cmd and address for write.
1217 * @param[in] addr_len - write length.
1218 * @param[in] data - the pointer to the data for read.
1219 * @param[in] data_len - read length.
1220 * @return none
1221 */
1222 void spi_master_write_read_dma(spi_sel_e spi_sel, unsigned char *addr, unsigned int addr_len, unsigned char *data, unsigned int data_len);
1223
1224 /**
1225 * @brief This function serves to single/dual/quad write to the SPI slave by dma.
1226 * @param[in] spi_sel - the spi module.
1227 * @param[in] cmd - cmd one byte will first write.
1228 * @param[in] addr - the address of slave.
1229 * @param[in] data - pointer to the data need to write.
1230 * @param[in] data_len - length in byte of the data need to write.
1231 * @param[in] wr_mode - write mode.dummy or not dummy.
1232 * @return none
1233 */
1234 void spi_master_write_dma_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int addr, unsigned char *data, unsigned int data_len, spi_wr_tans_mode_e wr_mode);
1235
1236 /**
1237 * @brief This function serves to single/dual/quad read from the SPI slave by dma.
1238 * @param[in] spi_sel - the spi module.
1239 * @param[in] cmd - cmd one byte will first write.
1240 * @param[in] addr - the address of slave.
1241 * @param[in] dst_addr - pointer to the buffer that will cache the reading out data.
1242 * @param[in] data_len - length in byte of the data need to read.
1243 * @param[in] rd_mode - read mode.dummy or not dummy.
1244 * @return none
1245 */
1246 void spi_master_read_dma_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int addr, unsigned char *dst_addr, unsigned int data_len, spi_rd_tans_mode_e rd_mode);
1247
1248 /**
1249 * @brief This function serves to single/dual/quad write address and read from the SPI slave by dma.
1250 * @param[in] spi_sel - the spi module.
1251 * @param[in] cmd - cmd one byte will first write.
1252 * @param[in] addr - the address of slave.
1253 * @param[in] addr_len - the length of address.
1254 * @param[in] rd_data - pointer to the buffer that will cache the reading out data.
1255 * @param[in] rd_len - length in byte of the data need to read.
1256 * @param[in] rd_mode - read mode.dummy or not dummy.
1257 * @return none
1258 */
1259 void spi_master_write_read_dma_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned char *addr, unsigned int addr_len, unsigned char *rd_data, unsigned int rd_len, spi_rd_tans_mode_e rd_mode);
1260
1261 /**
1262 * @brief This function serves to single/dual (quad) write to the SPI slave by xip.
1263 * @param[in] cmd - cmd one byte will first write.
1264 * @param[in] addr_offset - offset of xip base address.
1265 * @param[in] data - pointer to the data need to write.
1266 * @param[in] data_len - length in byte of the data need to write.
1267 * @param[in] wr_mode - write mode dummy or not dummy.
1268 * @return none
1269 */
1270 void hspi_master_write_xip(unsigned char cmd, unsigned int addr_offset, unsigned char *data, unsigned int data_len, spi_wr_tans_mode_e wr_mode);
1271
1272 /**
1273 * @brief This function serves to single/dual (quad) read from the SPI slave by xip.
1274 * @param[in] cmd - cmd one byte will first write.
1275 * @param[in] addr_offset - offset of xip base address.
1276 * @param[in] data - pointer to the data need to read.
1277 * @param[in] data_len - length in byte of the data need to read.
1278 * @param[in] rd_mode - read mode.dummy or not dummy.
1279 * @return none
1280 */
1281 void hspi_master_read_xip(unsigned char cmd, unsigned int addr_offset, unsigned char *data, unsigned int data_len, spi_rd_tans_mode_e rd_mode);
1282
1283 /**
1284 * @brief This function serves to a cmd and one data write to the SPI slave by xip.
1285 * @param[in] cmd - cmd one byte will first write.
1286 * @param[in] addr_offset - offset of xip base address.
1287 * @param[in] data_in - data need to write.
1288 * @param[in] wr_mode - write mode dummy or not dummy.
1289 * @return none
1290 */
1291 void hspi_master_write_xip_cmd_data(unsigned char cmd, unsigned int addr_offset, unsigned char data_in, spi_wr_tans_mode_e wr_mode);
1292
1293 #endif
1294
1295
1296
