1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_hrtim.h 4 * @author MCD Application Team 5 * @brief Header file of HRTIM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_HAL_HRTIM_H 21 #define STM32G4xx_HAL_HRTIM_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 #if defined(HRTIM1) 31 /** @addtogroup STM32G4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup HRTIM HRTIM 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants 41 * @{ 42 */ 43 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer 44 * @{ 45 */ 46 #define MAX_HRTIM_TIMER 7U 47 /** 48 * @} 49 */ 50 /** 51 * @} 52 */ 53 54 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types 55 * @{ 56 */ 57 58 /** 59 * @brief HRTIM Configuration Structure definition - Time base related parameters 60 */ 61 typedef struct 62 { 63 uint32_t HRTIMInterruptRequests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. 64 This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ 65 uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. 66 The HRTIM instance can be configured to act as a slave (waiting for a trigger 67 to be synchronized) or a master (generating a synchronization signal) or both. 68 This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/ 69 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when 70 the HRTIM instance is configured as a slave). 71 This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */ 72 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs 73 (significant only when the HRTIM instance is configured as a master). 74 This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */ 75 uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization 76 outputs (significant only when the HRTIM instance is configured as a master). 77 This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */ 78 } HRTIM_InitTypeDef; 79 80 /** 81 * @brief HAL State structures definition 82 */ 83 typedef enum 84 { 85 HAL_HRTIM_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ 86 HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 87 HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 88 HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ 89 HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */ 90 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 91 HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U /*!< Invalid Callback error */ 92 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 93 } HAL_HRTIM_StateTypeDef; 94 95 /** 96 * @brief HRTIM Timer Structure definition 97 */ 98 typedef struct 99 { 100 uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1. 101 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels. 102 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */ 103 uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2. 104 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels. 105 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */ 106 uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */ 107 uint32_t DMARequests; /*!< DMA requests enabled for the timer. */ 108 uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */ 109 uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */ 110 uint32_t DMASize; /*!< Size of the DMA transfer */ 111 } HRTIM_TimerParamTypeDef; 112 113 /** 114 * @brief HRTIM Handle Structure definition 115 */ 116 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 117 typedef struct __HRTIM_HandleTypeDef 118 #else 119 typedef struct 120 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 121 { 122 HRTIM_TypeDef *Instance; /*!< Register base address */ 123 124 HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ 125 126 HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */ 127 128 HAL_LockTypeDef Lock; /*!< Locking object */ 129 130 __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ 131 132 DMA_HandleTypeDef *hdmaMaster; /*!< Master timer DMA handle parameters */ 133 DMA_HandleTypeDef *hdmaTimerA; /*!< Timer A DMA handle parameters */ 134 DMA_HandleTypeDef *hdmaTimerB; /*!< Timer B DMA handle parameters */ 135 DMA_HandleTypeDef *hdmaTimerC; /*!< Timer C DMA handle parameters */ 136 DMA_HandleTypeDef *hdmaTimerD; /*!< Timer D DMA handle parameters */ 137 DMA_HandleTypeDef *hdmaTimerE; /*!< Timer E DMA handle parameters */ 138 DMA_HandleTypeDef *hdmaTimerF; /*!< Timer F DMA handle parameters */ 139 140 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 141 void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ 142 void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 2 interrupt callback function pointer */ 143 void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 3 interrupt callback function pointer */ 144 void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 4 interrupt callback function pointer */ 145 void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 5 interrupt callback function pointer */ 146 void (* Fault6Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 6 interrupt callback function pointer */ 147 void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< System fault interrupt callback function pointer */ 148 void (* DLLCalibrationReadyCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< DLL Ready interrupt callback function pointer */ 149 void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Burst mode period interrupt callback function pointer */ 150 void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Sync Input interrupt callback function pointer */ 151 void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< DMA error callback function pointer */ 152 153 void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Update interrupt callback function pointer */ 154 void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Repetition interrupt callback function pointer */ 155 void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 1 match interrupt callback function pointer */ 156 void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 2 match interrupt callback function pointer */ 157 void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 3 match interrupt callback function pointer */ 158 void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 4 match interrupt callback function pointer */ 159 void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 1 interrupts callback function pointer */ 160 void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 2 interrupts callback function pointer */ 161 void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer */ 162 void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x counter reset/roll-over interrupt callback function pointer */ 163 void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 set interrupt callback function pointer */ 164 void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 reset interrupt callback function pointer */ 165 void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 set interrupt callback function pointer */ 166 void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 reset interrupt callback function pointer */ 167 void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Burst DMA completed interrupt callback function pointer */ 168 169 void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */ 170 void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */ 171 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 172 } HRTIM_HandleTypeDef; 173 174 /** 175 * @brief Simple output compare mode configuration definition 176 */ 177 typedef struct 178 { 179 uint32_t Period; /*!< Specifies the timer period. 180 The period value must be above 3 periods of the fHRTIM clock. 181 Maximum value is = 0xFFDFU */ 182 uint32_t RepetitionCounter; /*!< Specifies the timer repetition period. 183 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 184 uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio. 185 This parameter can be any value of @ref HRTIM_Prescaler_Ratio */ 186 uint32_t Mode; /*!< Specifies the counter operating mode. 187 This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */ 188 } HRTIM_TimeBaseCfgTypeDef; 189 190 /** 191 * @brief Simple output compare mode configuration definition 192 */ 193 typedef struct 194 { 195 uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive). 196 This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */ 197 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 198 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 199 uint32_t Polarity; /*!< Specifies the output polarity. 200 This parameter can be any value of @ref HRTIM_Output_Polarity */ 201 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 202 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 203 } HRTIM_SimpleOCChannelCfgTypeDef; 204 205 /** 206 * @brief Simple PWM output mode configuration definition 207 */ 208 typedef struct 209 { 210 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 211 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 212 uint32_t Polarity; /*!< Specifies the output polarity. 213 This parameter can be any value of @ref HRTIM_Output_Polarity */ 214 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 215 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 216 } HRTIM_SimplePWMChannelCfgTypeDef; 217 218 /** 219 * @brief Simple capture mode configuration definition 220 */ 221 typedef struct 222 { 223 uint32_t Event; /*!< Specifies the external event triggering the capture. 224 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */ 225 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 226 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 227 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event. 228 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */ 229 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 230 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 231 } HRTIM_SimpleCaptureChannelCfgTypeDef; 232 233 /** 234 * @brief Simple One Pulse mode configuration definition 235 */ 236 typedef struct 237 { 238 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 239 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 240 uint32_t OutputPolarity; /*!< Specifies the output polarity. 241 This parameter can be any value of @ref HRTIM_Output_Polarity */ 242 uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 243 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 244 uint32_t Event; /*!< Specifies the external event triggering the pulse generation. 245 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */ 246 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 247 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 248 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event. 249 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */ 250 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 251 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 252 } HRTIM_SimpleOnePulseChannelCfgTypeDef; 253 254 /** 255 * @brief Timer configuration definition 256 */ 257 typedef struct 258 { 259 uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master. 260 Specifies which interrupts requests must enabled for the timer. 261 This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable 262 or @ref HRTIM_Timing_Unit_Interrupt_Enable */ 263 uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master. 264 Specifies which DMA requests must be enabled for the timer. 265 This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable 266 or @ref HRTIM_Timing_Unit_DMA_Request_Enable */ 267 uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master. 268 Specifies the address of the source address of the DMA transfer */ 269 uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master. 270 Specifies the address of the destination address of the DMA transfer */ 271 uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master. 272 Specifies the size of the DMA transfer */ 273 uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master. 274 Specifies whether or not half mode is enabled 275 This parameter can be any value of @ref HRTIM_Half_Mode_Enable */ 276 uint32_t InterleavedMode; /*!< Relevant for all HRTIM timers, including the master. 277 Specifies whether or not half mode is enabled 278 This parameter can be any value of @ref HRTIM_Interleaved_Mode */ 279 uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master. 280 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). 281 This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */ 282 uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master. 283 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). 284 This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */ 285 uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master. 286 Indicates whether or not the a DAC synchronization event is generated. 287 This parameter can be any value of @ref HRTIM_DAC_Synchronization */ 288 uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master. 289 Specifies whether or not register preload is enabled. 290 This parameter can be any value of @ref HRTIM_Register_Preload_Enable */ 291 uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master. 292 Specifies how the update occurs with respect to a burst DMA transaction or 293 update enable inputs (Slave timers only). 294 This parameter can be any value of @ref HRTIM_Update_Gating */ 295 uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master. 296 Specifies how the timer behaves during a burst mode operation. 297 This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */ 298 uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master. 299 Specifies whether or not registers update is triggered by the repetition event. 300 This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */ 301 uint32_t PushPull; /*!< Relevant for Timer A to Timer F. 302 Specifies whether or not the push-pull mode is enabled. 303 This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */ 304 uint32_t FaultEnable; /*!< Relevant for Timer A to Timer F. 305 Specifies which fault channels are enabled for the timer. 306 This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */ 307 uint32_t FaultLock; /*!< Relevant for Timer A to Timer F. 308 Specifies whether or not fault enabling status is write protected. 309 This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */ 310 uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer F. 311 Specifies whether or not dead-time insertion is enabled for the timer. 312 This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */ 313 uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer F. 314 Specifies the delayed protection mode. 315 This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */ 316 uint32_t BalancedIdleAutomaticResume; /*!< Indicates whether or not outputs are automatically re-enabled after a balanced idle event. 317 This parameters can be any value of @ref HRTIM_Output_Balanced_Idle_Auto_Resume */ 318 uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer F. 319 Specifies source(s) triggering the timer registers update. 320 This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */ 321 uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer F. 322 Specifies source(s) triggering the timer counter reset. 323 This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */ 324 uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer F. 325 Specifies whether or not registers update is triggered when the timer counter is reset. 326 This parameter can be a value of @ref HRTIM_Timer_Reset_Update */ 327 uint32_t ReSyncUpdate; /*!< Relevant for Timer A to Timer F. 328 Specifies whether update source is coming from the timing unit @ref HRTIM_Timer_ReSyncUpdate */ 329 330 } HRTIM_TimerCfgTypeDef; 331 332 /** 333 * @brief Timer control definition 334 */ 335 typedef struct 336 { 337 uint32_t UpDownMode; /*!< Relevant for Timer A to Timer F. 338 Specifies whether or not counter is operating in up or up-down counting mode. 339 This parameter can be a value of @ref HRTIM_Timer_UpDown_Mode */ 340 uint32_t TrigHalf; /*!< Relevant for Timer A to Timer F. 341 Specifies whether or not compare 2 is operating in Trigger half mode. 342 This parameter can be a value of @ref HRTIM_Timer_TrigHalf_Mode */ 343 uint32_t GreaterCMP3; /*!< Relevant for Timer A to Timer F. 344 Specifies whether or not compare 3 is operating in compare match or greater mode. 345 This parameter can be a value of @ref HRTIM_Timer_GreaterCMP3_Mode */ 346 uint32_t GreaterCMP1; /*!< Relevant for Timer A to Timer F. 347 Specifies whether or not compare 1 is operating in compare match or greater mode. 348 This parameter can be a value of @ref HRTIM_Timer_GreaterCMP1_Mode */ 349 uint32_t DualChannelDacReset; /*!< Relevant for Timer A to Timer F. 350 Specifies how the hrtim_dac_reset_trgx trigger is generated. 351 This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Reset */ 352 uint32_t DualChannelDacStep; /*!< Relevant for Timer A to Timer F. 353 Specifies how the hrtim_dac_step_trgx trigger is generated. 354 This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Step */ 355 uint32_t DualChannelDacEnable; /*!< Relevant for Timer A to Timer F. 356 Enables or not the dual channel DAC triggering mechanism. 357 This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Enable */ 358 } HRTIM_TimerCtlTypeDef; 359 360 /** 361 * @brief Compare unit configuration definition 362 */ 363 typedef struct 364 { 365 uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit. 366 The minimum value must be greater than or equal to 3 periods of the fHRTIM clock. 367 The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */ 368 uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4. 369 This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */ 370 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected. 371 CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */ 372 } HRTIM_CompareCfgTypeDef; 373 374 /** 375 * @brief Capture unit content definition 376 */ 377 typedef struct 378 { 379 uint32_t Value; /*!< Holds the counter value when the capture event occurred. 380 This parameter can be a number between 0x0 and 0xFFFFU */ 381 uint32_t Dir ; /*!< Holds the counting direction value when the capture event occurred. 382 This parameter can be a value of @ref HRTIM_Timer_UpDown_Mode */ 383 } HRTIM_CaptureValueTypeDef; 384 385 /** 386 * @brief Capture unit configuration definition 387 */ 388 typedef struct 389 { 390 uint64_t Trigger; /*!< Specifies source(s) triggering the capture. 391 This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */ 392 } HRTIM_CaptureCfgTypeDef; 393 394 /** 395 * @brief Output configuration definition 396 */ 397 typedef struct 398 { 399 uint32_t Polarity; /*!< Specifies the output polarity. 400 This parameter can be any value of @ref HRTIM_Output_Polarity */ 401 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level. 402 This parameter can be a combination of @ref HRTIM_Output_Set_Source */ 403 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level. 404 This parameter can be a combination of @ref HRTIM_Output_Reset_Source */ 405 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation. 406 This parameter can be any value of @ref HRTIM_Output_Idle_Mode */ 407 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 408 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 409 uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state. 410 This parameter can be any value of @ref HRTIM_Output_FAULT_Level */ 411 uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled 412 This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */ 413 uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation. 414 This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */ 415 } HRTIM_OutputCfgTypeDef; 416 417 /** 418 * @brief External event filtering in timing units configuration definition 419 */ 420 typedef struct 421 { 422 uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit. 423 This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */ 424 uint32_t Latch; /*!< Specifies whether or not the signal is latched. 425 This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */ 426 } HRTIM_TimerEventFilteringCfgTypeDef; 427 428 /** 429 * @brief Dead time feature configuration definition 430 */ 431 typedef struct 432 { 433 uint32_t Prescaler; /*!< Specifies the dead-time prescaler. 434 This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */ 435 uint32_t RisingValue; /*!< Specifies the dead-time following a rising edge. 436 This parameter can be a number between 0x0 and 0x1FFU */ 437 uint32_t RisingSign; /*!< Specifies whether the dead-time is positive or negative on rising edge. 438 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */ 439 uint32_t RisingLock; /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected. 440 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */ 441 uint32_t RisingSignLock; /*!< Specifies whether or not dead-time rising sign is write protected. 442 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */ 443 uint32_t FallingValue; /*!< Specifies the dead-time following a falling edge. 444 This parameter can be a number between 0x0 and 0x1FFU */ 445 uint32_t FallingSign; /*!< Specifies whether the dead-time is positive or negative on falling edge. 446 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */ 447 uint32_t FallingLock; /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected. 448 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */ 449 uint32_t FallingSignLock; /*!< Specifies whether or not dead-time falling sign is write protected. 450 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */ 451 } HRTIM_DeadTimeCfgTypeDef; 452 453 /** 454 * @brief Chopper mode configuration definition 455 */ 456 typedef struct 457 { 458 uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value. 459 This parameter can be a value of @ref HRTIM_Chopper_Frequency */ 460 uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value. 461 This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */ 462 uint32_t StartPulse; /*!< Specifies the Timer pulse width value. 463 This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */ 464 } HRTIM_ChopperModeCfgTypeDef; 465 466 /** 467 * @brief External event channel configuration definition 468 */ 469 typedef struct 470 { 471 uint32_t Source; /*!< Identifies the source of the external event. 472 This parameter can be a value of @ref HRTIM_External_Event_Sources */ 473 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 474 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 475 uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event. 476 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */ 477 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 478 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 479 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event. 480 This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */ 481 } HRTIM_EventCfgTypeDef; 482 483 /** 484 * @brief Fault channel configuration definition 485 */ 486 typedef struct 487 { 488 uint32_t Source; /*!< Identifies the source of the fault. 489 This parameter can be a value of @ref HRTIM_Fault_Sources */ 490 uint32_t Polarity; /*!< Specifies the polarity of the fault event. 491 This parameter can be a value of @ref HRTIM_Fault_Polarity */ 492 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter. 493 This parameter can be a value of @ref HRTIM_Fault_Filter */ 494 uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected. 495 This parameter can be a value of @ref HRTIM_Fault_Lock */ 496 } HRTIM_FaultCfgTypeDef; 497 498 typedef struct 499 { 500 uint32_t Threshold; /*!< Specifies the Fault counter Threshold. 501 This parameter can be a number between 0x0 and 0xF */ 502 uint32_t ResetMode; /*!< Specifies the reset mode of a fault event counter. 503 This parameter can be a value of @ref HRTIM_Fault_ResetMode */ 504 uint32_t BlankingSource;/*!< Specifies the blanking source of a fault event. 505 This parameter can be a value of @ref HRTIM_Fault_Blanking */ 506 } HRTIM_FaultBlankingCfgTypeDef; 507 508 /** 509 * @brief Burst mode configuration definition 510 */ 511 typedef struct 512 { 513 uint32_t Mode; /*!< Specifies the burst mode operating mode. 514 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */ 515 uint32_t ClockSource; /*!< Specifies the burst mode clock source. 516 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */ 517 uint32_t Prescaler; /*!< Specifies the burst mode prescaler. 518 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */ 519 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER). 520 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */ 521 uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation. 522 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */ 523 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state. 524 This parameter can be a number between 0x0 and 0xFFFF */ 525 uint32_t Period; /*!< Specifies burst mode repetition period. 526 This parameter can be a number between 0x1 and 0xFFFF */ 527 } HRTIM_BurstModeCfgTypeDef; 528 529 /** 530 * @brief ADC trigger configuration definition 531 */ 532 typedef struct 533 { 534 uint32_t UpdateSource; /*!< Specifies the ADC trigger update source. 535 This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source */ 536 uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion. 537 This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event */ 538 } HRTIM_ADCTriggerCfgTypeDef; 539 540 /** 541 * @brief External Event Counter A or B configuration definition 542 */ 543 typedef struct 544 { 545 uint32_t ResetMode; /*!< Specifies the External Event Counter A or B Reset Mode. 546 This parameter can be a value of @ref HRTIM_Timer_External_Event_ResetMode */ 547 uint32_t Source; /*!< Specifies the External Event Counter source selection. 548 This parameter can be one of @ref HRTIM_External_Event_Channels */ 549 uint32_t Counter; /*!< Specifies the External Event Counter Threshold. 550 This parameter can be a number between 0x0 and 0x3F */ 551 } HRTIM_ExternalEventCfgTypeDef; 552 553 554 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 555 /** 556 * @brief HAL HRTIM Callback ID enumeration definition 557 */ 558 typedef enum 559 { 560 HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ 561 HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ 562 HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ 563 HAL_HRTIM_FAULT4CALLBACK_CB_ID = 0x03U, /*!< Fault 4 interrupt callback ID */ 564 HAL_HRTIM_FAULT5CALLBACK_CB_ID = 0x04U, /*!< Fault 5 interrupt callback ID */ 565 HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID = 0x05U, /*!< System fault interrupt callback ID */ 566 HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID = 0x06U, /*!< DLL Ready interrupt callback ID */ 567 HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID = 0x07U, /*!< Burst mode period interrupt callback ID */ 568 HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID */ 569 HAL_HRTIM_ERRORCALLBACK_CB_ID = 0x09U, /*!< DMA error callback ID */ 570 571 HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID = 0x10U, /*!< Timer x Update interrupt callback ID */ 572 HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID = 0x11U, /*!< Timer x Repetition interrupt callback ID */ 573 HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID */ 574 HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID */ 575 HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID */ 576 HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID */ 577 HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID = 0x16U, /*!< Timer x Capture 1 interrupts callback ID */ 578 HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID = 0x17U, /*!< Timer x Capture 2 interrupts callback ID */ 579 HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID = 0x18U, /*!< Timer x Delayed protection interrupt callback ID */ 580 HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */ 581 HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID = 0x1AU, /*!< Timer x output 1 set interrupt callback ID */ 582 HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID */ 583 HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID = 0x1CU, /*!< Timer x output 2 set interrupt callback ID */ 584 HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID */ 585 HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID */ 586 587 HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ 588 HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ 589 HAL_HRTIM_FAULT6CALLBACK_CB_ID = 0x22U, /*!< Fault 6 interrupt callback ID */ 590 } HAL_HRTIM_CallbackIDTypeDef; 591 592 /** 593 * @brief HAL HRTIM Callback function pointer definitions 594 */ 595 typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM related callback function pointer */ 596 597 typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< HRTIM Timer x related callback function pointer */ 598 uint32_t TimerIdx); 599 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 600 601 /** 602 * @} 603 */ 604 605 /* Exported constants --------------------------------------------------------*/ 606 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants 607 * @{ 608 */ 609 610 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index 611 * @{ 612 * @brief Constants defining the timer indexes 613 */ 614 #define HRTIM_TIMERINDEX_TIMER_A 0x0U /*!< Index used to access timer A registers */ 615 #define HRTIM_TIMERINDEX_TIMER_B 0x1U /*!< Index used to access timer B registers */ 616 #define HRTIM_TIMERINDEX_TIMER_C 0x2U /*!< Index used to access timer C registers */ 617 #define HRTIM_TIMERINDEX_TIMER_D 0x3U /*!< Index used to access timer D registers */ 618 #define HRTIM_TIMERINDEX_TIMER_E 0x4U /*!< Index used to access timer E registers */ 619 #define HRTIM_TIMERINDEX_TIMER_F 0x5U /*!< Index used to access timer F registers */ 620 #define HRTIM_TIMERINDEX_MASTER 0x6U /*!< Index used to access master registers */ 621 #define HRTIM_TIMERINDEX_COMMON 0xFFU /*!< Index used to access HRTIM common registers */ 622 /** 623 * @} 624 */ 625 626 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier 627 * @{ 628 * @brief Constants defining timer identifiers 629 */ 630 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier */ 631 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */ 632 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */ 633 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */ 634 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ 635 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ 636 #define HRTIM_TIMERID_TIMER_F (HRTIM_MCR_TFCEN) /*!< Timer F identifier */ 637 /** 638 * @} 639 */ 640 641 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit 642 * @{ 643 * @brief Constants defining compare unit identifiers 644 */ 645 #define HRTIM_COMPAREUNIT_1 0x00000001U /*!< Compare unit 1 identifier */ 646 #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ 647 #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ 648 #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ 649 /** 650 * @} 651 */ 652 653 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit 654 * @{ 655 * @brief Constants defining capture unit identifiers 656 */ 657 #define HRTIM_CAPTUREUNIT_1 0x00000001U /*!< Capture unit 1 identifier */ 658 #define HRTIM_CAPTUREUNIT_2 0x00000002U /*!< Capture unit 2 identifier */ 659 /** 660 * @} 661 */ 662 663 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output 664 * @{ 665 * @brief Constants defining timer output identifiers 666 */ 667 #define HRTIM_OUTPUT_TA1 0x00000001U /*!< Timer A - Output 1 identifier */ 668 #define HRTIM_OUTPUT_TA2 0x00000002U /*!< Timer A - Output 2 identifier */ 669 #define HRTIM_OUTPUT_TB1 0x00000004U /*!< Timer B - Output 1 identifier */ 670 #define HRTIM_OUTPUT_TB2 0x00000008U /*!< Timer B - Output 2 identifier */ 671 #define HRTIM_OUTPUT_TC1 0x00000010U /*!< Timer C - Output 1 identifier */ 672 #define HRTIM_OUTPUT_TC2 0x00000020U /*!< Timer C - Output 2 identifier */ 673 #define HRTIM_OUTPUT_TD1 0x00000040U /*!< Timer D - Output 1 identifier */ 674 #define HRTIM_OUTPUT_TD2 0x00000080U /*!< Timer D - Output 2 identifier */ 675 #define HRTIM_OUTPUT_TE1 0x00000100U /*!< Timer E - Output 1 identifier */ 676 #define HRTIM_OUTPUT_TE2 0x00000200U /*!< Timer E - Output 2 identifier */ 677 #define HRTIM_OUTPUT_TF1 0x00000400U /*!< Timer F - Output 1 identifier */ 678 #define HRTIM_OUTPUT_TF2 0x00000800U /*!< Timer F - Output 2 identifier */ 679 /** 680 * @} 681 */ 682 683 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger 684 * @{ 685 * @brief Constants defining ADC triggers identifiers 686 */ 687 #define HRTIM_ADCTRIGGER_1 0x00000001U /*!< ADC trigger 1 identifier */ 688 #define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */ 689 #define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */ 690 #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */ 691 /** 692 * @} 693 */ 694 695 /** @defgroup HRTIM_ADC_Ext_Trigger HRTIM ADC Extended Trigger 696 * @{ 697 * @brief Constants defining ADC Extended triggers identifiers 698 */ 699 #define HRTIM_ADCTRIGGER_5 0x00000010U /*!< ADC trigger 5 identifier */ 700 #define HRTIM_ADCTRIGGER_6 0x00000020U /*!< ADC trigger 6 identifier */ 701 #define HRTIM_ADCTRIGGER_7 0x00000040U /*!< ADC trigger 7 identifier */ 702 #define HRTIM_ADCTRIGGER_8 0x00000080U /*!< ADC trigger 8 identifier */ 703 #define HRTIM_ADCTRIGGER_9 0x00000100U /*!< ADC trigger 9 identifier */ 704 #define HRTIM_ADCTRIGGER_10 0x00000200U /*!< ADC trigger 10 identifier */ 705 706 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ 707 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ 708 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ 709 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ 710 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4) || \ 711 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_5) || \ 712 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6) || \ 713 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7) || \ 714 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8) || \ 715 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9) || \ 716 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10)) 717 #define IS_HRTIM_ADCEXTTRIGGER(ADCTRIGGER)\ 718 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_5) || \ 719 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6) || \ 720 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7) || \ 721 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8) || \ 722 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9) || \ 723 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10)) 724 /** 725 * @} 726 */ 727 728 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels 729 * @{ 730 * @brief Constants defining external event channel identifiers 731 */ 732 #define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */ 733 #define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */ 734 #define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */ 735 #define HRTIM_EVENT_3 (0x00000003U) /*!< External event channel 3 identifier */ 736 #define HRTIM_EVENT_4 (0x00000004U) /*!< External event channel 4 identifier */ 737 #define HRTIM_EVENT_5 (0x00000005U) /*!< External event channel 5 identifier */ 738 #define HRTIM_EVENT_6 (0x00000006U) /*!< External event channel 6 identifier */ 739 #define HRTIM_EVENT_7 (0x00000007U) /*!< External event channel 7 identifier */ 740 #define HRTIM_EVENT_8 (0x00000008U) /*!< External event channel 8 identifier */ 741 #define HRTIM_EVENT_9 (0x00000009U) /*!< External event channel 9 identifier */ 742 #define HRTIM_EVENT_10 (0x0000000AU) /*!< External event channel 10 identifier */ 743 /** 744 * @} 745 */ 746 747 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel 748 * @{ 749 * @brief Constants defining fault channel identifiers 750 */ 751 #define HRTIM_FAULT_1 (0x01U) /*!< Fault channel 1 identifier */ 752 #define HRTIM_FAULT_2 (0x02U) /*!< Fault channel 2 identifier */ 753 #define HRTIM_FAULT_3 (0x04U) /*!< Fault channel 3 identifier */ 754 #define HRTIM_FAULT_4 (0x08U) /*!< Fault channel 4 identifier */ 755 #define HRTIM_FAULT_5 (0x10U) /*!< Fault channel 5 identifier */ 756 #define HRTIM_FAULT_6 (0x20U) /*!< Fault channel 6 identifier */ 757 /** 758 * @} 759 */ 760 761 762 /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio 763 * @{ 764 * @brief Constants defining timer high-resolution clock prescaler ratio. 765 */ 766 #define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */ 767 #define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */ 768 #define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */ 769 #define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */ 770 #define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */ 771 #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ 772 #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ 773 #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ 774 /** 775 * @} 776 */ 777 778 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode 779 * @{ 780 * @brief Constants defining timer counter operating mode. 781 */ 782 #define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */ 783 #define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */ 784 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */ 785 /** 786 * @} 787 */ 788 789 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable 790 * @{ 791 * @brief Constants defining half mode enabling status. 792 */ 793 #define HRTIM_HALFMODE_DISABLED (0x00000000U) /*!< Half mode is disabled */ 794 #define HRTIM_HALFMODE_ENABLED (0x00000020U) /*!< Half mode is enabled */ 795 /** 796 * @} 797 */ 798 799 /** @defgroup HRTIM_Interleaved_Mode HRTIM Interleaved Mode 800 * @{ 801 * @brief Constants defining interleaved mode enabling status. 802 */ 803 #define HRTIM_INTERLEAVED_MODE_DISABLED 0x000U /*!< HRTIM interleaved Mode is disabled */ 804 #define HRTIM_INTERLEAVED_MODE_DUAL 0x002U /*!< HRTIM interleaved Mode is Half */ 805 #define HRTIM_INTERLEAVED_MODE_TRIPLE 0x003U /*!< HRTIM interleaved Mode is Triple */ 806 #define HRTIM_INTERLEAVED_MODE_QUAD 0x004U /*!< HRTIM interleaved Mode is Quad */ 807 /** 808 * @} 809 */ 810 811 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event 812 * @{ 813 * @brief Constants defining the timer behavior following the synchronization event 814 */ 815 #define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */ 816 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */ 817 /** 818 * @} 819 */ 820 821 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event 822 * @{ 823 * @brief Constants defining the timer behavior following the synchronization event 824 */ 825 #define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */ 826 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */ 827 /** 828 * @} 829 */ 830 831 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization 832 * @{ 833 * @brief Constants defining on which output the DAC synchronization event is sent 834 */ 835 #define HRTIM_DACSYNC_NONE 0x00000000U /*!< No DAC synchronization event generated */ 836 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */ 837 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */ 838 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */ 839 /** 840 * @} 841 */ 842 843 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable 844 * @{ 845 * @brief Constants defining whether a write access into a preloadable 846 * register is done into the active or the preload register. 847 */ 848 #define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */ 849 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */ 850 /** 851 * @} 852 */ 853 854 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating 855 * @{ 856 * @brief Constants defining how the update occurs relatively to the burst DMA 857 * transaction and the external update request on update enable inputs 1 to 3. 858 */ 859 #define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */ 860 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */ 861 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/ 862 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */ 863 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */ 864 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */ 865 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */ 866 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */ 867 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */ 868 /** 869 * @} 870 */ 871 872 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode 873 * @{ 874 * @brief Constants defining how the timer behaves during a burst 875 mode operation. 876 */ 877 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U /*!< Timer counter clock is maintained and the timer operates normally */ 878 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */ 879 /** 880 * @} 881 */ 882 883 /** @defgroup HRTIM_Timer_UpDown_Mode HRTIM Timer UpDown Mode 884 * @{ 885 * @brief Constants defining how the timer counter operates 886 */ 887 #define HRTIM_TIMERUPDOWNMODE_UP 0x00000000U /*!< Timer counter is operating in up-counting mode */ 888 #define HRTIM_TIMERUPDOWNMODE_UPDOWN 0x00000001U /*!< Timer counter is operating in up-down counting mode */ 889 /** 890 * @} 891 */ 892 893 /** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode 894 * @{ 895 * @brief Constants defining how the timer counter operates 896 */ 897 #define HRTIM_TIMERTRIGHALF_DISABLED 0x00000000U /*!< Timer Compare 2 register is behaving in standard mode */ 898 #define HRTIM_TIMERTRIGHALF_ENABLED (HRTIM_TIMCR2_TRGHLF) /*!< Timer Compare 2 register is behaving in triggered-half mode */ 899 /** 900 * @} 901 */ 902 903 /** @defgroup HRTIM_Timer_GreaterCMP3_Mode HRTIM Timer Greater than Compare 3 PWM Mode 904 * @{ 905 * @brief Constants defining how the timer compare operates 906 */ 907 #define HRTIM_TIMERGTCMP3_EQUAL 0x00000000U /*!< Timer Compare 3 event is generated when counter is equal */ 908 #define HRTIM_TIMERGTCMP3_GREATER (HRTIM_TIMCR2_GTCMP3) /*!< Timer Compare 3 Reset event is generated when counter is greater */ 909 /** 910 * @} 911 */ 912 913 /** @defgroup HRTIM_Timer_GreaterCMP1_Mode HRTIM Timer Greater than Compare 1 PWM Mode 914 * @{ 915 * @brief Constants defining how the timer compare operates 916 */ 917 #define HRTIM_TIMERGTCMP1_EQUAL 0x00000000U /*!< Timer Compare 1 event is generated when counter is equal */ 918 #define HRTIM_TIMERGTCMP1_GREATER (HRTIM_TIMCR2_GTCMP1) /*!< Timer Compare 1 event is generated when counter is greater */ 919 /** 920 * @} 921 */ 922 923 /** @defgroup HRTIM_Timer_DualChannelDac_Reset HRTIM Dual Channel Dac Reset Trigger 924 * @{ 925 * @brief Constants defining when the hrtim_dac_reset_trgx trigger is generated 926 */ 927 #define HRTIM_TIMER_DCDR_COUNTER 0x00000000U /*!< the trigger is generated on counter reset or roll-over event */ 928 #define HRTIM_TIMER_DCDR_OUT1SET (HRTIM_TIMCR2_DCDR) /*!< the trigger is generated on output 1 set event */ 929 /** 930 * @} 931 */ 932 933 /** @defgroup HRTIM_Timer_DualChannelDac_Step HRTIM Dual Channel Dac Step Trigger 934 * @{ 935 * @brief Constants defining when the hrtim_dac_step_trgx trigger is generated 936 is generated 937 */ 938 #define HRTIM_TIMER_DCDS_CMP2 0x00000000U /*!< the trigger is generated on compare 2 event */ 939 #define HRTIM_TIMER_DCDS_OUT1RST (HRTIM_TIMCR2_DCDS) /*!< the trigger is generated on output 1 reset event */ 940 /** 941 * @} 942 */ 943 944 /** @defgroup HRTIM_Timer_DualChannelDac_Enable HRTIM Dual Channel DAC Trigger Enable 945 * @{ 946 * @brief Constants enabling the dual channel DAC triggering mechanism 947 */ 948 #define HRTIM_TIMER_DCDE_DISABLED 0x00000000U /*!< the Dual channel DAC trigger is disabled */ 949 #define HRTIM_TIMER_DCDE_ENABLED (HRTIM_TIMCR2_DCDE) /*!< the Dual channel DAC trigger is enabled */ 950 /** 951 * @} 952 */ 953 954 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update 955 * @{ 956 * @brief Constants defining whether registers are updated when the timer 957 * repetition period is completed (either due to roll-over or 958 * reset events) 959 */ 960 #define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /*!< Update on repetition disabled */ 961 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */ 962 /** 963 * @} 964 */ 965 966 967 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode 968 * @{ 969 * @brief Constants defining whether or not the push-pull mode is enabled for 970 * a timer. 971 */ 972 #define HRTIM_TIMPUSHPULLMODE_DISABLED 0x00000000U /*!< Push-Pull mode disabled */ 973 #define HRTIM_TIMPUSHPULLMODE_ENABLED (HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */ 974 /** 975 * @} 976 */ 977 978 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling 979 * @{ 980 * @brief Constants defining whether a fault channel is enabled for a timer 981 */ 982 #define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */ 983 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */ 984 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */ 985 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */ 986 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */ 987 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */ 988 #define HRTIM_TIMFAULTENABLE_FAULT6 (HRTIM_FLTR_FLT6EN) /*!< Fault 6 enabled */ 989 /** 990 * @} 991 */ 992 993 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock 994 * @{ 995 * @brief Constants defining whether or not fault enabling bits are write 996 * protected for a timer 997 */ 998 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */ 999 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */ 1000 /** 1001 * @} 1002 */ 1003 1004 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion 1005 * @{ 1006 * @brief Constants defining whether or not fault the dead time insertion 1007 * feature is enabled for a timer 1008 */ 1009 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */ 1010 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Dead-time is inserted between output 1 and output 2U */ 1011 /** 1012 * @} 1013 */ 1014 1015 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode 1016 * @{ 1017 * @brief Constants defining all possible delayed protection modes 1018 * for a timer. Also define the source and outputs on which the delayed 1019 * protection schemes are applied 1020 */ 1021 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 1022 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */ 1023 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */ 1024 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */ 1025 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */ 1026 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */ 1027 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */ 1028 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */ 1029 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */ 1030 1031 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 1032 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */ 1033 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */ 1034 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */ 1035 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */ 1036 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */ 1037 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */ 1038 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */ 1039 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */ 1040 1041 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 1042 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 delayed Idle on external Event 6U */ 1043 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 2 delayed Idle on external Event 6U */ 1044 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 and output 2 delayed Idle on external Event 6U */ 1045 #define HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Balanced Idle on external Event 6U */ 1046 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 delayed Idle on external Event 7U */ 1047 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 2 delayed Idle on external Event 7U */ 1048 #define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 and output2 delayed Idle on external Event 7U */ 1049 #define HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Balanced Idle on external Event 7U */ 1050 /** 1051 * @} 1052 */ 1053 1054 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger 1055 * @{ 1056 * @brief Constants defining whether the registers update is done synchronously 1057 * with any other timer or master update 1058 */ 1059 #define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */ 1060 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */ 1061 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */ 1062 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */ 1063 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/ 1064 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */ 1065 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */ 1066 #define HRTIM_TIMUPDATETRIGGER_TIMER_F (HRTIM_TIMCR_TFU) /*!< Register update is triggered by the timer F update */ 1067 /** 1068 * @} 1069 */ 1070 1071 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger 1072 * @{ 1073 * @brief Constants defining the events that can be selected to trigger the reset 1074 * of the timer counter 1075 */ 1076 #define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /*!< No counter reset trigger */ 1077 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */ 1078 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */ 1079 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */ 1080 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */ 1081 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */ 1082 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */ 1083 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */ 1084 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */ 1085 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */ 1086 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */ 1087 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */ 1088 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */ 1089 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */ 1090 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */ 1091 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */ 1092 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */ 1093 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */ 1094 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */ 1095 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 1096 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 1097 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 1098 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 1099 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 1100 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 1101 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 1102 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 1103 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 1104 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 1105 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 1106 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 1107 #define HRTIM_TIMRESETTRIGGER_OTHER5_CMP1 (HRTIM_RSTR_TIMFCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 1108 #define HRTIM_TIMRESETTRIGGER_OTHER5_CMP2 (HRTIM_RSTR_TIMFCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 1109 /** 1110 * @} 1111 */ 1112 1113 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update 1114 * @{ 1115 * @brief Constants defining whether the register are updated upon Timerx 1116 * counter reset or roll-over to 0 after reaching the period value 1117 * in continuous mode 1118 */ 1119 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */ 1120 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */ 1121 /** 1122 * @} 1123 */ 1124 1125 /** @defgroup HRTIM_Timer_RollOver_Mode HRTIM Timer RollOver Mode 1126 * @{ 1127 * @brief Constants defining when the roll-over is generated upon Timerx 1128 * event generated when the counter is equal to 0 ('VALLEY' mode) or to HRTIM_PERxR value ('CREST' mode) or BOTH 1129 * This setting only applies when the UDM bit is set. It is not significant otherwise. 1130 */ 1131 #define HRTIM_TIM_FEROM_BOTH 0x00000000U /*!< Roll-over event used by */ 1132 #define HRTIM_TIM_FEROM_CREST (HRTIM_TIMCR2_FEROM_1) /*!< the Fault and */ 1133 #define HRTIM_TIM_FEROM_VALLEY (HRTIM_TIMCR2_FEROM_0) /*!< Event counters */ 1134 #define HRTIM_TIM_BMROM_BOTH 0x00000000U /*!< Roll-over event used in the Burst mode controller */ 1135 #define HRTIM_TIM_BMROM_CREST (HRTIM_TIMCR2_BMROM_1) /*!< as clock */ 1136 #define HRTIM_TIM_BMROM_VALLEY (HRTIM_TIMCR2_BMROM_0) /*!< and as burst mode trigger */ 1137 #define HRTIM_TIM_ADROM_BOTH 0x00000000U /*!< Roll-over event which triggers */ 1138 #define HRTIM_TIM_ADROM_CREST (HRTIM_TIMCR2_ADROM_1) /*!< the */ 1139 #define HRTIM_TIM_ADROM_VALLEY (HRTIM_TIMCR2_ADROM_0) /*!< ADC */ 1140 #define HRTIM_TIM_OUTROM_BOTH 0x00000000U /*!< Roll-over event which sets and/or resets the outputs */ 1141 #define HRTIM_TIM_OUTROM_CREST (HRTIM_TIMCR2_OUTROM_1) /*!< as per HRTIM_SETxyR */ 1142 #define HRTIM_TIM_OUTROM_VALLEY (HRTIM_TIMCR2_OUTROM_0) /*!< and HRTIM_RSTxyR settings */ 1143 #define HRTIM_TIM_ROM_BOTH 0x00000000U /*!< Roll-over event with the following destinations: IRQ and DMA requests,*/ 1144 #define HRTIM_TIM_ROM_CREST (HRTIM_TIMCR2_ROM_1) /*!< Update trigger (to transfer content from preload to active registers), */ 1145 #define HRTIM_TIM_ROM_VALLEY (HRTIM_TIMCR2_ROM_0) /*!< repetition counter decrement and External Event filtering */ 1146 1147 #define IS_HRTIM_ROLLOVERMODE(ROLLOVER)\ 1148 ((((ROLLOVER) == HRTIM_TIM_FEROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_FEROM_CREST) || ((ROLLOVER) == HRTIM_TIM_FEROM_VALLEY)) ||\ 1149 (((ROLLOVER) == HRTIM_TIM_ADROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_ADROM_CREST) || ((ROLLOVER) == HRTIM_TIM_ADROM_VALLEY)) ||\ 1150 (((ROLLOVER) == HRTIM_TIM_BMROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_BMROM_CREST) || ((ROLLOVER) == HRTIM_TIM_BMROM_VALLEY)) ||\ 1151 (((ROLLOVER) == HRTIM_TIM_OUTROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_OUTROM_CREST) || ((ROLLOVER) == HRTIM_TIM_OUTROM_VALLEY)) ||\ 1152 (((ROLLOVER) == HRTIM_TIM_ROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_ROM_CREST) || ((ROLLOVER) == HRTIM_TIM_ROM_VALLEY))) 1153 /** 1154 * @} 1155 */ 1156 1157 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode 1158 * @{ 1159 * @brief Constants defining whether the compare register is behaving in 1160 * regular mode (compare match issued as soon as counter equal compare), 1161 * or in auto-delayed mode 1162 */ 1163 #define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /*!< standard compare mode */ 1164 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */ 1165 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */ 1166 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */ 1167 /** 1168 * @} 1169 */ 1170 1171 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode 1172 * @{ 1173 * @brief Constants defining the behavior of the output signal when the timer 1174 operates in basic output compare mode 1175 */ 1176 #define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /*!< Output toggles when the timer counter reaches the compare value */ 1177 #define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /*!< Output forced to active level when the timer counter reaches the compare value */ 1178 #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ 1179 1180 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ 1181 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ 1182 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ 1183 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) 1184 /** 1185 * @} 1186 */ 1187 1188 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity 1189 * @{ 1190 * @brief Constants defining the polarity of a timer output 1191 */ 1192 #define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is active HIGH */ 1193 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */ 1194 /** 1195 * @} 1196 */ 1197 1198 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source 1199 * @{ 1200 * @brief Constants defining the events that can be selected to configure the 1201 * set crossbar of a timer output 1202 */ 1203 #define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */ 1204 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */ 1205 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */ 1206 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */ 1207 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */ 1208 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */ 1209 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */ 1210 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */ 1211 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */ 1212 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */ 1213 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */ 1214 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */ 1215 /* Timer Events mapping for Timer A */ 1216 #define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1217 #define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1218 #define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1219 #define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1220 #define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1221 #define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1222 #define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1223 #define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1224 #define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1225 /* Timer Events mapping for Timer B */ 1226 #define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1227 #define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1228 #define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1229 #define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1230 #define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1231 #define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1232 #define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1233 #define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1234 #define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1235 /* Timer Events mapping for Timer C */ 1236 #define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1237 #define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1238 #define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1239 #define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1240 #define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1241 #define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1242 #define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1243 #define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1244 #define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1245 /* Timer Events mapping for Timer D */ 1246 #define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1247 #define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1248 #define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1249 #define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1250 #define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1251 #define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1252 #define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1253 #define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1254 #define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1255 /* Timer Events mapping for Timer E */ 1256 #define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1257 #define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1258 #define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1259 #define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1260 #define HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1261 #define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1262 #define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1263 #define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1264 #define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1265 /* Timer Events mapping for Timer F */ 1266 #define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 1267 #define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 1268 #define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 1269 #define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 1270 #define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 1271 #define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 1272 #define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 1273 #define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 1274 #define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 1275 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */ 1276 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */ 1277 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */ 1278 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */ 1279 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */ 1280 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */ 1281 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */ 1282 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */ 1283 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */ 1284 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */ 1285 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */ 1286 /** 1287 * @} 1288 */ 1289 1290 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source 1291 * @{ 1292 * @brief Constants defining the events that can be selected to configure the 1293 * reset crossbar of a timer output 1294 */ 1295 #define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ 1296 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ 1297 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */ 1298 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */ 1299 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */ 1300 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */ 1301 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */ 1302 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */ 1303 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */ 1304 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ 1305 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ 1306 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ 1307 /* Timer Events mapping for Timer A */ 1308 #define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1309 #define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1310 #define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1311 #define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1312 #define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1313 #define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1314 #define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1315 #define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1316 #define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1317 /* Timer Events mapping for Timer B */ 1318 #define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1319 #define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1320 #define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1321 #define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1322 #define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1323 #define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1324 #define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1325 #define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1326 #define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1327 /* Timer Events mapping for Timer C */ 1328 #define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1329 #define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1330 #define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1331 #define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1332 #define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1333 #define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1334 #define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1335 #define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1336 #define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1337 /* Timer Events mapping for Timer D */ 1338 #define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1339 #define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1340 #define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1341 #define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1342 #define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1343 #define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1344 #define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1345 #define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1346 #define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1347 /* Timer Events mapping for Timer E */ 1348 #define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1349 #define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1350 #define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1351 #define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1352 #define HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1353 #define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1354 #define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1355 #define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1356 #define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1357 /* Timer Events mapping for Timer F */ 1358 #define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */ 1359 #define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */ 1360 #define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */ 1361 #define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */ 1362 #define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */ 1363 #define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */ 1364 #define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */ 1365 #define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */ 1366 #define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */ 1367 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ 1368 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ 1369 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ 1370 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */ 1371 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */ 1372 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */ 1373 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */ 1374 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */ 1375 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */ 1376 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */ 1377 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */ 1378 /** 1379 * @} 1380 */ 1381 1382 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode 1383 * @{ 1384 * @brief Constants defining whether or not the timer output transition to its 1385 IDLE state when burst mode is entered 1386 */ 1387 #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ 1388 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ 1389 /** 1390 * @} 1391 */ 1392 1393 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level 1394 * @{ 1395 * @brief Constants defining the output level when output is in IDLE state 1396 */ 1397 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */ 1398 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */ 1399 /** 1400 * @} 1401 */ 1402 1403 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level 1404 * @{ 1405 * @brief Constants defining the output level when output is in FAULT state 1406 */ 1407 #define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */ 1408 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */ 1409 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */ 1410 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */ 1411 /** 1412 * @} 1413 */ 1414 1415 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable 1416 * @{ 1417 * @brief Constants defining whether or not chopper mode is enabled for a timer 1418 output 1419 */ 1420 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */ 1421 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */ 1422 /** 1423 * @} 1424 */ 1425 1426 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed 1427 * @{ 1428 * @brief Constants defining the idle mode entry is delayed by forcing a 1429 dead-time insertion before switching the outputs to their idle state 1430 */ 1431 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */ 1432 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Dead-time is inserted on output before entering the idle mode */ 1433 /** 1434 * @} 1435 */ 1436 1437 /** @defgroup HRTIM_Output_Balanced_Idle_Auto_Resume HRTIM Output Balanced Idle Automatic Resume 1438 * @{ 1439 * @brief Constants defining if the outputs are automatically 1440 re-enabled after a balanced idle event. 1441 */ 1442 #define HRTIM_OUTPUTBIAR_DISABLED 0x00000000U /*!< output is not automatically re-enabled */ 1443 #define HRTIM_OUTPUTBIAR_ENABLED (HRTIM_OUTR_BIAR) /*!< output is automatically re-enabled */ 1444 /** 1445 * @} 1446 */ 1447 1448 1449 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger 1450 * @{ 1451 * @brief Constants defining the events that can be selected to trigger the 1452 * capture of the timing unit counter 1453 */ 1454 #define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */ 1455 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */ 1456 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */ 1457 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */ 1458 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */ 1459 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */ 1460 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */ 1461 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */ 1462 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */ 1463 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */ 1464 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */ 1465 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */ 1466 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */ 1467 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */ 1468 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */ 1469 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */ 1470 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */ 1471 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */ 1472 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */ 1473 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */ 1474 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */ 1475 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */ 1476 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */ 1477 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */ 1478 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */ 1479 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */ 1480 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */ 1481 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */ 1482 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */ 1483 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */ 1484 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */ 1485 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */ 1486 /** 1487 * @} 1488 */ 1489 /** @defgroup HRTIM_Capture_Unit_TimerF_Trigger HRTIM Capture Unit TimerF Trigger 1490 * @{ 1491 * @brief Constants defining the events that can be selected to trigger the 1492 * capture of the timing unit counter 1493 */ 1494 #define HRTIM_CAPTURETRIGGER_TF1_SET ((uint64_t)(HRTIM_CPT1CR_TF1SET ) << 32) /*!< Capture is triggered by TF1 output inactive to active transition */ 1495 #define HRTIM_CAPTURETRIGGER_TF1_RESET ((uint64_t)(HRTIM_CPT1CR_TF1RST ) << 32) /*!< Capture is triggered by TF1 output active to inactive transition */ 1496 #define HRTIM_CAPTURETRIGGER_TIMERF_CMP1 ((uint64_t)(HRTIM_CPT1CR_TIMFCMP1) << 32) /*!< Timer F Compare 1 triggers Capture */ 1497 #define HRTIM_CAPTURETRIGGER_TIMERF_CMP2 ((uint64_t)(HRTIM_CPT1CR_TIMFCMP2) << 32) /*!< Timer F Compare 2 triggers Capture */ 1498 /** 1499 * @} 1500 */ 1501 1502 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter 1503 * @{ 1504 * @brief Constants defining the event filtering applied to external events 1505 * by a timer 1506 */ 1507 #define HRTIM_TIMEEVFLT_NONE (0x00000000U) 1508 #define HRTIM_TIMEEVFLT_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */ 1509 #define HRTIM_TIMEEVFLT_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */ 1510 #define HRTIM_TIMEEVFLT_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */ 1511 #define HRTIM_TIMEEVFLT_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */ 1512 /* Blanking Filter for TIMER A */ 1513 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1514 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1515 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1516 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1517 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1518 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1519 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1520 #define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1521 /* Blanking Filter for TIMER B */ 1522 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1523 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1524 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1525 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1526 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1527 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1528 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1529 #define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1530 /* Blanking Filter for TIMER C */ 1531 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1532 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1533 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1534 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1535 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1536 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1537 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1538 #define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1539 /* Blanking Filter for TIMER D */ 1540 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1541 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1542 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1543 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1544 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1545 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1546 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1547 #define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1548 /* Blanking Filter for TIMER E */ 1549 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1550 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1551 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1552 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1553 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1554 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1555 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1556 #define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1557 /* Blanking Filter for TIMER F */ 1558 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 1559 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 1560 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 1561 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 1562 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 1563 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 1564 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 1565 #define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 1566 1567 #define HRTIM_TIMEEVFLT_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ 1568 #define HRTIM_TIMEEVFLT_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ 1569 #define HRTIM_TIMEEVFLT_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\ 1570 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ 1571 /** 1572 * @} 1573 */ 1574 1575 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch 1576 * @{ 1577 * @brief Constants defining whether or not the external event is 1578 * memorized (latched) and generated as soon as the blanking period 1579 * is completed or the window ends 1580 */ 1581 #define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */ 1582 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */ 1583 /** 1584 * @} 1585 */ 1586 1587 /** @defgroup HRTIM_Timer_External_Event HRTIM Timer External Event Counter A or B 1588 * @{ 1589 * @brief Constants defining the External Event Counter A or B 1590 */ 1591 #define HRTIM_EVENTCOUNTER_A (HRTIM_EEFR3_EEVACE) /*!< External Event Counter A */ 1592 #define HRTIM_EVENTCOUNTER_B (HRTIM_EEFR3_EEVBCE) /*!< External Event Counter B */ 1593 /** 1594 * @} 1595 */ 1596 1597 /** @defgroup HRTIM_Timer_External_Event_ResetMode HRTIM Timer External Counter Reset Mode 1598 * @{ 1599 * @brief Constants enabling the External Event Counter A or B Reset Mode 1600 */ 1601 #define HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL (0x00000000U) /*!< External Event Counter is reset on each reset / roll-over event */ 1602 #define HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL (0x00000001U) /*!< External Event Counter is reset on each reset / roll-over event only 1603 if no event occurs during last counting period */ 1604 /** 1605 * @} 1606 */ 1607 1608 /** @defgroup HRTIM_Timer_ReSyncUpdate HRTIM Timer Re-Synchronized update 1609 * @{ 1610 * @brief Constants defining the update coming condition 1611 */ 1612 #define HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL (0x00000000U) /*!< update taken into account immediately */ 1613 #define HRTIM_TIMERESYNC_UPDATE_CONDITIONAL (0x00000001U) /*!< update taken into account on the following Reset/Roll-over event */ 1614 /** 1615 * @} 1616 */ 1617 1618 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio 1619 * @{ 1620 * @brief Constants defining division ratio between the timer clock frequency 1621 * (fHRTIM) and the dead-time generator clock (fDTG) 1622 */ 1623 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */ 1624 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */ 1625 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */ 1626 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */ 1627 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */ 1628 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */ 1629 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */ 1630 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */ 1631 /** 1632 * @} 1633 */ 1634 1635 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign 1636 * @{ 1637 * @brief Constants defining whether the dead-time is positive or negative 1638 * (overlapping signal) on rising edge 1639 */ 1640 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on rising edge */ 1641 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative dead-time on rising edge */ 1642 /** 1643 * @} 1644 */ 1645 1646 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock 1647 * @{ 1648 * @brief Constants defining whether or not the dead-time (rising sign and 1649 * value) is write protected 1650 */ 1651 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Dead-time rising value and sign is writeable */ 1652 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Dead-time rising value and sign is read-only */ 1653 /** 1654 * @} 1655 */ 1656 1657 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock 1658 * @{ 1659 * @brief Constants defining whether or not the dead-time rising sign is write 1660 * protected 1661 */ 1662 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time rising sign is writeable */ 1663 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Dead-time rising sign is read-only */ 1664 /** 1665 * @} 1666 */ 1667 1668 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign 1669 * @{ 1670 * @brief Constants defining whether the dead-time is positive or negative 1671 * (overlapping signal) on falling edge 1672 */ 1673 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on falling edge */ 1674 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative dead-time on falling edge */ 1675 /** 1676 * @} 1677 */ 1678 1679 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock 1680 * @{ 1681 * @brief Constants defining whether or not the dead-time (falling sign and 1682 * value) is write protected 1683 */ 1684 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Dead-time falling value and sign is writeable */ 1685 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Dead-time falling value and sign is read-only */ 1686 /** 1687 * @} 1688 */ 1689 1690 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock 1691 * @{ 1692 * @brief Constants defining whether or not the dead-time falling sign is write 1693 * protected 1694 */ 1695 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time falling sign is writeable */ 1696 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Dead-time falling sign is read-only */ 1697 /** 1698 * @} 1699 */ 1700 1701 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency 1702 * @{ 1703 * @brief Constants defining the frequency of the generated high frequency carrier 1704 */ 1705 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /*!< fCHPFRQ = fHRTIM / 16 */ 1706 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */ 1707 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */ 1708 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */ 1709 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */ 1710 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */ 1711 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */ 1712 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */ 1713 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */ 1714 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */ 1715 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */ 1716 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */ 1717 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */ 1718 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ 1719 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ 1720 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ 1721 /** 1722 * @} 1723 */ 1724 1725 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle 1726 * @{ 1727 * @brief Constants defining the duty cycle of the generated high frequency carrier 1728 * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8) 1729 */ 1730 #define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */ 1731 #define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */ 1732 #define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */ 1733 #define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */ 1734 #define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */ 1735 #define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */ 1736 #define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */ 1737 #define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */ 1738 /** 1739 * @} 1740 */ 1741 1742 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width 1743 * @{ 1744 * @brief Constants defining the pulse width of the first pulse of the generated 1745 * high frequency carrier 1746 */ 1747 #define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */ 1748 #define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */ 1749 #define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */ 1750 #define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */ 1751 #define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */ 1752 #define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */ 1753 #define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */ 1754 #define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */ 1755 #define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */ 1756 #define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */ 1757 #define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */ 1758 #define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */ 1759 #define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */ 1760 #define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */ 1761 #define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */ 1762 #define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */ 1763 /** 1764 * @} 1765 */ 1766 1767 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options 1768 * @{ 1769 * @brief Constants defining the options for synchronizing multiple HRTIM 1770 * instances, as a master unit (generating a synchronization signal) 1771 * or as a slave (waiting for a trigger to be synchronized) 1772 */ 1773 #define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */ 1774 #define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/ 1775 #define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */ 1776 /** 1777 * @} 1778 */ 1779 1780 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source 1781 * @{ 1782 * @brief Constants defining defining the synchronization input source 1783 */ 1784 #define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */ 1785 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */ 1786 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */ 1787 /** 1788 * @} 1789 */ 1790 1791 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source 1792 * @{ 1793 * @brief Constants defining the source and event to be sent on the 1794 * synchronization outputs 1795 */ 1796 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */ 1797 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */ 1798 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */ 1799 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */ 1800 /** 1801 * @} 1802 */ 1803 1804 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity 1805 * @{ 1806 * @brief Constants defining the routing and conditioning of the synchronization output event 1807 */ 1808 #define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */ 1809 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */ 1810 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */ 1811 /** 1812 * @} 1813 */ 1814 1815 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources 1816 * @{ 1817 * @brief Constants defining available sources associated to external events 1818 */ 1819 #define HRTIM_EEV1SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 1 */ 1820 #define HRTIM_EEV2SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 2 */ 1821 #define HRTIM_EEV3SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 3 */ 1822 #define HRTIM_EEV4SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 4 */ 1823 #define HRTIM_EEV5SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 5 */ 1824 #define HRTIM_EEV6SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 6 */ 1825 #define HRTIM_EEV7SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 7 */ 1826 #define HRTIM_EEV8SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 8 */ 1827 #define HRTIM_EEV9SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 9 */ 1828 #define HRTIM_EEV10SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 10 */ 1829 #define HRTIM_EEV1SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 1 */ 1830 #define HRTIM_EEV2SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 2 */ 1831 #define HRTIM_EEV3SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 3 */ 1832 #define HRTIM_EEV4SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 4 */ 1833 #define HRTIM_EEV5SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 5 */ 1834 #define HRTIM_EEV6SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 6 */ 1835 #define HRTIM_EEV7SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 7 */ 1836 #define HRTIM_EEV8SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 8 */ 1837 #define HRTIM_EEV9SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 9 */ 1838 #define HRTIM_EEV10SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 10 */ 1839 #define HRTIM_EEV1SRC_TIM1_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 1 */ 1840 #define HRTIM_EEV2SRC_TIM2_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 2 */ 1841 #define HRTIM_EEV3SRC_TIM3_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 3 */ 1842 #define HRTIM_EEV4SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 4 */ 1843 #define HRTIM_EEV5SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 5 */ 1844 #define HRTIM_EEV6SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 6 */ 1845 #define HRTIM_EEV7SRC_TIM7_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 7 */ 1846 #define HRTIM_EEV8SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 8 */ 1847 #define HRTIM_EEV9SRC_TIM15_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 9 */ 1848 #define HRTIM_EEV10SRC_TIM6_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 10 */ 1849 #define HRTIM_EEV1SRC_ADC1_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 1 */ 1850 #define HRTIM_EEV2SRC_ADC1_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 2 */ 1851 #define HRTIM_EEV3SRC_ADC1_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 3 */ 1852 #define HRTIM_EEV4SRC_ADC2_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 4 */ 1853 #define HRTIM_EEV5SRC_ADC2_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 5 */ 1854 #define HRTIM_EEV6SRC_ADC2_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 6 */ 1855 #define HRTIM_EEV7SRC_ADC3_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 7 */ 1856 #define HRTIM_EEV8SRC_ADC4_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 8 */ 1857 #define HRTIM_EEV9SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 9 */ 1858 #define HRTIM_EEV10SRC_ADC5_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 10 */ 1859 /** 1860 * @} 1861 */ 1862 1863 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity 1864 * @{ 1865 * @brief Constants defining the polarity of an external event 1866 */ 1867 #define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /*!< External event is active high */ 1868 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */ 1869 /** 1870 * @} 1871 */ 1872 1873 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity 1874 * @{ 1875 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) 1876 * of an external event 1877 */ 1878 #define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /*!< External event is active on level */ 1879 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */ 1880 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */ 1881 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */ 1882 /** 1883 * @} 1884 */ 1885 1886 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode 1887 * @{ 1888 * @brief Constants defining whether or not an external event is programmed in 1889 fast mode 1890 */ 1891 #define HRTIM_EVENTFASTMODE_DISABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */ 1892 #define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */ 1893 /** 1894 * @} 1895 */ 1896 1897 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter 1898 * @{ 1899 * @brief Constants defining the frequency used to sample an external event 6 1900 * input and the length (N) of the digital filter applied 1901 */ 1902 #define HRTIM_EVENTFILTER_NONE (0x00000000U) /*!< Filter disabled */ 1903 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2U */ 1904 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4U */ 1905 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */ 1906 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2U, N=6U */ 1907 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */ 1908 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */ 1909 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */ 1910 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8U, N=6U */ 1911 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */ 1912 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */ 1913 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */ 1914 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */ 1915 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */ 1916 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */ 1917 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */ 1918 /** 1919 * @} 1920 */ 1921 1922 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler 1923 * @{ 1924 * @brief Constants defining division ratio between the timer clock frequency 1925 * fHRTIM) and the external event signal sampling clock (fEEVS) 1926 * used by the digital filters 1927 */ 1928 #define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /*!< fEEVS=fHRTIM */ 1929 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2U */ 1930 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4U */ 1931 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */ 1932 /** 1933 * @} 1934 */ 1935 1936 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources 1937 * @{ 1938 * @brief Constants defining whether a fault is triggered by any external 1939 * or internal fault source 1940 */ 1941 #define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */ 1942 #define HRTIM_FAULTSOURCE_INTERNAL (0x00000001U) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */ 1943 #define HRTIM_FAULTSOURCE_EEVINPUT (0x00000002U) /*!< Fault input is EEV pin */ 1944 /** 1945 * @} 1946 */ 1947 1948 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity 1949 * @{ 1950 * @brief Constants defining the polarity of a fault event 1951 */ 1952 #define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */ 1953 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */ 1954 /** 1955 * @} 1956 */ 1957 1958 /** @defgroup HRTIM_Fault_Blanking HRTIM Fault Blanking Source 1959 * @{ 1960 * @brief Constants defining the blanking source of a fault event 1961 */ 1962 #define HRTIM_FAULTBLANKINGMODE_RSTALIGNED (0x00000000U) /*!< Fault blanking source is Reset-aligned window */ 1963 #define HRTIM_FAULTBLANKINGMODE_MOVING (0x00000001U) /*!< Fault blanking source is Moving window */ 1964 /** 1965 * @} 1966 */ 1967 1968 /** @defgroup HRTIM_Fault_ResetMode HRTIM Fault Reset Mode 1969 * @{ 1970 * @brief Constants defining the Counter reset mode of a fault event 1971 */ 1972 #define HRTIM_FAULTCOUNTERRST_UNCONDITIONAL (0x00000000U) /*!< Fault counter is reset on each reset / roll-over event */ 1973 #define HRTIM_FAULTCOUNTERRST_CONDITIONAL (0x00000001U) /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last countingperiod.*/ 1974 /** 1975 * @} 1976 */ 1977 1978 /** @defgroup HRTIM_Fault_Blanking_Control HRTIM Fault Blanking Control 1979 * @{ 1980 * @brief Constants used to enable or disable the blanking mode of a fault channel 1981 */ 1982 #define HRTIM_FAULTBLANKINGCTL_DISABLED 0x00000000U /*!< No blanking on Fault */ 1983 #define HRTIM_FAULTBLANKINGCTL_ENABLED 0x00000001U /*!< Fault blanking mode */ 1984 /** 1985 * @} 1986 */ 1987 1988 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter 1989 * @{ 1990 * @ brief Constants defining the frequency used to sample the fault input and 1991 * the length (N) of the digital filter applied 1992 */ 1993 #define HRTIM_FAULTFILTER_NONE (0x00000000U) /*!< Filter disabled */ 1994 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2U */ 1995 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4U */ 1996 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */ 1997 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2U, N=6U */ 1998 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */ 1999 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */ 2000 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */ 2001 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8U, N=6U */ 2002 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */ 2003 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */ 2004 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */ 2005 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */ 2006 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */ 2007 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */ 2008 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */ 2009 /** 2010 * @} 2011 */ 2012 2013 /** @defgroup HRTIM_Fault_Counter HRTIM Fault counter threshold value 2014 * @{ 2015 * @ brief Constants defining the FAULT Counter threshold 2016 */ 2017 #define HRTIM_FAULTCOUNTER_NONE ((uint32_t)0U ) /*!< Counter threshold = 0U */ 2018 #define HRTIM_FAULTCOUNTER_1 ((uint32_t)1U ) /*!< Counter threshold = 1U */ 2019 #define HRTIM_FAULTCOUNTER_2 ((uint32_t)2U ) /*!< Counter threshold = 2U */ 2020 #define HRTIM_FAULTCOUNTER_3 ((uint32_t)3U ) /*!< Counter threshold = 3U */ 2021 #define HRTIM_FAULTCOUNTER_4 ((uint32_t)4U ) /*!< Counter threshold = 4U */ 2022 #define HRTIM_FAULTCOUNTER_5 ((uint32_t)5U ) /*!< Counter threshold = 5U */ 2023 #define HRTIM_FAULTCOUNTER_6 ((uint32_t)6U ) /*!< Counter threshold = 6U */ 2024 #define HRTIM_FAULTCOUNTER_7 ((uint32_t)7U ) /*!< Counter threshold = 7U */ 2025 #define HRTIM_FAULTCOUNTER_8 ((uint32_t)8U ) /*!< Counter threshold = 8U */ 2026 #define HRTIM_FAULTCOUNTER_9 ((uint32_t)9U ) /*!< Counter threshold = 9U */ 2027 #define HRTIM_FAULTCOUNTER_10 ((uint32_t)10U) /*!< Counter threshold = 10U */ 2028 #define HRTIM_FAULTCOUNTER_11 ((uint32_t)11U) /*!< Counter threshold = 11U */ 2029 #define HRTIM_FAULTCOUNTER_12 ((uint32_t)12U) /*!< Counter threshold = 12U */ 2030 #define HRTIM_FAULTCOUNTER_13 ((uint32_t)13U) /*!< Counter threshold = 13U */ 2031 #define HRTIM_FAULTCOUNTER_14 ((uint32_t)14U) /*!< Counter threshold = 14U */ 2032 #define HRTIM_FAULTCOUNTER_15 ((uint32_t)15U) /*!< Counter threshold = 15U */ 2033 /** 2034 * @} 2035 */ 2036 2037 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock 2038 * @{ 2039 * @brief Constants defining whether or not the fault programming bits are 2040 write protected 2041 */ 2042 #define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */ 2043 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */ 2044 /** 2045 * @} 2046 */ 2047 2048 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler 2049 * @{ 2050 * @brief Constants defining the division ratio between the timer clock 2051 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used 2052 * by the digital filters. 2053 */ 2054 #define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /*!< fFLTS=fHRTIM */ 2055 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2U */ 2056 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4U */ 2057 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */ 2058 /** 2059 * @} 2060 */ 2061 2062 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode 2063 * @{ 2064 * @brief Constants defining if the burst mode is entered once or if it is 2065 * continuously operating 2066 */ 2067 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */ 2068 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */ 2069 /** 2070 * @} 2071 */ 2072 2073 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source 2074 * @{ 2075 * @brief Constants defining the clock source for the burst mode counter 2076 */ 2077 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */ 2078 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */ 2079 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */ 2080 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */ 2081 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */ 2082 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */ 2083 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_F (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */ 2084 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */ 2085 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */ 2086 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */ 2087 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */ 2088 /** 2089 * @} 2090 */ 2091 2092 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler 2093 * @{ 2094 * @brief Constants defining the prescaling ratio of the fHRTIM clock 2095 * for the burst mode controller 2096 */ 2097 #define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /*!< fBRST = fHRTIM */ 2098 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2U */ 2099 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4U */ 2100 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */ 2101 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16U */ 2102 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */ 2103 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */ 2104 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */ 2105 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256U */ 2106 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */ 2107 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */ 2108 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/ 2109 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */ 2110 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */ 2111 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */ 2112 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */ 2113 /** 2114 * @} 2115 */ 2116 2117 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable 2118 * @{ 2119 * @brief Constants defining whether or not burst mode registers preload 2120 mechanism is enabled, i.e. a write access into a preloadable register 2121 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register 2122 */ 2123 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */ 2124 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */ 2125 /** 2126 * @} 2127 */ 2128 2129 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger 2130 * @{ 2131 * @brief Constants defining the events that can be used to trig the burst 2132 * mode operation 2133 */ 2134 #define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */ 2135 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */ 2136 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */ 2137 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */ 2138 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2U */ 2139 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3U */ 2140 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4U */ 2141 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */ 2142 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */ 2143 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */ 2144 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */ 2145 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */ 2146 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */ 2147 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */ 2148 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */ 2149 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */ 2150 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */ 2151 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */ 2152 #define HRTIM_BURSTMODETRIGGER_TIMERF_RESET (HRTIM_BMTRGR_TFRST) /*!< Timer F reset */ 2153 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */ 2154 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */ 2155 #define HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION (HRTIM_BMTRGR_TFREP) /*!< Timer F repetition */ 2156 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */ 2157 #define HRTIM_BURSTMODETRIGGER_TIMERF_CMP1 (HRTIM_BMTRGR_TFCMP1) /*!< Timer F compare 1 */ 2158 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */ 2159 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */ 2160 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */ 2161 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */ 2162 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */ 2163 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */ 2164 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/ 2165 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */ 2166 /** 2167 * @} 2168 */ 2169 2170 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source 2171 * @{ 2172 * @brief constants defining the source triggering the update of the 2173 HRTIM_ADCxR register (transfer from preload to active register). 2174 */ 2175 #define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */ 2176 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */ 2177 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */ 2178 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */ 2179 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */ 2180 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */ 2181 #define HRTIM_ADCTRIGGERUPDATE_TIMER_F (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_1) /*!< Timer F */ 2182 /** 2183 * @} 2184 */ 2185 2186 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event 2187 * @{ 2188 * @brief constants defining the events triggering ADC conversion. 2189 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3 2190 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4 2191 * HRTIM_ADCTRIGGEREVENT579_*: ADC Triggers 5 and 7 and 9 2192 * HRTIM_ADCTRIGGEREVENT6810_*: ADC Triggers 6 and 8 and 10 2193 */ 2194 #define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */ 2195 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */ 2196 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */ 2197 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */ 2198 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */ 2199 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */ 2200 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */ 2201 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */ 2202 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */ 2203 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */ 2204 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */ 2205 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP2 (HRTIM_ADC1R_AD1TFC2) /*!< ADC Trigger on Timer F compare 2U */ 2206 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */ 2207 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */ 2208 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */ 2209 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */ 2210 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP3 (HRTIM_ADC1R_AD1TFC3) /*!< ADC Trigger on Timer F compare 3U */ 2211 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */ 2212 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */ 2213 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */ 2214 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */ 2215 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP4 (HRTIM_ADC1R_AD1TFC4) /*!< ADC Trigger on Timer F compare 4U */ 2216 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */ 2217 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */ 2218 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */ 2219 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_PERIOD (HRTIM_ADC1R_AD1TFPER) /*!< ADC Trigger on Timer F period */ 2220 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */ 2221 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */ 2222 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */ 2223 #define HRTIM_ADCTRIGGEREVENT13_TIMERF_RESET (HRTIM_ADC1R_AD1TFRST) /*!< ADC Trigger on Timer F reset */ 2224 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */ 2225 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */ 2226 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */ 2227 2228 #define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /*!< No ADC trigger event */ 2229 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */ 2230 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */ 2231 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */ 2232 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */ 2233 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */ 2234 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */ 2235 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */ 2236 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */ 2237 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */ 2238 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */ 2239 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */ 2240 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP2 (HRTIM_ADC2R_AD2TFC2) /*!< ADC Trigger on Timer F compare 2U */ 2241 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */ 2242 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */ 2243 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */ 2244 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP3 (HRTIM_ADC2R_AD2TFC3) /*!< ADC Trigger on Timer F compare 3U */ 2245 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */ 2246 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */ 2247 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */ 2248 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP4 (HRTIM_ADC2R_AD2TFC4) /*!< ADC Trigger on Timer F compare 4U */ 2249 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */ 2250 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */ 2251 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */ 2252 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */ 2253 #define HRTIM_ADCTRIGGEREVENT24_TIMERF_PERIOD (HRTIM_ADC2R_AD2TFPER) /*!< ADC Trigger on Timer F period */ 2254 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */ 2255 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */ 2256 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */ 2257 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */ 2258 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */ 2259 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */ 2260 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */ 2261 2262 2263 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP1 ((uint32_t)0x00U) /*!< ADC Trigger on master compare 1U */ 2264 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP2 ((uint32_t)0x01U) /*!< ADC Trigger on master compare 2U */ 2265 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP3 ((uint32_t)0x02U) /*!< ADC Trigger on master compare 3U */ 2266 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP4 ((uint32_t)0x03U) /*!< ADC Trigger on master compare 4U */ 2267 #define HRTIM_ADCTRIGGEREVENT6810_MASTER_PERIOD ((uint32_t)0x04U) /*!< ADC Trigger on master period */ 2268 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_6 ((uint32_t)0x05U) /*!< ADC Trigger on external event 6U */ 2269 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_7 ((uint32_t)0x06U) /*!< ADC Trigger on external event 7U */ 2270 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_8 ((uint32_t)0x07U) /*!< ADC Trigger on external event 8U */ 2271 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_9 ((uint32_t)0x08U) /*!< ADC Trigger on external event 9U */ 2272 #define HRTIM_ADCTRIGGEREVENT6810_EVENT_10 ((uint32_t)0x09U) /*!< ADC Trigger on external event 10U */ 2273 #define HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP2 ((uint32_t)0x0AU) /*!< ADC Trigger on Timer A compare 2U */ 2274 #define HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP4 ((uint32_t)0x0BU) /*!< ADC Trigger on Timer A compare 4U */ 2275 #define HRTIM_ADCTRIGGEREVENT6810_TIMERA_PERIOD ((uint32_t)0x0CU) /*!< ADC Trigger on Timer A period */ 2276 #define HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP2 ((uint32_t)0x0DU) /*!< ADC Trigger on Timer B compare 2U */ 2277 #define HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP4 ((uint32_t)0x0EU) /*!< ADC Trigger on Timer B compare 4U */ 2278 #define HRTIM_ADCTRIGGEREVENT6810_TIMERB_PERIOD ((uint32_t)0x0FU) /*!< ADC Trigger on Timer B period */ 2279 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP2 ((uint32_t)0x10U) /*!< ADC Trigger on Timer C compare 2U */ 2280 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP4 ((uint32_t)0x11U) /*!< ADC Trigger on Timer C compare 4U */ 2281 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_PERIOD ((uint32_t)0x12U) /*!< ADC Trigger on Timer C period */ 2282 #define HRTIM_ADCTRIGGEREVENT6810_TIMERC_RESET ((uint32_t)0x13U) /*!< ADC Trigger on Timer C reset */ 2283 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP2 ((uint32_t)0x14U) /*!< ADC Trigger on Timer D compare 2U */ 2284 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP4 ((uint32_t)0x15U) /*!< ADC Trigger on Timer D compare 4U */ 2285 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_PERIOD ((uint32_t)0x16U) /*!< ADC Trigger on Timer D period */ 2286 #define HRTIM_ADCTRIGGEREVENT6810_TIMERD_RESET ((uint32_t)0x17U) /*!< ADC Trigger on Timer D reset */ 2287 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP2 ((uint32_t)0x18U) /*!< ADC Trigger on Timer E compare 2U */ 2288 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP3 ((uint32_t)0x19U) /*!< ADC Trigger on Timer E compare 3U */ 2289 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP4 ((uint32_t)0x1AU) /*!< ADC Trigger on Timer E compare 4U */ 2290 #define HRTIM_ADCTRIGGEREVENT6810_TIMERE_RESET ((uint32_t)0x1BU) /*!< ADC Trigger on Timer E reset */ 2291 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP2 ((uint32_t)0x1CU) /*!< ADC Trigger on Timer F compare 2U */ 2292 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP3 ((uint32_t)0x1DU) /*!< ADC Trigger on Timer F compare 3U */ 2293 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP4 ((uint32_t)0x1EU) /*!< ADC Trigger on Timer F compare 4U */ 2294 #define HRTIM_ADCTRIGGEREVENT6810_TIMERF_PERIOD ((uint32_t)0x1FU) /*!< ADC Trigger on Timer F period */ 2295 2296 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP1 ((uint32_t)0x00U) /*!< ADC Trigger on master compare 1U */ 2297 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP2 ((uint32_t)0x01U) /*!< ADC Trigger on master compare 2U */ 2298 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP3 ((uint32_t)0x02U) /*!< ADC Trigger on master compare 3U */ 2299 #define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP4 ((uint32_t)0x03U) /*!< ADC Trigger on master compare 4U */ 2300 #define HRTIM_ADCTRIGGEREVENT579_MASTER_PERIOD ((uint32_t)0x04U) /*!< ADC Trigger on master period */ 2301 #define HRTIM_ADCTRIGGEREVENT579_EVENT_1 ((uint32_t)0x05U) /*!< ADC Trigger on external event 1U */ 2302 #define HRTIM_ADCTRIGGEREVENT579_EVENT_2 ((uint32_t)0x06U) /*!< ADC Trigger on external event 2U */ 2303 #define HRTIM_ADCTRIGGEREVENT579_EVENT_3 ((uint32_t)0x07U) /*!< ADC Trigger on external event 3U */ 2304 #define HRTIM_ADCTRIGGEREVENT579_EVENT_4 ((uint32_t)0x08U) /*!< ADC Trigger on external event 4U */ 2305 #define HRTIM_ADCTRIGGEREVENT579_EVENT_5 ((uint32_t)0x09U) /*!< ADC Trigger on external event 5U */ 2306 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP3 ((uint32_t)0x0AU) /*!< ADC Trigger on Timer A compare 3U */ 2307 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP4 ((uint32_t)0x0BU) /*!< ADC Trigger on Timer A compare 4U */ 2308 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_PERIOD ((uint32_t)0x0CU) /*!< ADC Trigger on Timer A period */ 2309 #define HRTIM_ADCTRIGGEREVENT579_TIMERA_RESET ((uint32_t)0x0DU) /*!< ADC Trigger on Timer A reset */ 2310 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP3 ((uint32_t)0x0EU) /*!< ADC Trigger on Timer B compare 3U */ 2311 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP4 ((uint32_t)0x0FU) /*!< ADC Trigger on Timer B compare 4U */ 2312 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_PERIOD ((uint32_t)0x10U) /*!< ADC Trigger on Timer B period */ 2313 #define HRTIM_ADCTRIGGEREVENT579_TIMERB_RESET ((uint32_t)0x11U) /*!< ADC Trigger on Timer B reset */ 2314 #define HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP3 ((uint32_t)0x12U) /*!< ADC Trigger on Timer C compare 3U */ 2315 #define HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP4 ((uint32_t)0x13U) /*!< ADC Trigger on Timer C compare 4U */ 2316 #define HRTIM_ADCTRIGGEREVENT579_TIMERC_PERIOD ((uint32_t)0x14U) /*!< ADC Trigger on Timer C period */ 2317 #define HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP3 ((uint32_t)0x15U) /*!< ADC Trigger on Timer D compare 3U */ 2318 #define HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP4 ((uint32_t)0x16U) /*!< ADC Trigger on Timer D compare 4U */ 2319 #define HRTIM_ADCTRIGGEREVENT579_TIMERD_PERIOD ((uint32_t)0x17U) /*!< ADC Trigger on Timer D period */ 2320 #define HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP3 ((uint32_t)0x18U) /*!< ADC Trigger on Timer E compare 3U */ 2321 #define HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP4 ((uint32_t)0x19U) /*!< ADC Trigger on Timer E compare 4U */ 2322 #define HRTIM_ADCTRIGGEREVENT579_TIMERE_PERIOD ((uint32_t)0x1AU) /*!< ADC Trigger on Timer E period */ 2323 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP2 ((uint32_t)0x1BU) /*!< ADC Trigger on Timer F compare 2U */ 2324 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP3 ((uint32_t)0x1CU) /*!< ADC Trigger on Timer F compare 3U */ 2325 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP4 ((uint32_t)0x1DU) /*!< ADC Trigger on Timer F compare 4U */ 2326 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_PERIOD ((uint32_t)0x1EU) /*!< ADC Trigger on Timer F period */ 2327 #define HRTIM_ADCTRIGGEREVENT579_TIMERF_RESET ((uint32_t)0x1FU) /*!< ADC Trigger on Timer F reset */ 2328 /** 2329 * @} 2330 */ 2331 2332 /** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate 2333 * @{ 2334 * @brief Constants defining the DLL calibration periods (in micro seconds) 2335 */ 2336 #define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */ 2337 #define HRTIM_CALIBRATIONRATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */ 2338 #define HRTIM_CALIBRATIONRATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */ 2339 #define HRTIM_CALIBRATIONRATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */ 2340 #define HRTIM_CALIBRATIONRATE_3 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */ 2341 /** 2342 * @} 2343 */ 2344 2345 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update 2346 * @{ 2347 * @brief Constants defining the registers that can be written during a burst 2348 * DMA operation 2349 */ 2350 #define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */ 2351 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */ 2352 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */ 2353 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */ 2354 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */ 2355 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */ 2356 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */ 2357 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */ 2358 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */ 2359 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */ 2360 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */ 2361 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */ 2362 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */ 2363 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */ 2364 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */ 2365 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */ 2366 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */ 2367 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */ 2368 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */ 2369 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */ 2370 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */ 2371 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */ 2372 #define HRTIM_BURSTDMA_CR2 (HRTIM_BDTUPR_TIMCR2) /*!< TIMxCR2 register is updated by Burst DMA accesses */ 2373 #define HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3) /*!< EEFxR3 register is updated by Burst DMA accesses */ 2374 /** 2375 * @} 2376 */ 2377 2378 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control 2379 * @{ 2380 * @brief Constants used to enable or disable the burst mode controller 2381 */ 2382 #define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */ 2383 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */ 2384 /** 2385 * @} 2386 */ 2387 2388 /** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control 2389 * @{ 2390 * @brief Constants used to enable or disable a fault channel 2391 */ 2392 #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */ 2393 #define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */ 2394 /** 2395 * @} 2396 */ 2397 2398 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update 2399 * @{ 2400 * @brief Constants used to force timer registers update 2401 */ 2402 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Force an immediate transfer from the preload to the active register in the master timer */ 2403 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Force an immediate transfer from the preload to the active register in the timer A */ 2404 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Force an immediate transfer from the preload to the active register in the timer B */ 2405 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Force an immediate transfer from the preload to the active register in the timer C */ 2406 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Force an immediate transfer from the preload to the active register in the timer D */ 2407 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Force an immediate transfer from the preload to the active register in the timer E */ 2408 #define HRTIM_TIMERUPDATE_F (HRTIM_CR2_TFSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer F */ 2409 /** 2410 * @} 2411 */ 2412 2413 /** @defgroup HRTIM_Software_Timer_SwapOutput HRTIM Software Timer swap Output 2414 * @{ 2415 * @brief Constants used to swap the output of the timer registers 2416 */ 2417 #define HRTIM_TIMERSWAP_A (HRTIM_CR2_SWPA) /*!< Swap the output of the Timer A */ 2418 #define HRTIM_TIMERSWAP_B (HRTIM_CR2_SWPB) /*!< Swap the output of the Timer B */ 2419 #define HRTIM_TIMERSWAP_C (HRTIM_CR2_SWPC) /*!< Swap the output of the Timer C */ 2420 #define HRTIM_TIMERSWAP_D (HRTIM_CR2_SWPD) /*!< Swap the output of the Timer D */ 2421 #define HRTIM_TIMERSWAP_E (HRTIM_CR2_SWPE) /*!< Swap the output of the Timer E */ 2422 #define HRTIM_TIMERSWAP_F (HRTIM_CR2_SWPF) /*!< Swap the output of the Timer F */ 2423 /** 2424 * @} 2425 */ 2426 2427 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset 2428 * @{ 2429 * @brief Constants used to force timer counter reset 2430 */ 2431 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Reset the master timer counter */ 2432 #define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Reset the timer A counter */ 2433 #define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Reset the timer B counter */ 2434 #define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Reset the timer C counter */ 2435 #define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Reset the timer D counter */ 2436 #define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Reset the timer E counter */ 2437 #define HRTIM_TIMERRESET_TIMER_F (HRTIM_CR2_TFRST) /*!< Reset the timer F counter */ 2438 /** 2439 * @} 2440 */ 2441 2442 /** @defgroup HRTIM_Output_Level HRTIM Output Level 2443 * @{ 2444 * @brief Constants defining the level of a timer output 2445 */ 2446 #define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /*!< Force the output to its active state */ 2447 #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ 2448 2449 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ 2450 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ 2451 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) 2452 /** 2453 * @} 2454 */ 2455 2456 /** @defgroup HRTIM_Output_State HRTIM Output State 2457 * @{ 2458 * @brief Constants defining the state of a timer output 2459 */ 2460 #define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or 2461 inactive level as programmed in the crossbar unit */ 2462 #define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the 2463 outputs are disabled by software or during a burst mode operation */ 2464 #define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on 2465 FAULTx inputs */ 2466 /** 2467 * @} 2468 */ 2469 2470 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status 2471 * @{ 2472 * @brief Constants defining the operating state of the burst mode controller 2473 */ 2474 #define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */ 2475 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */ 2476 /** 2477 * @} 2478 */ 2479 2480 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status 2481 * @{ 2482 * @brief Constants defining on which output the signal is currently applied 2483 * in push-pull mode 2484 */ 2485 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */ 2486 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */ 2487 /** 2488 * @} 2489 */ 2490 2491 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status 2492 * @{ 2493 * @brief Constants defining on which output the signal was applied, in 2494 * push-pull mode balanced fault mode or delayed idle mode, when the 2495 * protection was triggered 2496 */ 2497 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */ 2498 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */ 2499 /** 2500 * @} 2501 */ 2502 2503 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable 2504 * @{ 2505 */ 2506 #define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ 2507 #define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */ 2508 #define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */ 2509 #define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */ 2510 #define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */ 2511 #define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */ 2512 #define HRTIM_IT_FLT6 HRTIM_IER_FLT6 /*!< Fault 6 interrupt enable */ 2513 #define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */ 2514 #define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /*!< DLL ready interrupt enable */ 2515 #define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */ 2516 /** 2517 * @} 2518 */ 2519 2520 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable 2521 * @{ 2522 */ 2523 #define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */ 2524 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */ 2525 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */ 2526 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */ 2527 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */ 2528 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */ 2529 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */ 2530 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */ 2531 /** 2532 * @} 2533 */ 2534 2535 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable 2536 * @{ 2537 */ 2538 #define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ 2539 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */ 2540 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */ 2541 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */ 2542 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */ 2543 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */ 2544 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */ 2545 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */ 2546 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */ 2547 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */ 2548 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */ 2549 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */ 2550 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */ 2551 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */ 2552 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */ 2553 /** 2554 * @} 2555 */ 2556 2557 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag 2558 * @{ 2559 */ 2560 #define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */ 2561 #define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */ 2562 #define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */ 2563 #define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */ 2564 #define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */ 2565 #define HRTIM_FLAG_FLT6 HRTIM_ISR_FLT6 /*!< Fault 6 interrupt flag */ 2566 #define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */ 2567 #define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */ 2568 #define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */ 2569 /** 2570 * @} 2571 */ 2572 2573 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag 2574 * @{ 2575 */ 2576 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */ 2577 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */ 2578 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */ 2579 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */ 2580 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */ 2581 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */ 2582 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */ 2583 /** 2584 * @} 2585 */ 2586 2587 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag 2588 * @{ 2589 */ 2590 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */ 2591 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */ 2592 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */ 2593 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */ 2594 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */ 2595 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */ 2596 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */ 2597 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */ 2598 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */ 2599 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */ 2600 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */ 2601 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */ 2602 #define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */ 2603 #define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */ 2604 /** 2605 * @} 2606 */ 2607 2608 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable 2609 * @{ 2610 */ 2611 #define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */ 2612 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */ 2613 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */ 2614 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */ 2615 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */ 2616 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */ 2617 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */ 2618 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */ 2619 /** 2620 * @} 2621 */ 2622 2623 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable 2624 * @{ 2625 */ 2626 #define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */ 2627 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */ 2628 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */ 2629 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */ 2630 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */ 2631 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */ 2632 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */ 2633 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */ 2634 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */ 2635 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */ 2636 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */ 2637 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */ 2638 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */ 2639 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */ 2640 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */ 2641 /** 2642 * @} 2643 */ 2644 2645 /** 2646 * @} 2647 */ 2648 2649 /* Private Constants --------------------------------------------------------*/ 2650 /** @addtogroup HRTIM_Private_Constants 2651 * @{ 2652 */ 2653 #define HRTIM_CAPTUREFTRIGGER_NONE 0x00000000U /*!< 32bit value Capture trigger is disabled */ 2654 #define HRTIM_CAPTUREFTRIGGER_TF1_SET (HRTIM_CPT1CR_TF1SET) /*!< 32bit value Capture is triggered by TF1 output inactive to active transition */ 2655 #define HRTIM_CAPTUREFTRIGGER_TF1_RESET (HRTIM_CPT1CR_TF1RST) /*!< 32bit value Capture is triggered by TF1 output active to inactive transition */ 2656 #define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1 (HRTIM_CPT1CR_TIMFCMP1) /*!< 32bit value Timer F Compare 1 triggers Capture */ 2657 #define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2 (HRTIM_CPT1CR_TIMFCMP2) /*!< 32bit value Timer F Compare 2 triggers Capture */ 2658 /** 2659 * @} 2660 */ 2661 2662 /* Private macros --------------------------------------------------------*/ 2663 /** @addtogroup HRTIM_Private_Macros 2664 * @{ 2665 */ 2666 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ 2667 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ 2668 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ 2669 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ 2670 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ 2671 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ 2672 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E) || \ 2673 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F)) 2674 2675 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ 2676 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ 2677 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ 2678 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ 2679 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ 2680 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E) || \ 2681 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F)) 2682 2683 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFF80FFFFU) == 0x00000000U) 2684 2685 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ 2686 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ 2687 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ 2688 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ 2689 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) 2690 2691 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ 2692 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ 2693 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) 2694 2695 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFF000U) == 0x00000000U) 2696 2697 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ 2698 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 2699 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ 2700 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ 2701 || \ 2702 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 2703 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ 2704 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ 2705 || \ 2706 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 2707 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ 2708 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ 2709 || \ 2710 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 2711 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ 2712 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ 2713 || \ 2714 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 2715 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ 2716 ((OUTPUT) == HRTIM_OUTPUT_TE2))) \ 2717 || \ 2718 (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \ 2719 (((OUTPUT) == HRTIM_OUTPUT_TF1) || \ 2720 ((OUTPUT) == HRTIM_OUTPUT_TF2)))) 2721 2722 #define IS_HRTIM_TIMEEVENT(EVENT)\ 2723 (((EVENT) == HRTIM_EVENTCOUNTER_A) || \ 2724 ((EVENT) == HRTIM_EVENTCOUNTER_B)) 2725 2726 #define IS_HRTIM_TIMEEVENT_RESETMODE(EVENT)\ 2727 (((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL) || \ 2728 ((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL)) 2729 2730 #define IS_HRTIM_TIMSYNCUPDATE(EVENT)\ 2731 (((EVENT) == HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL) || \ 2732 ((EVENT) == HRTIM_TIMERESYNC_UPDATE_CONDITIONAL)) 2733 2734 #define IS_HRTIM_TIMEEVENT_COUNTER(COUNTER)\ 2735 ((((COUNTER) > (uint32_t)0x00U) && ((COUNTER) <= (uint32_t)0x3FU)) ||\ 2736 ((COUNTER) == (uint32_t)0x00U)) 2737 2738 #define IS_HRTIM_TIMEEVENT_SOURCE(SOURCE)\ 2739 (((SOURCE) >= (uint32_t)0x00U) && ((SOURCE) <= (uint32_t)0x9U)) 2740 2741 #define IS_HRTIM_EVENT(EVENT)\ 2742 (((EVENT) == HRTIM_EVENT_NONE)|| \ 2743 ((EVENT) == HRTIM_EVENT_1) || \ 2744 ((EVENT) == HRTIM_EVENT_2) || \ 2745 ((EVENT) == HRTIM_EVENT_3) || \ 2746 ((EVENT) == HRTIM_EVENT_4) || \ 2747 ((EVENT) == HRTIM_EVENT_5) || \ 2748 ((EVENT) == HRTIM_EVENT_6) || \ 2749 ((EVENT) == HRTIM_EVENT_7) || \ 2750 ((EVENT) == HRTIM_EVENT_8) || \ 2751 ((EVENT) == HRTIM_EVENT_9) || \ 2752 ((EVENT) == HRTIM_EVENT_10)) 2753 2754 #define IS_HRTIM_FAULT(FAULT)\ 2755 (((FAULT) == HRTIM_FAULT_1) || \ 2756 ((FAULT) == HRTIM_FAULT_2) || \ 2757 ((FAULT) == HRTIM_FAULT_3) || \ 2758 ((FAULT) == HRTIM_FAULT_4) || \ 2759 ((FAULT) == HRTIM_FAULT_5) || \ 2760 ((FAULT) == HRTIM_FAULT_6)) 2761 2762 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ 2763 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \ 2764 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \ 2765 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \ 2766 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \ 2767 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \ 2768 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ 2769 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ 2770 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) 2771 2772 #define IS_HRTIM_MODE(MODE)\ 2773 (((MODE) == HRTIM_MODE_CONTINUOUS) || \ 2774 ((MODE) == HRTIM_MODE_SINGLESHOT) || \ 2775 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) 2776 2777 #define IS_HRTIM_MODE_ONEPULSE(MODE)\ 2778 (((MODE) == HRTIM_MODE_SINGLESHOT) || \ 2779 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) 2780 2781 2782 #define IS_HRTIM_HALFMODE(HALFMODE)\ 2783 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ 2784 ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) 2785 2786 #define IS_HRTIM_INTERLEAVEDMODE(INTLVDMODE)\ 2787 (((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ 2788 ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DUAL) || \ 2789 ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ 2790 ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_TRIPLE) || \ 2791 ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \ 2792 ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_QUAD)) 2793 2794 #define IS_HRTIM_SYNCSTART(SYNCSTART)\ 2795 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ 2796 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) 2797 2798 #define IS_HRTIM_SYNCRESET(SYNCRESET)\ 2799 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ 2800 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) 2801 2802 #define IS_HRTIM_DACSYNC(DACSYNC)\ 2803 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ 2804 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ 2805 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ 2806 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) 2807 2808 #define IS_HRTIM_PRELOAD(PRELOAD)\ 2809 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ 2810 ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) 2811 2812 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ 2813 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ 2814 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ 2815 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) 2816 2817 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ 2818 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ 2819 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ 2820 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ 2821 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ 2822 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ 2823 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ 2824 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ 2825 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ 2826 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) 2827 2828 #define IS_HRTIM_TIMERBURSTMODE(MODE) \ 2829 (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ 2830 ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) 2831 #define IS_HRTIM_TIMERUPDOWNMODE(MODE) \ 2832 (((MODE) == HRTIM_TIMERUPDOWNMODE_UP) || \ 2833 ((MODE) == HRTIM_TIMERUPDOWNMODE_UPDOWN)) 2834 2835 #define IS_HRTIM_TIMERTRGHLFMODE(MODE) \ 2836 (((MODE) == HRTIM_TIMERTRIGHALF_DISABLED) || \ 2837 ((MODE) == HRTIM_TIMERTRIGHALF_ENABLED)) 2838 2839 #define IS_HRTIM_TIMERGTCMP3(MODE) \ 2840 (((MODE) == HRTIM_TIMERGTCMP3_EQUAL) || \ 2841 ((MODE) == HRTIM_TIMERGTCMP3_GREATER)) 2842 2843 #define IS_HRTIM_TIMERGTCMP1(MODE) \ 2844 (((MODE) == HRTIM_TIMERGTCMP1_EQUAL) || \ 2845 ((MODE) == HRTIM_TIMERGTCMP1_GREATER)) 2846 2847 #define IS_HRTIM_DUALDAC_RESET(DUALCHANNELDAC) \ 2848 (((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_COUNTER) || \ 2849 ((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_OUT1SET)) 2850 2851 #define IS_HRTIM_DUALDAC_STEP(DUALCHANNELDAC) \ 2852 (((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_CMP2) || \ 2853 ((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_OUT1RST)) 2854 2855 #define IS_HRTIM_DUALDAC_ENABLE(DUALCHANNELDAC) \ 2856 (((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_DISABLED) || \ 2857 ((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_ENABLED )) 2858 2859 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ 2860 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ 2861 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) 2862 2863 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ 2864 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ 2865 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) 2866 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFC0U) == 0x00000000U) 2867 2868 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ 2869 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ 2870 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) 2871 2872 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ 2873 (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ 2874 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)) 2875 2876 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ 2877 ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ 2878 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ 2879 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ 2880 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ 2881 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ 2882 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ 2883 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ 2884 || \ 2885 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ 2886 (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ 2887 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) 2888 2889 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE06FFFFU) == 0x00000000U) 2890 2891 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x00000000U) == 0x00000000U) 2892 2893 2894 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ 2895 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ 2896 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) 2897 2898 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ 2899 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2900 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2901 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2902 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) 2903 2904 /* Auto delayed mode is only available for compare units 2 and 4U */ 2905 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ 2906 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ 2907 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2908 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2909 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2910 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ 2911 || \ 2912 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ 2913 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 2914 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 2915 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 2916 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) 2917 2918 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ 2919 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ 2920 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) 2921 2922 #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) 2923 2924 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ 2925 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ 2926 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ 2927 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ 2928 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ 2929 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ 2930 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ 2931 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ 2932 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ 2933 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ 2934 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ 2935 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ 2936 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ 2937 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1) || \ 2938 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2) || \ 2939 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2) || \ 2940 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3) || \ 2941 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1) || \ 2942 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2) || \ 2943 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3) || \ 2944 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4) || \ 2945 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4) || \ 2946 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ 2947 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ 2948 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ 2949 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ 2950 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ 2951 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ 2952 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ 2953 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ 2954 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ 2955 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ 2956 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) 2957 2958 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ 2959 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ 2960 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ 2961 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ 2962 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ 2963 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ 2964 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ 2965 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ 2966 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ 2967 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ 2968 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ 2969 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ 2970 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ 2971 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1) || \ 2972 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2) || \ 2973 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2) || \ 2974 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3) || \ 2975 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1) || \ 2976 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2) || \ 2977 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3) || \ 2978 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4) || \ 2979 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4) || \ 2980 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ 2981 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ 2982 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ 2983 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ 2984 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ 2985 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ 2986 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ 2987 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ 2988 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ 2989 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ 2990 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) 2991 2992 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ 2993 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ 2994 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) 2995 2996 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ 2997 (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ 2998 ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) 2999 3000 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ 3001 (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ 3002 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ 3003 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ 3004 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) 3005 3006 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ 3007 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ 3008 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) 3009 3010 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ 3011 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ 3012 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) 3013 3014 #define IS_HRTIM_OUTPUTBALANCEDIDLE(OUTPUTBIAR)\ 3015 (((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_DISABLED) || \ 3016 ((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_ENABLED)) 3017 3018 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ 3019 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ 3020 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ 3021 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ 3022 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ 3023 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \ 3024 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \ 3025 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \ 3026 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \ 3027 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \ 3028 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \ 3029 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \ 3030 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ 3031 || \ 3032 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 3033 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 3034 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 3035 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 3036 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 3037 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 3038 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 3039 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 3040 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 3041 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 3042 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 3043 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 3044 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 3045 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 3046 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 3047 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 3048 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 3049 || \ 3050 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 3051 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 3052 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 3053 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 3054 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 3055 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 3056 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 3057 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 3058 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 3059 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 3060 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 3061 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 3062 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 3063 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 3064 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 3065 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 3066 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 3067 || \ 3068 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 3069 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 3070 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 3071 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 3072 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 3073 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 3074 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 3075 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 3076 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 3077 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 3078 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 3079 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 3080 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 3081 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 3082 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 3083 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 3084 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 3085 || \ 3086 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 3087 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 3088 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 3089 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 3090 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 3091 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 3092 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 3093 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 3094 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 3095 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 3096 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 3097 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 3098 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 3099 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 3100 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 3101 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 3102 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 3103 || \ 3104 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 3105 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 3106 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 3107 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 3108 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 3109 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 3110 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 3111 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 3112 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 3113 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 3114 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 3115 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 3116 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 3117 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 3118 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 3119 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 3120 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \ 3121 || \ 3122 (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \ 3123 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 3124 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 3125 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 3126 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 3127 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 3128 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 3129 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 3130 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 3131 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 3132 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 3133 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 3134 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 3135 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 3136 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 3137 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 3138 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 3139 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 3140 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 3141 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 3142 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))) 3143 3144 #define IS_HRTIM_TIMER_CAPTUREFTRIGGER(TIMER, CAPTUREFTRIGGER) \ 3145 ( ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_NONE) || \ 3146 ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_SET) || \ 3147 ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_RESET) || \ 3148 ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1) || \ 3149 ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2)) 3150 3151 #define IS_HRTIM_TIMEVENTFILTER(TIMER,TIMEVENTFILTER)\ 3152 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_NONE) || \ 3153 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP1) || \ 3154 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP2) || \ 3155 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP3) || \ 3156 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP4) || \ 3157 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP2) || \ 3158 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP3) || \ 3159 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGTIM) \ 3160 || \ 3161 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 3162 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1) || \ 3163 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4) || \ 3164 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2) || \ 3165 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1) || \ 3166 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4) || \ 3167 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1) || \ 3168 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1) || \ 3169 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2))) \ 3170 || \ 3171 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 3172 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1) || \ 3173 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4) || \ 3174 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2) || \ 3175 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1) || \ 3176 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2) || \ 3177 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2) || \ 3178 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2) || \ 3179 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1))) \ 3180 || \ 3181 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 3182 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2) || \ 3183 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1) || \ 3184 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4) || \ 3185 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1) || \ 3186 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1) || \ 3187 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4) || \ 3188 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2) || \ 3189 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4))) \ 3190 || \ 3191 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 3192 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1) || \ 3193 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2) || \ 3194 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1) || \ 3195 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2) || \ 3196 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2) || \ 3197 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1) || \ 3198 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4) || \ 3199 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4))) \ 3200 || \ 3201 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 3202 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2) || \ 3203 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1) || \ 3204 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1) || \ 3205 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4) || \ 3206 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2) || \ 3207 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1) || \ 3208 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4) || \ 3209 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2))) \ 3210 || \ 3211 (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \ 3212 (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4) || \ 3213 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2) || \ 3214 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4) || \ 3215 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2) || \ 3216 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4) || \ 3217 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1) || \ 3218 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4) || \ 3219 ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2)))) 3220 3221 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ 3222 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ 3223 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) 3224 3225 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ 3226 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \ 3227 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \ 3228 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \ 3229 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ 3230 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ 3231 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ 3232 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ 3233 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) 3234 3235 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ 3236 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ 3237 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) 3238 3239 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ 3240 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ 3241 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) 3242 3243 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ 3244 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ 3245 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) 3246 3247 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ 3248 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ 3249 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) 3250 3251 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ 3252 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ 3253 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) 3254 3255 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ 3256 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ 3257 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) 3258 3259 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ 3260 (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ 3261 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ 3262 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ 3263 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ 3264 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ 3265 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ 3266 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ 3267 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ 3268 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ 3269 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ 3270 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ 3271 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ 3272 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ 3273 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ 3274 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ 3275 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) 3276 3277 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ 3278 (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ 3279 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ 3280 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ 3281 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ 3282 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ 3283 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ 3284 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ 3285 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) 3286 3287 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ 3288 (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ 3289 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ 3290 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ 3291 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ 3292 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ 3293 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ 3294 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ 3295 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ 3296 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ 3297 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ 3298 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ 3299 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ 3300 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ 3301 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ 3302 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ 3303 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) 3304 3305 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ 3306 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ 3307 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ 3308 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) 3309 3310 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ 3311 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ 3312 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ 3313 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ 3314 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) 3315 3316 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ 3317 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ 3318 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ 3319 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) 3320 3321 #define IS_HRTIM_EVENTSRC(EVENT, EVENTSRC) \ 3322 ((((EVENT) == HRTIM_EVENT_1) && \ 3323 (((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \ 3324 ((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \ 3325 ((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \ 3326 ((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ))) \ 3327 || \ 3328 (((EVENT) == HRTIM_EVENT_2) && \ 3329 (((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \ 3330 ((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \ 3331 ((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \ 3332 ((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ))) \ 3333 || \ 3334 (((EVENT) == HRTIM_EVENT_3) && \ 3335 (((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \ 3336 ((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \ 3337 ((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \ 3338 ((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ))) \ 3339 || \ 3340 (((EVENT) == HRTIM_EVENT_4) && \ 3341 (((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \ 3342 ((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \ 3343 ((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \ 3344 ((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ))) \ 3345 || \ 3346 (((EVENT) == HRTIM_EVENT_5) && \ 3347 (((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \ 3348 ((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \ 3349 ((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \ 3350 ((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ))) \ 3351 || \ 3352 (((EVENT) == HRTIM_EVENT_6) && \ 3353 (((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \ 3354 ((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \ 3355 ((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \ 3356 ((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ))) \ 3357 || \ 3358 (((EVENT) == HRTIM_EVENT_7) && \ 3359 (((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \ 3360 ((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \ 3361 ((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \ 3362 ((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ))) \ 3363 || \ 3364 (((EVENT) == HRTIM_EVENT_8) && \ 3365 (((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \ 3366 ((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \ 3367 ((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \ 3368 ((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ))) \ 3369 || \ 3370 (((EVENT) == HRTIM_EVENT_9) && \ 3371 (((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \ 3372 ((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \ 3373 ((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \ 3374 ((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ))) \ 3375 || \ 3376 (((EVENT) == HRTIM_EVENT_10) && \ 3377 (((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \ 3378 ((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \ 3379 ((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \ 3380 ((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1)))) 3381 3382 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ 3383 ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ 3384 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ 3385 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ 3386 || \ 3387 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ 3388 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ 3389 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) 3390 3391 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ 3392 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ 3393 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ 3394 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ 3395 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) 3396 3397 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ 3398 (((((EVENT) == HRTIM_EVENT_1) || \ 3399 ((EVENT) == HRTIM_EVENT_2) || \ 3400 ((EVENT) == HRTIM_EVENT_3) || \ 3401 ((EVENT) == HRTIM_EVENT_4) || \ 3402 ((EVENT) == HRTIM_EVENT_5)) && \ 3403 (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ 3404 ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ 3405 || \ 3406 (((EVENT) == HRTIM_EVENT_6) || \ 3407 ((EVENT) == HRTIM_EVENT_7) || \ 3408 ((EVENT) == HRTIM_EVENT_8) || \ 3409 ((EVENT) == HRTIM_EVENT_9) || \ 3410 ((EVENT) == HRTIM_EVENT_10))) 3411 3412 3413 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ 3414 ((((EVENT) == HRTIM_EVENT_1) || \ 3415 ((EVENT) == HRTIM_EVENT_2) || \ 3416 ((EVENT) == HRTIM_EVENT_3) || \ 3417 ((EVENT) == HRTIM_EVENT_4) || \ 3418 ((EVENT) == HRTIM_EVENT_5)) \ 3419 || \ 3420 ((((EVENT) == HRTIM_EVENT_6) || \ 3421 ((EVENT) == HRTIM_EVENT_7) || \ 3422 ((EVENT) == HRTIM_EVENT_8) || \ 3423 ((EVENT) == HRTIM_EVENT_9) || \ 3424 ((EVENT) == HRTIM_EVENT_10)) && \ 3425 (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ 3426 ((FILTER) == HRTIM_EVENTFILTER_1) || \ 3427 ((FILTER) == HRTIM_EVENTFILTER_2) || \ 3428 ((FILTER) == HRTIM_EVENTFILTER_3) || \ 3429 ((FILTER) == HRTIM_EVENTFILTER_4) || \ 3430 ((FILTER) == HRTIM_EVENTFILTER_5) || \ 3431 ((FILTER) == HRTIM_EVENTFILTER_6) || \ 3432 ((FILTER) == HRTIM_EVENTFILTER_7) || \ 3433 ((FILTER) == HRTIM_EVENTFILTER_8) || \ 3434 ((FILTER) == HRTIM_EVENTFILTER_9) || \ 3435 ((FILTER) == HRTIM_EVENTFILTER_10) || \ 3436 ((FILTER) == HRTIM_EVENTFILTER_11) || \ 3437 ((FILTER) == HRTIM_EVENTFILTER_12) || \ 3438 ((FILTER) == HRTIM_EVENTFILTER_13) || \ 3439 ((FILTER) == HRTIM_EVENTFILTER_14) || \ 3440 ((FILTER) == HRTIM_EVENTFILTER_15)))) 3441 3442 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ 3443 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ 3444 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ 3445 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ 3446 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) 3447 3448 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ 3449 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ 3450 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL) || \ 3451 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_EEVINPUT)) 3452 3453 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ 3454 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ 3455 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) 3456 3457 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ 3458 (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ 3459 ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) 3460 3461 #define IS_HRTIM_FAULTBLANKNGMODE(FAULTBLANKINGMODE)\ 3462 (((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_RSTALIGNED) || \ 3463 ((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_MOVING)) 3464 3465 #define IS_HRTIM_FAULTBLANKING(FAULTBLANKINGCTL)\ 3466 (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_DISABLED) || \ 3467 ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_ENABLED)) 3468 3469 #define IS_HRTIM_FAULTCOUNTERRST(HRTIM_FAULTCOUNTERRST)\ 3470 (((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_UNCONDITIONAL) || \ 3471 ((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_CONDITIONAL)) 3472 3473 #define IS_HRTIM_FAULTBLANKINGCTL(FAULTBLANKINGCTL)\ 3474 (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_DISABLED) || \ 3475 ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_ENABLED)) 3476 3477 #define IS_HRTIM_FAULTCOUNTER(FAULTCOUNTER)\ 3478 (((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_NONE) || \ 3479 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_1) || \ 3480 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_2) || \ 3481 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_3) || \ 3482 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_4) || \ 3483 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_5) || \ 3484 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_6) || \ 3485 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_7) || \ 3486 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_8) || \ 3487 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_9) || \ 3488 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_10) || \ 3489 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_11) || \ 3490 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_12) || \ 3491 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_13) || \ 3492 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_14) || \ 3493 ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_15)) 3494 3495 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ 3496 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ 3497 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ 3498 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ 3499 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ 3500 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ 3501 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ 3502 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ 3503 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ 3504 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ 3505 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ 3506 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ 3507 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ 3508 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ 3509 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ 3510 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ 3511 ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) 3512 3513 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ 3514 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ 3515 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) 3516 3517 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ 3518 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ 3519 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ 3520 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ 3521 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) 3522 3523 #define IS_HRTIM_BURSTMODE(BURSTMODE)\ 3524 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ 3525 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) 3526 3527 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ 3528 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ 3529 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ 3530 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ 3531 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ 3532 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ 3533 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ 3534 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_F) || \ 3535 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ 3536 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ 3537 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ 3538 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) 3539 3540 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ 3541 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ 3542 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ 3543 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ 3544 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ 3545 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ 3546 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ 3547 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ 3548 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ 3549 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ 3550 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ 3551 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ 3552 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ 3553 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ 3554 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ 3555 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ 3556 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) 3557 3558 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ 3559 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ 3560 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) 3561 3562 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ 3563 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ 3564 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ 3565 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ 3566 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ 3567 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ 3568 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ 3569 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ 3570 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ 3571 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ 3572 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ 3573 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ 3574 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ 3575 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ 3576 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ 3577 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ 3578 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ 3579 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ 3580 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ 3581 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_RESET) || \ 3582 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ 3583 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ 3584 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION) || \ 3585 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ 3586 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_CMP1) || \ 3587 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ 3588 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ 3589 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ 3590 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ 3591 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ 3592 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ 3593 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ 3594 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) 3595 3596 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ 3597 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ 3598 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ 3599 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ 3600 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ 3601 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ 3602 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E) || \ 3603 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_F)) 3604 3605 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ 3606 (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ 3607 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \ 3608 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_1) || \ 3609 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_2) || \ 3610 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_3)) 3611 3612 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ 3613 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ 3614 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ 3615 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ 3616 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ 3617 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ 3618 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \ 3619 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U))) 3620 3621 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ 3622 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ 3623 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) 3624 3625 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFF80U) == 0x00000000U) 3626 3627 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFF80FFU) == 0x00000000U) 3628 3629 #define IS_HRTIM_TIMERSWAP(TIMERSWAP) (((TIMERSWAP) & 0xFFC0FFFFU) == 0x00000000U) 3630 3631 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFF80U) == 0x00000000U) 3632 3633 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U) 3634 3635 3636 #define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U) 3637 3638 3639 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U) 3640 3641 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U) 3642 /** 3643 * @} 3644 */ 3645 3646 /* Exported macros -----------------------------------------------------------*/ 3647 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros 3648 * @{ 3649 */ 3650 3651 /** 3652 * @brief configures the actual direction of the counter to UP counting mode 3653 * @param __HANDLE__ : HRTIM handle. 3654 * @param __TIMER__ : Timer index 3655 * This parameter can be a combination of the following values: 3656 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A 3657 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B 3658 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C 3659 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D 3660 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E 3661 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F 3662 * @retval none 3663 */ 3664 #define __HAL_HRTIM_COUNTER_MODE_UP(__HANDLE__, __TIMERS__)\ 3665 do {\ 3666 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ 3667 {\ 3668 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3669 }\ 3670 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 3671 {\ 3672 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3673 }\ 3674 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ 3675 {\ 3676 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3677 }\ 3678 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ 3679 {\ 3680 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3681 }\ 3682 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ 3683 {\ 3684 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3685 }\ 3686 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ 3687 {\ 3688 CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3689 }\ 3690 } while(0U) 3691 3692 /** 3693 * @brief configures the actual direction of the counter to UP-DOWN counting mode 3694 * @param __HANDLE__ : HRTIM handle. 3695 * @param __TIMER__ : Timer index 3696 * This parameter can be a combination of the following values: 3697 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A 3698 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B 3699 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C 3700 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D 3701 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E 3702 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F 3703 * @retval none 3704 */ 3705 #define __HAL_HRTIM_COUNTER_MODE_UPDOWN(__HANDLE__, __TIMERS__)\ 3706 do {\ 3707 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ 3708 {\ 3709 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3710 }\ 3711 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 3712 {\ 3713 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3714 }\ 3715 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ 3716 {\ 3717 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3718 }\ 3719 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ 3720 {\ 3721 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3722 }\ 3723 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ 3724 {\ 3725 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3726 }\ 3727 if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ 3728 {\ 3729 SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \ 3730 }\ 3731 } while(0U) 3732 3733 /** 3734 * @brief swap the output of the timer 3735 * HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2, 3736 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1 3737 * @param __HANDLE__ : HRTIM handle. 3738 * @param __TIMER__ : Timer index 3739 * This parameter can be a combination of the following values: 3740 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A 3741 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B 3742 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C 3743 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D 3744 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E 3745 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F 3746 * @retval none 3747 */ 3748 #define __HAL_HRTIM_TIMER_OUTPUT_SWAP(__HANDLE__, __TIMERS__)\ 3749 do {\ 3750 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ 3751 {\ 3752 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \ 3753 }\ 3754 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ 3755 {\ 3756 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \ 3757 }\ 3758 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ 3759 {\ 3760 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \ 3761 }\ 3762 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ 3763 {\ 3764 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \ 3765 }\ 3766 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ 3767 {\ 3768 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \ 3769 }\ 3770 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\ 3771 {\ 3772 SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \ 3773 }\ 3774 } while(0U) 3775 3776 /** 3777 * @brief Un-swap the output of the timer 3778 * HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1, 3779 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2 3780 * @param __HANDLE__ : HRTIM handle. 3781 * @param __TIMER__ : Timer index 3782 * This parameter can be a combination of the following values: 3783 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A 3784 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B 3785 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C 3786 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D 3787 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E 3788 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F 3789 * @retval none 3790 3791 */ 3792 #define __HAL_HRTIM_TIMER_OUTPUT_NOSWAP(__HANDLE__, __TIMERS__)\ 3793 do {\ 3794 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ 3795 {\ 3796 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \ 3797 }\ 3798 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ 3799 {\ 3800 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \ 3801 }\ 3802 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ 3803 {\ 3804 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \ 3805 }\ 3806 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ 3807 {\ 3808 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \ 3809 }\ 3810 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ 3811 {\ 3812 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \ 3813 }\ 3814 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\ 3815 {\ 3816 CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \ 3817 }\ 3818 } while(0U) 3819 3820 /** @brief Reset HRTIM handle state 3821 * @param __HANDLE__ HRTIM handle. 3822 * @retval None 3823 */ 3824 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 3825 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ 3826 (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ 3827 (__HANDLE__)->MspInitCallback = NULL; \ 3828 (__HANDLE__)->MspDeInitCallback = NULL; \ 3829 } while(0) 3830 #else 3831 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) 3832 #endif 3833 3834 /** @brief Enables or disables the timer counter(s) 3835 * @param __HANDLE__ specifies the HRTIM Handle. 3836 * @param __TIMERS__ timers to enable/disable 3837 * This parameter can be any combinations of the following values: 3838 * @arg HRTIM_TIMERID_MASTER: Master timer identifier 3839 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier 3840 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier 3841 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier 3842 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier 3843 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier 3844 * @arg HRTIM_TIMERID_TIMER_F: Timer F identifier 3845 * @retval None 3846 */ 3847 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__)) 3848 3849 /* The counter of a timing unit is disabled only if all the timer outputs */ 3850 /* are disabled and no capture is configured */ 3851 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN) 3852 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN) 3853 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN) 3854 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN) 3855 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN) 3856 #define HRTIM_TFOEN_MASK (HRTIM_OENR_TF2OEN | HRTIM_OENR_TF1OEN) 3857 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ 3858 do {\ 3859 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ 3860 {\ 3861 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ 3862 }\ 3863 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ 3864 {\ 3865 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ 3866 {\ 3867 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ 3868 }\ 3869 }\ 3870 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ 3871 {\ 3872 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ 3873 {\ 3874 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ 3875 }\ 3876 }\ 3877 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ 3878 {\ 3879 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ 3880 {\ 3881 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ 3882 }\ 3883 }\ 3884 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ 3885 {\ 3886 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ 3887 {\ 3888 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ 3889 }\ 3890 }\ 3891 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ 3892 {\ 3893 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ 3894 {\ 3895 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ 3896 }\ 3897 }\ 3898 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\ 3899 {\ 3900 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TFOEN_MASK) == (uint32_t)RESET)\ 3901 {\ 3902 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_F);\ 3903 }\ 3904 }\ 3905 } while(0U) 3906 3907 /** @brief Enables the External Event counter 3908 * @param __HANDLE__ specifies the HRTIM Handle. 3909 * @param __TIMERS__ timers to enable/disable 3910 * This parameter can be one of the following values: 3911 * @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier 3912 * @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier 3913 * @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier 3914 * @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier 3915 * @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier 3916 * @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier 3917 * @param Event external event Counter A or B for which timer event must be enabled 3918 * This parameter can be one of the following values: 3919 * @arg HRTIM_EVENTCOUNTER_A 3920 * @arg HRTIM_EVENTCOUNTER_B 3921 * @retval None 3922 */ 3923 #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_ENABLE(__HANDLE__, __TIMER__, __EVENT__)\ 3924 do {\ 3925 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ 3926 {\ 3927 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3928 {\ 3929 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3930 }\ 3931 if (((__EVENT__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 3932 {\ 3933 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3934 }\ 3935 }\ 3936 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 3937 {\ 3938 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3939 {\ 3940 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3941 }\ 3942 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 3943 {\ 3944 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3945 }\ 3946 }\ 3947 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ 3948 {\ 3949 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3950 {\ 3951 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3952 }\ 3953 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 3954 {\ 3955 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3956 }\ 3957 }\ 3958 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ 3959 {\ 3960 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3961 {\ 3962 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3963 }\ 3964 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 3965 {\ 3966 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3967 }\ 3968 }\ 3969 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ 3970 {\ 3971 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3972 {\ 3973 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3974 }\ 3975 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 3976 {\ 3977 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3978 }\ 3979 }\ 3980 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ 3981 {\ 3982 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 3983 {\ 3984 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACE;\ 3985 }\ 3986 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 3987 {\ 3988 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\ 3989 }\ 3990 }\ 3991 } while(0U) 3992 3993 /** @brief Disables the External Event counter 3994 * @param __HANDLE__ specifies the HRTIM Handle. 3995 * @param __TIMERS__ timers to enable/disable 3996 * This parameter can be one of the following values: 3997 * @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier 3998 * @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier 3999 * @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier 4000 * @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier 4001 * @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier 4002 * @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier 4003 * @param Event external event A or B for which timer event must be disabled 4004 * This parameter can be one of the following values: 4005 * @arg HRTIM_EVENTCOUNTER_A 4006 * @arg HRTIM_EVENTCOUNTER_B 4007 * @retval None 4008 */ 4009 #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_DISABLE(__HANDLE__, __TIMER__, __EVENT__)\ 4010 do {\ 4011 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ 4012 {\ 4013 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4014 {\ 4015 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4016 }\ 4017 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4018 {\ 4019 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4020 }\ 4021 }\ 4022 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 4023 {\ 4024 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4025 {\ 4026 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4027 }\ 4028 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4029 {\ 4030 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4031 }\ 4032 }\ 4033 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ 4034 {\ 4035 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4036 {\ 4037 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4038 }\ 4039 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4040 {\ 4041 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4042 }\ 4043 }\ 4044 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ 4045 {\ 4046 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4047 {\ 4048 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4049 }\ 4050 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4051 {\ 4052 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4053 }\ 4054 }\ 4055 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ 4056 {\ 4057 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4058 {\ 4059 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4060 }\ 4061 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4062 {\ 4063 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4064 }\ 4065 }\ 4066 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ 4067 {\ 4068 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4069 {\ 4070 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\ 4071 }\ 4072 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4073 {\ 4074 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\ 4075 }\ 4076 }\ 4077 } while(0U) 4078 4079 /** @brief Resets the External Event counter 4080 * @param __HANDLE__ specifies the HRTIM Handle. 4081 * @param __TIMERS__ timers to enable/disable 4082 * This parameter can be one of the following values: 4083 * @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier 4084 * @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier 4085 * @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier 4086 * @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier 4087 * @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier 4088 * @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier 4089 * @param Event external event A or B for which timer event must be reset 4090 * This parameter can be one of the following values: 4091 * @arg HRTIM_EVENTCOUNTER_A 4092 * @arg HRTIM_EVENTCOUNTER_B 4093 * @retval None 4094 */ 4095 #define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_RESET(__HANDLE__, __TIMER__, __EVENT__)\ 4096 do {\ 4097 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\ 4098 {\ 4099 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4100 {\ 4101 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4102 }\ 4103 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4104 {\ 4105 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4106 }\ 4107 }\ 4108 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\ 4109 {\ 4110 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4111 {\ 4112 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4113 }\ 4114 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4115 {\ 4116 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4117 }\ 4118 }\ 4119 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\ 4120 {\ 4121 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4122 {\ 4123 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4124 }\ 4125 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4126 {\ 4127 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4128 }\ 4129 }\ 4130 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\ 4131 {\ 4132 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4133 {\ 4134 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4135 }\ 4136 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4137 {\ 4138 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4139 }\ 4140 }\ 4141 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\ 4142 {\ 4143 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4144 {\ 4145 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4146 }\ 4147 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4148 {\ 4149 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4150 }\ 4151 }\ 4152 if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\ 4153 {\ 4154 if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\ 4155 {\ 4156 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\ 4157 }\ 4158 if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\ 4159 {\ 4160 ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\ 4161 }\ 4162 }\ 4163 } while(0U) 4164 4165 4166 /** @brief Enables or disables the specified HRTIM common interrupts. 4167 * @param __HANDLE__ specifies the HRTIM Handle. 4168 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 4169 * This parameter can be one of the following values: 4170 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable 4171 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable 4172 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable 4173 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable 4174 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable 4175 * @arg HRTIM_IT_FLT6: Fault 6 interrupt enable 4176 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable 4177 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable 4178 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable 4179 * @retval None 4180 */ 4181 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__)) 4182 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__)) 4183 4184 /** @brief Enables or disables the specified HRTIM Master timer interrupts. 4185 * @param __HANDLE__ specifies the HRTIM Handle. 4186 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 4187 * This parameter can be one of the following values: 4188 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 4189 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 4190 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 4191 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 4192 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 4193 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 4194 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 4195 * @retval None 4196 */ 4197 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ 4198 |= (__INTERRUPT__)) 4199 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \ 4200 &= ~(__INTERRUPT__)) 4201 4202 /** @brief Enables or disables the specified HRTIM Timerx interrupts. 4203 * @param __HANDLE__ specifies the HRTIM Handle. 4204 * @param __TIMER__ specified the timing unit (Timer A to F) 4205 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 4206 * This parameter can be one of the following values: 4207 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable 4208 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable 4209 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable 4210 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable 4211 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable 4212 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable 4213 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable 4214 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable 4215 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable 4216 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable 4217 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable 4218 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable 4219 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable 4220 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable 4221 * @retval None 4222 */ 4223 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__)) 4224 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__)) 4225 4226 /** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled. 4227 * @param __HANDLE__ specifies the HRTIM Handle. 4228 * @param __INTERRUPT__ specifies the interrupt source to check. 4229 * This parameter can be one of the following values: 4230 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable 4231 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable 4232 * @arg HRTIM_IT_FLT3: Fault 3 enable 4233 * @arg HRTIM_IT_FLT4: Fault 4 enable 4234 * @arg HRTIM_IT_FLT5: Fault 5 enable 4235 * @arg HRTIM_IT_FLT6: Fault 6 enable 4236 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable 4237 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable 4238 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable 4239 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4240 */ 4241 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER &\ 4242 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 4243 4244 /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. 4245 * @param __HANDLE__ specifies the HRTIM Handle. 4246 * @param __INTERRUPT__ specifies the interrupt source to check. 4247 * This parameter can be one of the following values: 4248 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 4249 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 4250 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 4251 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 4252 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 4253 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 4254 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 4255 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4256 */ 4257 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\ 4258 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 4259 4260 /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. 4261 * @param __HANDLE__ specifies the HRTIM Handle. 4262 * @param __TIMER__ specified the timing unit (Timer A to F) 4263 * @param __INTERRUPT__ specifies the interrupt source to check. 4264 * This parameter can be one of the following values: 4265 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 4266 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 4267 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 4268 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 4269 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 4270 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 4271 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 4272 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable 4273 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable 4274 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable 4275 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable 4276 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable 4277 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable 4278 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable 4279 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable 4280 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable 4281 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable 4282 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable 4283 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable 4284 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable 4285 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable 4286 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 4287 */ 4288 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &\ 4289 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 4290 4291 /** @brief Clears the specified HRTIM common pending flag. 4292 * @param __HANDLE__ specifies the HRTIM Handle. 4293 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4294 * This parameter can be one of the following values: 4295 * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag 4296 * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag 4297 * @arg HRTIM_IT_FLT3: Fault 3 clear flag 4298 * @arg HRTIM_IT_FLT4: Fault 4 clear flag 4299 * @arg HRTIM_IT_FLT5: Fault 5 clear flag 4300 * @arg HRTIM_IT_FLT6: Fault 6 clear flag 4301 * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag 4302 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag 4303 * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag 4304 * @retval None 4305 */ 4306 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__)) 4307 4308 /** @brief Clears the specified HRTIM Master pending flag. 4309 * @param __HANDLE__ specifies the HRTIM Handle. 4310 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4311 * This parameter can be one of the following values: 4312 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag 4313 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag 4314 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag 4315 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag 4316 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag 4317 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag 4318 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag 4319 * @retval None 4320 */ 4321 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR\ 4322 = (__INTERRUPT__)) 4323 4324 /** @brief Clears the specified HRTIM Timerx pending flag. 4325 * @param __HANDLE__ specifies the HRTIM Handle. 4326 * @param __TIMER__ specified the timing unit (Timer A to F) 4327 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 4328 * This parameter can be one of the following values: 4329 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag 4330 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag 4331 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag 4332 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag 4333 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag 4334 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag 4335 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag 4336 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag 4337 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag 4338 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag 4339 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag 4340 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag 4341 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag 4342 * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag 4343 * @retval None 4344 */ 4345 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ 4346 = (__INTERRUPT__)) 4347 4348 /* DMA HANDLING */ 4349 /** @brief Enables or disables the specified HRTIM Master timer DMA requests. 4350 * @param __HANDLE__ specifies the HRTIM Handle. 4351 * @param __DMA__ specifies the DMA request to enable or disable. 4352 * This parameter can be one of the following values: 4353 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable 4354 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable 4355 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable 4356 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable 4357 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable 4358 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable 4359 * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable 4360 * @retval None 4361 */ 4362 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__)) 4363 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__)) 4364 4365 /** @brief Enables or disables the specified HRTIM Timerx DMA requests. 4366 * @param __HANDLE__ specifies the HRTIM Handle. 4367 * @param __TIMER__ specified the timing unit (Timer A to F) 4368 * @param __DMA__ specifies the DMA request to enable or disable. 4369 * This parameter can be one of the following values: 4370 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable 4371 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable 4372 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable 4373 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable 4374 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable 4375 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable 4376 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable 4377 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable 4378 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable 4379 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable 4380 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable 4381 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable 4382 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable 4383 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable 4384 * @retval None 4385 */ 4386 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) 4387 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) 4388 4389 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR &\ 4390 (__FLAG__)) == (__FLAG__)) 4391 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) 4392 4393 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR &\ 4394 (__FLAG__)) == (__FLAG__)) 4395 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) 4396 4397 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR &\ 4398 (__FLAG__)) == (__FLAG__)) 4399 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\ 4400 = (__FLAG__)) 4401 4402 /** @brief Sets the HRTIM timer Counter Register value on runtime 4403 * @param __HANDLE__ HRTIM Handle. 4404 * @param __TIMER__ HRTIM timer 4405 * This parameter can be one of the following values: 4406 * @arg 0x6 for master timer 4407 * @arg 0x0 to 0x5 for timers A to F 4408 * @param __COUNTER__ specifies the Counter Register new value. 4409 * @retval None 4410 */ 4411 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \ 4412 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\ 4413 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__))) 4414 4415 /** @brief Gets the HRTIM timer Counter Register value on runtime 4416 * @param __HANDLE__ HRTIM Handle. 4417 * @param __TIMER__ HRTIM timer 4418 * This parameter can be one of the following values: 4419 * @arg 0x6 for master timer 4420 * @arg 0x0 to 0x5 for timers A to F 4421 * @retval HRTIM timer Counter Register value 4422 */ 4423 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \ 4424 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\ 4425 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR)) 4426 4427 /** @brief Sets the HRTIM timer Period value on runtime 4428 * @param __HANDLE__ HRTIM Handle. 4429 * @param __TIMER__ HRTIM timer 4430 * This parameter can be one of the following values: 4431 * @arg 0x6 for master timer 4432 * @arg 0x0 to 0x5 for timers A to F 4433 * @param __PERIOD__ specifies the Period Register new value. 4434 * @retval None 4435 */ 4436 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \ 4437 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\ 4438 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__))) 4439 4440 /** @brief Gets the HRTIM timer Period Register value on runtime 4441 * @param __HANDLE__ HRTIM Handle. 4442 * @param __TIMER__ HRTIM timer 4443 * This parameter can be one of the following values: 4444 * @arg 0x6 for master timer 4445 * @arg 0x0 to 0x5 for timers A to F 4446 * @retval timer Period Register 4447 */ 4448 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \ 4449 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\ 4450 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR)) 4451 4452 /** @brief Sets the HRTIM timer clock prescaler value on runtime 4453 * @param __HANDLE__ HRTIM Handle. 4454 * @param __TIMER__ HRTIM timer 4455 * This parameter can be one of the following values: 4456 * @arg 0x6 for master timer 4457 * @arg 0x0 to 0x5 for timers A to F 4458 * @param __PRESCALER__ specifies the clock prescaler new value. 4459 * This parameter can be one of the following values: 4460 * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) 4461 * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) 4462 * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) 4463 * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) 4464 * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) 4465 * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) 4466 * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) 4467 * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) 4468 * @retval None 4469 */ 4470 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \ 4471 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\ 4472 (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__)))) 4473 4474 /** @brief Gets the HRTIM timer clock prescaler value on runtime 4475 * @param __HANDLE__ HRTIM Handle. 4476 * @param __TIMER__ HRTIM timer 4477 * This parameter can be one of the following values: 4478 * @arg 0x6 for master timer 4479 * @arg 0x0 to 0x5 for timers A to F 4480 * @retval timer clock prescaler value 4481 */ 4482 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \ 4483 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\ 4484 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC)) 4485 4486 /** @brief Sets the HRTIM timer Compare Register value on runtime 4487 * @param __HANDLE__ HRTIM Handle. 4488 * @param __TIMER__ HRTIM timer 4489 * This parameter can be one of the following values: 4490 * @arg 0x0 to 0x5 for timers A to F 4491 * @param __COMPAREUNIT__ timer compare unit 4492 * This parameter can be one of the following values: 4493 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 4494 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 4495 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 4496 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 4497 * @param __COMPARE__ specifies the Compare new value. 4498 * @retval None 4499 */ 4500 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ 4501 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ 4502 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ 4503 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ 4504 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ 4505 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ 4506 : \ 4507 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ 4508 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ 4509 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ 4510 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) 4511 4512 /** @brief Gets the HRTIM timer Compare Register value on runtime 4513 * @param __HANDLE__ HRTIM Handle. 4514 * @param __TIMER__ HRTIM timer 4515 * This parameter can be one of the following values: 4516 * @arg 0x0 to 0x5 for timers A to F 4517 * @param __COMPAREUNIT__ timer compare unit 4518 * This parameter can be one of the following values: 4519 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 4520 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 4521 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 4522 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 4523 * @retval Compare value 4524 */ 4525 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ 4526 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ 4527 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ 4528 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ 4529 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ 4530 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ 4531 : \ 4532 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ 4533 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ 4534 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ 4535 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) 4536 4537 /** 4538 * @brief Enables the Fault Counter 4539 * @param hhrtim pointer to HAL HRTIM handle 4540 * @param Fault fault input to enable 4541 * This parameter can be one of the following values: 4542 * @arg HRTIM_FAULT_1: Fault input 1 4543 * @arg HRTIM_FAULT_2: Fault input 2 4544 * @arg HRTIM_FAULT_3: Fault input 3 4545 * @arg HRTIM_FAULT_4: Fault input 4 4546 * @arg HRTIM_FAULT_5: Fault input 5 4547 * @arg HRTIM_FAULT_6: Fault input 6 4548 * @note This function must be called when fault is not enabled 4549 * @retval HAL status 4550 */ 4551 #define __HAL_HRTIM_FAULT_BLANKING_ENABLE(__HANDLE__, __FAULT__)\ 4552 do {\ 4553 if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\ 4554 {\ 4555 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT1BLKE;\ 4556 }\ 4557 if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\ 4558 {\ 4559 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT2BLKE;\ 4560 }\ 4561 if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\ 4562 {\ 4563 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT3BLKE;\ 4564 }\ 4565 if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\ 4566 {\ 4567 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT4BLKE;\ 4568 }\ 4569 if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\ 4570 {\ 4571 ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT5BLKE;\ 4572 }\ 4573 if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\ 4574 {\ 4575 ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT6BLKE;\ 4576 }\ 4577 } while(0U) 4578 4579 /** 4580 * @brief Disables the Fault Counter 4581 * @param hhrtim pointer to HAL HRTIM handle 4582 * @param Fault fault input to disable 4583 * This parameter can be one of the following values: 4584 * @arg HRTIM_FAULT_1: Fault input 1 4585 * @arg HRTIM_FAULT_2: Fault input 2 4586 * @arg HRTIM_FAULT_3: Fault input 3 4587 * @arg HRTIM_FAULT_4: Fault input 4 4588 * @arg HRTIM_FAULT_5: Fault input 5 4589 * @arg HRTIM_FAULT_6: Fault input 6 4590 * @retval HAL status 4591 */ 4592 #define __HAL_HRTIM_FAULT_BLANKING_DISABLE(__HANDLE__, __FAULT__)\ 4593 do {\ 4594 if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\ 4595 {\ 4596 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT1BLKE;\ 4597 }\ 4598 if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\ 4599 {\ 4600 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT2BLKE;\ 4601 }\ 4602 if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\ 4603 {\ 4604 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT3BLKE;\ 4605 }\ 4606 if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\ 4607 {\ 4608 ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT4BLKE;\ 4609 }\ 4610 if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\ 4611 {\ 4612 ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT5BLKE;\ 4613 }\ 4614 if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\ 4615 {\ 4616 ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT6BLKE;\ 4617 }\ 4618 } while(0U) 4619 4620 /** 4621 * @} 4622 */ 4623 4624 /* Exported functions --------------------------------------------------------*/ 4625 /** @addtogroup HRTIM_Exported_Functions 4626 * @{ 4627 */ 4628 4629 /** @addtogroup HRTIM_Exported_Functions_Group1 4630 * @{ 4631 */ 4632 4633 /* Initialization and Configuration functions ********************************/ 4634 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); 4635 4636 HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim); 4637 4638 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); 4639 4640 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); 4641 4642 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, 4643 uint32_t TimerIdx, 4644 const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg); 4645 4646 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim, 4647 uint32_t CalibrationRate); 4648 4649 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim, 4650 uint32_t CalibrationRate); 4651 4652 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim, 4653 uint32_t Timeout); 4654 4655 /** 4656 * @} 4657 */ 4658 4659 /** @addtogroup HRTIM_Exported_Functions_Group2 4660 * @{ 4661 */ 4662 4663 /* Simple time base related functions *****************************************/ 4664 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, 4665 uint32_t TimerIdx); 4666 4667 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, 4668 uint32_t TimerIdx); 4669 4670 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, 4671 uint32_t TimerIdx); 4672 4673 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, 4674 uint32_t TimerIdx); 4675 4676 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, 4677 uint32_t TimerIdx, 4678 uint32_t SrcAddr, 4679 uint32_t DestAddr, 4680 uint32_t Length); 4681 4682 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, 4683 uint32_t TimerIdx); 4684 4685 /** 4686 * @} 4687 */ 4688 4689 /** @addtogroup HRTIM_Exported_Functions_Group3 4690 * @{ 4691 */ 4692 /* Simple output compare related functions ************************************/ 4693 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, 4694 uint32_t TimerIdx, 4695 uint32_t OCChannel, 4696 const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg); 4697 4698 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, 4699 uint32_t TimerIdx, 4700 uint32_t OCChannel); 4701 4702 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, 4703 uint32_t TimerIdx, 4704 uint32_t OCChannel); 4705 4706 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, 4707 uint32_t TimerIdx, 4708 uint32_t OCChannel); 4709 4710 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, 4711 uint32_t TimerIdx, 4712 uint32_t OCChannel); 4713 4714 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, 4715 uint32_t TimerIdx, 4716 uint32_t OCChannel, 4717 uint32_t SrcAddr, 4718 uint32_t DestAddr, 4719 uint32_t Length); 4720 4721 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, 4722 uint32_t TimerIdx, 4723 uint32_t OCChannel); 4724 4725 /** 4726 * @} 4727 */ 4728 4729 /** @addtogroup HRTIM_Exported_Functions_Group4 4730 * @{ 4731 */ 4732 /* Simple PWM output related functions ****************************************/ 4733 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, 4734 uint32_t TimerIdx, 4735 uint32_t PWMChannel, 4736 const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg); 4737 4738 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, 4739 uint32_t TimerIdx, 4740 uint32_t PWMChannel); 4741 4742 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, 4743 uint32_t TimerIdx, 4744 uint32_t PWMChannel); 4745 4746 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, 4747 uint32_t TimerIdx, 4748 uint32_t PWMChannel); 4749 4750 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, 4751 uint32_t TimerIdx, 4752 uint32_t PWMChannel); 4753 4754 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, 4755 uint32_t TimerIdx, 4756 uint32_t PWMChannel, 4757 uint32_t SrcAddr, 4758 uint32_t DestAddr, 4759 uint32_t Length); 4760 4761 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, 4762 uint32_t TimerIdx, 4763 uint32_t PWMChannel); 4764 4765 /** 4766 * @} 4767 */ 4768 4769 /** @addtogroup HRTIM_Exported_Functions_Group5 4770 * @{ 4771 */ 4772 /* Simple capture related functions *******************************************/ 4773 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, 4774 uint32_t TimerIdx, 4775 uint32_t CaptureChannel, 4776 const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg); 4777 4778 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, 4779 uint32_t TimerIdx, 4780 uint32_t CaptureChannel); 4781 4782 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, 4783 uint32_t TimerIdx, 4784 uint32_t CaptureChannel); 4785 4786 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, 4787 uint32_t TimerIdx, 4788 uint32_t CaptureChannel); 4789 4790 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, 4791 uint32_t TimerIdx, 4792 uint32_t CaptureChannel); 4793 4794 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, 4795 uint32_t TimerIdx, 4796 uint32_t CaptureChannel, 4797 uint32_t SrcAddr, 4798 uint32_t DestAddr, 4799 uint32_t Length); 4800 4801 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, 4802 uint32_t TimerIdx, 4803 uint32_t CaptureChannel); 4804 4805 /** 4806 * @} 4807 */ 4808 4809 /** @addtogroup HRTIM_Exported_Functions_Group6 4810 * @{ 4811 */ 4812 /* Simple one pulse related functions *****************************************/ 4813 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, 4814 uint32_t TimerIdx, 4815 uint32_t OnePulseChannel, 4816 const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg); 4817 4818 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, 4819 uint32_t TimerIdx, 4820 uint32_t OnePulseChannel); 4821 4822 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, 4823 uint32_t TimerIdx, 4824 uint32_t OnePulseChannel); 4825 4826 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, 4827 uint32_t TimerIdx, 4828 uint32_t OnePulseChannel); 4829 4830 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, 4831 uint32_t TimerIdx, 4832 uint32_t OnePulseChannel); 4833 4834 /** 4835 * @} 4836 */ 4837 4838 /** @addtogroup HRTIM_Exported_Functions_Group7 4839 * @{ 4840 */ 4841 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, 4842 const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg); 4843 4844 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, 4845 uint32_t Event, 4846 const HRTIM_EventCfgTypeDef *pEventCfg); 4847 4848 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, 4849 uint32_t Prescaler); 4850 4851 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, 4852 uint32_t Fault, 4853 const HRTIM_FaultCfgTypeDef *pFaultCfg); 4854 4855 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, 4856 uint32_t Prescaler); 4857 4858 HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef *hhrtim, 4859 uint32_t Fault, 4860 const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg); 4861 4862 HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef *hhrtim, 4863 uint32_t Fault, 4864 const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg); 4865 4866 HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef *hhrtim, 4867 uint32_t Fault); 4868 4869 HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef *hhrtim, 4870 uint32_t Timers); 4871 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim, 4872 uint32_t Faults, 4873 uint32_t Enable); 4874 4875 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, 4876 uint32_t ADCTrigger, 4877 const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg); 4878 4879 HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef *hhrtim, 4880 uint32_t ADCTrigger, 4881 uint32_t Postscaler); 4882 4883 HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef *hhrtim, 4884 uint32_t TimerIdx, 4885 uint32_t RollOverCfg); 4886 4887 HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef *hhrtim, 4888 uint32_t Timers); 4889 4890 HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef *hhrtim, 4891 uint32_t Timers); 4892 /** 4893 * @} 4894 */ 4895 4896 /** @addtogroup HRTIM_Exported_Functions_Group8 4897 * @{ 4898 */ 4899 /* Waveform related functions *************************************************/ 4900 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, 4901 uint32_t TimerIdx, 4902 const HRTIM_TimerCfgTypeDef *pTimerCfg); 4903 4904 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef *hhrtim, 4905 uint32_t TimerIdx, 4906 const HRTIM_TimerCtlTypeDef *pTimerCtl); 4907 4908 HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef *hhrtim, 4909 uint32_t TimerIdx, 4910 const HRTIM_TimerCtlTypeDef *pTimerCtl); 4911 4912 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, 4913 uint32_t TimerIdx, 4914 uint32_t CompareUnit, 4915 const HRTIM_CompareCfgTypeDef *pCompareCfg); 4916 4917 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, 4918 uint32_t TimerIdx, 4919 uint32_t CaptureUnit, 4920 const HRTIM_CaptureCfgTypeDef *pCaptureCfg); 4921 4922 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, 4923 uint32_t TimerIdx, 4924 uint32_t Output, 4925 const HRTIM_OutputCfgTypeDef *pOutputCfg); 4926 4927 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, 4928 uint32_t TimerIdx, 4929 uint32_t Output, 4930 uint32_t OutputLevel); 4931 4932 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, 4933 uint32_t TimerIdx, 4934 uint32_t Event, 4935 const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg); 4936 4937 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef *hhrtim, 4938 uint32_t TimerIdx, 4939 uint32_t EventCounter, 4940 const HRTIM_ExternalEventCfgTypeDef *pTimerExternalEventCfg); 4941 4942 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef *hhrtim, 4943 uint32_t TimerIdx, 4944 uint32_t EventCounter); 4945 4946 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef *hhrtim, 4947 uint32_t TimerIdx, 4948 uint32_t EventCounter); 4949 4950 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef *hhrtim, 4951 uint32_t TimerIdx, 4952 uint32_t EventCounter); 4953 4954 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, 4955 uint32_t TimerIdx, 4956 const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg); 4957 4958 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, 4959 uint32_t TimerIdx, 4960 const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg); 4961 4962 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, 4963 uint32_t TimerIdx, 4964 uint32_t RegistersToUpdate); 4965 4966 4967 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, 4968 uint32_t Timers); 4969 4970 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, 4971 uint32_t Timers); 4972 4973 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, 4974 uint32_t Timers); 4975 4976 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, 4977 uint32_t Timers); 4978 4979 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, 4980 uint32_t Timers); 4981 4982 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, 4983 uint32_t Timers); 4984 4985 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, 4986 uint32_t OutputsToStart); 4987 4988 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, 4989 uint32_t OutputsToStop); 4990 4991 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim, 4992 uint32_t Enable); 4993 4994 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim); 4995 4996 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim, 4997 uint32_t TimerIdx, 4998 uint32_t CaptureUnit); 4999 5000 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim, 5001 uint32_t Timers); 5002 5003 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim, 5004 uint32_t Timers); 5005 5006 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, 5007 uint32_t TimerIdx, 5008 uint32_t BurstBufferAddress, 5009 uint32_t BurstBufferLength); 5010 5011 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, 5012 uint32_t Timers); 5013 5014 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, 5015 uint32_t Timers); 5016 5017 /** 5018 * @} 5019 */ 5020 5021 /** @addtogroup HRTIM_Exported_Functions_Group9 5022 * @{ 5023 */ 5024 /* HRTIM peripheral state functions */ 5025 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim); 5026 5027 uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim, 5028 uint32_t TimerIdx, 5029 uint32_t CaptureUnit); 5030 5031 uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef *hhrtim, 5032 uint32_t TimerIdx, 5033 uint32_t CaptureUnit); 5034 5035 HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef *hhrtim, 5036 uint32_t TimerIdx, 5037 uint32_t CaptureUnit); 5038 5039 uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim, 5040 uint32_t TimerIdx, 5041 uint32_t Output); 5042 5043 uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim, 5044 uint32_t TimerIdx, 5045 uint32_t Output); 5046 5047 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim, 5048 uint32_t TimerIdx, 5049 uint32_t Output); 5050 5051 uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim); 5052 5053 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim, 5054 uint32_t TimerIdx); 5055 5056 uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim, 5057 uint32_t TimerIdx); 5058 5059 /** 5060 * @} 5061 */ 5062 5063 /** @addtogroup HRTIM_Exported_Functions_Group10 5064 * @{ 5065 */ 5066 /* IRQ handler */ 5067 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, 5068 uint32_t TimerIdx); 5069 5070 /* HRTIM events related callback functions */ 5071 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim); 5072 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim); 5073 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim); 5074 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim); 5075 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim); 5076 void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef *hhrtim); 5077 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim); 5078 void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef *hhrtim); 5079 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim); 5080 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); 5081 5082 /* Timer events related callback functions */ 5083 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, 5084 uint32_t TimerIdx); 5085 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, 5086 uint32_t TimerIdx); 5087 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, 5088 uint32_t TimerIdx); 5089 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, 5090 uint32_t TimerIdx); 5091 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, 5092 uint32_t TimerIdx); 5093 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, 5094 uint32_t TimerIdx); 5095 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, 5096 uint32_t TimerIdx); 5097 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, 5098 uint32_t TimerIdx); 5099 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, 5100 uint32_t TimerIdx); 5101 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, 5102 uint32_t TimerIdx); 5103 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, 5104 uint32_t TimerIdx); 5105 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, 5106 uint32_t TimerIdx); 5107 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, 5108 uint32_t TimerIdx); 5109 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, 5110 uint32_t TimerIdx); 5111 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, 5112 uint32_t TimerIdx); 5113 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); 5114 5115 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 5116 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *hhrtim, 5117 HAL_HRTIM_CallbackIDTypeDef CallbackID, 5118 pHRTIM_CallbackTypeDef pCallback); 5119 5120 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, 5121 HAL_HRTIM_CallbackIDTypeDef CallbackID); 5122 5123 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim, 5124 HAL_HRTIM_CallbackIDTypeDef CallbackID, 5125 pHRTIM_TIMxCallbackTypeDef pCallback); 5126 5127 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim, 5128 HAL_HRTIM_CallbackIDTypeDef CallbackID); 5129 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 5130 5131 /** 5132 * @} 5133 */ 5134 5135 /** 5136 * @} 5137 */ 5138 5139 /** 5140 * @} 5141 */ 5142 5143 /** 5144 * @} 5145 */ 5146 5147 #endif /* HRTIM1 */ 5148 5149 #ifdef __cplusplus 5150 } 5151 #endif 5152 5153 #endif /* STM32G4xx_HAL_HRTIM_H */ 5154
