1 /* 2 * Copyright (c) 2024 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file host_css_memory_map.h 19 * \brief This file contains addresses that are defined in the compute 20 * subsystem (CSS) memory map. 21 */ 22 23 #ifndef __HOST_CSS_MEMORY_MAP_H__ 24 #define __HOST_CSS_MEMORY_MAP_H__ 25 26 #include "host_css_io_block_memory_map.h" 27 28 /* AP Shared (ARSM) SRAM base address */ 29 #define HOST_AP_SHARED_SRAM_PHYS_BASE 0x000000000ULL 30 /* AP Shared (ARSM) SRAM end address */ 31 #define HOST_AP_SHARED_SRAM_PHYS_LIMIT 0x0000FFFFFULL 32 33 /* AP Memory Expansion region 1 base address */ 34 #define HOST_AP_MEM_EXP_1_PHYS_BASE 0x008000000ULL 35 /* AP Memory Expansion region 1 end address */ 36 #define HOST_AP_MEM_EXP_1_PHYS_LIMIT 0x00FFFFFFFULL 37 38 /* System Control block NI-Tower base address */ 39 #define HOST_SYSCTRL_NI_TOWER_PHYS_BASE 0x020000000ULL 40 /* System Control block NI-Tower end address */ 41 #define HOST_SYSCTRL_NI_TOWER_PHYS_LIMIT 0x020FFFFFFULL 42 /* IO Block NI-Tower base address */ 43 #define HOST_IO_MACRO_NI_TOWER_PHYS_BASE 0x021000000ULL 44 /* IO Block NI-Tower end address */ 45 #define HOST_IO_MACRO_NI_TOWER_PHYS_LIMIT 0x021FFFFFFULL 46 /* Peripheral block NI-Tower base address */ 47 #define HOST_PERIPH_NI_TOWER_PHYS_BASE 0x022000000ULL 48 /* Peripheral block NI-Tower end address */ 49 #define HOST_PERIPH_NI_TOWER_PHYS_LIMIT 0x022FFFFFFULL 50 /* System Fabric NI-Tower base address */ 51 #define HOST_FABRIC_NI_TOWER_PHYS_BASE 0x023000000ULL 52 /* System Fabric NI-Tower end address */ 53 #define HOST_FABRIC_NI_TOWER_PHYS_LIMIT 0x023FFFFFFULL 54 55 /* Non-secure Uart peripheral base address */ 56 #define HOST_NS_UART_PHYS_BASE 0x02A400000ULL 57 /* Non-secure Uart peripheral end address */ 58 #define HOST_NS_UART_PHYS_LIMIT 0x02A40FFFFULL 59 /* Secure Uart peripheral base address */ 60 #define HOST_S_UART_PHYS_BASE 0x02A410000ULL 61 /* Secure Uart peripheral end address */ 62 #define HOST_S_UART_PHYS_LIMIT 0x02A41FFFFULL 63 /* RMM Uart peripheral base address */ 64 #define HOST_RMM_NS_UART_PHYS_BASE 0x02A420000ULL 65 /* RMM Uart peripheral end address */ 66 #define HOST_RMM_NS_UART_PHYS_LIMIT 0x02A42FFFFULL 67 68 /* Generic refclk cntcontrol register base address */ 69 #define HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_BASE 0x02A430000ULL 70 /* Generic refclk cntcontrol register end address */ 71 #define HOST_GENERIC_REFCLK_CNTCONTROL_PHYS_LIMIT 0x02A43FFFFULL 72 /* Non-secure AP watchdog base address */ 73 #define HOST_AP_NS_WDOG_PHYS_BASE 0x02A440000ULL 74 /* Non-secure AP watchdog end address */ 75 #define HOST_AP_NS_WDOG_PHYS_LIMIT 0x02A45FFFFULL 76 /* Root AP watchdog base address */ 77 #define HOST_AP_RT_WDOG_PHYS_BASE 0x02A460000ULL 78 /* Root AP watchdog end address */ 79 #define HOST_AP_RT_WDOG_PHYS_LIMIT 0x02A47FFFFULL 80 /* Secure AP watchdog base address */ 81 #define HOST_AP_S_WDOG_PHYS_BASE 0x02A480000ULL 82 /* Secure AP watchdog end address */ 83 #define HOST_AP_S_WDOG_PHYS_LIMIT 0x02A49FFFFULL 84 /* SID register base address */ 85 #define HOST_SID_PHYS_BASE 0x02A4A0000ULL 86 /* SID register end address */ 87 #define HOST_SID_PHYS_LIMIT 0x02A4AFFFFULL 88 89 /* Secure AP ECC error record register base address */ 90 #define HOST_AP_S_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A4B0000ULL 91 /* Secure AP ECC error record register end address */ 92 #define HOST_AP_S_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A4BFFFFULL 93 /* Non-Secure AP ECC error record register base address */ 94 #define HOST_AP_NS_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A4C0000ULL 95 /* Non-Secure AP ECC error record register end address */ 96 #define HOST_AP_NS_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A4CFFFFULL 97 /* Root AP ECC error record register base address */ 98 #define HOST_AP_RT_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A4D0000ULL 99 /* Root AP ECC error record register end address */ 100 #define HOST_AP_RT_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A4DFFFFULL 101 /* Realm AP ECC error record register base address */ 102 #define HOST_AP_RL_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A4E0000ULL 103 /* Realm AP ECC error record register end address */ 104 #define HOST_AP_RL_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A4EFFFFULL 105 /* Secure SCP ECC error record register base address */ 106 #define HOST_SCP_S_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A4F0000ULL 107 /* Secure SCP ECC error record register end address */ 108 #define HOST_SCP_S_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A4FFFFFULL 109 /* Non-secure SCP ECC error record register base address */ 110 #define HOST_SCP_NS_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A500000ULL 111 /* Non-secure SCP ECC error record register end address */ 112 #define HOST_SCP_NS_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A50FFFFULL 113 /* Root SCP ECC error record register base address */ 114 #define HOST_SCP_RT_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A510000ULL 115 /* Root SCP ECC error record register end address */ 116 #define HOST_SCP_RT_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A51FFFFULL 117 /* Realm SCP ECC error record register base address */ 118 #define HOST_SCP_RL_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A520000ULL 119 /* Realm SCP ECC error record register end address */ 120 #define HOST_SCP_RL_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A52FFFFULL 121 /* Secure MCP ECC error record register base address */ 122 #define HOST_MCP_S_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A530000ULL 123 /* Secure MCP ECC error record register end address */ 124 #define HOST_MCP_S_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A53FFFFULL 125 /* Non-secure MCP ECC error record register base address */ 126 #define HOST_MCP_NS_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A540000ULL 127 /* Non-secure MCP ECC error record register end address */ 128 #define HOST_MCP_NS_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A54FFFFULL 129 /* Root MCP ECC error record register base address */ 130 #define HOST_MCP_RT_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A550000ULL 131 /* Root MCP ECC error record register end address */ 132 #define HOST_MCP_RT_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A55FFFFULL 133 /* Realm MCP ECC error record register base address */ 134 #define HOST_MCP_RL_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A560000ULL 135 /* Realm MCP ECC error record register end address */ 136 #define HOST_MCP_RL_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A56FFFFULL 137 /* Secure RSE ECC error record register base address */ 138 #define HOST_RSE_S_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A570000ULL 139 /* Secure RSE ECC error record register end address */ 140 #define HOST_RSE_S_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A57FFFFULL 141 /* Non-secure RSE ECC error record register base address */ 142 #define HOST_RSE_NS_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A580000ULL 143 /* Non-secure RSE ECC error record register end address */ 144 #define HOST_RSE_NS_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A58FFFFULL 145 /* Root RSE ECC error record register base address */ 146 #define HOST_RSE_RT_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A590000ULL 147 /* Root RSE ECC error record register end address */ 148 #define HOST_RSE_RT_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A59FFFFULL 149 /* Realm RSE ECC error record register base address */ 150 #define HOST_RSE_RL_ARSM_RAM_ECC_REC_PHYS_BASE 0x02A5A0000ULL 151 /* Realm RSE ECC error record register end address */ 152 #define HOST_RSE_RL_ARSM_RAM_ECC_REC_PHYS_LIMIT 0x02A5AFFFFULL 153 154 /* Secure RSE ECC error record register for RSM base address */ 155 #define HOST_RSE_S_RSM_RAM_ECC_REC_PHYS_BASE 0x02A5B0000ULL 156 /* Secure RSE ECC error record register for RSM end address */ 157 #define HOST_RSE_S_RSM_RAM_ECC_REC_PHYS_LIMIT 0x02A5BFFFFULL 158 /* Non-secure RSE ECC error record register for RSM base address */ 159 #define HOST_RSE_NS_RSM_RAM_ECC_REC_PHYS_BASE 0x02A5C0000ULL 160 /* Non-secure RSE ECC error record register for RSM end address */ 161 #define HOST_RSE_NS_RSM_RAM_ECC_REC_PHYS_LIMIT 0x02A5CFFFFULL 162 /* Secure SCP ECC error record register for RSM base address */ 163 #define HOST_SCP_S_RSM_RAM_ECC_REC_PHYS_BASE 0x02A5D0000ULL 164 /* Secure SCP ECC error record register for RSM end address */ 165 #define HOST_SCP_S_RSM_RAM_ECC_REC_PHYS_LIMIT 0x02A5DFFFFULL 166 /* Non-secure SCP ECC error record register for RSM base address */ 167 #define HOST_SCP_NS_RSM_RAM_ECC_REC_PHYS_BASE 0x02A5E0000ULL 168 /* Non-secure SCP ECC error record register for RSM end address */ 169 #define HOST_SCP_NS_RSM_RAM_ECC_REC_PHYS_LIMIT 0x02A5EFFFFULL 170 /* Secure MCP ECC error record register for RSM base address */ 171 #define HOST_MCP_S_RSM_RAM_ECC_REC_PHYS_BASE 0x02A5F0000ULL 172 /* Secure MCP ECC error record register for RSM end address */ 173 #define HOST_MCP_S_RSM_RAM_ECC_REC_PHYS_LIMIT 0x02A5FFFFFULL 174 /* Non-secure MCP ECC error record register for RSM base address */ 175 #define HOST_MCP_NS_RSM_RAM_ECC_REC_PHYS_BASE 0x02A600000ULL 176 /* Non-secure MCP ECC error record register for RSM end address */ 177 #define HOST_MCP_NS_RSM_RAM_ECC_REC_PHYS_LIMIT 0x02A60FFFFULL 178 179 /* Generic refclk cntread register base address */ 180 #define HOST_GENERIC_REFCLK_CNTREAD_PHYS_BASE 0x02A800000ULL 181 /* Generic refclk cntread register end address */ 182 #define HOST_GENERIC_REFCLK_CNTREAD_PHYS_LIMIT 0x02A80FFFFULL 183 /* AP refclk cntctl register base address */ 184 #define HOST_AP_REFCLK_CNTCTL_PHYS_BASE 0x02A810000ULL 185 /* AP refclk cntctl register end address */ 186 #define HOST_AP_REFCLK_CNTCTL_PHYS_LIMIT 0x02A81FFFFULL 187 /* AP refclk cntbase0 register base address */ 188 #define HOST_AP_S_REFCLK_CNTBASE0_PHYS_BASE 0x02A820000ULL 189 /* AP refclk cntbase0 register end address */ 190 #define HOST_AP_S_REFCLK_CNTBASE0_PHYS_LIMIT 0x02A82FFFFULL 191 /* AP refclk cntbase1 register base address */ 192 #define HOST_AP_NS_REFCLK_CNTBASE1_PHYS_BASE 0x02A830000ULL 193 /* AP refclk cntbase1 register end address */ 194 #define HOST_AP_NS_REFCLK_CNTBASE1_PHYS_LIMIT 0x02A83FFFFULL 195 196 /* Non-secure AP<->SCP MHUv3 Send and recieve registers base address */ 197 #define HOST_AP_NS_SCP_MHUV3_PHYS_BASE 0x02A900000ULL 198 /* Non-secure AP<->SCP MHUv3 Send and recieve registers end address */ 199 #define HOST_AP_NS_SCP_MHUV3_PHYS_LIMIT 0x02A91FFFFULL 200 /* Secure AP<->SCP MHUv3 Send and recieve registers base address */ 201 #define HOST_AP_S_SCP_MHUV3_PHYS_BASE 0x02A920000ULL 202 /* Secure AP<->SCP MHUv3 Send and recieve registers end address */ 203 #define HOST_AP_S_SCP_MHUV3_PHYS_LIMIT 0x02A93FFFFULL 204 /* Root AP<->SCP MHUv3 Send and recieve registers base address */ 205 #define HOST_AP_RT_SCP_MHUV3_PHYS_BASE 0x02A940000ULL 206 /* Root AP<->SCP MHUv3 Send and recieve registers end address */ 207 #define HOST_AP_RT_SCP_MHUV3_PHYS_LIMIT 0x02A95FFFFULL 208 209 /* Non-secure AP<->MCP MHUv3 Send and recieve registers base address */ 210 #define HOST_AP_NS_MCP_MHUV3_SEND_BASE 0x02AA00000ULL 211 /* Non-secure AP<->MCP MHUv3 Send and recieve registers end address */ 212 #define HOST_AP_NS_MCP_MHUV3_SEND_LIMIT 0x02AA1FFFFULL 213 /* Secure AP<->MCP MHUv3 Send and recieve registers base address */ 214 #define HOST_AP_S_MCP_MHUV3_PHYS_BASE 0x02AA20000ULL 215 /* Secure AP<->MCP MHUv3 Send and recieve registers end address */ 216 #define HOST_AP_S_MCP_MHUV3_PHYS_LIMIT 0x02AA3FFFFULL 217 /* Root AP<->MCP MHUv3 Send and recieve registers base address */ 218 #define HOST_AP_RT_MCP_MHUV3_PHYS_BASE 0x02AA40000ULL 219 /* Root AP<->MCP MHUv3 Send and recieve registers end address */ 220 #define HOST_AP_RT_MCP_MHUV3_PHYS_LIMIT 0x02AA5FFFFULL 221 222 /* Non-secure AP<->RSE MHUv3 Send and recieve registers base address */ 223 #define HOST_AP_NS_RSE_MHUV3_PHYS_BASE 0x02AB00000ULL 224 /* Non-secure AP<->RSE MHUv3 Send and recieve registers end address */ 225 #define HOST_AP_NS_RSE_MHUV3_PHYS_LIMIT 0x02AB1FFFFULL 226 /* Secure AP<->RSE MHUv3 Send and recieve registers base address */ 227 #define HOST_AP_S_RSE_MHUV3_PHYS_BASE 0x02AB20000ULL 228 /* Secure AP<->RSE MHUv3 Send and recieve registers end address */ 229 #define HOST_AP_S_RSE_MHUV3_PHYS_LIMIT 0x02AB3FFFFULL 230 /* Root AP<->RSE MHUv3 Send and recieve registers base address */ 231 #define HOST_AP_RT_RSE_MHUV3_PHYS_BASE 0x02AB40000ULL 232 /* Root AP<->RSE MHUv3 Send and recieve registers end address */ 233 #define HOST_AP_RT_RSE_MHUV3_PHYS_LIMIT 0x02AB5FFFFULL 234 /* Realm AP<->RSE MHUv3 Send and recieve registers base address */ 235 #define HOST_AP_RL_RSE_MHUV3_PHYS_BASE 0x02AB60000ULL 236 /* Realm AP<->RSE MHUv3 Send and recieve registers end address */ 237 #define HOST_AP_RL_RSE_MHUV3_PHYS_LIMIT 0x02AB7FFFFULL 238 239 /* SCP<->SCP MHU Send registers base address */ 240 #define HOST_SCP_TO_SCP_MHU_PHYS_BASE 0x02AC00000ULL 241 /* SCP<->SCP MHU Send registers end address */ 242 #define HOST_SCP_TO_SCP_MHU_PHYS_LIMIT 0x02AC2FFFFULL 243 /* MCP<->MCP MHU Send registers base address */ 244 #define HOST_MCP_TO_MCP_MHU_PHYS_BASE 0x02AC60000ULL 245 /* MCP<->MCP MHU Send registers end address */ 246 #define HOST_MCP_TO_MCP_MHU_PHYS_LIMIT 0x02AC8FFFFULL 247 /* RSE<->RSE MHU Send registers base address */ 248 #define HOST_RSE_TO_RSE_MHU_PHYS_BASE 0x02ACC0000ULL 249 /* RSE<->RSE MHU Send registers end address */ 250 #define HOST_RSE_TO_RSE_MHU_PHYS_LIMIT 0x02ACEFFFFULL 251 252 /* Macro wrappers for MHU physical address for cross chip send frames */ 253 #define HOST_RSE_N_TO_RSE_N_MHU_PHYS_BASE(chip_id_a, chip_id_b) \ 254 HOST_RSE_##chip_id_a##_TO_RSE_##chip_id_b##_MHU_FRAME_PHYS_BASE 255 #define HOST_RSE_N_TO_RSE_N_MHU_PHYS_LIMIT(chip_id_a, chip_id_b) \ 256 HOST_RSE_##chip_id_a##_TO_RSE_##chip_id_b##_MHU_FRAME_PHYS_LIMIT 257 #define HOST_SCP_N_TO_SCP_N_MHU_PHYS_BASE(chip_id_a, chip_id_b) \ 258 HOST_SCP_##chip_id_a##_TO_SCP_##chip_id_b##_MHU_FRAME_PHYS_BASE 259 #define HOST_SCP_N_TO_SCP_N_MHU_PHYS_LIMIT(chip_id_a, chip_id_b) \ 260 HOST_SCP_##chip_id_a##_TO_SCP_##chip_id_b##_MHU_FRAME_PHYS_LIMIT 261 #define HOST_MCP_N_TO_MCP_N_MHU_PHYS_BASE(chip_id_a, chip_id_b) \ 262 HOST_MCP_##chip_id_a##_TO_MCP_##chip_id_b##_MHU_FRAME_PHYS_BASE 263 #define HOST_MCP_N_TO_MCP_N_MHU_PHYS_LIMIT(chip_id_a, chip_id_b) \ 264 HOST_MCP_##chip_id_a##_TO_MCP_##chip_id_b##_MHU_FRAME_PHYS_LIMIT 265 266 #define HOST_RSE_0_TO_RSE_1_MHU_FRAME_PHYS_BASE 0x102ACC0000ULL 267 #define HOST_RSE_0_TO_RSE_1_MHU_FRAME_PHYS_LIMIT 0x102ACCFFFFULL 268 #define HOST_RSE_0_TO_RSE_2_MHU_FRAME_PHYS_BASE 0x202ACC0000ULL 269 #define HOST_RSE_0_TO_RSE_2_MHU_FRAME_PHYS_LIMIT 0x202ACCFFFFULL 270 #define HOST_RSE_0_TO_RSE_3_MHU_FRAME_PHYS_BASE 0x302ACC0000ULL 271 #define HOST_RSE_0_TO_RSE_3_MHU_FRAME_PHYS_LIMIT 0x302ACCFFFFULL 272 #define HOST_RSE_1_TO_RSE_0_MHU_FRAME_PHYS_BASE 0x002ACC0000ULL 273 #define HOST_RSE_1_TO_RSE_0_MHU_FRAME_PHYS_LIMIT 0x002ACCFFFFULL 274 #define HOST_RSE_1_TO_RSE_2_MHU_FRAME_PHYS_BASE 0x202ACD0000ULL 275 #define HOST_RSE_1_TO_RSE_2_MHU_FRAME_PHYS_LIMIT 0x202ACDFFFFULL 276 #define HOST_RSE_1_TO_RSE_3_MHU_FRAME_PHYS_BASE 0x302ACD0000ULL 277 #define HOST_RSE_1_TO_RSE_3_MHU_FRAME_PHYS_LIMIT 0x302ACDFFFFULL 278 #define HOST_RSE_2_TO_RSE_0_MHU_FRAME_PHYS_BASE 0x002ACD0000ULL 279 #define HOST_RSE_2_TO_RSE_0_MHU_FRAME_PHYS_LIMIT 0x002ACDFFFFULL 280 #define HOST_RSE_2_TO_RSE_1_MHU_FRAME_PHYS_BASE 0x102ACD0000ULL 281 #define HOST_RSE_2_TO_RSE_1_MHU_FRAME_PHYS_LIMIT 0x102ACDFFFFULL 282 #define HOST_RSE_2_TO_RSE_3_MHU_FRAME_PHYS_BASE 0x302ACE0000ULL 283 #define HOST_RSE_2_TO_RSE_3_MHU_FRAME_PHYS_LIMIT 0x302ACEFFFFULL 284 #define HOST_RSE_3_TO_RSE_0_MHU_FRAME_PHYS_BASE 0x002ACE0000ULL 285 #define HOST_RSE_3_TO_RSE_0_MHU_FRAME_PHYS_LIMIT 0x002ACEFFFFULL 286 #define HOST_RSE_3_TO_RSE_1_MHU_FRAME_PHYS_BASE 0x102ACE0000ULL 287 #define HOST_RSE_3_TO_RSE_1_MHU_FRAME_PHYS_LIMIT 0x102ACEFFFFULL 288 #define HOST_RSE_3_TO_RSE_2_MHU_FRAME_PHYS_BASE 0x202ACE0000ULL 289 #define HOST_RSE_3_TO_RSE_2_MHU_FRAME_PHYS_LIMIT 0x202ACEFFFFULL 290 #define HOST_SCP_0_TO_SCP_1_MHU_FRAME_PHYS_BASE 0x102AC00000ULL 291 #define HOST_SCP_0_TO_SCP_1_MHU_FRAME_PHYS_LIMIT 0x102AC0FFFFULL 292 #define HOST_SCP_0_TO_SCP_2_MHU_FRAME_PHYS_BASE 0x202AC00000ULL 293 #define HOST_SCP_0_TO_SCP_2_MHU_FRAME_PHYS_LIMIT 0x202AC0FFFFULL 294 #define HOST_SCP_0_TO_SCP_3_MHU_FRAME_PHYS_BASE 0x302AC00000ULL 295 #define HOST_SCP_0_TO_SCP_3_MHU_FRAME_PHYS_LIMIT 0x302AC0FFFFULL 296 #define HOST_SCP_1_TO_SCP_0_MHU_FRAME_PHYS_BASE 0x002AC00000ULL 297 #define HOST_SCP_1_TO_SCP_0_MHU_FRAME_PHYS_LIMIT 0x002AC0FFFFULL 298 #define HOST_SCP_1_TO_SCP_2_MHU_FRAME_PHYS_BASE 0x202AC10000ULL 299 #define HOST_SCP_1_TO_SCP_2_MHU_FRAME_PHYS_LIMIT 0x202AC1FFFFULL 300 #define HOST_SCP_1_TO_SCP_3_MHU_FRAME_PHYS_BASE 0x302AC10000ULL 301 #define HOST_SCP_1_TO_SCP_3_MHU_FRAME_PHYS_LIMIT 0x302AC1FFFFULL 302 #define HOST_SCP_2_TO_SCP_0_MHU_FRAME_PHYS_BASE 0x002AC10000ULL 303 #define HOST_SCP_2_TO_SCP_0_MHU_FRAME_PHYS_LIMIT 0x002AC1FFFFULL 304 #define HOST_SCP_2_TO_SCP_1_MHU_FRAME_PHYS_BASE 0x102AC10000ULL 305 #define HOST_SCP_2_TO_SCP_1_MHU_FRAME_PHYS_LIMIT 0x102AC1FFFFULL 306 #define HOST_SCP_2_TO_SCP_3_MHU_FRAME_PHYS_BASE 0x302AC20000ULL 307 #define HOST_SCP_2_TO_SCP_3_MHU_FRAME_PHYS_LIMIT 0x302AC2FFFFULL 308 #define HOST_SCP_3_TO_SCP_0_MHU_FRAME_PHYS_BASE 0x002AC20000ULL 309 #define HOST_SCP_3_TO_SCP_0_MHU_FRAME_PHYS_LIMIT 0x002AC2FFFFULL 310 #define HOST_SCP_3_TO_SCP_1_MHU_FRAME_PHYS_BASE 0x102AC20000ULL 311 #define HOST_SCP_3_TO_SCP_1_MHU_FRAME_PHYS_LIMIT 0x102AC2FFFFULL 312 #define HOST_SCP_3_TO_SCP_2_MHU_FRAME_PHYS_BASE 0x202AC20000ULL 313 #define HOST_SCP_3_TO_SCP_2_MHU_FRAME_PHYS_LIMIT 0x202AC2FFFFULL 314 #define HOST_MCP_0_TO_MCP_1_MHU_FRAME_PHYS_BASE 0x102AC60000ULL 315 #define HOST_MCP_0_TO_MCP_1_MHU_FRAME_PHYS_LIMIT 0x102AC6FFFFULL 316 #define HOST_MCP_0_TO_MCP_2_MHU_FRAME_PHYS_BASE 0x202AC60000ULL 317 #define HOST_MCP_0_TO_MCP_2_MHU_FRAME_PHYS_LIMIT 0x202AC6FFFFULL 318 #define HOST_MCP_0_TO_MCP_3_MHU_FRAME_PHYS_BASE 0x302AC60000ULL 319 #define HOST_MCP_0_TO_MCP_3_MHU_FRAME_PHYS_LIMIT 0x302AC6FFFFULL 320 #define HOST_MCP_1_TO_MCP_0_MHU_FRAME_PHYS_BASE 0x002AC60000ULL 321 #define HOST_MCP_1_TO_MCP_0_MHU_FRAME_PHYS_LIMIT 0x002AC6FFFFULL 322 #define HOST_MCP_1_TO_MCP_2_MHU_FRAME_PHYS_BASE 0x202AC70000ULL 323 #define HOST_MCP_1_TO_MCP_2_MHU_FRAME_PHYS_LIMIT 0x202AC7FFFFULL 324 #define HOST_MCP_1_TO_MCP_3_MHU_FRAME_PHYS_BASE 0x302AC70000ULL 325 #define HOST_MCP_1_TO_MCP_3_MHU_FRAME_PHYS_LIMIT 0x302AC7FFFFULL 326 #define HOST_MCP_2_TO_MCP_0_MHU_FRAME_PHYS_BASE 0x002AC70000ULL 327 #define HOST_MCP_2_TO_MCP_0_MHU_FRAME_PHYS_LIMIT 0x002AC7FFFFULL 328 #define HOST_MCP_2_TO_MCP_1_MHU_FRAME_PHYS_BASE 0x102AC70000ULL 329 #define HOST_MCP_2_TO_MCP_1_MHU_FRAME_PHYS_LIMIT 0x102AC7FFFFULL 330 #define HOST_MCP_2_TO_MCP_3_MHU_FRAME_PHYS_BASE 0x302AC80000ULL 331 #define HOST_MCP_2_TO_MCP_3_MHU_FRAME_PHYS_LIMIT 0x302AC8FFFFULL 332 #define HOST_MCP_3_TO_MCP_0_MHU_FRAME_PHYS_BASE 0x002AC80000ULL 333 #define HOST_MCP_3_TO_MCP_0_MHU_FRAME_PHYS_LIMIT 0x002AC8FFFFULL 334 #define HOST_MCP_3_TO_MCP_1_MHU_FRAME_PHYS_BASE 0x102AC80000ULL 335 #define HOST_MCP_3_TO_MCP_1_MHU_FRAME_PHYS_LIMIT 0x102AC8FFFFULL 336 #define HOST_MCP_3_TO_MCP_2_MHU_FRAME_PHYS_BASE 0x202AC80000ULL 337 #define HOST_MCP_3_TO_MCP_2_MHU_FRAME_PHYS_LIMIT 0x202AC8FFFFULL 338 339 /* Timer synchronization register base address */ 340 #define HOST_SYNCNT_MSTUPDTVAL_ADDR_PHYS_BASE 0x02B100000ULL 341 /* Timer synchronization register end address */ 342 #define HOST_SYNCNT_MSTUPDTVAL_ADDR_PHYS_LIMIT 0x02B12FFFFULL 343 344 /* STM base address */ 345 #define HOST_STM_PHYS_BASE 0x02E000000ULL 346 /* STM end address */ 347 #define HOST_STM_PHYS_LIMIT 0x02EFFFFFFULL 348 349 /* Shared SRAM for RSM base address */ 350 #define HOST_RSM_SRAM_PHYS_BASE 0x02F000000ULL 351 /* Shared SRAM for RSM end address */ 352 #define HOST_RSM_SRAM_PHYS_LIMIT 0x02F3FFFFFULL 353 354 /* GIC-700 base address */ 355 #define HOST_GIC_700_PHYS_BASE 0x030000000ULL 356 /* GIC-700 end address */ 357 #define HOST_GIC_700_PHYS_LIMIT 0x037FFFFFFULL 358 359 /* PCIe NCI Memory space 1 base address */ 360 #define HOST_PCIE_NCI_1_PHYS_BASE 0x060000000ULL 361 /* PCIe NCI Memory space 1 end address */ 362 #define HOST_PCIE_NCI_1_PHYS_LIMIT 0x07FFFFFFFULL 363 364 /* DRAM base address */ 365 #define HOST_DRAM_PHYS_BASE 0x080000000ULL 366 /* DRAM end address */ 367 #define HOST_DRAM_PHYS_LIMIT 0x0FFFFFFFFULL 368 369 /* CMN GPV base address */ 370 #define HOST_CMN_GPV_PHYS_BASE 0x100000000ULL 371 /* CMN GPV end address */ 372 #define HOST_CMN_GPV_PHYS_LIMIT 0x13FFFFFFFULL 373 374 /* Memory controller + MPE register region base address */ 375 #define HOST_MPE_PHYS_BASE 0x180000000ULL 376 /* Memory controller + MPE register region end address */ 377 #define HOST_MPE_PHYS_LIMIT 0x1BFFFFFFFULL 378 379 /* LCP peripherals + Cluster utility memory region base address */ 380 #define HOST_CLUST_UTIL_PHYS_BASE 0x200000000ULL 381 /* LCP peripherals + Cluster utility memory region end address */ 382 #define HOST_CLUST_UTIL_PHYS_LIMIT 0x23FFFFFFFULL 383 384 /* Base address for IO Block memory region */ 385 #define HOST_IO_BLOCK_PHYS_BASE HOST_IO_TCU_PHYS_BASE(0) 386 /* End address for IO Block memory region */ 387 #define HOST_IO_BLOCK_PHYS_LIMIT HOST_IO_PCIE_CTRL_EXP_PHYS_LIMIT(11) 388 389 /* SYSCTRL SMMU base address */ 390 #define HOST_SYSCTRL_SMMU_PHYS_BASE 0x300000000ULL 391 /* SYSCTRL SMMU end address */ 392 #define HOST_SYSCTRL_SMMU_PHYS_LIMIT 0x307FFFFFFULL 393 394 /* Debug Memory map base address */ 395 #define HOST_DEBUG_MMAP_PHYS_BASE 0x400000000ULL 396 /* Debug Memory map end address */ 397 #define HOST_DEBUG_MMAP_PHYS_LIMIT 0x5FFFFFFFFULL 398 /* AP Memory Expansion region 2 base address */ 399 #define HOST_AP_MEM_EXP_2_PHYS_BASE 0x600000000ULL 400 /* AP Memory Expansion region 2 end address */ 401 #define HOST_AP_MEM_EXP_2_PHYS_LIMIT 0x7FFFFFFFFULL 402 403 /* Address offset of AP region of different chips */ 404 #define HOST_AP_CHIP_OFFSET 0x1000000000ULL 405 /* Base address of the AP region of the nth chip */ 406 #define HOST_AP_CHIP_N_PHYS_BASE(n) (0x0ULL + \ 407 HOST_AP_CHIP_OFFSET * (n)) 408 /* End address of the AP region of the nth chip */ 409 #define HOST_AP_CHIP_N_PHYS_LIMIT(n) (0xFFFFFFFFFULL + \ 410 HOST_AP_CHIP_OFFSET * (n)) 411 412 /* PCIe NCI Memory space 2 base address */ 413 #define HOST_PCIE_NCI_2_PHYS_BASE 0x4000000000ULL 414 /* PCIe NCI Memory space 2 end address */ 415 #define HOST_PCIE_NCI_2_PHYS_LIMIT 0x403FFFFFFFULL 416 /* PCIe NCI Memory space 3 base address */ 417 #define HOST_PCIE_NCI_3_PHYS_BASE 0x4040000000ULL 418 /* PCIe NCI Memory space 3 end address */ 419 #define HOST_PCIE_NCI_3_PHYS_LIMIT 0x807FFFFFFFULL 420 421 /* AP Memory Expansion region 3 base address */ 422 #define HOST_AP_MEM_EXP_3_PHYS_BASE 0xC00000000000ULL 423 /* AP Memory Expansion region 3 end address */ 424 #define HOST_AP_MEM_EXP_3_PHYS_LIMIT 0xFFFFFFFFFFFFULL 425 426 #endif /* __HOST_CSS_MEMORY_MAP_H__ */ 427
