1 /* 2 * Copyright (c) 2024 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file host_css_io_block_memory_map.h 19 * \brief This file contains addresses that are defined in the compute 20 * subsystem (CSS) memory map for IO Block. 21 */ 22 23 #ifndef __HOST_CSS_IO_BLOCK_MEMORY_MAP_H__ 24 #define __HOST_CSS_IO_BLOCK_MEMORY_MAP_H__ 25 26 /* IO Block memory region offset value */ 27 #define HOST_IO_BLOCK_COMP_OFFSET 0x8000000ULL 28 /* Base address for TCU */ 29 #define HOST_IO_TCU_PHYS_BASE(n) (0x280000000ULL + \ 30 (HOST_IO_BLOCK_COMP_OFFSET * (n))) 31 /* End address for TCU */ 32 #define HOST_IO_TCU_PHYS_LIMIT(n) (0x283FFFFFFULL + \ 33 (HOST_IO_BLOCK_COMP_OFFSET * (n))) 34 /* Base address for NCI GPV Space */ 35 #define HOST_IO_NCI_GPV_PHYS_BASE(n) (0x284000000ULL + \ 36 (HOST_IO_BLOCK_COMP_OFFSET * (n))) 37 /* End address for NCI GPV Space */ 38 #define HOST_IO_NCI_GPV_PHYS_LIMIT(n) (0x284FFFFFFULL + \ 39 (HOST_IO_BLOCK_COMP_OFFSET * (n))) 40 /* Base address for IO Integration Control registers */ 41 #define HOST_IO_INTEGRATION_CTRL_PHYS_BASE(n) (0x285B00000ULL + \ 42 (HOST_IO_BLOCK_COMP_OFFSET * (n))) 43 /* End address for IO Integration Control registers */ 44 #define HOST_IO_INTEGRATION_CTRL_PHYS_LIMIT(n) (0x285B0FFFFULL + \ 45 (HOST_IO_BLOCK_COMP_OFFSET * (n))) 46 /* Base address for PHY Expansion interface */ 47 #define HOST_IO_EXP_INTERFACE_PHYS_BASE(n) (0x285C00000ULL + \ 48 (HOST_IO_BLOCK_COMP_OFFSET * (n))) 49 /* End address for PHY Expansion interface */ 50 #define HOST_IO_EXP_INTERFACE_PHYS_LIMIT(n) (0x285FFFFFFULL + \ 51 (HOST_IO_BLOCK_COMP_OFFSET * (n))) 52 /* Base address for PCIe Controller Expansion interface */ 53 #define HOST_IO_PCIE_CTRL_EXP_PHYS_BASE(n) (0x286000000ULL + \ 54 (HOST_IO_BLOCK_COMP_OFFSET * (n))) 55 /* End address for PCIe Controller Expansion interface */ 56 #define HOST_IO_PCIE_CTRL_EXP_PHYS_LIMIT(n) (0x287FFFFFFULL + \ 57 (HOST_IO_BLOCK_COMP_OFFSET * (n))) 58 59 #endif /* __HOST_CSS_IO_BLOCK_MEMORY_MAP_H__ */ 60
