1 /* 2 Copyright (c) 2010 - 2025, Nordic Semiconductor ASA All rights reserved. 3 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, this 10 list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of Nordic Semiconductor ASA nor the names of its 17 contributors may be used to endorse or promote products derived from this 18 software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 * 32 * @file nrf5340_application.h 33 * @brief CMSIS HeaderFile 34 * @version 1 35 * @date 07. January 2025 36 * @note Generated by SVDConv V3.3.35 on Tuesday, 07.01.2025 15:34:18 37 * from File 'nrf5340_application.svd', 38 * last modified on Friday, 13.12.2024 08:41:10 39 */ 40 41 42 43 /** @addtogroup Nordic Semiconductor 44 * @{ 45 */ 46 47 48 /** @addtogroup nrf5340_application 49 * @{ 50 */ 51 52 53 #ifndef NRF5340_APPLICATION_H 54 #define NRF5340_APPLICATION_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 61 /** @addtogroup Configuration_of_CMSIS 62 * @{ 63 */ 64 65 66 67 /* =========================================================================================================================== */ 68 /* ================ Interrupt Number Definition ================ */ 69 /* =========================================================================================================================== */ 70 71 typedef enum { 72 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 73 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 74 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 75 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 76 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 77 and No Match */ 78 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 79 related Fault */ 80 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 81 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 82 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 83 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 84 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 85 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 86 /* ==================================== nrf5340_application Specific Interrupt Numbers ===================================== */ 87 FPU_IRQn = 0, /*!< 0 FPU */ 88 CACHE_IRQn = 1, /*!< 1 CACHE */ 89 SPU_IRQn = 3, /*!< 3 SPU */ 90 CLOCK_POWER_IRQn = 5, /*!< 5 CLOCK_POWER */ 91 SERIAL0_IRQn = 8, /*!< 8 SERIAL0 */ 92 SERIAL1_IRQn = 9, /*!< 9 SERIAL1 */ 93 SPIM4_IRQn = 10, /*!< 10 SPIM4 */ 94 SERIAL2_IRQn = 11, /*!< 11 SERIAL2 */ 95 SERIAL3_IRQn = 12, /*!< 12 SERIAL3 */ 96 GPIOTE0_IRQn = 13, /*!< 13 GPIOTE0 */ 97 SAADC_IRQn = 14, /*!< 14 SAADC */ 98 TIMER0_IRQn = 15, /*!< 15 TIMER0 */ 99 TIMER1_IRQn = 16, /*!< 16 TIMER1 */ 100 TIMER2_IRQn = 17, /*!< 17 TIMER2 */ 101 RTC0_IRQn = 20, /*!< 20 RTC0 */ 102 RTC1_IRQn = 21, /*!< 21 RTC1 */ 103 WDT0_IRQn = 24, /*!< 24 WDT0 */ 104 WDT1_IRQn = 25, /*!< 25 WDT1 */ 105 COMP_LPCOMP_IRQn = 26, /*!< 26 COMP_LPCOMP */ 106 EGU0_IRQn = 27, /*!< 27 EGU0 */ 107 EGU1_IRQn = 28, /*!< 28 EGU1 */ 108 EGU2_IRQn = 29, /*!< 29 EGU2 */ 109 EGU3_IRQn = 30, /*!< 30 EGU3 */ 110 EGU4_IRQn = 31, /*!< 31 EGU4 */ 111 EGU5_IRQn = 32, /*!< 32 EGU5 */ 112 PWM0_IRQn = 33, /*!< 33 PWM0 */ 113 PWM1_IRQn = 34, /*!< 34 PWM1 */ 114 PWM2_IRQn = 35, /*!< 35 PWM2 */ 115 PWM3_IRQn = 36, /*!< 36 PWM3 */ 116 PDM0_IRQn = 38, /*!< 38 PDM0 */ 117 I2S0_IRQn = 40, /*!< 40 I2S0 */ 118 IPC_IRQn = 42, /*!< 42 IPC */ 119 QSPI_IRQn = 43, /*!< 43 QSPI */ 120 NFCT_IRQn = 45, /*!< 45 NFCT */ 121 GPIOTE1_IRQn = 47, /*!< 47 GPIOTE1 */ 122 QDEC0_IRQn = 51, /*!< 51 QDEC0 */ 123 QDEC1_IRQn = 52, /*!< 52 QDEC1 */ 124 USBD_IRQn = 54, /*!< 54 USBD */ 125 USBREGULATOR_IRQn = 55, /*!< 55 USBREGULATOR */ 126 KMU_IRQn = 57, /*!< 57 KMU */ 127 CRYPTOCELL_IRQn = 68 /*!< 68 CRYPTOCELL */ 128 } IRQn_Type; 129 130 131 132 /* =========================================================================================================================== */ 133 /* ================ Processor and Core Peripheral Section ================ */ 134 /* =========================================================================================================================== */ 135 136 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 137 #define __CM33_REV 0x0004U /*!< CM33 Core Revision */ 138 #define __INTERRUPTS_MAX 240 /*!< Top interrupt number */ 139 #define __DSP_PRESENT 1 /*!< DSP present or not */ 140 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 141 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 142 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 143 #define __MPU_PRESENT 1 /*!< MPU present */ 144 #define __FPU_PRESENT 1 /*!< FPU present */ 145 #define __FPU_DP 0 /*!< Double Precision FPU */ 146 #define __SAUREGION_PRESENT 0 /*!< SAU region present */ 147 148 149 /** @} */ /* End of group Configuration_of_CMSIS */ 150 151 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 152 #include "system_nrf5340_application.h" /*!< nrf5340_application System */ 153 154 #ifndef __IM /*!< Fallback for older CMSIS versions */ 155 #define __IM __I 156 #endif 157 #ifndef __OM /*!< Fallback for older CMSIS versions */ 158 #define __OM __O 159 #endif 160 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 161 #define __IOM __IO 162 #endif 163 164 165 /* =========================================================================================================================== */ 166 /* ================ Device Specific Cluster Section ================ */ 167 /* =========================================================================================================================== */ 168 169 170 /** @addtogroup Device_Peripheral_clusters 171 * @{ 172 */ 173 174 175 /** 176 * @brief CACHEDATA_SET_WAY [WAY] (Unspecified) 177 */ 178 typedef struct { 179 __IOM uint32_t DATA0; /*!< (@ 0x00000000) Description cluster: Cache data bits [31:0] of 180 SET[n], WAY[o]. */ 181 __IOM uint32_t DATA1; /*!< (@ 0x00000004) Description cluster: Cache data bits [63:32] 182 of SET[n], WAY[o]. */ 183 __IOM uint32_t DATA2; /*!< (@ 0x00000008) Description cluster: Cache data bits [95:64] 184 of SET[n], WAY[o]. */ 185 __IOM uint32_t DATA3; /*!< (@ 0x0000000C) Description cluster: Cache data bits [127:96] 186 of SET[n], WAY[o]. */ 187 } CACHEDATA_SET_WAY_Type; /*!< Size = 16 (0x10) */ 188 189 190 /** 191 * @brief CACHEDATA_SET [SET] (Unspecified) 192 */ 193 typedef struct { 194 __IOM CACHEDATA_SET_WAY_Type WAY[2]; /*!< (@ 0x00000000) Unspecified */ 195 } CACHEDATA_SET_Type; /*!< Size = 32 (0x20) */ 196 197 198 /** 199 * @brief CACHEINFO_SET [SET] (Unspecified) 200 */ 201 typedef struct { 202 __IOM uint32_t WAY[2]; /*!< (@ 0x00000000) Description collection: Cache information for 203 SET[n], WAY[o]. */ 204 } CACHEINFO_SET_Type; /*!< Size = 8 (0x8) */ 205 206 207 /** 208 * @brief FICR_INFO [INFO] (Device info) 209 */ 210 typedef struct { 211 __IM uint32_t CONFIGID; /*!< (@ 0x00000000) Configuration identifier */ 212 __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000004) Description collection: Device identifier */ 213 __IM uint32_t PART; /*!< (@ 0x0000000C) Part code */ 214 __IM uint32_t VARIANT; /*!< (@ 0x00000010) Part Variant, Hardware version and Production 215 configuration */ 216 __IM uint32_t PACKAGE; /*!< (@ 0x00000014) Package option */ 217 __IM uint32_t RAM; /*!< (@ 0x00000018) RAM variant */ 218 __IM uint32_t FLASH; /*!< (@ 0x0000001C) Flash variant */ 219 __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000020) Code memory page size in bytes */ 220 __IM uint32_t CODESIZE; /*!< (@ 0x00000024) Code memory size */ 221 __IM uint32_t DEVICETYPE; /*!< (@ 0x00000028) Device type */ 222 } FICR_INFO_Type; /*!< Size = 44 (0x2c) */ 223 224 225 /** 226 * @brief FICR_TRIMCNF [TRIMCNF] (Unspecified) 227 */ 228 typedef struct { 229 __IM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Address of the PAR register 230 which will be written */ 231 __IM uint32_t DATA; /*!< (@ 0x00000004) Description cluster: Data */ 232 } FICR_TRIMCNF_Type; /*!< Size = 8 (0x8) */ 233 234 235 /** 236 * @brief FICR_NFC [NFC] (Unspecified) 237 */ 238 typedef struct { 239 __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read 240 these values to populate NFCID1_3RD_LAST, 241 NFCID1_2ND_LAST and NFCID1_LAST. */ 242 __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read 243 these values to populate NFCID1_3RD_LAST, 244 NFCID1_2ND_LAST and NFCID1_LAST. */ 245 __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read 246 these values to populate NFCID1_3RD_LAST, 247 NFCID1_2ND_LAST and NFCID1_LAST. */ 248 __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read 249 these values to populate NFCID1_3RD_LAST, 250 NFCID1_2ND_LAST and NFCID1_LAST. */ 251 } FICR_NFC_Type; /*!< Size = 16 (0x10) */ 252 253 254 /** 255 * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) 256 */ 257 typedef struct { 258 __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ 259 __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ 260 __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ 261 __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ 262 __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ 263 __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ 264 __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ 265 __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ 266 } FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ 267 268 269 /** 270 * @brief UICR_KEYSLOT_CONFIG [CONFIG] (Unspecified) 271 */ 272 typedef struct { 273 __IOM uint32_t DEST; /*!< (@ 0x00000000) Description cluster: Destination address where 274 content of the key value registers (KEYSLOT.KEYn.VALUE[0-3 275 ) will be pushed by KMU. Note that this 276 address must match that of a peripherals 277 APB mapped write-only key registers, else 278 the KMU can push this key value into an 279 address range which the CPU can potentially 280 read. */ 281 __IOM uint32_t PERM; /*!< (@ 0x00000004) Description cluster: Define permissions for the 282 key slot. Bits 0-15 and 16-31 can only be 283 written when equal to 0xFFFF. */ 284 } UICR_KEYSLOT_CONFIG_Type; /*!< Size = 8 (0x8) */ 285 286 287 /** 288 * @brief UICR_KEYSLOT_KEY [KEY] (Unspecified) 289 */ 290 typedef struct { 291 __IOM uint32_t VALUE[4]; /*!< (@ 0x00000000) Description collection: Define bits [31+o*32:0+o*32] 292 of value assigned to KMU key slot. */ 293 } UICR_KEYSLOT_KEY_Type; /*!< Size = 16 (0x10) */ 294 295 296 /** 297 * @brief UICR_KEYSLOT [KEYSLOT] (Unspecified) 298 */ 299 typedef struct { 300 __IOM UICR_KEYSLOT_CONFIG_Type CONFIG[128]; /*!< (@ 0x00000000) Unspecified */ 301 __IOM UICR_KEYSLOT_KEY_Type KEY[128]; /*!< (@ 0x00000400) Unspecified */ 302 } UICR_KEYSLOT_Type; /*!< Size = 3072 (0xc00) */ 303 304 305 /** 306 * @brief TAD_PSEL [PSEL] (Unspecified) 307 */ 308 typedef struct { 309 __IOM uint32_t TRACECLK; /*!< (@ 0x00000000) Pin configuration for TRACECLK */ 310 __IOM uint32_t TRACEDATA0; /*!< (@ 0x00000004) Pin configuration for TRACEDATA[0] */ 311 __IOM uint32_t TRACEDATA1; /*!< (@ 0x00000008) Pin configuration for TRACEDATA[1] */ 312 __IOM uint32_t TRACEDATA2; /*!< (@ 0x0000000C) Pin configuration for TRACEDATA[2] */ 313 __IOM uint32_t TRACEDATA3; /*!< (@ 0x00000010) Pin configuration for TRACEDATA[3] */ 314 } TAD_PSEL_Type; /*!< Size = 20 (0x14) */ 315 316 317 /** 318 * @brief DCNF_EXTPERI [EXTPERI] (Unspecified) 319 */ 320 typedef struct { 321 __IOM uint32_t PROTECT; /*!< (@ 0x00000000) Description cluster: Control access for master 322 connected to AMLI master port EXTPERI[n] */ 323 } DCNF_EXTPERI_Type; /*!< Size = 4 (0x4) */ 324 325 326 /** 327 * @brief DCNF_EXTRAM [EXTRAM] (Unspecified) 328 */ 329 typedef struct { 330 __IOM uint32_t PROTECT; /*!< (@ 0x00000000) Description cluster: Control access from master 331 connected to AMLI master port EXTRAM[n] */ 332 } DCNF_EXTRAM_Type; /*!< Size = 4 (0x4) */ 333 334 335 /** 336 * @brief DCNF_EXTCODE [EXTCODE] (Unspecified) 337 */ 338 typedef struct { 339 __IOM uint32_t PROTECT; /*!< (@ 0x00000000) Description cluster: Control access from master 340 connected to AMLI master port EXTCODE[n] */ 341 } DCNF_EXTCODE_Type; /*!< Size = 4 (0x4) */ 342 343 344 /** 345 * @brief CACHE_PROFILING [PROFILING] (Unspecified) 346 */ 347 typedef struct { 348 __IM uint32_t IHIT; /*!< (@ 0x00000000) Description cluster: Instruction fetch cache 349 hit counter for cache region n, where n=0 350 means Flash and n=1 means XIP. */ 351 __IM uint32_t IMISS; /*!< (@ 0x00000004) Description cluster: Instruction fetch cache 352 miss counter for cache region n, where n=0 353 means Flash and n=1 means XIP. */ 354 __IM uint32_t DHIT; /*!< (@ 0x00000008) Description cluster: Data fetch cache hit counter 355 for cache region n, where n=0 means Flash 356 and n=1 means XIP. */ 357 __IM uint32_t DMISS; /*!< (@ 0x0000000C) Description cluster: Data fetch cache miss counter 358 for cache region n, where n=0 means Flash 359 and n=1 means XIP. */ 360 __IM uint32_t RESERVED[4]; 361 } CACHE_PROFILING_Type; /*!< Size = 32 (0x20) */ 362 363 364 /** 365 * @brief SPU_EXTDOMAIN [EXTDOMAIN] (Unspecified) 366 */ 367 typedef struct { 368 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access for bus access generated 369 from the external domain n List capabilities 370 of the external domain n */ 371 } SPU_EXTDOMAIN_Type; /*!< Size = 4 (0x4) */ 372 373 374 /** 375 * @brief SPU_DPPI [DPPI] (Unspecified) 376 */ 377 typedef struct { 378 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 379 non-secure attribute for the DPPI channels */ 380 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 381 of the corresponding PERM register */ 382 } SPU_DPPI_Type; /*!< Size = 8 (0x8) */ 383 384 385 /** 386 * @brief SPU_GPIOPORT [GPIOPORT] (Unspecified) 387 */ 388 typedef struct { 389 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Select between secure and 390 non-secure attribute for pins 0 to 31 of 391 port n */ 392 __IOM uint32_t LOCK; /*!< (@ 0x00000004) Description cluster: Prevent further modification 393 of the corresponding PERM register */ 394 } SPU_GPIOPORT_Type; /*!< Size = 8 (0x8) */ 395 396 397 /** 398 * @brief SPU_FLASHNSC [FLASHNSC] (Unspecified) 399 */ 400 typedef struct { 401 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which flash region 402 can contain the non-secure callable (NSC) 403 region n */ 404 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 405 callable (NSC) region n */ 406 } SPU_FLASHNSC_Type; /*!< Size = 8 (0x8) */ 407 408 409 /** 410 * @brief SPU_RAMNSC [RAMNSC] (Unspecified) 411 */ 412 typedef struct { 413 __IOM uint32_t REGION; /*!< (@ 0x00000000) Description cluster: Define which RAM region 414 can contain the non-secure callable (NSC) 415 region n */ 416 __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Define the size of the non-secure 417 callable (NSC) region n */ 418 } SPU_RAMNSC_Type; /*!< Size = 8 (0x8) */ 419 420 421 /** 422 * @brief SPU_FLASHREGION [FLASHREGION] (Unspecified) 423 */ 424 typedef struct { 425 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for flash 426 region n */ 427 } SPU_FLASHREGION_Type; /*!< Size = 4 (0x4) */ 428 429 430 /** 431 * @brief SPU_RAMREGION [RAMREGION] (Unspecified) 432 */ 433 typedef struct { 434 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: Access permissions for RAM 435 region n */ 436 } SPU_RAMREGION_Type; /*!< Size = 4 (0x4) */ 437 438 439 /** 440 * @brief SPU_PERIPHID [PERIPHID] (Unspecified) 441 */ 442 typedef struct { 443 __IOM uint32_t PERM; /*!< (@ 0x00000000) Description cluster: List capabilities and access 444 permissions for the peripheral with ID n */ 445 } SPU_PERIPHID_Type; /*!< Size = 4 (0x4) */ 446 447 448 /** 449 * @brief OSCILLATORS_XOSC32KI [XOSC32KI] (Unspecified) 450 */ 451 typedef struct { 452 __IOM uint32_t BYPASS; /*!< (@ 0x00000000) Enable or disable bypass of LFCLK crystal oscillator 453 with external clock source */ 454 __IM uint32_t RESERVED[3]; 455 __IOM uint32_t INTCAP; /*!< (@ 0x00000010) Control usage of internal load capacitors */ 456 } OSCILLATORS_XOSC32KI_Type; /*!< Size = 20 (0x14) */ 457 458 459 /** 460 * @brief REGULATORS_VREGMAIN [VREGMAIN] (Unspecified) 461 */ 462 typedef struct { 463 __IOM uint32_t DCDCEN; /*!< (@ 0x00000000) DC/DC enable register for VREGMAIN */ 464 } REGULATORS_VREGMAIN_Type; /*!< Size = 4 (0x4) */ 465 466 467 /** 468 * @brief REGULATORS_VREGRADIO [VREGRADIO] (Unspecified) 469 */ 470 typedef struct { 471 __IM uint32_t RESERVED; 472 __IOM uint32_t DCDCEN; /*!< (@ 0x00000004) DC/DC enable register for VREGRADIO */ 473 } REGULATORS_VREGRADIO_Type; /*!< Size = 8 (0x8) */ 474 475 476 /** 477 * @brief REGULATORS_VREGH [VREGH] (Unspecified) 478 */ 479 typedef struct { 480 __IOM uint32_t DCDCEN; /*!< (@ 0x00000000) DC/DC enable register for VREGH */ 481 __IM uint32_t RESERVED[15]; 482 __IOM uint32_t EXTSILENTEN; /*!< (@ 0x00000040) When VREGH is in DC/DC mode, enable VREGH silent 483 mode to supply external components from 484 VDD. Silent mode has lower voltage ripple. 485 Silent mode is used when DC/DC is enabled, 486 and is ignored in LDO mode. Disabling silent 487 mode reduces current consumption in sleep. */ 488 } REGULATORS_VREGH_Type; /*!< Size = 68 (0x44) */ 489 490 491 /** 492 * @brief CLOCK_HFCLKAUDIO [HFCLKAUDIO] (Unspecified) 493 */ 494 typedef struct { 495 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000000) Audio PLL frequency in 11.176 MHz - 11.402 MHz 496 or 12.165 MHz - 12.411 MHz frequency bands */ 497 } CLOCK_HFCLKAUDIO_Type; /*!< Size = 4 (0x4) */ 498 499 500 /** 501 * @brief RESET_NETWORK [NETWORK] (Unspecified) 502 */ 503 typedef struct { 504 __IM uint32_t RESERVED; 505 __IOM uint32_t FORCEOFF; /*!< (@ 0x00000004) Force network core off */ 506 } RESET_NETWORK_Type; /*!< Size = 8 (0x8) */ 507 508 509 /** 510 * @brief CTRLAPPERI_MAILBOX [MAILBOX] (Unspecified) 511 */ 512 typedef struct { 513 __IM uint32_t RXDATA; /*!< (@ 0x00000000) Data sent from the debugger to the CPU. */ 514 __IM uint32_t RXSTATUS; /*!< (@ 0x00000004) This register shows a status that indicates if 515 data sent from the debugger to the CPU has 516 been read. */ 517 __IM uint32_t RESERVED[30]; 518 __IOM uint32_t TXDATA; /*!< (@ 0x00000080) Data sent from the CPU to the debugger. */ 519 __IM uint32_t TXSTATUS; /*!< (@ 0x00000084) This register shows a status that indicates if 520 the data sent from the CPU to the debugger 521 has been read. */ 522 } CTRLAPPERI_MAILBOX_Type; /*!< Size = 136 (0x88) */ 523 524 525 /** 526 * @brief CTRLAPPERI_ERASEPROTECT [ERASEPROTECT] (Unspecified) 527 */ 528 typedef struct { 529 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the ERASEPROTECT.DISABLE 530 register from being written until next reset. */ 531 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the ERASEPROTECT register 532 and performs an ERASEALL operation. */ 533 } CTRLAPPERI_ERASEPROTECT_Type; /*!< Size = 8 (0x8) */ 534 535 536 /** 537 * @brief CTRLAPPERI_APPROTECT [APPROTECT] (Unspecified) 538 */ 539 typedef struct { 540 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the APPROTECT.DISABLE register 541 from being written to until next reset. */ 542 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the APPROTECT register 543 and enables debug access to non-secure mode. */ 544 } CTRLAPPERI_APPROTECT_Type; /*!< Size = 8 (0x8) */ 545 546 547 /** 548 * @brief CTRLAPPERI_SECUREAPPROTECT [SECUREAPPROTECT] (Unspecified) 549 */ 550 typedef struct { 551 __IOM uint32_t LOCK; /*!< (@ 0x00000000) This register locks the SECUREAPPROTECT.DISABLE 552 register from being written until next reset. */ 553 __IOM uint32_t DISABLE; /*!< (@ 0x00000004) This register disables the SECUREAPPROTECT register 554 and enables debug access to secure mode. */ 555 } CTRLAPPERI_SECUREAPPROTECT_Type; /*!< Size = 8 (0x8) */ 556 557 558 /** 559 * @brief SPIM_PSEL [PSEL] (Unspecified) 560 */ 561 typedef struct { 562 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 563 __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ 564 __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ 565 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ 566 } SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ 567 568 569 /** 570 * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) 571 */ 572 typedef struct { 573 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 574 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 575 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 576 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 577 } SPIM_RXD_Type; /*!< Size = 16 (0x10) */ 578 579 580 /** 581 * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) 582 */ 583 typedef struct { 584 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 585 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ 586 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 587 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 588 } SPIM_TXD_Type; /*!< Size = 16 (0x10) */ 589 590 591 /** 592 * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) 593 */ 594 typedef struct { 595 __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ 596 __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge 597 of SCK. When SHORTS.END_START is used, this 598 is also the minimum duration CSN must stay 599 high between transactions. */ 600 } SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ 601 602 603 /** 604 * @brief SPIS_PSEL [PSEL] (Unspecified) 605 */ 606 typedef struct { 607 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ 608 __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ 609 __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ 610 __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ 611 } SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ 612 613 614 /** 615 * @brief SPIS_RXD [RXD] (Unspecified) 616 */ 617 typedef struct { 618 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ 619 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 620 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ 621 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 622 } SPIS_RXD_Type; /*!< Size = 16 (0x10) */ 623 624 625 /** 626 * @brief SPIS_TXD [TXD] (Unspecified) 627 */ 628 typedef struct { 629 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ 630 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 631 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ 632 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 633 } SPIS_TXD_Type; /*!< Size = 16 (0x10) */ 634 635 636 /** 637 * @brief TWIM_PSEL [PSEL] (Unspecified) 638 */ 639 typedef struct { 640 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 641 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 642 } TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ 643 644 645 /** 646 * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) 647 */ 648 typedef struct { 649 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 650 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 651 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 652 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 653 } TWIM_RXD_Type; /*!< Size = 16 (0x10) */ 654 655 656 /** 657 * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) 658 */ 659 typedef struct { 660 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 661 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 662 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 663 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 664 } TWIM_TXD_Type; /*!< Size = 16 (0x10) */ 665 666 667 /** 668 * @brief TWIS_PSEL [PSEL] (Unspecified) 669 */ 670 typedef struct { 671 __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ 672 __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ 673 } TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ 674 675 676 /** 677 * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) 678 */ 679 typedef struct { 680 __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ 681 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ 682 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ 683 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 684 } TWIS_RXD_Type; /*!< Size = 16 (0x10) */ 685 686 687 /** 688 * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) 689 */ 690 typedef struct { 691 __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ 692 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ 693 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ 694 __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ 695 } TWIS_TXD_Type; /*!< Size = 16 (0x10) */ 696 697 698 /** 699 * @brief UARTE_PSEL [PSEL] (Unspecified) 700 */ 701 typedef struct { 702 __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ 703 __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ 704 __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ 705 __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ 706 } UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ 707 708 709 /** 710 * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) 711 */ 712 typedef struct { 713 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 714 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ 715 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 716 } UARTE_RXD_Type; /*!< Size = 12 (0xc) */ 717 718 719 /** 720 * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) 721 */ 722 typedef struct { 723 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 724 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ 725 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 726 } UARTE_TXD_Type; /*!< Size = 12 (0xc) */ 727 728 729 /** 730 * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) 731 */ 732 typedef struct { 733 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last results is equal or 734 above CH[n].LIMIT.HIGH */ 735 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last results is equal or 736 below CH[n].LIMIT.LOW */ 737 } SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ 738 739 740 /** 741 * @brief SAADC_PUBLISH_CH [PUBLISH_CH] (Publish configuration for events) 742 */ 743 typedef struct { 744 __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Publish configuration for 745 event CH[n].LIMITH */ 746 __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Publish configuration for 747 event CH[n].LIMITL */ 748 } SAADC_PUBLISH_CH_Type; /*!< Size = 8 (0x8) */ 749 750 751 /** 752 * @brief SAADC_CH [CH] (Unspecified) 753 */ 754 typedef struct { 755 __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection 756 for CH[n] */ 757 __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection 758 for CH[n] */ 759 __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for 760 CH[n] */ 761 __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event 762 monitoring a channel */ 763 } SAADC_CH_Type; /*!< Size = 16 (0x10) */ 764 765 766 /** 767 * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) 768 */ 769 typedef struct { 770 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 771 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ 772 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last 773 START */ 774 } SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ 775 776 777 /** 778 * @brief DPPIC_TASKS_CHG [TASKS_CHG] (Channel group tasks) 779 */ 780 typedef struct { 781 __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ 782 __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ 783 } DPPIC_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ 784 785 786 /** 787 * @brief DPPIC_SUBSCRIBE_CHG [SUBSCRIBE_CHG] (Subscribe configuration for tasks) 788 */ 789 typedef struct { 790 __IOM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Subscribe configuration 791 for task CHG[n].EN */ 792 __IOM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Subscribe configuration 793 for task CHG[n].DIS */ 794 } DPPIC_SUBSCRIBE_CHG_Type; /*!< Size = 8 (0x8) */ 795 796 797 /** 798 * @brief PWM_SEQ [SEQ] (Unspecified) 799 */ 800 typedef struct { 801 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM 802 of this sequence */ 803 __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) 804 in this sequence */ 805 __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM 806 periods between samples loaded into compare 807 register */ 808 __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ 809 __IM uint32_t RESERVED[4]; 810 } PWM_SEQ_Type; /*!< Size = 32 (0x20) */ 811 812 813 /** 814 * @brief PWM_PSEL [PSEL] (Unspecified) 815 */ 816 typedef struct { 817 __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for 818 PWM channel n */ 819 } PWM_PSEL_Type; /*!< Size = 16 (0x10) */ 820 821 822 /** 823 * @brief PDM_PSEL [PSEL] (Unspecified) 824 */ 825 typedef struct { 826 __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ 827 __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ 828 } PDM_PSEL_Type; /*!< Size = 8 (0x8) */ 829 830 831 /** 832 * @brief PDM_SAMPLE [SAMPLE] (Unspecified) 833 */ 834 typedef struct { 835 __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with 836 EasyDMA */ 837 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA 838 mode */ 839 } PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ 840 841 842 /** 843 * @brief I2S_CONFIG [CONFIG] (Unspecified) 844 */ 845 typedef struct { 846 __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode */ 847 __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable */ 848 __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable */ 849 __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable */ 850 __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) I2S clock generator control */ 851 __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio */ 852 __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width */ 853 __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame */ 854 __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format */ 855 __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels */ 856 __IOM uint32_t CLKCONFIG; /*!< (@ 0x00000028) Clock source selection for the I2S module */ 857 } I2S_CONFIG_Type; /*!< Size = 44 (0x2c) */ 858 859 860 /** 861 * @brief I2S_RXD [RXD] (Unspecified) 862 */ 863 typedef struct { 864 __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ 865 } I2S_RXD_Type; /*!< Size = 4 (0x4) */ 866 867 868 /** 869 * @brief I2S_TXD [TXD] (Unspecified) 870 */ 871 typedef struct { 872 __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address */ 873 } I2S_TXD_Type; /*!< Size = 4 (0x4) */ 874 875 876 /** 877 * @brief I2S_RXTXD [RXTXD] (Unspecified) 878 */ 879 typedef struct { 880 __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers */ 881 } I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ 882 883 884 /** 885 * @brief I2S_PSEL [PSEL] (Unspecified) 886 */ 887 typedef struct { 888 __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal */ 889 __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal */ 890 __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal */ 891 __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal */ 892 __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal */ 893 } I2S_PSEL_Type; /*!< Size = 20 (0x14) */ 894 895 896 /** 897 * @brief QSPI_READ [READ] (Unspecified) 898 */ 899 typedef struct { 900 __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ 901 __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ 902 __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ 903 } QSPI_READ_Type; /*!< Size = 12 (0xc) */ 904 905 906 /** 907 * @brief QSPI_WRITE [WRITE] (Unspecified) 908 */ 909 typedef struct { 910 __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ 911 __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ 912 __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ 913 } QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ 914 915 916 /** 917 * @brief QSPI_ERASE [ERASE] (Unspecified) 918 */ 919 typedef struct { 920 __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ 921 __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ 922 } QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ 923 924 925 /** 926 * @brief QSPI_PSEL [PSEL] (Unspecified) 927 */ 928 typedef struct { 929 __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ 930 __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ 931 __IM uint32_t RESERVED; 932 __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ 933 __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ 934 __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data WP/IO2. */ 935 __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data HOLD/IO3. */ 936 } QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ 937 938 939 /** 940 * @brief QSPI_XIP_ENC [XIP_ENC] (Unspecified) 941 */ 942 typedef struct { 943 __OM uint32_t KEY0; /*!< (@ 0x00000000) Bits 31:0 of XIP AES KEY */ 944 __OM uint32_t KEY1; /*!< (@ 0x00000004) Bits 63:32 of XIP AES KEY */ 945 __OM uint32_t KEY2; /*!< (@ 0x00000008) Bits 95:64 of XIP AES KEY */ 946 __OM uint32_t KEY3; /*!< (@ 0x0000000C) Bits 127:96 of XIP AES KEY */ 947 __OM uint32_t NONCE0; /*!< (@ 0x00000010) Bits 31:0 of XIP NONCE */ 948 __OM uint32_t NONCE1; /*!< (@ 0x00000014) Bits 63:32 of XIP NONCE */ 949 __OM uint32_t NONCE2; /*!< (@ 0x00000018) Bits 95:64 of XIP NONCE */ 950 __IOM uint32_t ENABLE; /*!< (@ 0x0000001C) Enable stream cipher for XIP */ 951 } QSPI_XIP_ENC_Type; /*!< Size = 32 (0x20) */ 952 953 954 /** 955 * @brief QSPI_DMA_ENC [DMA_ENC] (Unspecified) 956 */ 957 typedef struct { 958 __OM uint32_t KEY0; /*!< (@ 0x00000000) Bits 31:0 of DMA AES KEY */ 959 __OM uint32_t KEY1; /*!< (@ 0x00000004) Bits 63:32 of DMA AES KEY */ 960 __OM uint32_t KEY2; /*!< (@ 0x00000008) Bits 95:64 of DMA AES KEY */ 961 __OM uint32_t KEY3; /*!< (@ 0x0000000C) Bits 127:96 of DMA AES KEY */ 962 __OM uint32_t NONCE0; /*!< (@ 0x00000010) Bits 31:0 of DMA NONCE */ 963 __OM uint32_t NONCE1; /*!< (@ 0x00000014) Bits 63:32 of DMA NONCE */ 964 __OM uint32_t NONCE2; /*!< (@ 0x00000018) Bits 95:64 of DMA NONCE */ 965 __IOM uint32_t ENABLE; /*!< (@ 0x0000001C) Enable stream cipher for EasyDMA */ 966 } QSPI_DMA_ENC_Type; /*!< Size = 32 (0x20) */ 967 968 969 /** 970 * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) 971 */ 972 typedef struct { 973 __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ 974 } NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ 975 976 977 /** 978 * @brief NFCT_TXD [TXD] (Unspecified) 979 */ 980 typedef struct { 981 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ 982 __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ 983 } NFCT_TXD_Type; /*!< Size = 8 (0x8) */ 984 985 986 /** 987 * @brief NFCT_RXD [RXD] (Unspecified) 988 */ 989 typedef struct { 990 __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ 991 __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ 992 } NFCT_RXD_Type; /*!< Size = 8 (0x8) */ 993 994 995 /** 996 * @brief QDEC_PSEL [PSEL] (Unspecified) 997 */ 998 typedef struct { 999 __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ 1000 __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ 1001 __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ 1002 } QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ 1003 1004 1005 /** 1006 * @brief USBD_HALTED [HALTED] (Unspecified) 1007 */ 1008 typedef struct { 1009 __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. 1010 Can be used as is as response to a GetStatus() 1011 request to endpoint. */ 1012 __IM uint32_t RESERVED; 1013 __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. 1014 Can be used as is as response to a GetStatus() 1015 request to endpoint. */ 1016 } USBD_HALTED_Type; /*!< Size = 68 (0x44) */ 1017 1018 1019 /** 1020 * @brief USBD_SIZE [SIZE] (Unspecified) 1021 */ 1022 typedef struct { 1023 __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received 1024 last in the data stage of this OUT endpoint */ 1025 __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT 1026 data endpoint */ 1027 } USBD_SIZE_Type; /*!< Size = 36 (0x24) */ 1028 1029 1030 /** 1031 * @brief USBD_EPIN [EPIN] (Unspecified) 1032 */ 1033 typedef struct { 1034 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 1035 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 1036 to transfer */ 1037 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 1038 in the last transaction */ 1039 __IM uint32_t RESERVED[2]; 1040 } USBD_EPIN_Type; /*!< Size = 20 (0x14) */ 1041 1042 1043 /** 1044 * @brief USBD_ISOIN [ISOIN] (Unspecified) 1045 */ 1046 typedef struct { 1047 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 1048 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 1049 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 1050 } USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ 1051 1052 1053 /** 1054 * @brief USBD_EPOUT [EPOUT] (Unspecified) 1055 */ 1056 typedef struct { 1057 __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ 1058 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes 1059 to transfer */ 1060 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred 1061 in the last transaction */ 1062 __IM uint32_t RESERVED[2]; 1063 } USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ 1064 1065 1066 /** 1067 * @brief USBD_ISOOUT [ISOOUT] (Unspecified) 1068 */ 1069 typedef struct { 1070 __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ 1071 __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ 1072 __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ 1073 } USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ 1074 1075 1076 /** 1077 * @brief VMC_RAM [RAM] (Unspecified) 1078 */ 1079 typedef struct { 1080 __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAM[n] power control register */ 1081 __IOM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAM[n] power control set 1082 register */ 1083 __IOM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAM[n] power control clear 1084 register */ 1085 __IM uint32_t RESERVED; 1086 } VMC_RAM_Type; /*!< Size = 16 (0x10) */ 1087 1088 1089 /** @} */ /* End of group Device_Peripheral_clusters */ 1090 1091 1092 /* =========================================================================================================================== */ 1093 /* ================ Device Specific Peripheral Section ================ */ 1094 /* =========================================================================================================================== */ 1095 1096 1097 /** @addtogroup Device_Peripheral_peripherals 1098 * @{ 1099 */ 1100 1101 1102 1103 /* =========================================================================================================================== */ 1104 /* ================ CACHEDATA_S ================ */ 1105 /* =========================================================================================================================== */ 1106 1107 1108 /** 1109 * @brief CACHEDATA (CACHEDATA_S) 1110 */ 1111 1112 typedef struct { /*!< (@ 0x00F00000) CACHEDATA_S Structure */ 1113 __IOM CACHEDATA_SET_Type SET[256]; /*!< (@ 0x00000000) Unspecified */ 1114 } NRF_CACHEDATA_Type; /*!< Size = 8192 (0x2000) */ 1115 1116 1117 1118 /* =========================================================================================================================== */ 1119 /* ================ CACHEINFO_S ================ */ 1120 /* =========================================================================================================================== */ 1121 1122 1123 /** 1124 * @brief CACHEINFO (CACHEINFO_S) 1125 */ 1126 1127 typedef struct { /*!< (@ 0x00F08000) CACHEINFO_S Structure */ 1128 __IOM CACHEINFO_SET_Type SET[256]; /*!< (@ 0x00000000) Unspecified */ 1129 } NRF_CACHEINFO_Type; /*!< Size = 2048 (0x800) */ 1130 1131 1132 1133 /* =========================================================================================================================== */ 1134 /* ================ FICR_S ================ */ 1135 /* =========================================================================================================================== */ 1136 1137 1138 /** 1139 * @brief Factory Information Configuration Registers (FICR_S) 1140 */ 1141 1142 typedef struct { /*!< (@ 0x00FF0000) FICR_S Structure */ 1143 __IM uint32_t RESERVED[128]; 1144 __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000200) Device info */ 1145 __IM uint32_t RESERVED1[53]; 1146 __IOM FICR_TRIMCNF_Type TRIMCNF[32]; /*!< (@ 0x00000300) Unspecified */ 1147 __IM uint32_t RESERVED2[20]; 1148 __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ 1149 __IM uint32_t RESERVED3[488]; 1150 __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ 1151 __IM uint32_t XOSC32MTRIM; /*!< (@ 0x00000C20) XOSC32M capacitor selection trim values */ 1152 } NRF_FICR_Type; /*!< Size = 3108 (0xc24) */ 1153 1154 1155 1156 /* =========================================================================================================================== */ 1157 /* ================ UICR_S ================ */ 1158 /* =========================================================================================================================== */ 1159 1160 1161 /** 1162 * @brief User Information Configuration Registers User information configuration registers (UICR_S) 1163 */ 1164 1165 typedef struct { /*!< (@ 0x00FF8000) UICR_S Structure */ 1166 __IOM uint32_t APPROTECT; /*!< (@ 0x00000000) Access port protection */ 1167 __IM uint32_t RESERVED[3]; 1168 __IOM uint32_t VREGHVOUT; /*!< (@ 0x00000010) Output voltage from the high voltage (VREGH) 1169 regulator stage. The maximum output voltage 1170 from this stage is given as VDDH - VREGHDROP. */ 1171 __IOM uint32_t HFXOCNT; /*!< (@ 0x00000014) HFXO startup counter */ 1172 __IM uint32_t RESERVED1; 1173 __IOM uint32_t SECUREAPPROTECT; /*!< (@ 0x0000001C) Secure access port protection */ 1174 __IOM uint32_t ERASEPROTECT; /*!< (@ 0x00000020) Erase protection */ 1175 __IOM uint32_t TINSTANCE; /*!< (@ 0x00000024) SW-DP Target instance */ 1176 __IOM uint32_t NFCPINS; /*!< (@ 0x00000028) Setting of pins dedicated to NFC functionality: 1177 NFC antenna or GPIO */ 1178 __IM uint32_t RESERVED2[53]; 1179 __IOM uint32_t OTP[192]; /*!< (@ 0x00000100) Description collection: One time programmable 1180 memory */ 1181 __IOM UICR_KEYSLOT_Type KEYSLOT; /*!< (@ 0x00000400) Unspecified */ 1182 } NRF_UICR_Type; /*!< Size = 4096 (0x1000) */ 1183 1184 1185 1186 /* =========================================================================================================================== */ 1187 /* ================ CTI_S ================ */ 1188 /* =========================================================================================================================== */ 1189 1190 1191 /** 1192 * @brief Cross-Trigger Interface control. NOTE: this is not a separate peripheral, but describes CM33 functionality. (CTI_S) 1193 */ 1194 1195 typedef struct { /*!< (@ 0xE0042000) CTI_S Structure */ 1196 __IOM uint32_t CTICONTROL; /*!< (@ 0x00000000) CTI Control register */ 1197 __IM uint32_t RESERVED[3]; 1198 __OM uint32_t CTIINTACK; /*!< (@ 0x00000010) CTI Interrupt Acknowledge register */ 1199 __IOM uint32_t CTIAPPSET; /*!< (@ 0x00000014) CTI Application Trigger Set register */ 1200 __OM uint32_t CTIAPPCLEAR; /*!< (@ 0x00000018) CTI Application Trigger Clear register */ 1201 __OM uint32_t CTIAPPPULSE; /*!< (@ 0x0000001C) CTI Application Pulse register */ 1202 __IOM uint32_t CTIINEN[8]; /*!< (@ 0x00000020) Description collection: CTI Trigger to Channel 1203 Enable register */ 1204 __IM uint32_t RESERVED1[24]; 1205 __IOM uint32_t CTIOUTEN[8]; /*!< (@ 0x000000A0) Description collection: CTI Channel to Trigger 1206 Enable register */ 1207 __IM uint32_t RESERVED2[28]; 1208 __IM uint32_t CTITRIGINSTATUS; /*!< (@ 0x00000130) CTI Trigger In Status register */ 1209 __IM uint32_t CTITRIGOUTSTATUS; /*!< (@ 0x00000134) CTI Trigger Out Status register */ 1210 __IM uint32_t CTICHINSTATUS; /*!< (@ 0x00000138) CTI Channel In Status register */ 1211 __IM uint32_t RESERVED3; 1212 __IOM uint32_t CTIGATE; /*!< (@ 0x00000140) Enable CTI Channel Gate register */ 1213 __IM uint32_t RESERVED4[926]; 1214 __IM uint32_t DEVARCH; /*!< (@ 0x00000FBC) Device Architecture register */ 1215 __IM uint32_t RESERVED5[2]; 1216 __IM uint32_t DEVID; /*!< (@ 0x00000FC8) Device Configuration register */ 1217 __IM uint32_t DEVTYPE; /*!< (@ 0x00000FCC) Device Type Identifier register */ 1218 __IM uint32_t PIDR4; /*!< (@ 0x00000FD0) Peripheral ID4 Register */ 1219 __IM uint32_t PIDR5; /*!< (@ 0x00000FD4) Peripheral ID5 register */ 1220 __IM uint32_t PIDR6; /*!< (@ 0x00000FD8) Peripheral ID6 register */ 1221 __IM uint32_t PIDR7; /*!< (@ 0x00000FDC) Peripheral ID7 register */ 1222 __IM uint32_t PIDR0; /*!< (@ 0x00000FE0) Peripheral ID0 Register */ 1223 __IM uint32_t PIDR1; /*!< (@ 0x00000FE4) Peripheral ID1 Register */ 1224 __IM uint32_t PIDR2; /*!< (@ 0x00000FE8) Peripheral ID2 Register */ 1225 __IM uint32_t PIDR3; /*!< (@ 0x00000FEC) Peripheral ID3 Register */ 1226 __IM uint32_t CIDR0; /*!< (@ 0x00000FF0) Component ID0 Register */ 1227 __IM uint32_t CIDR1; /*!< (@ 0x00000FF4) Component ID1 Register */ 1228 __IM uint32_t CIDR2; /*!< (@ 0x00000FF8) Component ID2 Register */ 1229 __IM uint32_t CIDR3; /*!< (@ 0x00000FFC) Component ID3 Register */ 1230 } NRF_CTI_Type; /*!< Size = 4096 (0x1000) */ 1231 1232 1233 1234 /* =========================================================================================================================== */ 1235 /* ================ TAD_S ================ */ 1236 /* =========================================================================================================================== */ 1237 1238 1239 /** 1240 * @brief Trace and debug control (TAD_S) 1241 */ 1242 1243 typedef struct { /*!< (@ 0xE0080000) TAD_S Structure */ 1244 __IM uint32_t RESERVED; 1245 __OM uint32_t CLOCKSTART; /*!< (@ 0x00000004) Start all trace and debug clocks. */ 1246 __OM uint32_t CLOCKSTOP; /*!< (@ 0x00000008) Stop all trace and debug clocks. */ 1247 __IM uint32_t RESERVED1[317]; 1248 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable debug domain and aquire selected GPIOs */ 1249 __IOM TAD_PSEL_Type PSEL; /*!< (@ 0x00000504) Unspecified */ 1250 __IOM uint32_t TRACEPORTSPEED; /*!< (@ 0x00000518) Clocking options for the Trace Port debug interface 1251 Reset behavior is the same as debug components */ 1252 } NRF_TAD_Type; /*!< Size = 1308 (0x51c) */ 1253 1254 1255 1256 /* =========================================================================================================================== */ 1257 /* ================ DCNF_NS ================ */ 1258 /* =========================================================================================================================== */ 1259 1260 1261 /** 1262 * @brief Domain configuration management 0 (DCNF_NS) 1263 */ 1264 1265 typedef struct { /*!< (@ 0x40000000) DCNF_NS Structure */ 1266 __IM uint32_t RESERVED[264]; 1267 __IM uint32_t CPUID; /*!< (@ 0x00000420) CPU ID of this subsystem */ 1268 __IM uint32_t RESERVED1[7]; 1269 __IOM DCNF_EXTPERI_Type EXTPERI[1]; /*!< (@ 0x00000440) Unspecified */ 1270 __IM uint32_t RESERVED2[7]; 1271 __IOM DCNF_EXTRAM_Type EXTRAM[1]; /*!< (@ 0x00000460) Unspecified */ 1272 __IM uint32_t RESERVED3[7]; 1273 __IOM DCNF_EXTCODE_Type EXTCODE[1]; /*!< (@ 0x00000480) Unspecified */ 1274 } NRF_DCNF_Type; /*!< Size = 1156 (0x484) */ 1275 1276 1277 1278 /* =========================================================================================================================== */ 1279 /* ================ FPU_NS ================ */ 1280 /* =========================================================================================================================== */ 1281 1282 1283 /** 1284 * @brief FPU control peripheral 0 (FPU_NS) 1285 */ 1286 1287 typedef struct { /*!< (@ 0x40000000) FPU_NS Structure */ 1288 __IM uint32_t RESERVED[64]; 1289 __IOM uint32_t EVENTS_INVALIDOPERATION; /*!< (@ 0x00000100) An FPUIOC exception triggered by an invalid operation 1290 has occurred in the FPU */ 1291 __IOM uint32_t EVENTS_DIVIDEBYZERO; /*!< (@ 0x00000104) An FPUDZC exception triggered by a floating-point 1292 divide-by-zero operation has occurred in 1293 the FPU */ 1294 __IOM uint32_t EVENTS_OVERFLOW; /*!< (@ 0x00000108) An FPUOFC exception triggered by a floating-point 1295 overflow has occurred in the FPU */ 1296 __IOM uint32_t EVENTS_UNDERFLOW; /*!< (@ 0x0000010C) An FPUUFC exception triggered by a floating-point 1297 underflow has occurred in the FPU */ 1298 __IOM uint32_t EVENTS_INEXACT; /*!< (@ 0x00000110) An FPUIXC exception triggered by an inexact floating-point 1299 operation has occurred in the FPU */ 1300 __IOM uint32_t EVENTS_DENORMALINPUT; /*!< (@ 0x00000114) An FPUIDC exception triggered by a denormal floating-point 1301 input has occurred in the FPU */ 1302 __IM uint32_t RESERVED1[122]; 1303 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1304 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1305 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1306 } NRF_FPU_Type; /*!< Size = 780 (0x30c) */ 1307 1308 1309 1310 /* =========================================================================================================================== */ 1311 /* ================ CACHE_S ================ */ 1312 /* =========================================================================================================================== */ 1313 1314 1315 /** 1316 * @brief Cache (CACHE_S) 1317 */ 1318 1319 typedef struct { /*!< (@ 0x50001000) CACHE_S Structure */ 1320 __IM uint32_t RESERVED[256]; 1321 __IOM CACHE_PROFILING_Type PROFILING[2]; /*!< (@ 0x00000400) Unspecified */ 1322 __IM uint32_t RESERVED1[48]; 1323 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable cache. */ 1324 __OM uint32_t INVALIDATE; /*!< (@ 0x00000504) Invalidate the cache. */ 1325 __OM uint32_t ERASE; /*!< (@ 0x00000508) Erase the cache. */ 1326 __IOM uint32_t PROFILINGENABLE; /*!< (@ 0x0000050C) Enable the profiling counters. */ 1327 __OM uint32_t PROFILINGCLEAR; /*!< (@ 0x00000510) Clear the profiling counters. */ 1328 __IOM uint32_t MODE; /*!< (@ 0x00000514) Cache mode. Switching from Cache to Ram mode 1329 causes the RAM to be cleared. Switching 1330 from RAM to Cache mode causes the cache 1331 to be invalidated. */ 1332 __IOM uint32_t DEBUGLOCK; /*!< (@ 0x00000518) Lock debug mode. */ 1333 __IOM uint32_t ERASESTATUS; /*!< (@ 0x0000051C) Cache erase status. */ 1334 __IOM uint32_t WRITELOCK; /*!< (@ 0x00000520) Lock cache updates. Prevents updating of cache 1335 content on cache misses, but will continue 1336 to lookup instruction/data fetches in content 1337 already present in the cache. Ignored in 1338 RAM mode. */ 1339 } NRF_CACHE_Type; /*!< Size = 1316 (0x524) */ 1340 1341 1342 1343 /* =========================================================================================================================== */ 1344 /* ================ SPU_S ================ */ 1345 /* =========================================================================================================================== */ 1346 1347 1348 /** 1349 * @brief System protection unit (SPU_S) 1350 */ 1351 1352 typedef struct { /*!< (@ 0x50003000) SPU_S Structure */ 1353 __IM uint32_t RESERVED[64]; 1354 __IOM uint32_t EVENTS_RAMACCERR; /*!< (@ 0x00000100) A security violation has been detected for the 1355 RAM memory space */ 1356 __IOM uint32_t EVENTS_FLASHACCERR; /*!< (@ 0x00000104) A security violation has been detected for the 1357 flash memory space */ 1358 __IOM uint32_t EVENTS_PERIPHACCERR; /*!< (@ 0x00000108) A security violation has been detected on one 1359 or several peripherals */ 1360 __IM uint32_t RESERVED1[29]; 1361 __IOM uint32_t PUBLISH_RAMACCERR; /*!< (@ 0x00000180) Publish configuration for event RAMACCERR */ 1362 __IOM uint32_t PUBLISH_FLASHACCERR; /*!< (@ 0x00000184) Publish configuration for event FLASHACCERR */ 1363 __IOM uint32_t PUBLISH_PERIPHACCERR; /*!< (@ 0x00000188) Publish configuration for event PERIPHACCERR */ 1364 __IM uint32_t RESERVED2[93]; 1365 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1366 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1367 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1368 __IM uint32_t RESERVED3[61]; 1369 __IM uint32_t CAP; /*!< (@ 0x00000400) Show implemented features for the current device */ 1370 __IOM uint32_t CPULOCK; /*!< (@ 0x00000404) Configure bits to lock down CPU features at runtime */ 1371 __IM uint32_t RESERVED4[14]; 1372 __IOM SPU_EXTDOMAIN_Type EXTDOMAIN[1]; /*!< (@ 0x00000440) Unspecified */ 1373 __IM uint32_t RESERVED5[15]; 1374 __IOM SPU_DPPI_Type DPPI[1]; /*!< (@ 0x00000480) Unspecified */ 1375 __IM uint32_t RESERVED6[14]; 1376 __IOM SPU_GPIOPORT_Type GPIOPORT[2]; /*!< (@ 0x000004C0) Unspecified */ 1377 __IM uint32_t RESERVED7[12]; 1378 __IOM SPU_FLASHNSC_Type FLASHNSC[2]; /*!< (@ 0x00000500) Unspecified */ 1379 __IM uint32_t RESERVED8[12]; 1380 __IOM SPU_RAMNSC_Type RAMNSC[2]; /*!< (@ 0x00000540) Unspecified */ 1381 __IM uint32_t RESERVED9[44]; 1382 __IOM SPU_FLASHREGION_Type FLASHREGION[64]; /*!< (@ 0x00000600) Unspecified */ 1383 __IOM SPU_RAMREGION_Type RAMREGION[64]; /*!< (@ 0x00000700) Unspecified */ 1384 __IOM SPU_PERIPHID_Type PERIPHID[256]; /*!< (@ 0x00000800) Unspecified */ 1385 } NRF_SPU_Type; /*!< Size = 3072 (0xc00) */ 1386 1387 1388 1389 /* =========================================================================================================================== */ 1390 /* ================ OSCILLATORS_NS ================ */ 1391 /* =========================================================================================================================== */ 1392 1393 1394 /** 1395 * @brief Oscillator control 0 (OSCILLATORS_NS) 1396 */ 1397 1398 typedef struct { /*!< (@ 0x40004000) OSCILLATORS_NS Structure */ 1399 __IM uint32_t RESERVED[369]; 1400 __IOM uint32_t XOSC32MCAPS; /*!< (@ 0x000005C4) Programmable capacitance of XC1 and XC2 */ 1401 __IM uint32_t RESERVED1[62]; 1402 __IOM OSCILLATORS_XOSC32KI_Type XOSC32KI; /*!< (@ 0x000006C0) Unspecified */ 1403 } NRF_OSCILLATORS_Type; /*!< Size = 1748 (0x6d4) */ 1404 1405 1406 1407 /* =========================================================================================================================== */ 1408 /* ================ REGULATORS_NS ================ */ 1409 /* =========================================================================================================================== */ 1410 1411 1412 /** 1413 * @brief Voltage regulators 0 (REGULATORS_NS) 1414 */ 1415 1416 typedef struct { /*!< (@ 0x40004000) REGULATORS_NS Structure */ 1417 __IM uint32_t RESERVED[266]; 1418 __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000428) Main supply status */ 1419 __IM uint32_t RESERVED1[53]; 1420 __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ 1421 __IM uint32_t RESERVED2[3]; 1422 __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ 1423 __IM uint32_t RESERVED3[124]; 1424 __IOM REGULATORS_VREGMAIN_Type VREGMAIN; /*!< (@ 0x00000704) Unspecified */ 1425 __IM uint32_t RESERVED4[126]; 1426 __IOM REGULATORS_VREGRADIO_Type VREGRADIO; /*!< (@ 0x00000900) Unspecified */ 1427 __IM uint32_t RESERVED5[126]; 1428 __IOM REGULATORS_VREGH_Type VREGH; /*!< (@ 0x00000B00) Unspecified */ 1429 } NRF_REGULATORS_Type; /*!< Size = 2884 (0xb44) */ 1430 1431 1432 1433 /* =========================================================================================================================== */ 1434 /* ================ CLOCK_NS ================ */ 1435 /* =========================================================================================================================== */ 1436 1437 1438 /** 1439 * @brief Clock management 0 (CLOCK_NS) 1440 */ 1441 1442 typedef struct { /*!< (@ 0x40005000) CLOCK_NS Structure */ 1443 __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK128M/HFCLK64M source as selected in 1444 HFCLKSRC */ 1445 __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK128M/HFCLK64M source */ 1446 __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source as selected in LFCLKSRC */ 1447 __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ 1448 __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ 1449 __IM uint32_t RESERVED; 1450 __OM uint32_t TASKS_HFCLKAUDIOSTART; /*!< (@ 0x00000018) Start HFCLKAUDIO source */ 1451 __OM uint32_t TASKS_HFCLKAUDIOSTOP; /*!< (@ 0x0000001C) Stop HFCLKAUDIO source */ 1452 __OM uint32_t TASKS_HFCLK192MSTART; /*!< (@ 0x00000020) Start HFCLK192M source as selected in HFCLK192MSRC */ 1453 __OM uint32_t TASKS_HFCLK192MSTOP; /*!< (@ 0x00000024) Stop HFCLK192M source */ 1454 __IM uint32_t RESERVED1[22]; 1455 __IOM uint32_t SUBSCRIBE_HFCLKSTART; /*!< (@ 0x00000080) Subscribe configuration for task HFCLKSTART */ 1456 __IOM uint32_t SUBSCRIBE_HFCLKSTOP; /*!< (@ 0x00000084) Subscribe configuration for task HFCLKSTOP */ 1457 __IOM uint32_t SUBSCRIBE_LFCLKSTART; /*!< (@ 0x00000088) Subscribe configuration for task LFCLKSTART */ 1458 __IOM uint32_t SUBSCRIBE_LFCLKSTOP; /*!< (@ 0x0000008C) Subscribe configuration for task LFCLKSTOP */ 1459 __IOM uint32_t SUBSCRIBE_CAL; /*!< (@ 0x00000090) Subscribe configuration for task CAL */ 1460 __IM uint32_t RESERVED2; 1461 __IOM uint32_t SUBSCRIBE_HFCLKAUDIOSTART; /*!< (@ 0x00000098) Subscribe configuration for task HFCLKAUDIOSTART */ 1462 __IOM uint32_t SUBSCRIBE_HFCLKAUDIOSTOP; /*!< (@ 0x0000009C) Subscribe configuration for task HFCLKAUDIOSTOP */ 1463 __IOM uint32_t SUBSCRIBE_HFCLK192MSTART; /*!< (@ 0x000000A0) Subscribe configuration for task HFCLK192MSTART */ 1464 __IOM uint32_t SUBSCRIBE_HFCLK192MSTOP; /*!< (@ 0x000000A4) Subscribe configuration for task HFCLK192MSTOP */ 1465 __IM uint32_t RESERVED3[22]; 1466 __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK128M/HFCLK64M source started */ 1467 __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK source started */ 1468 __IM uint32_t RESERVED4[5]; 1469 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000011C) Calibration of LFRC oscillator complete event */ 1470 __IOM uint32_t EVENTS_HFCLKAUDIOSTARTED; /*!< (@ 0x00000120) HFCLKAUDIO source started */ 1471 __IOM uint32_t EVENTS_HFCLK192MSTARTED; /*!< (@ 0x00000124) HFCLK192M source started */ 1472 __IM uint32_t RESERVED5[22]; 1473 __IOM uint32_t PUBLISH_HFCLKSTARTED; /*!< (@ 0x00000180) Publish configuration for event HFCLKSTARTED */ 1474 __IOM uint32_t PUBLISH_LFCLKSTARTED; /*!< (@ 0x00000184) Publish configuration for event LFCLKSTARTED */ 1475 __IM uint32_t RESERVED6[5]; 1476 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x0000019C) Publish configuration for event DONE */ 1477 __IOM uint32_t PUBLISH_HFCLKAUDIOSTARTED; /*!< (@ 0x000001A0) Publish configuration for event HFCLKAUDIOSTARTED */ 1478 __IOM uint32_t PUBLISH_HFCLK192MSTARTED; /*!< (@ 0x000001A4) Publish configuration for event HFCLK192MSTARTED */ 1479 __IM uint32_t RESERVED7[86]; 1480 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1481 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1482 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1483 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 1484 __IM uint32_t RESERVED8[62]; 1485 __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been 1486 triggered */ 1487 __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) Status indicating which HFCLK128M/HFCLK64M source 1488 is running This register value in any CLOCK 1489 instance reflects status only due to configurations/action 1490 in that CLOCK instance. */ 1491 __IM uint32_t RESERVED9; 1492 __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been 1493 triggered */ 1494 __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Status indicating which LFCLK source is running 1495 This register value in any CLOCK instance 1496 reflects status only due to configurations/actions 1497 in that CLOCK instance. */ 1498 __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART 1499 task was triggered */ 1500 __IM uint32_t RESERVED10[12]; 1501 __IM uint32_t HFCLKAUDIORUN; /*!< (@ 0x00000450) Status indicating that HFCLKAUDIOSTART task has 1502 been triggered */ 1503 __IM uint32_t HFCLKAUDIOSTAT; /*!< (@ 0x00000454) Status indicating which HFCLKAUDIO source is 1504 running */ 1505 __IM uint32_t HFCLK192MRUN; /*!< (@ 0x00000458) Status indicating that HFCLK192MSTART task has 1506 been triggered */ 1507 __IM uint32_t HFCLK192MSTAT; /*!< (@ 0x0000045C) Status indicating which HFCLK192M source is running */ 1508 __IM uint32_t RESERVED11[45]; 1509 __IOM uint32_t HFCLKSRC; /*!< (@ 0x00000514) Clock source for HFCLK128M/HFCLK64M */ 1510 __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for LFCLK */ 1511 __IM uint32_t RESERVED12[15]; 1512 __IOM uint32_t HFCLKCTRL; /*!< (@ 0x00000558) HFCLK128M frequency configuration */ 1513 __IOM CLOCK_HFCLKAUDIO_Type HFCLKAUDIO; /*!< (@ 0x0000055C) Unspecified */ 1514 __IM uint32_t RESERVED13[4]; 1515 __IOM uint32_t HFCLKALWAYSRUN; /*!< (@ 0x00000570) Automatic or manual control of HFCLK128M/HFCLK64M */ 1516 __IOM uint32_t LFCLKALWAYSRUN; /*!< (@ 0x00000574) Automatic or manual control of LFCLK */ 1517 __IM uint32_t RESERVED14; 1518 __IOM uint32_t HFCLKAUDIOALWAYSRUN; /*!< (@ 0x0000057C) Automatic or manual control of HFCLKAUDIO */ 1519 __IOM uint32_t HFCLK192MSRC; /*!< (@ 0x00000580) Clock source for HFCLK192M */ 1520 __IOM uint32_t HFCLK192MALWAYSRUN; /*!< (@ 0x00000584) Automatic or manual control of HFCLK192M */ 1521 __IM uint32_t RESERVED15[12]; 1522 __IOM uint32_t HFCLK192MCTRL; /*!< (@ 0x000005B8) HFCLK192M frequency configuration */ 1523 } NRF_CLOCK_Type; /*!< Size = 1468 (0x5bc) */ 1524 1525 1526 1527 /* =========================================================================================================================== */ 1528 /* ================ POWER_NS ================ */ 1529 /* =========================================================================================================================== */ 1530 1531 1532 /** 1533 * @brief Power control 0 (POWER_NS) 1534 */ 1535 1536 typedef struct { /*!< (@ 0x40005000) POWER_NS Structure */ 1537 __IM uint32_t RESERVED[30]; 1538 __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ 1539 __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-Power mode (variable latency) */ 1540 __IM uint32_t RESERVED1[30]; 1541 __IOM uint32_t SUBSCRIBE_CONSTLAT; /*!< (@ 0x000000F8) Subscribe configuration for task CONSTLAT */ 1542 __IOM uint32_t SUBSCRIBE_LOWPWR; /*!< (@ 0x000000FC) Subscribe configuration for task LOWPWR */ 1543 __IM uint32_t RESERVED2[2]; 1544 __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ 1545 __IM uint32_t RESERVED3[2]; 1546 __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ 1547 __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ 1548 __IM uint32_t RESERVED4[27]; 1549 __IOM uint32_t PUBLISH_POFWARN; /*!< (@ 0x00000188) Publish configuration for event POFWARN */ 1550 __IM uint32_t RESERVED5[2]; 1551 __IOM uint32_t PUBLISH_SLEEPENTER; /*!< (@ 0x00000194) Publish configuration for event SLEEPENTER */ 1552 __IOM uint32_t PUBLISH_SLEEPEXIT; /*!< (@ 0x00000198) Publish configuration for event SLEEPEXIT */ 1553 __IM uint32_t RESERVED6[89]; 1554 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1555 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1556 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1557 __IM uint32_t RESERVED7[132]; 1558 __IOM uint32_t GPREGRET[2]; /*!< (@ 0x0000051C) Description collection: General purpose retention 1559 register */ 1560 } NRF_POWER_Type; /*!< Size = 1316 (0x524) */ 1561 1562 1563 1564 /* =========================================================================================================================== */ 1565 /* ================ RESET_NS ================ */ 1566 /* =========================================================================================================================== */ 1567 1568 1569 /** 1570 * @brief Reset control 0 (RESET_NS) 1571 */ 1572 1573 typedef struct { /*!< (@ 0x40005000) RESET_NS Structure */ 1574 __IM uint32_t RESERVED[256]; 1575 __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ 1576 __IM uint32_t RESERVED1[131]; 1577 __IOM RESET_NETWORK_Type NETWORK; /*!< (@ 0x00000610) Unspecified */ 1578 } NRF_RESET_Type; /*!< Size = 1560 (0x618) */ 1579 1580 1581 1582 /* =========================================================================================================================== */ 1583 /* ================ CTRLAP_NS ================ */ 1584 /* =========================================================================================================================== */ 1585 1586 1587 /** 1588 * @brief Control access port 0 (CTRLAP_NS) 1589 */ 1590 1591 typedef struct { /*!< (@ 0x40006000) CTRLAP_NS Structure */ 1592 __IM uint32_t RESERVED[256]; 1593 __IOM CTRLAPPERI_MAILBOX_Type MAILBOX; /*!< (@ 0x00000400) Unspecified */ 1594 __IM uint32_t RESERVED1[30]; 1595 __IOM CTRLAPPERI_ERASEPROTECT_Type ERASEPROTECT;/*!< (@ 0x00000500) Unspecified */ 1596 __IM uint32_t RESERVED2[14]; 1597 __IOM CTRLAPPERI_APPROTECT_Type APPROTECT; /*!< (@ 0x00000540) Unspecified */ 1598 __IOM CTRLAPPERI_SECUREAPPROTECT_Type SECUREAPPROTECT;/*!< (@ 0x00000548) Unspecified */ 1599 __IM uint32_t RESERVED3[44]; 1600 __IM uint32_t STATUS; /*!< (@ 0x00000600) Status bits for CTRL-AP peripheral. */ 1601 } NRF_CTRLAPPERI_Type; /*!< Size = 1540 (0x604) */ 1602 1603 1604 1605 /* =========================================================================================================================== */ 1606 /* ================ SPIM0_NS ================ */ 1607 /* =========================================================================================================================== */ 1608 1609 1610 /** 1611 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0_NS) 1612 */ 1613 1614 typedef struct { /*!< (@ 0x40008000) SPIM0_NS Structure */ 1615 __IM uint32_t RESERVED[4]; 1616 __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ 1617 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ 1618 __IM uint32_t RESERVED1; 1619 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ 1620 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ 1621 __IM uint32_t RESERVED2[27]; 1622 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000090) Subscribe configuration for task START */ 1623 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1624 __IM uint32_t RESERVED3; 1625 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1626 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1627 __IM uint32_t RESERVED4[24]; 1628 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ 1629 __IM uint32_t RESERVED5[2]; 1630 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1631 __IM uint32_t RESERVED6; 1632 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ 1633 __IM uint32_t RESERVED7; 1634 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ 1635 __IM uint32_t RESERVED8[10]; 1636 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ 1637 __IM uint32_t RESERVED9[13]; 1638 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1639 __IM uint32_t RESERVED10[2]; 1640 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1641 __IM uint32_t RESERVED11; 1642 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000198) Publish configuration for event END */ 1643 __IM uint32_t RESERVED12; 1644 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1645 __IM uint32_t RESERVED13[10]; 1646 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001CC) Publish configuration for event STARTED */ 1647 __IM uint32_t RESERVED14[12]; 1648 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1649 __IM uint32_t RESERVED15[64]; 1650 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1651 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1652 __IM uint32_t RESERVED16[61]; 1653 __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields 1654 in this register are set to STALL by hardware 1655 whenever a stall occurres and can be cleared 1656 (set to NOSTALL) by the CPU. */ 1657 __IM uint32_t RESERVED17[63]; 1658 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ 1659 __IM uint32_t RESERVED18; 1660 __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1661 __IM uint32_t RESERVED19[3]; 1662 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK 1663 source selected. */ 1664 __IM uint32_t RESERVED20[3]; 1665 __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1666 __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1667 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1668 __IM uint32_t RESERVED21[2]; 1669 __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ 1670 __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ 1671 __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ 1672 __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ 1673 __IM uint32_t RESERVED22[19]; 1674 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have 1675 been transmitted in the case when RXD.MAXCNT 1676 is greater than TXD.MAXCNT */ 1677 } NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ 1678 1679 1680 1681 /* =========================================================================================================================== */ 1682 /* ================ SPIS0_NS ================ */ 1683 /* =========================================================================================================================== */ 1684 1685 1686 /** 1687 * @brief SPI Slave 0 (SPIS0_NS) 1688 */ 1689 1690 typedef struct { /*!< (@ 0x40008000) SPIS0_NS Structure */ 1691 __IM uint32_t RESERVED[9]; 1692 __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ 1693 __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave 1694 to acquire it */ 1695 __IM uint32_t RESERVED1[30]; 1696 __IOM uint32_t SUBSCRIBE_ACQUIRE; /*!< (@ 0x000000A4) Subscribe configuration for task ACQUIRE */ 1697 __IOM uint32_t SUBSCRIBE_RELEASE; /*!< (@ 0x000000A8) Subscribe configuration for task RELEASE */ 1698 __IM uint32_t RESERVED2[22]; 1699 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ 1700 __IM uint32_t RESERVED3[2]; 1701 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ 1702 __IM uint32_t RESERVED4[5]; 1703 __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ 1704 __IM uint32_t RESERVED5[22]; 1705 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 1706 __IM uint32_t RESERVED6[2]; 1707 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1708 __IM uint32_t RESERVED7[5]; 1709 __IOM uint32_t PUBLISH_ACQUIRED; /*!< (@ 0x000001A8) Publish configuration for event ACQUIRED */ 1710 __IM uint32_t RESERVED8[21]; 1711 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1712 __IM uint32_t RESERVED9[64]; 1713 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1714 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1715 __IM uint32_t RESERVED10[61]; 1716 __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ 1717 __IM uint32_t RESERVED11[15]; 1718 __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ 1719 __IM uint32_t RESERVED12[47]; 1720 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ 1721 __IM uint32_t RESERVED13; 1722 __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1723 __IM uint32_t RESERVED14[7]; 1724 __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ 1725 __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ 1726 __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ 1727 __IM uint32_t RESERVED15; 1728 __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case 1729 of an ignored transaction. */ 1730 __IM uint32_t RESERVED16[24]; 1731 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ 1732 } NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ 1733 1734 1735 1736 /* =========================================================================================================================== */ 1737 /* ================ TWIM0_NS ================ */ 1738 /* =========================================================================================================================== */ 1739 1740 1741 /** 1742 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0_NS) 1743 */ 1744 1745 typedef struct { /*!< (@ 0x40008000) TWIM0_NS Structure */ 1746 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ 1747 __IM uint32_t RESERVED; 1748 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ 1749 __IM uint32_t RESERVED1[2]; 1750 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the 1751 TWI master is not suspended. */ 1752 __IM uint32_t RESERVED2; 1753 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1754 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1755 __IM uint32_t RESERVED3[23]; 1756 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1757 __IM uint32_t RESERVED4; 1758 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1759 __IM uint32_t RESERVED5[2]; 1760 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1761 __IM uint32_t RESERVED6; 1762 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1763 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1764 __IM uint32_t RESERVED7[24]; 1765 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1766 __IM uint32_t RESERVED8[7]; 1767 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1768 __IM uint32_t RESERVED9[8]; 1769 __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is 1770 now suspended. */ 1771 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1772 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1773 __IM uint32_t RESERVED10[2]; 1774 __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ 1775 __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last 1776 byte */ 1777 __IM uint32_t RESERVED11[8]; 1778 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1779 __IM uint32_t RESERVED12[7]; 1780 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1781 __IM uint32_t RESERVED13[8]; 1782 __IOM uint32_t PUBLISH_SUSPENDED; /*!< (@ 0x000001C8) Publish configuration for event SUSPENDED */ 1783 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1784 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1785 __IM uint32_t RESERVED14[2]; 1786 __IOM uint32_t PUBLISH_LASTRX; /*!< (@ 0x000001DC) Publish configuration for event LASTRX */ 1787 __IOM uint32_t PUBLISH_LASTTX; /*!< (@ 0x000001E0) Publish configuration for event LASTTX */ 1788 __IM uint32_t RESERVED15[7]; 1789 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1790 __IM uint32_t RESERVED16[63]; 1791 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1792 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1793 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1794 __IM uint32_t RESERVED17[110]; 1795 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ 1796 __IM uint32_t RESERVED18[14]; 1797 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ 1798 __IM uint32_t RESERVED19; 1799 __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1800 __IM uint32_t RESERVED20[5]; 1801 __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK 1802 source selected. */ 1803 __IM uint32_t RESERVED21[3]; 1804 __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1805 __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1806 __IM uint32_t RESERVED22[13]; 1807 __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ 1808 } NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ 1809 1810 1811 1812 /* =========================================================================================================================== */ 1813 /* ================ TWIS0_NS ================ */ 1814 /* =========================================================================================================================== */ 1815 1816 1817 /** 1818 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0_NS) 1819 */ 1820 1821 typedef struct { /*!< (@ 0x40008000) TWIS0_NS Structure */ 1822 __IM uint32_t RESERVED[5]; 1823 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ 1824 __IM uint32_t RESERVED1; 1825 __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ 1826 __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ 1827 __IM uint32_t RESERVED2[3]; 1828 __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ 1829 __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ 1830 __IM uint32_t RESERVED3[23]; 1831 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000094) Subscribe configuration for task STOP */ 1832 __IM uint32_t RESERVED4; 1833 __IOM uint32_t SUBSCRIBE_SUSPEND; /*!< (@ 0x0000009C) Subscribe configuration for task SUSPEND */ 1834 __IOM uint32_t SUBSCRIBE_RESUME; /*!< (@ 0x000000A0) Subscribe configuration for task RESUME */ 1835 __IM uint32_t RESERVED5[3]; 1836 __IOM uint32_t SUBSCRIBE_PREPARERX; /*!< (@ 0x000000B0) Subscribe configuration for task PREPARERX */ 1837 __IOM uint32_t SUBSCRIBE_PREPARETX; /*!< (@ 0x000000B4) Subscribe configuration for task PREPARETX */ 1838 __IM uint32_t RESERVED6[19]; 1839 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ 1840 __IM uint32_t RESERVED7[7]; 1841 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ 1842 __IM uint32_t RESERVED8[9]; 1843 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ 1844 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ 1845 __IM uint32_t RESERVED9[4]; 1846 __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ 1847 __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ 1848 __IM uint32_t RESERVED10[6]; 1849 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 1850 __IM uint32_t RESERVED11[7]; 1851 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1852 __IM uint32_t RESERVED12[9]; 1853 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1854 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1855 __IM uint32_t RESERVED13[4]; 1856 __IOM uint32_t PUBLISH_WRITE; /*!< (@ 0x000001E4) Publish configuration for event WRITE */ 1857 __IOM uint32_t PUBLISH_READ; /*!< (@ 0x000001E8) Publish configuration for event READ */ 1858 __IM uint32_t RESERVED14[5]; 1859 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1860 __IM uint32_t RESERVED15[63]; 1861 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1862 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1863 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1864 __IM uint32_t RESERVED16[113]; 1865 __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ 1866 __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had 1867 a match */ 1868 __IM uint32_t RESERVED17[10]; 1869 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ 1870 __IM uint32_t RESERVED18; 1871 __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1872 __IM uint32_t RESERVED19[9]; 1873 __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1874 __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1875 __IM uint32_t RESERVED20[13]; 1876 __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ 1877 __IM uint32_t RESERVED21; 1878 __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match 1879 mechanism */ 1880 __IM uint32_t RESERVED22[10]; 1881 __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case 1882 of an over-read of the transmit buffer. */ 1883 } NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ 1884 1885 1886 1887 /* =========================================================================================================================== */ 1888 /* ================ UARTE0_NS ================ */ 1889 /* =========================================================================================================================== */ 1890 1891 1892 /** 1893 * @brief UART with EasyDMA 0 (UARTE0_NS) 1894 */ 1895 1896 typedef struct { /*!< (@ 0x40008000) UARTE0_NS Structure */ 1897 __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ 1898 __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ 1899 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ 1900 __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ 1901 __IM uint32_t RESERVED[7]; 1902 __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ 1903 __IM uint32_t RESERVED1[20]; 1904 __IOM uint32_t SUBSCRIBE_STARTRX; /*!< (@ 0x00000080) Subscribe configuration for task STARTRX */ 1905 __IOM uint32_t SUBSCRIBE_STOPRX; /*!< (@ 0x00000084) Subscribe configuration for task STOPRX */ 1906 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x00000088) Subscribe configuration for task STARTTX */ 1907 __IOM uint32_t SUBSCRIBE_STOPTX; /*!< (@ 0x0000008C) Subscribe configuration for task STOPTX */ 1908 __IM uint32_t RESERVED2[7]; 1909 __IOM uint32_t SUBSCRIBE_FLUSHRX; /*!< (@ 0x000000AC) Subscribe configuration for task FLUSHRX */ 1910 __IM uint32_t RESERVED3[20]; 1911 __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ 1912 __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ 1913 __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet 1914 transferred to Data RAM) */ 1915 __IM uint32_t RESERVED4; 1916 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ 1917 __IM uint32_t RESERVED5[2]; 1918 __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ 1919 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ 1920 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ 1921 __IM uint32_t RESERVED6[7]; 1922 __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ 1923 __IM uint32_t RESERVED7; 1924 __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ 1925 __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ 1926 __IM uint32_t RESERVED8; 1927 __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ 1928 __IM uint32_t RESERVED9[9]; 1929 __IOM uint32_t PUBLISH_CTS; /*!< (@ 0x00000180) Publish configuration for event CTS */ 1930 __IOM uint32_t PUBLISH_NCTS; /*!< (@ 0x00000184) Publish configuration for event NCTS */ 1931 __IOM uint32_t PUBLISH_RXDRDY; /*!< (@ 0x00000188) Publish configuration for event RXDRDY */ 1932 __IM uint32_t RESERVED10; 1933 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x00000190) Publish configuration for event ENDRX */ 1934 __IM uint32_t RESERVED11[2]; 1935 __IOM uint32_t PUBLISH_TXDRDY; /*!< (@ 0x0000019C) Publish configuration for event TXDRDY */ 1936 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001A0) Publish configuration for event ENDTX */ 1937 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x000001A4) Publish configuration for event ERROR */ 1938 __IM uint32_t RESERVED12[7]; 1939 __IOM uint32_t PUBLISH_RXTO; /*!< (@ 0x000001C4) Publish configuration for event RXTO */ 1940 __IM uint32_t RESERVED13; 1941 __IOM uint32_t PUBLISH_RXSTARTED; /*!< (@ 0x000001CC) Publish configuration for event RXSTARTED */ 1942 __IOM uint32_t PUBLISH_TXSTARTED; /*!< (@ 0x000001D0) Publish configuration for event TXSTARTED */ 1943 __IM uint32_t RESERVED14; 1944 __IOM uint32_t PUBLISH_TXSTOPPED; /*!< (@ 0x000001D8) Publish configuration for event TXSTOPPED */ 1945 __IM uint32_t RESERVED15[9]; 1946 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 1947 __IM uint32_t RESERVED16[63]; 1948 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 1949 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 1950 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 1951 __IM uint32_t RESERVED17[93]; 1952 __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ 1953 __IM uint32_t RESERVED18[31]; 1954 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ 1955 __IM uint32_t RESERVED19; 1956 __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ 1957 __IM uint32_t RESERVED20[3]; 1958 __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source 1959 selected. */ 1960 __IM uint32_t RESERVED21[3]; 1961 __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ 1962 __IM uint32_t RESERVED22; 1963 __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ 1964 __IM uint32_t RESERVED23[7]; 1965 __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ 1966 } NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ 1967 1968 1969 1970 /* =========================================================================================================================== */ 1971 /* ================ GPIOTE0_S ================ */ 1972 /* =========================================================================================================================== */ 1973 1974 1975 /** 1976 * @brief GPIO Tasks and Events 0 (GPIOTE0_S) 1977 */ 1978 1979 typedef struct { /*!< (@ 0x5000D000) GPIOTE0_S Structure */ 1980 __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin 1981 specified in CONFIG[n].PSEL. Action on pin 1982 is configured in CONFIG[n].POLARITY. */ 1983 __IM uint32_t RESERVED[4]; 1984 __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin 1985 specified in CONFIG[n].PSEL. Action on pin 1986 is to set it high. */ 1987 __IM uint32_t RESERVED1[4]; 1988 __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin 1989 specified in CONFIG[n].PSEL. Action on pin 1990 is to set it low. */ 1991 __IOM uint32_t SUBSCRIBE_OUT[8]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 1992 for task OUT[n] */ 1993 __IM uint32_t RESERVED2[4]; 1994 __IOM uint32_t SUBSCRIBE_SET[8]; /*!< (@ 0x000000B0) Description collection: Subscribe configuration 1995 for task SET[n] */ 1996 __IM uint32_t RESERVED3[4]; 1997 __IOM uint32_t SUBSCRIBE_CLR[8]; /*!< (@ 0x000000E0) Description collection: Subscribe configuration 1998 for task CLR[n] */ 1999 __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from 2000 pin specified in CONFIG[n].PSEL */ 2001 __IM uint32_t RESERVED4[23]; 2002 __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins 2003 with SENSE mechanism enabled */ 2004 __IOM uint32_t PUBLISH_IN[8]; /*!< (@ 0x00000180) Description collection: Publish configuration 2005 for event IN[n] */ 2006 __IM uint32_t RESERVED5[23]; 2007 __IOM uint32_t PUBLISH_PORT; /*!< (@ 0x000001FC) Publish configuration for event PORT */ 2008 __IM uint32_t RESERVED6[65]; 2009 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2010 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2011 __IM uint32_t RESERVED7[126]; 2012 __IOM uint32_t LATENCY; /*!< (@ 0x00000504) Latency selection for Event mode (MODE=Event) 2013 with rising or falling edge detection on 2014 the pin. */ 2015 __IM uint32_t RESERVED8[2]; 2016 __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], 2017 SET[n], and CLR[n] tasks and IN[n] event */ 2018 } NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ 2019 2020 2021 2022 /* =========================================================================================================================== */ 2023 /* ================ SAADC_NS ================ */ 2024 /* =========================================================================================================================== */ 2025 2026 2027 /** 2028 * @brief Analog to Digital Converter 0 (SAADC_NS) 2029 */ 2030 2031 typedef struct { /*!< (@ 0x4000E000) SAADC_NS Structure */ 2032 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in 2033 RAM */ 2034 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels 2035 are sampled */ 2036 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any ongoing conversion */ 2037 __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ 2038 __IM uint32_t RESERVED[28]; 2039 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2040 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000084) Subscribe configuration for task SAMPLE */ 2041 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000088) Subscribe configuration for task STOP */ 2042 __IOM uint32_t SUBSCRIBE_CALIBRATEOFFSET; /*!< (@ 0x0000008C) Subscribe configuration for task CALIBRATEOFFSET */ 2043 __IM uint32_t RESERVED1[28]; 2044 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ 2045 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ 2046 __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending 2047 on the mode, multiple conversions might 2048 be needed for a result to be transferred 2049 to RAM. */ 2050 __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM */ 2051 __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ 2052 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ 2053 __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ 2054 __IM uint32_t RESERVED2[10]; 2055 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 2056 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000184) Publish configuration for event END */ 2057 __IOM uint32_t PUBLISH_DONE; /*!< (@ 0x00000188) Publish configuration for event DONE */ 2058 __IOM uint32_t PUBLISH_RESULTDONE; /*!< (@ 0x0000018C) Publish configuration for event RESULTDONE */ 2059 __IOM uint32_t PUBLISH_CALIBRATEDONE; /*!< (@ 0x00000190) Publish configuration for event CALIBRATEDONE */ 2060 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000194) Publish configuration for event STOPPED */ 2061 __IOM SAADC_PUBLISH_CH_Type PUBLISH_CH[8]; /*!< (@ 0x00000198) Publish configuration for events */ 2062 __IM uint32_t RESERVED3[74]; 2063 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2064 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2065 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2066 __IM uint32_t RESERVED4[61]; 2067 __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ 2068 __IM uint32_t RESERVED5[63]; 2069 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ 2070 __IM uint32_t RESERVED6[3]; 2071 __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ 2072 __IM uint32_t RESERVED7[24]; 2073 __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ 2074 __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should 2075 not be combined with SCAN. The RESOLUTION 2076 is applied before averaging, thus for high 2077 OVERSAMPLE a higher RESOLUTION should be 2078 used. */ 2079 __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ 2080 __IM uint32_t RESERVED8[12]; 2081 __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ 2082 } NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ 2083 2084 2085 2086 /* =========================================================================================================================== */ 2087 /* ================ TIMER0_NS ================ */ 2088 /* =========================================================================================================================== */ 2089 2090 2091 /** 2092 * @brief Timer/Counter 0 (TIMER0_NS) 2093 */ 2094 2095 typedef struct { /*!< (@ 0x4000F000) TIMER0_NS Structure */ 2096 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ 2097 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ 2098 __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ 2099 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ 2100 __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ 2101 __IM uint32_t RESERVED[11]; 2102 __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to 2103 CC[n] register */ 2104 __IM uint32_t RESERVED1[10]; 2105 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2106 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2107 __IOM uint32_t SUBSCRIBE_COUNT; /*!< (@ 0x00000088) Subscribe configuration for task COUNT */ 2108 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x0000008C) Subscribe configuration for task CLEAR */ 2109 __IOM uint32_t SUBSCRIBE_SHUTDOWN; /*!< (@ 0x00000090) Deprecated register - Subscribe configuration 2110 for task SHUTDOWN */ 2111 __IM uint32_t RESERVED2[11]; 2112 __IOM uint32_t SUBSCRIBE_CAPTURE[6]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 2113 for task CAPTURE[n] */ 2114 __IM uint32_t RESERVED3[26]; 2115 __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 2116 match */ 2117 __IM uint32_t RESERVED4[26]; 2118 __IOM uint32_t PUBLISH_COMPARE[6]; /*!< (@ 0x000001C0) Description collection: Publish configuration 2119 for event COMPARE[n] */ 2120 __IM uint32_t RESERVED5[10]; 2121 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2122 __IM uint32_t RESERVED6[63]; 2123 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2124 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2125 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2126 __IM uint32_t RESERVED7[126]; 2127 __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ 2128 __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ 2129 __IM uint32_t RESERVED8; 2130 __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ 2131 __IM uint32_t RESERVED9[11]; 2132 __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register 2133 n */ 2134 __IM uint32_t RESERVED10[10]; 2135 __IOM uint32_t ONESHOTEN[6]; /*!< (@ 0x00000580) Description collection: Enable one-shot operation 2136 for Capture/Compare channel n */ 2137 } NRF_TIMER_Type; /*!< Size = 1432 (0x598) */ 2138 2139 2140 2141 /* =========================================================================================================================== */ 2142 /* ================ RTC0_NS ================ */ 2143 /* =========================================================================================================================== */ 2144 2145 2146 /** 2147 * @brief Real-time counter 0 (RTC0_NS) 2148 */ 2149 2150 typedef struct { /*!< (@ 0x40014000) RTC0_NS Structure */ 2151 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC counter */ 2152 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC counter */ 2153 __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC counter */ 2154 __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set counter to 0xFFFFF0 */ 2155 __IM uint32_t RESERVED[12]; 2156 __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Description collection: Capture RTC counter to 2157 CC[n] register */ 2158 __IM uint32_t RESERVED1[12]; 2159 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2160 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2161 __IOM uint32_t SUBSCRIBE_CLEAR; /*!< (@ 0x00000088) Subscribe configuration for task CLEAR */ 2162 __IOM uint32_t SUBSCRIBE_TRIGOVRFLW; /*!< (@ 0x0000008C) Subscribe configuration for task TRIGOVRFLW */ 2163 __IM uint32_t RESERVED2[12]; 2164 __IOM uint32_t SUBSCRIBE_CAPTURE[4]; /*!< (@ 0x000000C0) Description collection: Subscribe configuration 2165 for task CAPTURE[n] */ 2166 __IM uint32_t RESERVED3[12]; 2167 __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on counter increment */ 2168 __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on counter overflow */ 2169 __IM uint32_t RESERVED4[14]; 2170 __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] 2171 match */ 2172 __IM uint32_t RESERVED5[12]; 2173 __IOM uint32_t PUBLISH_TICK; /*!< (@ 0x00000180) Publish configuration for event TICK */ 2174 __IOM uint32_t PUBLISH_OVRFLW; /*!< (@ 0x00000184) Publish configuration for event OVRFLW */ 2175 __IM uint32_t RESERVED6[14]; 2176 __IOM uint32_t PUBLISH_COMPARE[4]; /*!< (@ 0x000001C0) Description collection: Publish configuration 2177 for event COMPARE[n] */ 2178 __IM uint32_t RESERVED7[12]; 2179 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2180 __IM uint32_t RESERVED8[64]; 2181 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2182 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2183 __IM uint32_t RESERVED9[13]; 2184 __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ 2185 __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ 2186 __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ 2187 __IM uint32_t RESERVED10[110]; 2188 __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current counter value */ 2189 __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for counter frequency (32768 2190 / (PRESCALER + 1)). Must be written when 2191 RTC is stopped. */ 2192 __IM uint32_t RESERVED11[13]; 2193 __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ 2194 } NRF_RTC_Type; /*!< Size = 1360 (0x550) */ 2195 2196 2197 2198 /* =========================================================================================================================== */ 2199 /* ================ DPPIC_NS ================ */ 2200 /* =========================================================================================================================== */ 2201 2202 2203 /** 2204 * @brief Distributed programmable peripheral interconnect controller 0 (DPPIC_NS) 2205 */ 2206 2207 typedef struct { /*!< (@ 0x40017000) DPPIC_NS Structure */ 2208 __OM DPPIC_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ 2209 __IM uint32_t RESERVED[20]; 2210 __IOM DPPIC_SUBSCRIBE_CHG_Type SUBSCRIBE_CHG[6];/*!< (@ 0x00000080) Subscribe configuration for tasks */ 2211 __IM uint32_t RESERVED1[276]; 2212 __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ 2213 __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ 2214 __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ 2215 __IM uint32_t RESERVED2[189]; 2216 __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n Note: 2217 Writes to this register are ignored if either 2218 SUBSCRIBE_CHG[n].EN or SUBSCRIBE_CHG[n].DIS 2219 is enabled */ 2220 } NRF_DPPIC_Type; /*!< Size = 2072 (0x818) */ 2221 2222 2223 2224 /* =========================================================================================================================== */ 2225 /* ================ WDT0_NS ================ */ 2226 /* =========================================================================================================================== */ 2227 2228 2229 /** 2230 * @brief Watchdog Timer 0 (WDT0_NS) 2231 */ 2232 2233 typedef struct { /*!< (@ 0x40018000) WDT0_NS Structure */ 2234 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start WDT */ 2235 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop WDT */ 2236 __IM uint32_t RESERVED[30]; 2237 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2238 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2239 __IM uint32_t RESERVED1[30]; 2240 __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ 2241 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Watchdog stopped */ 2242 __IM uint32_t RESERVED2[30]; 2243 __IOM uint32_t PUBLISH_TIMEOUT; /*!< (@ 0x00000180) Publish configuration for event TIMEOUT */ 2244 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 2245 __IM uint32_t RESERVED3[95]; 2246 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2247 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2248 __IM uint32_t RESERVED4[6]; 2249 __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ 2250 __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ 2251 __IM uint32_t RESERVED5[53]; 2252 __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ 2253 __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ 2254 __IM uint32_t RESERVED6[63]; 2255 __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ 2256 __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ 2257 __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ 2258 __IM uint32_t RESERVED7[4]; 2259 __OM uint32_t TSEN; /*!< (@ 0x00000520) Task stop enable */ 2260 __IM uint32_t RESERVED8[55]; 2261 __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ 2262 } NRF_WDT_Type; /*!< Size = 1568 (0x620) */ 2263 2264 2265 2266 /* =========================================================================================================================== */ 2267 /* ================ COMP_NS ================ */ 2268 /* =========================================================================================================================== */ 2269 2270 2271 /** 2272 * @brief Comparator 0 (COMP_NS) 2273 */ 2274 2275 typedef struct { /*!< (@ 0x4001A000) COMP_NS Structure */ 2276 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2277 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2278 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2279 __IM uint32_t RESERVED[29]; 2280 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2281 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2282 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE */ 2283 __IM uint32_t RESERVED1[29]; 2284 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ 2285 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2286 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2287 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2288 __IM uint32_t RESERVED2[28]; 2289 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 2290 __IOM uint32_t PUBLISH_DOWN; /*!< (@ 0x00000184) Publish configuration for event DOWN */ 2291 __IOM uint32_t PUBLISH_UP; /*!< (@ 0x00000188) Publish configuration for event UP */ 2292 __IOM uint32_t PUBLISH_CROSS; /*!< (@ 0x0000018C) Publish configuration for event CROSS */ 2293 __IM uint32_t RESERVED3[28]; 2294 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2295 __IM uint32_t RESERVED4[63]; 2296 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2297 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2298 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2299 __IM uint32_t RESERVED5[61]; 2300 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2301 __IM uint32_t RESERVED6[63]; 2302 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ 2303 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ 2304 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ 2305 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2306 __IM uint32_t RESERVED7[8]; 2307 __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ 2308 __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ 2309 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2310 __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ 2311 } NRF_COMP_Type; /*!< Size = 1344 (0x540) */ 2312 2313 2314 2315 /* =========================================================================================================================== */ 2316 /* ================ LPCOMP_NS ================ */ 2317 /* =========================================================================================================================== */ 2318 2319 2320 /** 2321 * @brief Low-power comparator 0 (LPCOMP_NS) 2322 */ 2323 2324 typedef struct { /*!< (@ 0x4001A000) LPCOMP_NS Structure */ 2325 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ 2326 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ 2327 __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ 2328 __IM uint32_t RESERVED[29]; 2329 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2330 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2331 __IOM uint32_t SUBSCRIBE_SAMPLE; /*!< (@ 0x00000088) Subscribe configuration for task SAMPLE */ 2332 __IM uint32_t RESERVED1[29]; 2333 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ 2334 __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ 2335 __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ 2336 __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ 2337 __IM uint32_t RESERVED2[28]; 2338 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 2339 __IOM uint32_t PUBLISH_DOWN; /*!< (@ 0x00000184) Publish configuration for event DOWN */ 2340 __IOM uint32_t PUBLISH_UP; /*!< (@ 0x00000188) Publish configuration for event UP */ 2341 __IOM uint32_t PUBLISH_CROSS; /*!< (@ 0x0000018C) Publish configuration for event CROSS */ 2342 __IM uint32_t RESERVED3[28]; 2343 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2344 __IM uint32_t RESERVED4[64]; 2345 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2346 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2347 __IM uint32_t RESERVED5[61]; 2348 __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ 2349 __IM uint32_t RESERVED6[63]; 2350 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ 2351 __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ 2352 __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ 2353 __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ 2354 __IM uint32_t RESERVED7[4]; 2355 __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ 2356 __IM uint32_t RESERVED8[5]; 2357 __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ 2358 } NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ 2359 2360 2361 2362 /* =========================================================================================================================== */ 2363 /* ================ EGU0_NS ================ */ 2364 /* =========================================================================================================================== */ 2365 2366 2367 /** 2368 * @brief Event generator unit 0 (EGU0_NS) 2369 */ 2370 2371 typedef struct { /*!< (@ 0x4001B000) EGU0_NS Structure */ 2372 __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering 2373 the corresponding TRIGGERED[n] event */ 2374 __IM uint32_t RESERVED[16]; 2375 __IOM uint32_t SUBSCRIBE_TRIGGER[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 2376 for task TRIGGER[n] */ 2377 __IM uint32_t RESERVED1[16]; 2378 __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated 2379 by triggering the corresponding TRIGGER[n] 2380 task */ 2381 __IM uint32_t RESERVED2[16]; 2382 __IOM uint32_t PUBLISH_TRIGGERED[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 2383 for event TRIGGERED[n] */ 2384 __IM uint32_t RESERVED3[80]; 2385 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2386 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2387 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2388 } NRF_EGU_Type; /*!< Size = 780 (0x30c) */ 2389 2390 2391 2392 /* =========================================================================================================================== */ 2393 /* ================ PWM0_NS ================ */ 2394 /* =========================================================================================================================== */ 2395 2396 2397 /** 2398 * @brief Pulse width modulation unit 0 (PWM0_NS) 2399 */ 2400 2401 typedef struct { /*!< (@ 0x40021000) PWM0_NS Structure */ 2402 __IM uint32_t RESERVED; 2403 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at 2404 the end of current PWM period, and stops 2405 sequence playback */ 2406 __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value 2407 on all enabled channels from sequence n, 2408 and starts playing that sequence at the 2409 rate defined in SEQ[n]REFRESH and/or DECODER.MODE. 2410 Causes PWM generation to start if not running. */ 2411 __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on 2412 all enabled channels if DECODER.MODE=NextStep. 2413 Does not cause PWM generation to start if 2414 not running. */ 2415 __IM uint32_t RESERVED1[28]; 2416 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2417 __IOM uint32_t SUBSCRIBE_SEQSTART[2]; /*!< (@ 0x00000088) Description collection: Subscribe configuration 2418 for task SEQSTART[n] */ 2419 __IOM uint32_t SUBSCRIBE_NEXTSTEP; /*!< (@ 0x00000090) Subscribe configuration for task NEXTSTEP */ 2420 __IM uint32_t RESERVED2[28]; 2421 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses 2422 are no longer generated */ 2423 __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started 2424 on sequence n */ 2425 __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every 2426 sequence n, when last value from RAM has 2427 been applied to wave counter */ 2428 __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ 2429 __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount 2430 of times defined in LOOP.CNT */ 2431 __IM uint32_t RESERVED3[25]; 2432 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 2433 __IOM uint32_t PUBLISH_SEQSTARTED[2]; /*!< (@ 0x00000188) Description collection: Publish configuration 2434 for event SEQSTARTED[n] */ 2435 __IOM uint32_t PUBLISH_SEQEND[2]; /*!< (@ 0x00000190) Description collection: Publish configuration 2436 for event SEQEND[n] */ 2437 __IOM uint32_t PUBLISH_PWMPERIODEND; /*!< (@ 0x00000198) Publish configuration for event PWMPERIODEND */ 2438 __IOM uint32_t PUBLISH_LOOPSDONE; /*!< (@ 0x0000019C) Publish configuration for event LOOPSDONE */ 2439 __IM uint32_t RESERVED4[24]; 2440 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2441 __IM uint32_t RESERVED5[63]; 2442 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2443 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2444 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2445 __IM uint32_t RESERVED6[125]; 2446 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ 2447 __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ 2448 __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter 2449 counts */ 2450 __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ 2451 __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ 2452 __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ 2453 __IM uint32_t RESERVED7[2]; 2454 __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ 2455 __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2456 } NRF_PWM_Type; /*!< Size = 1392 (0x570) */ 2457 2458 2459 2460 /* =========================================================================================================================== */ 2461 /* ================ PDM0_NS ================ */ 2462 /* =========================================================================================================================== */ 2463 2464 2465 /** 2466 * @brief Pulse Density Modulation (Digital Microphone) Interface 0 (PDM0_NS) 2467 */ 2468 2469 typedef struct { /*!< (@ 0x40026000) PDM0_NS Structure */ 2470 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ 2471 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ 2472 __IM uint32_t RESERVED[30]; 2473 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2474 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2475 __IM uint32_t RESERVED1[30]; 2476 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ 2477 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ 2478 __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified 2479 by SAMPLE.MAXCNT (or the last sample after 2480 a STOP task has been received) to Data RAM */ 2481 __IM uint32_t RESERVED2[29]; 2482 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000180) Publish configuration for event STARTED */ 2483 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000184) Publish configuration for event STOPPED */ 2484 __IOM uint32_t PUBLISH_END; /*!< (@ 0x00000188) Publish configuration for event END */ 2485 __IM uint32_t RESERVED3[93]; 2486 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2487 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2488 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2489 __IM uint32_t RESERVED4[125]; 2490 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ 2491 __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ 2492 __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' 2493 signals */ 2494 __IM uint32_t RESERVED5[3]; 2495 __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ 2496 __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ 2497 __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output 2498 sample rate. Change PDMCLKCTRL accordingly. */ 2499 __IM uint32_t RESERVED6[7]; 2500 __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ 2501 __IM uint32_t RESERVED7; 2502 __IOM uint32_t MCLKCONFIG; /*!< (@ 0x0000054C) Master clock generator configuration */ 2503 __IM uint32_t RESERVED8[4]; 2504 __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ 2505 } NRF_PDM_Type; /*!< Size = 1384 (0x568) */ 2506 2507 2508 2509 /* =========================================================================================================================== */ 2510 /* ================ I2S0_NS ================ */ 2511 /* =========================================================================================================================== */ 2512 2513 2514 /** 2515 * @brief Inter-IC Sound 0 (I2S0_NS) 2516 */ 2517 2518 typedef struct { /*!< (@ 0x40028000) I2S0_NS Structure */ 2519 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK 2520 generator when this is enabled */ 2521 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer and MCK generator. Triggering 2522 this task will cause the event STOPPED to 2523 be generated. */ 2524 __IM uint32_t RESERVED[30]; 2525 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2526 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2527 __IM uint32_t RESERVED1[31]; 2528 __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal 2529 double-buffers. When the I2S module is started 2530 and RX is enabled, this event will be generated 2531 for every RXTXD.MAXCNT words received on 2532 the SDIN pin. */ 2533 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ 2534 __IM uint32_t RESERVED2[2]; 2535 __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal 2536 double-buffers. When the I2S module is started 2537 and TX is enabled, this event will be generated 2538 for every RXTXD.MAXCNT words that are sent 2539 on the SDOUT pin. */ 2540 __IM uint32_t RESERVED3; 2541 __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x0000011C) Frame start event, generated on the active edge 2542 of LRCK */ 2543 __IM uint32_t RESERVED4[25]; 2544 __IOM uint32_t PUBLISH_RXPTRUPD; /*!< (@ 0x00000184) Publish configuration for event RXPTRUPD */ 2545 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000188) Publish configuration for event STOPPED */ 2546 __IM uint32_t RESERVED5[2]; 2547 __IOM uint32_t PUBLISH_TXPTRUPD; /*!< (@ 0x00000194) Publish configuration for event TXPTRUPD */ 2548 __IM uint32_t RESERVED6; 2549 __IOM uint32_t PUBLISH_FRAMESTART; /*!< (@ 0x0000019C) Publish configuration for event FRAMESTART */ 2550 __IM uint32_t RESERVED7[88]; 2551 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2552 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2553 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2554 __IM uint32_t RESERVED8[125]; 2555 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module */ 2556 __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ 2557 __IM uint32_t RESERVED9[2]; 2558 __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ 2559 __IM uint32_t RESERVED10; 2560 __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ 2561 __IM uint32_t RESERVED11[3]; 2562 __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ 2563 __IM uint32_t RESERVED12[3]; 2564 __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ 2565 } NRF_I2S_Type; /*!< Size = 1396 (0x574) */ 2566 2567 2568 2569 /* =========================================================================================================================== */ 2570 /* ================ IPC_NS ================ */ 2571 /* =========================================================================================================================== */ 2572 2573 2574 /** 2575 * @brief Interprocessor communication 0 (IPC_NS) 2576 */ 2577 2578 typedef struct { /*!< (@ 0x4002A000) IPC_NS Structure */ 2579 __OM uint32_t TASKS_SEND[16]; /*!< (@ 0x00000000) Description collection: Trigger events on IPC 2580 channel enabled in SEND_CNF[n] */ 2581 __IM uint32_t RESERVED[16]; 2582 __IOM uint32_t SUBSCRIBE_SEND[16]; /*!< (@ 0x00000080) Description collection: Subscribe configuration 2583 for task SEND[n] */ 2584 __IM uint32_t RESERVED1[16]; 2585 __IOM uint32_t EVENTS_RECEIVE[16]; /*!< (@ 0x00000100) Description collection: Event received on one 2586 or more of the enabled IPC channels in RECEIVE_CNF[n] */ 2587 __IM uint32_t RESERVED2[16]; 2588 __IOM uint32_t PUBLISH_RECEIVE[16]; /*!< (@ 0x00000180) Description collection: Publish configuration 2589 for event RECEIVE[n] */ 2590 __IM uint32_t RESERVED3[80]; 2591 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2592 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2593 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2594 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 2595 __IM uint32_t RESERVED4[128]; 2596 __IOM uint32_t SEND_CNF[16]; /*!< (@ 0x00000510) Description collection: Send event configuration 2597 for TASKS_SEND[n] */ 2598 __IM uint32_t RESERVED5[16]; 2599 __IOM uint32_t RECEIVE_CNF[16]; /*!< (@ 0x00000590) Description collection: Receive event configuration 2600 for EVENTS_RECEIVE[n] */ 2601 __IM uint32_t RESERVED6[16]; 2602 __IOM uint32_t GPMEM[2]; /*!< (@ 0x00000610) Description collection: General purpose memory */ 2603 } NRF_IPC_Type; /*!< Size = 1560 (0x618) */ 2604 2605 2606 2607 /* =========================================================================================================================== */ 2608 /* ================ QSPI_NS ================ */ 2609 /* =========================================================================================================================== */ 2610 2611 2612 /** 2613 * @brief External flash interface 0 (QSPI_NS) 2614 */ 2615 2616 typedef struct { /*!< (@ 0x4002B000) QSPI_NS Structure */ 2617 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ 2618 __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to 2619 internal RAM */ 2620 __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external 2621 flash memory */ 2622 __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ 2623 __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ 2624 __IM uint32_t RESERVED[27]; 2625 __IOM uint32_t SUBSCRIBE_ACTIVATE; /*!< (@ 0x00000080) Subscribe configuration for task ACTIVATE */ 2626 __IOM uint32_t SUBSCRIBE_READSTART; /*!< (@ 0x00000084) Subscribe configuration for task READSTART */ 2627 __IOM uint32_t SUBSCRIBE_WRITESTART; /*!< (@ 0x00000088) Subscribe configuration for task WRITESTART */ 2628 __IOM uint32_t SUBSCRIBE_ERASESTART; /*!< (@ 0x0000008C) Subscribe configuration for task ERASESTART */ 2629 __IOM uint32_t SUBSCRIBE_DEACTIVATE; /*!< (@ 0x00000090) Subscribe configuration for task DEACTIVATE */ 2630 __IM uint32_t RESERVED1[27]; 2631 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be 2632 generated as a response to all QSPI tasks 2633 except DEACTIVATE. */ 2634 __IM uint32_t RESERVED2[31]; 2635 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 2636 __IM uint32_t RESERVED3[95]; 2637 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2638 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2639 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2640 __IM uint32_t RESERVED4[125]; 2641 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected 2642 in PSELn registers */ 2643 __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ 2644 __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ 2645 __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ 2646 __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ 2647 __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute 2648 in Place operation. */ 2649 __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ 2650 __IM uint32_t RESERVED5; 2651 __IOM uint32_t XIPEN; /*!< (@ 0x0000054C) Enable Execute in Place operation. */ 2652 __IM uint32_t RESERVED6[4]; 2653 __IOM QSPI_XIP_ENC_Type XIP_ENC; /*!< (@ 0x00000560) Unspecified */ 2654 __IOM QSPI_DMA_ENC_Type DMA_ENC; /*!< (@ 0x00000580) Unspecified */ 2655 __IM uint32_t RESERVED7[24]; 2656 __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ 2657 __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ 2658 __IM uint32_t RESERVED8[3]; 2659 __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep 2660 power-down mode (DPM). */ 2661 __IM uint32_t RESERVED9[3]; 2662 __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ 2663 __IM uint32_t RESERVED10[3]; 2664 __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ 2665 __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ 2666 __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ 2667 __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ 2668 } NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ 2669 2670 2671 2672 /* =========================================================================================================================== */ 2673 /* ================ NFCT_NS ================ */ 2674 /* =========================================================================================================================== */ 2675 2676 2677 /** 2678 * @brief NFC-A compatible radio 0 (NFCT_NS) 2679 */ 2680 2681 typedef struct { /*!< (@ 0x4002D000) NFCT_NS Structure */ 2682 __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing 2683 frames, change state to activated */ 2684 __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ 2685 __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to 2686 sense mode */ 2687 __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change 2688 state to transmit */ 2689 __IM uint32_t RESERVED[3]; 2690 __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ 2691 __IM uint32_t RESERVED1; 2692 __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ 2693 __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ 2694 __IM uint32_t RESERVED2[21]; 2695 __IOM uint32_t SUBSCRIBE_ACTIVATE; /*!< (@ 0x00000080) Subscribe configuration for task ACTIVATE */ 2696 __IOM uint32_t SUBSCRIBE_DISABLE; /*!< (@ 0x00000084) Subscribe configuration for task DISABLE */ 2697 __IOM uint32_t SUBSCRIBE_SENSE; /*!< (@ 0x00000088) Subscribe configuration for task SENSE */ 2698 __IOM uint32_t SUBSCRIBE_STARTTX; /*!< (@ 0x0000008C) Subscribe configuration for task STARTTX */ 2699 __IM uint32_t RESERVED3[3]; 2700 __IOM uint32_t SUBSCRIBE_ENABLERXDATA; /*!< (@ 0x0000009C) Subscribe configuration for task ENABLERXDATA */ 2701 __IM uint32_t RESERVED4; 2702 __IOM uint32_t SUBSCRIBE_GOIDLE; /*!< (@ 0x000000A4) Subscribe configuration for task GOIDLE */ 2703 __IOM uint32_t SUBSCRIBE_GOSLEEP; /*!< (@ 0x000000A8) Subscribe configuration for task GOSLEEP */ 2704 __IM uint32_t RESERVED5[21]; 2705 __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send 2706 frames */ 2707 __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ 2708 __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ 2709 __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted 2710 frame */ 2711 __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air 2712 symbol of a frame */ 2713 __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received 2714 frame */ 2715 __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) 2716 and transferred to RAM, and EasyDMA has 2717 ended accessing the RX buffer */ 2718 __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register 2719 contains details on the source of the error. */ 2720 __IM uint32_t RESERVED6[2]; 2721 __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX 2722 register contains details on the source 2723 of the error. */ 2724 __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) 2725 in Data RAM full. */ 2726 __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA 2727 has ended accessing the TX buffer */ 2728 __IM uint32_t RESERVED7; 2729 __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ 2730 __IM uint32_t RESERVED8[3]; 2731 __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ 2732 __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ 2733 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ 2734 __IM uint32_t RESERVED9[11]; 2735 __IOM uint32_t PUBLISH_READY; /*!< (@ 0x00000180) Publish configuration for event READY */ 2736 __IOM uint32_t PUBLISH_FIELDDETECTED; /*!< (@ 0x00000184) Publish configuration for event FIELDDETECTED */ 2737 __IOM uint32_t PUBLISH_FIELDLOST; /*!< (@ 0x00000188) Publish configuration for event FIELDLOST */ 2738 __IOM uint32_t PUBLISH_TXFRAMESTART; /*!< (@ 0x0000018C) Publish configuration for event TXFRAMESTART */ 2739 __IOM uint32_t PUBLISH_TXFRAMEEND; /*!< (@ 0x00000190) Publish configuration for event TXFRAMEEND */ 2740 __IOM uint32_t PUBLISH_RXFRAMESTART; /*!< (@ 0x00000194) Publish configuration for event RXFRAMESTART */ 2741 __IOM uint32_t PUBLISH_RXFRAMEEND; /*!< (@ 0x00000198) Publish configuration for event RXFRAMEEND */ 2742 __IOM uint32_t PUBLISH_ERROR; /*!< (@ 0x0000019C) Publish configuration for event ERROR */ 2743 __IM uint32_t RESERVED10[2]; 2744 __IOM uint32_t PUBLISH_RXERROR; /*!< (@ 0x000001A8) Publish configuration for event RXERROR */ 2745 __IOM uint32_t PUBLISH_ENDRX; /*!< (@ 0x000001AC) Publish configuration for event ENDRX */ 2746 __IOM uint32_t PUBLISH_ENDTX; /*!< (@ 0x000001B0) Publish configuration for event ENDTX */ 2747 __IM uint32_t RESERVED11; 2748 __IOM uint32_t PUBLISH_AUTOCOLRESSTARTED; /*!< (@ 0x000001B8) Publish configuration for event AUTOCOLRESSTARTED */ 2749 __IM uint32_t RESERVED12[3]; 2750 __IOM uint32_t PUBLISH_COLLISION; /*!< (@ 0x000001C8) Publish configuration for event COLLISION */ 2751 __IOM uint32_t PUBLISH_SELECTED; /*!< (@ 0x000001CC) Publish configuration for event SELECTED */ 2752 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x000001D0) Publish configuration for event STARTED */ 2753 __IM uint32_t RESERVED13[11]; 2754 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2755 __IM uint32_t RESERVED14[63]; 2756 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2757 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2758 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2759 __IM uint32_t RESERVED15[62]; 2760 __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ 2761 __IM uint32_t RESERVED16; 2762 __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ 2763 __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) Current operating state of NFC tag */ 2764 __IM uint32_t RESERVED17[3]; 2765 __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ 2766 __IM uint32_t RESERVED18[6]; 2767 __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ 2768 __IM uint32_t RESERVED19[49]; 2769 __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ 2770 __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ 2771 __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ 2772 __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in 2773 Data RAM */ 2774 __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD 2775 data storage each */ 2776 __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ 2777 __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ 2778 __IM uint32_t RESERVED20; 2779 __IOM uint32_t MODULATIONCTRL; /*!< (@ 0x0000052C) Enables the modulation output to a GPIO pin which 2780 can be connected to a second external antenna. */ 2781 __IM uint32_t RESERVED21[2]; 2782 __IOM uint32_t MODULATIONPSEL; /*!< (@ 0x00000538) Pin select for Modulation control */ 2783 __IM uint32_t RESERVED22[21]; 2784 __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ 2785 __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ 2786 __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ 2787 __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. 2788 This setting must be done before the NFCT 2789 peripheral is activated. */ 2790 __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ 2791 __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ 2792 } NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ 2793 2794 2795 2796 /* =========================================================================================================================== */ 2797 /* ================ MUTEX_NS ================ */ 2798 /* =========================================================================================================================== */ 2799 2800 2801 /** 2802 * @brief MUTEX 0 (MUTEX_NS) 2803 */ 2804 2805 typedef struct { /*!< (@ 0x40030000) MUTEX_NS Structure */ 2806 __IM uint32_t RESERVED[256]; 2807 __IOM uint32_t MUTEX[16]; /*!< (@ 0x00000400) Description collection: Mutex register */ 2808 } NRF_MUTEX_Type; /*!< Size = 1088 (0x440) */ 2809 2810 2811 2812 /* =========================================================================================================================== */ 2813 /* ================ QDEC0_NS ================ */ 2814 /* =========================================================================================================================== */ 2815 2816 2817 /** 2818 * @brief Quadrature Decoder 0 (QDEC0_NS) 2819 */ 2820 2821 typedef struct { /*!< (@ 0x40033000) QDEC0_NS Structure */ 2822 __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ 2823 __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ 2824 __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ 2825 __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ 2826 __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ 2827 __IM uint32_t RESERVED[27]; 2828 __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000080) Subscribe configuration for task START */ 2829 __IOM uint32_t SUBSCRIBE_STOP; /*!< (@ 0x00000084) Subscribe configuration for task STOP */ 2830 __IOM uint32_t SUBSCRIBE_READCLRACC; /*!< (@ 0x00000088) Subscribe configuration for task READCLRACC */ 2831 __IOM uint32_t SUBSCRIBE_RDCLRACC; /*!< (@ 0x0000008C) Subscribe configuration for task RDCLRACC */ 2832 __IOM uint32_t SUBSCRIBE_RDCLRDBL; /*!< (@ 0x00000090) Subscribe configuration for task RDCLRDBL */ 2833 __IM uint32_t RESERVED1[27]; 2834 __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value 2835 written to the SAMPLE register */ 2836 __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ 2837 __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ 2838 __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ 2839 __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ 2840 __IM uint32_t RESERVED2[27]; 2841 __IOM uint32_t PUBLISH_SAMPLERDY; /*!< (@ 0x00000180) Publish configuration for event SAMPLERDY */ 2842 __IOM uint32_t PUBLISH_REPORTRDY; /*!< (@ 0x00000184) Publish configuration for event REPORTRDY */ 2843 __IOM uint32_t PUBLISH_ACCOF; /*!< (@ 0x00000188) Publish configuration for event ACCOF */ 2844 __IOM uint32_t PUBLISH_DBLRDY; /*!< (@ 0x0000018C) Publish configuration for event DBLRDY */ 2845 __IOM uint32_t PUBLISH_STOPPED; /*!< (@ 0x00000190) Publish configuration for event STOPPED */ 2846 __IM uint32_t RESERVED3[27]; 2847 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2848 __IM uint32_t RESERVED4[64]; 2849 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2850 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2851 __IM uint32_t RESERVED5[125]; 2852 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ 2853 __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ 2854 __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ 2855 __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ 2856 __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY 2857 and DBLRDY events can be generated */ 2858 __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ 2859 __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the 2860 READCLRACC or RDCLRACC task */ 2861 __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ 2862 __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ 2863 __IM uint32_t RESERVED6[5]; 2864 __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ 2865 __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected 2866 double transitions */ 2867 __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC 2868 or RDCLRDBL task */ 2869 } NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ 2870 2871 2872 2873 /* =========================================================================================================================== */ 2874 /* ================ USBD_NS ================ */ 2875 /* =========================================================================================================================== */ 2876 2877 2878 /** 2879 * @brief Universal serial bus device 0 (USBD_NS) 2880 */ 2881 2882 typedef struct { /*!< (@ 0x40036000) USBD_NS Structure */ 2883 __IM uint32_t RESERVED; 2884 __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR 2885 and EPIN[n].MAXCNT registers values, and 2886 enables endpoint IN n to respond to traffic 2887 from host */ 2888 __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers 2889 values, and enables sending data on ISO 2890 endpoint */ 2891 __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR 2892 and EPOUT[n].MAXCNT registers values, and 2893 enables endpoint n to respond to traffic 2894 from host */ 2895 __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers 2896 values, and enables receiving of data on 2897 ISO endpoint */ 2898 __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ 2899 __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ 2900 __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint 2901 0 */ 2902 __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined 2903 in the DPDMVALUE register */ 2904 __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state 2905 (USB engine takes control) */ 2906 __IM uint32_t RESERVED1[9]; 2907 __IOM uint32_t SUBSCRIBE_STARTEPIN[8]; /*!< (@ 0x00000084) Description collection: Subscribe configuration 2908 for task STARTEPIN[n] */ 2909 __IOM uint32_t SUBSCRIBE_STARTISOIN; /*!< (@ 0x000000A4) Subscribe configuration for task STARTISOIN */ 2910 __IOM uint32_t SUBSCRIBE_STARTEPOUT[8]; /*!< (@ 0x000000A8) Description collection: Subscribe configuration 2911 for task STARTEPOUT[n] */ 2912 __IOM uint32_t SUBSCRIBE_STARTISOOUT; /*!< (@ 0x000000C8) Subscribe configuration for task STARTISOOUT */ 2913 __IOM uint32_t SUBSCRIBE_EP0RCVOUT; /*!< (@ 0x000000CC) Subscribe configuration for task EP0RCVOUT */ 2914 __IOM uint32_t SUBSCRIBE_EP0STATUS; /*!< (@ 0x000000D0) Subscribe configuration for task EP0STATUS */ 2915 __IOM uint32_t SUBSCRIBE_EP0STALL; /*!< (@ 0x000000D4) Subscribe configuration for task EP0STALL */ 2916 __IOM uint32_t SUBSCRIBE_DPDMDRIVE; /*!< (@ 0x000000D8) Subscribe configuration for task DPDMDRIVE */ 2917 __IOM uint32_t SUBSCRIBE_DPDMNODRIVE; /*!< (@ 0x000000DC) Subscribe configuration for task DPDMNODRIVE */ 2918 __IM uint32_t RESERVED2[8]; 2919 __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected 2920 on USB lines */ 2921 __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, 2922 or EPOUT[n].PTR and EPOUT[n].MAXCNT registers 2923 have been captured on all endpoints reported 2924 in the EPSTATUS register */ 2925 __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer 2926 has been consumed. The buffer can be accessed 2927 safely by software. */ 2928 __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place 2929 on the control endpoint */ 2930 __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The 2931 buffer can be accessed safely by software. */ 2932 __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer 2933 has been consumed. The buffer can be accessed 2934 safely by software. */ 2935 __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The 2936 buffer can be accessed safely by software. */ 2937 __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition 2938 has been detected on USB lines */ 2939 __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific 2940 events has occurred. Check EVENTCAUSE register 2941 to find the cause. */ 2942 __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) 2943 on the control endpoint */ 2944 __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, 2945 indicated by the EPDATASTATUS register */ 2946 __IM uint32_t RESERVED3[7]; 2947 __IOM uint32_t PUBLISH_USBRESET; /*!< (@ 0x00000180) Publish configuration for event USBRESET */ 2948 __IOM uint32_t PUBLISH_STARTED; /*!< (@ 0x00000184) Publish configuration for event STARTED */ 2949 __IOM uint32_t PUBLISH_ENDEPIN[8]; /*!< (@ 0x00000188) Description collection: Publish configuration 2950 for event ENDEPIN[n] */ 2951 __IOM uint32_t PUBLISH_EP0DATADONE; /*!< (@ 0x000001A8) Publish configuration for event EP0DATADONE */ 2952 __IOM uint32_t PUBLISH_ENDISOIN; /*!< (@ 0x000001AC) Publish configuration for event ENDISOIN */ 2953 __IOM uint32_t PUBLISH_ENDEPOUT[8]; /*!< (@ 0x000001B0) Description collection: Publish configuration 2954 for event ENDEPOUT[n] */ 2955 __IOM uint32_t PUBLISH_ENDISOOUT; /*!< (@ 0x000001D0) Publish configuration for event ENDISOOUT */ 2956 __IOM uint32_t PUBLISH_SOF; /*!< (@ 0x000001D4) Publish configuration for event SOF */ 2957 __IOM uint32_t PUBLISH_USBEVENT; /*!< (@ 0x000001D8) Publish configuration for event USBEVENT */ 2958 __IOM uint32_t PUBLISH_EP0SETUP; /*!< (@ 0x000001DC) Publish configuration for event EP0SETUP */ 2959 __IOM uint32_t PUBLISH_EPDATA; /*!< (@ 0x000001E0) Publish configuration for event EPDATA */ 2960 __IM uint32_t RESERVED4[7]; 2961 __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ 2962 __IM uint32_t RESERVED5[63]; 2963 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 2964 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 2965 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 2966 __IM uint32_t RESERVED6[61]; 2967 __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ 2968 __IM uint32_t RESERVED7[7]; 2969 __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ 2970 __IM uint32_t RESERVED8; 2971 __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA 2972 registers have been captured */ 2973 __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an 2974 acknowledged data transfer has occurred 2975 (EPDATA event) */ 2976 __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ 2977 __IM uint32_t RESERVED9[3]; 2978 __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ 2979 __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ 2980 __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ 2981 __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ 2982 __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ 2983 __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ 2984 __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ 2985 __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ 2986 __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ 2987 __IM uint32_t RESERVED10[15]; 2988 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ 2989 __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ 2990 __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by 2991 the DPDMDRIVE task. The DPDMNODRIVE task 2992 reverts the control of the lines to MAC 2993 IP (no forcing). */ 2994 __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ 2995 __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ 2996 __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ 2997 __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ 2998 __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ 2999 __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame 3000 counter */ 3001 __IM uint32_t RESERVED11[2]; 3002 __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral Low-power mode during 3003 USB suspend */ 3004 __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint 3005 to an IN token when no data is ready to 3006 be sent */ 3007 __IM uint32_t RESERVED12[51]; 3008 __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ 3009 __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ 3010 __IM uint32_t RESERVED13[21]; 3011 __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ 3012 __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ 3013 } NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ 3014 3015 3016 3017 /* =========================================================================================================================== */ 3018 /* ================ USBREGULATOR_NS ================ */ 3019 /* =========================================================================================================================== */ 3020 3021 3022 /** 3023 * @brief USB Regulator 0 (USBREGULATOR_NS) 3024 */ 3025 3026 typedef struct { /*!< (@ 0x40037000) USBREGULATOR_NS Structure */ 3027 __IM uint32_t RESERVED[64]; 3028 __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x00000100) Voltage supply detected on VBUS */ 3029 __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000104) Voltage supply removed from VBUS */ 3030 __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000108) USB 3.3 V supply ready */ 3031 __IM uint32_t RESERVED1[29]; 3032 __IOM uint32_t PUBLISH_USBDETECTED; /*!< (@ 0x00000180) Publish configuration for event USBDETECTED */ 3033 __IOM uint32_t PUBLISH_USBREMOVED; /*!< (@ 0x00000184) Publish configuration for event USBREMOVED */ 3034 __IOM uint32_t PUBLISH_USBPWRRDY; /*!< (@ 0x00000188) Publish configuration for event USBPWRRDY */ 3035 __IM uint32_t RESERVED2[93]; 3036 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 3037 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 3038 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 3039 __IM uint32_t RESERVED3[61]; 3040 __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000400) USB supply status */ 3041 } NRF_USBREG_Type; /*!< Size = 1028 (0x404) */ 3042 3043 3044 3045 /* =========================================================================================================================== */ 3046 /* ================ KMU_NS ================ */ 3047 /* =========================================================================================================================== */ 3048 3049 3050 /** 3051 * @brief Key management unit 0 (KMU_NS) 3052 */ 3053 3054 typedef struct { /*!< (@ 0x40039000) KMU_NS Structure */ 3055 __OM uint32_t TASKS_PUSH_KEYSLOT; /*!< (@ 0x00000000) Push a key slot over secure APB */ 3056 __IM uint32_t RESERVED[63]; 3057 __IOM uint32_t EVENTS_KEYSLOT_PUSHED; /*!< (@ 0x00000100) Key slot successfully pushed over secure APB */ 3058 __IOM uint32_t EVENTS_KEYSLOT_REVOKED; /*!< (@ 0x00000104) Key slot has been revoked and cannot be tasked 3059 for selection */ 3060 __IOM uint32_t EVENTS_KEYSLOT_ERROR; /*!< (@ 0x00000108) No key slot selected, no destination address 3061 defined, or error during push operation */ 3062 __IM uint32_t RESERVED1[125]; 3063 __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ 3064 __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ 3065 __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ 3066 __IM uint32_t INTPEND; /*!< (@ 0x0000030C) Pending interrupts */ 3067 __IM uint32_t RESERVED2[63]; 3068 __IM uint32_t STATUS; /*!< (@ 0x0000040C) Status bits for KMU operation */ 3069 __IM uint32_t RESERVED3[60]; 3070 __IOM uint32_t SELECTKEYSLOT; /*!< (@ 0x00000500) Select key slot to be read over AHB or pushed 3071 over secure APB when TASKS_PUSH_KEYSLOT 3072 is started */ 3073 } NRF_KMU_Type; /*!< Size = 1284 (0x504) */ 3074 3075 3076 3077 /* =========================================================================================================================== */ 3078 /* ================ NVMC_NS ================ */ 3079 /* =========================================================================================================================== */ 3080 3081 3082 /** 3083 * @brief Non-volatile memory controller 0 (NVMC_NS) 3084 */ 3085 3086 typedef struct { /*!< (@ 0x40039000) NVMC_NS Structure */ 3087 __IM uint32_t RESERVED[256]; 3088 __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ 3089 __IM uint32_t RESERVED1; 3090 __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ 3091 __IM uint32_t RESERVED2[62]; 3092 __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ 3093 __IM uint32_t RESERVED3; 3094 __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ 3095 __IM uint32_t RESERVED4[3]; 3096 __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ 3097 __IM uint32_t RESERVED5[25]; 3098 __IOM uint32_t CONFIGNS; /*!< (@ 0x00000584) Non-secure configuration register */ 3099 __OM uint32_t WRITEUICRNS; /*!< (@ 0x00000588) Non-secure APPROTECT enable register */ 3100 } NRF_NVMC_Type; /*!< Size = 1420 (0x58c) */ 3101 3102 3103 3104 /* =========================================================================================================================== */ 3105 /* ================ P0_NS ================ */ 3106 /* =========================================================================================================================== */ 3107 3108 3109 /** 3110 * @brief GPIO Port 0 (P0_NS) 3111 */ 3112 3113 typedef struct { /*!< (@ 0x40842500) P0_NS Structure */ 3114 __IM uint32_t RESERVED; 3115 __IOM uint32_t OUT; /*!< (@ 0x00000004) Write GPIO port */ 3116 __IOM uint32_t OUTSET; /*!< (@ 0x00000008) Set individual bits in GPIO port */ 3117 __IOM uint32_t OUTCLR; /*!< (@ 0x0000000C) Clear individual bits in GPIO port */ 3118 __IM uint32_t IN; /*!< (@ 0x00000010) Read GPIO port */ 3119 __IOM uint32_t DIR; /*!< (@ 0x00000014) Direction of GPIO pins */ 3120 __IOM uint32_t DIRSET; /*!< (@ 0x00000018) DIR set register */ 3121 __IOM uint32_t DIRCLR; /*!< (@ 0x0000001C) DIR clear register */ 3122 __IOM uint32_t LATCH; /*!< (@ 0x00000020) Latch register indicating what GPIO pins that 3123 have met the criteria set in the PIN_CNF[n].SENSE 3124 registers */ 3125 __IOM uint32_t DETECTMODE; /*!< (@ 0x00000024) Select between default DETECT signal behavior 3126 and LDETECT mode */ 3127 __IOM uint32_t DETECTMODE_SEC; /*!< (@ 0x00000028) Select between default DETECT signal behavior 3128 and LDETECT mode */ 3129 __IM uint32_t RESERVED1[117]; 3130 __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000200) Description collection: Configuration of GPIO 3131 pins */ 3132 } NRF_GPIO_Type; /*!< Size = 640 (0x280) */ 3133 3134 3135 3136 /* =========================================================================================================================== */ 3137 /* ================ CRYPTOCELL_S ================ */ 3138 /* =========================================================================================================================== */ 3139 3140 3141 /** 3142 * @brief CRYPTOCELL register interface (CRYPTOCELL_S) 3143 */ 3144 3145 typedef struct { /*!< (@ 0x50844000) CRYPTOCELL_S Structure */ 3146 __IM uint32_t RESERVED[320]; 3147 __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem. */ 3148 } NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ 3149 3150 3151 3152 /* =========================================================================================================================== */ 3153 /* ================ CC_AES_S ================ */ 3154 /* =========================================================================================================================== */ 3155 3156 3157 /** 3158 * @brief CRYPTOCELL AES engine (CC_AES_S) 3159 */ 3160 3161 typedef struct { /*!< (@ 0x50845000) CC_AES_S Structure */ 3162 __IM uint32_t RESERVED[256]; 3163 __OM uint32_t AES_KEY_0[8]; /*!< (@ 0x00000400) Description collection: AES key value to use 3164 in non-tunneling operations, or as the first 3165 tunnel stage key in tunneling operations. 3166 The initial AES_KEY_0[0] register holds 3167 the least significant bits [31:0] of the 3168 key value. */ 3169 __OM uint32_t AES_KEY_1[8]; /*!< (@ 0x00000420) Description collection: AES key value to use 3170 as the second tunnel stage key in tunneling 3171 operations. The initial AES_KEY_1[0] register 3172 holds the least significant bits [31:0] 3173 of the key value. */ 3174 __IOM uint32_t AES_IV_0[4]; /*!< (@ 0x00000440) Description collection: AES Initialization Vector 3175 (IV) to use in non-tunneling operations, 3176 or as the first tunnel stage IV in tunneling 3177 operations. The initial AES_IV_0[0] register 3178 holds the least significant bits [31:0] 3179 of the IV. */ 3180 __IOM uint32_t AES_IV_1[4]; /*!< (@ 0x00000450) Description collection: AES Initialization Vector 3181 (IV) to use as the second tunnel stage IV 3182 in tunneling operations. The initial AES_IV_1[0] 3183 register holds the least significant bits 3184 [31:0] of the IV. */ 3185 __IOM uint32_t AES_CTR[4]; /*!< (@ 0x00000460) Description collection: AES counter (CTR) to 3186 use in non-tunneling and tunneling operations. 3187 The initial AES_CTR[0] register holds the 3188 least significant bits [31:0] of the CTR. */ 3189 __IM uint32_t AES_BUSY; /*!< (@ 0x00000470) Status register for AES engine activity. */ 3190 __IM uint32_t RESERVED1[2]; 3191 __OM uint32_t AES_CMAC_INIT; /*!< (@ 0x0000047C) Writing to this address triggers the AES engine 3192 to generate K1 and K2 for AES-CMAC operations. */ 3193 __IM uint32_t RESERVED2[15]; 3194 __IOM uint32_t AES_REMAINING_BYTES; /*!< (@ 0x000004BC) This register should be set with the amount of 3195 remaining bytes until the end of the current 3196 AES operation. */ 3197 __IOM uint32_t AES_CONTROL; /*!< (@ 0x000004C0) Control the AES engine behavior. */ 3198 __IM uint32_t RESERVED3; 3199 __IM uint32_t AES_HW_FLAGS; /*!< (@ 0x000004C8) Hardware configuration of the AES engine. Reset 3200 value holds the supported features. */ 3201 __IM uint32_t RESERVED4[3]; 3202 __IOM uint32_t AES_CTR_NO_INCREMENT; /*!< (@ 0x000004D8) This register enables the AES CTR no increment 3203 mode in which the counter mode is not incremented 3204 between two blocks */ 3205 __IM uint32_t RESERVED5[6]; 3206 __OM uint32_t AES_SW_RESET; /*!< (@ 0x000004F4) Reset the AES engine. */ 3207 __IM uint32_t RESERVED6[11]; 3208 __OM uint32_t AES_CMAC_SIZE0_KICK; /*!< (@ 0x00000524) Writing to this address triggers the AES engine 3209 to perform a CMAC operation with size 0. 3210 The CMAC result can be read from the AES_IV_0 3211 register. */ 3212 } NRF_CC_AES_Type; /*!< Size = 1320 (0x528) */ 3213 3214 3215 3216 /* =========================================================================================================================== */ 3217 /* ================ CC_AHB_S ================ */ 3218 /* =========================================================================================================================== */ 3219 3220 3221 /** 3222 * @brief CRYPTOCELL AHB interface (CC_AHB_S) 3223 */ 3224 3225 typedef struct { /*!< (@ 0x50845000) CC_AHB_S Structure */ 3226 __IM uint32_t RESERVED[704]; 3227 __IOM uint32_t AHBM_SINGLES; /*!< (@ 0x00000B00) This register forces the AHB transactions from 3228 CRYPTOCELL master to be always singles. */ 3229 __IOM uint32_t AHBM_HPROT; /*!< (@ 0x00000B04) This register holds the AHB HPROT value */ 3230 __IOM uint32_t AHBM_HMASTLOCK; /*!< (@ 0x00000B08) This register holds AHB HMASTLOCK value */ 3231 __IOM uint32_t AHBM_HNONSEC; /*!< (@ 0x00000B0C) This register holds AHB HNONSEC value */ 3232 } NRF_CC_AHB_Type; /*!< Size = 2832 (0xb10) */ 3233 3234 3235 3236 /* =========================================================================================================================== */ 3237 /* ================ CC_AO_S ================ */ 3238 /* =========================================================================================================================== */ 3239 3240 3241 /** 3242 * @brief CryptoCell AO (CC_AO_S) 3243 */ 3244 3245 typedef struct { /*!< (@ 0x50845000) CC_AO_S Structure */ 3246 __IM uint32_t RESERVED[910]; 3247 __IOM uint32_t AO_APB_FILTERING; /*!< (@ 0x00000E38) This register holds the AO_APB_FILTERING configuration. */ 3248 __IM uint32_t RESERVED1; 3249 __OM uint32_t CC_SW_RESET; /*!< (@ 0x00000E40) Reset the CRYPTOCELL subsystem. */ 3250 } NRF_CC_AO_Type; /*!< Size = 3652 (0xe44) */ 3251 3252 3253 3254 /* =========================================================================================================================== */ 3255 /* ================ CC_CHACHA_S ================ */ 3256 /* =========================================================================================================================== */ 3257 3258 3259 /** 3260 * @brief CRYPTOCELL CHACHA engine (CC_CHACHA_S) 3261 */ 3262 3263 typedef struct { /*!< (@ 0x50845000) CC_CHACHA_S Structure */ 3264 __IM uint32_t RESERVED[224]; 3265 __IOM uint32_t CHACHA_CONTROL; /*!< (@ 0x00000380) Control the CHACHA engine behavior. */ 3266 __IM uint32_t CHACHA_VERSION; /*!< (@ 0x00000384) CHACHA engine HW version */ 3267 __OM uint32_t CHACHA_KEY[8]; /*!< (@ 0x00000388) Description collection: CHACHA key value to use. 3268 The initial CHACHA_KEY[0] register holds 3269 the least significant bits [31:0] of the 3270 key value. */ 3271 __IOM uint32_t CHACHA_IV[2]; /*!< (@ 0x000003A8) Description collection: CHACHA Initialization 3272 Vector (IV) to use. The IV is also known 3273 as the nonce. */ 3274 __IM uint32_t CHACHA_BUSY; /*!< (@ 0x000003B0) Status register for CHACHA engine activity. */ 3275 __IM uint32_t CHACHA_HW_FLAGS; /*!< (@ 0x000003B4) Hardware configuration of the CHACHA engine. 3276 Reset value holds the supported features. */ 3277 __IOM uint32_t CHACHA_BLOCK_CNT_LSB; /*!< (@ 0x000003B8) Store the LSB value of the block counter, in 3278 order to support suspend/resume of operation */ 3279 __IOM uint32_t CHACHA_BLOCK_CNT_MSB; /*!< (@ 0x000003BC) Store the MSB value of the block counter, in 3280 order to support suspend/resume of operation */ 3281 __OM uint32_t CHACHA_SW_RESET; /*!< (@ 0x000003C0) Reset the CHACHA engine. */ 3282 __IM uint32_t CHACHA_POLY1305_KEY[8]; /*!< (@ 0x000003C4) Description collection: The auto-generated key 3283 to use in Poly1305 MAC calculation. The 3284 initial CHACHA_POLY1305_KEY[0] register 3285 holds the least significant bits [31:0] 3286 of the key value. */ 3287 __IOM uint32_t CHACHA_ENDIANNESS; /*!< (@ 0x000003E4) CHACHA engine data order configuration. */ 3288 __IM uint32_t CHACHA_DEBUG; /*!< (@ 0x000003E8) Debug register for the CHACHA engine */ 3289 } NRF_CC_CHACHA_Type; /*!< Size = 1004 (0x3ec) */ 3290 3291 3292 3293 /* =========================================================================================================================== */ 3294 /* ================ CC_CTL_S ================ */ 3295 /* =========================================================================================================================== */ 3296 3297 3298 /** 3299 * @brief CRYPTOCELL CTL interface (CC_CTL_S) 3300 */ 3301 3302 typedef struct { /*!< (@ 0x50845000) CC_CTL_S Structure */ 3303 __IM uint32_t RESERVED[576]; 3304 __OM uint32_t CRYPTO_CTL; /*!< (@ 0x00000900) Defines the cryptographic flow. */ 3305 __IM uint32_t RESERVED1[3]; 3306 __IM uint32_t CRYPTO_BUSY; /*!< (@ 0x00000910) Status register for cryptographic cores engine 3307 activity. */ 3308 __IM uint32_t RESERVED2[2]; 3309 __IM uint32_t HASH_BUSY; /*!< (@ 0x0000091C) Status register for HASH engine activity. */ 3310 __IM uint32_t RESERVED3[4]; 3311 __IOM uint32_t CONTEXT_ID; /*!< (@ 0x00000930) A general-purpose read/write register. */ 3312 } NRF_CC_CTL_Type; /*!< Size = 2356 (0x934) */ 3313 3314 3315 3316 /* =========================================================================================================================== */ 3317 /* ================ CC_DIN_S ================ */ 3318 /* =========================================================================================================================== */ 3319 3320 3321 /** 3322 * @brief CRYPTOCELL Data IN interface (CC_DIN_S) 3323 */ 3324 3325 typedef struct { /*!< (@ 0x50845000) CC_DIN_S Structure */ 3326 __IM uint32_t RESERVED[768]; 3327 __OM uint32_t DIN_BUFFER; /*!< (@ 0x00000C00) Used by CPU to write data directly to the DIN 3328 buffer, which is then sent to the cryptographic 3329 engines for processing. */ 3330 __IM uint32_t RESERVED1[7]; 3331 __IM uint32_t DIN_DMA_MEM_BUSY; /*!< (@ 0x00000C20) Status register for DIN DMA engine activity when 3332 accessing memory. */ 3333 __IM uint32_t RESERVED2; 3334 __OM uint32_t SRC_MEM_ADDR; /*!< (@ 0x00000C28) Data source address in memory. */ 3335 __OM uint32_t SRC_MEM_SIZE; /*!< (@ 0x00000C2C) The number of bytes to be read from memory. Writing 3336 to this register triggers the DMA operation. */ 3337 __IOM uint32_t SRC_SRAM_ADDR; /*!< (@ 0x00000C30) Data source address in RNG SRAM. */ 3338 __OM uint32_t SRC_SRAM_SIZE; /*!< (@ 0x00000C34) The number of bytes to be read from RNG SRAM. 3339 Writing to this register triggers the DMA 3340 operation. */ 3341 __IM uint32_t DIN_DMA_SRAM_BUSY; /*!< (@ 0x00000C38) Status register for DIN DMA engine activity when 3342 accessing RNG SRAM. */ 3343 __IOM uint32_t DIN_DMA_SRAM_ENDIANNESS; /*!< (@ 0x00000C3C) Configure the endianness of DIN DMA transactions 3344 towards RNG SRAM. */ 3345 __IM uint32_t RESERVED3; 3346 __OM uint32_t DIN_SW_RESET; /*!< (@ 0x00000C44) Reset the DIN DMA engine. */ 3347 __OM uint32_t DIN_CPU_DATA; /*!< (@ 0x00000C48) Specifies the number of bytes the CPU will write 3348 to the DIN_BUFFER, ensuring the cryptographic 3349 engine processes the correct amount of data. */ 3350 __OM uint32_t DIN_WRITE_ALIGN; /*!< (@ 0x00000C4C) Indicates that the next CPU write to the DIN_BUFFER 3351 is the last in the sequence. This is needed 3352 only when the data size is NOT modulo 4 3353 (e.g. HASH padding). */ 3354 __IM uint32_t DIN_FIFO_EMPTY; /*!< (@ 0x00000C50) Register indicating if DIN FIFO is empty and 3355 if more data can be accepted. */ 3356 __IM uint32_t RESERVED4; 3357 __OM uint32_t DIN_FIFO_RESET; /*!< (@ 0x00000C58) Reset the DIN FIFO, effectively clearing the 3358 FIFO for new data. */ 3359 } NRF_CC_DIN_Type; /*!< Size = 3164 (0xc5c) */ 3360 3361 3362 3363 /* =========================================================================================================================== */ 3364 /* ================ CC_DOUT_S ================ */ 3365 /* =========================================================================================================================== */ 3366 3367 3368 /** 3369 * @brief CRYPTOCELL Data OUT interface (CC_DOUT_S) 3370 */ 3371 3372 typedef struct { /*!< (@ 0x50845000) CC_DOUT_S Structure */ 3373 __IM uint32_t RESERVED[832]; 3374 __IM uint32_t DOUT_BUFFER; /*!< (@ 0x00000D00) Cryptographic results directly accessible by 3375 the CPU. */ 3376 __IM uint32_t RESERVED1[7]; 3377 __IM uint32_t DOUT_DMA_MEM_BUSY; /*!< (@ 0x00000D20) Status register for DOUT DMA engine activity 3378 when accessing memory. */ 3379 __IM uint32_t RESERVED2; 3380 __OM uint32_t DST_MEM_ADDR; /*!< (@ 0x00000D28) Data destination address in memory. */ 3381 __OM uint32_t DST_MEM_SIZE; /*!< (@ 0x00000D2C) The number of bytes to be written to memory. */ 3382 __IOM uint32_t DST_SRAM_ADDR; /*!< (@ 0x00000D30) Data destination address in RNG SRAM. */ 3383 __OM uint32_t DST_SRAM_SIZE; /*!< (@ 0x00000D34) The number of bytes to be written to RNG SRAM. */ 3384 __IM uint32_t DOUT_DMA_SRAM_BUSY; /*!< (@ 0x00000D38) Status register for DOUT DMA engine activity 3385 when accessing RNG SRAM. */ 3386 __IOM uint32_t DOUT_DMA_SRAM_ENDIANNESS; /*!< (@ 0x00000D3C) Configure the endianness of DOUT DMA transactions 3387 towards RNG SRAM. */ 3388 __IM uint32_t RESERVED3; 3389 __OM uint32_t DOUT_READ_ALIGN; /*!< (@ 0x00000D44) Indication that the next CPU read from the DOUT_BUFFER 3390 is the last in the sequence. This is needed 3391 only when the data size is NOT modulo 4 3392 (e.g. HASH padding). */ 3393 __IM uint32_t RESERVED4[2]; 3394 __IM uint32_t DOUT_FIFO_EMPTY; /*!< (@ 0x00000D50) Register indicating if DOUT FIFO is empty or 3395 if more data will come. */ 3396 __IM uint32_t RESERVED5; 3397 __OM uint32_t DOUT_SW_RESET; /*!< (@ 0x00000D58) Reset the DOUT DMA engine. */ 3398 } NRF_CC_DOUT_Type; /*!< Size = 3420 (0xd5c) */ 3399 3400 3401 3402 /* =========================================================================================================================== */ 3403 /* ================ CC_GHASH_S ================ */ 3404 /* =========================================================================================================================== */ 3405 3406 3407 /** 3408 * @brief CRYPTOCELL GHASH engine (CC_GHASH_S) 3409 */ 3410 3411 typedef struct { /*!< (@ 0x50845000) CC_GHASH_S Structure */ 3412 __IM uint32_t RESERVED[600]; 3413 __OM uint32_t GHASH_SUBKEY[4]; /*!< (@ 0x00000960) Description collection: GHASH subkey value to 3414 use. The initial GHASH_SUBKEY[0] register 3415 holds the least significant bits [31:0] 3416 of the subkey value. */ 3417 __IOM uint32_t GHASH_IV[4]; /*!< (@ 0x00000970) Description collection: GHASH Initialization 3418 Vector (IV) to use. The initial GHASH_IV[0] 3419 register holds the least significant bits 3420 [31:0] of the IV. */ 3421 __IM uint32_t GHASH_BUSY; /*!< (@ 0x00000980) Status register for GHASH engine activity. */ 3422 __OM uint32_t GHASH_INIT; /*!< (@ 0x00000984) Configure the GHASH engine for a new GHASH operation. */ 3423 } NRF_CC_GHASH_Type; /*!< Size = 2440 (0x988) */ 3424 3425 3426 3427 /* =========================================================================================================================== */ 3428 /* ================ CC_HASH_S ================ */ 3429 /* =========================================================================================================================== */ 3430 3431 3432 /** 3433 * @brief CRYPTOCELL HASH engine (CC_HASH_S) 3434 */ 3435 3436 typedef struct { /*!< (@ 0x50845000) CC_HASH_S Structure */ 3437 __IM uint32_t RESERVED[400]; 3438 __IOM uint32_t HASH_H[8]; /*!< (@ 0x00000640) Description collection: HASH_H value registers. 3439 The initial HASH_H[0] register holds the 3440 least significant bits [31:0] of the value. */ 3441 __IM uint32_t RESERVED1[9]; 3442 __OM uint32_t HASH_PAD_AUTO; /*!< (@ 0x00000684) Configure the HASH engine to automatically pad 3443 data at the end of the DMA transfer to complete 3444 the digest operation. */ 3445 __IOM uint32_t HASH_XOR_DIN; /*!< (@ 0x00000688) Perform an XOR operation of the DIN DMA engine 3446 input data being fed into the HASH engine. 3447 Set this register to '0' if XOR is not required. */ 3448 __IM uint32_t RESERVED2[2]; 3449 __OM uint32_t HASH_INIT_STATE; /*!< (@ 0x00000694) Configure HASH engine initial state registers. */ 3450 __IM uint32_t RESERVED3[3]; 3451 __OM uint32_t HASH_SELECT; /*!< (@ 0x000006A4) Select HASH or GHASH engine as the digest engine 3452 to use. */ 3453 __IM uint32_t RESERVED4[70]; 3454 __IOM uint32_t HASH_CONTROL; /*!< (@ 0x000007C0) Control the HASH engine behavior. */ 3455 __IOM uint32_t HASH_PAD; /*!< (@ 0x000007C4) Enable the hardware padding feature of the HASH 3456 engine. */ 3457 __IOM uint32_t HASH_PAD_FORCE; /*!< (@ 0x000007C8) Force the hardware padding operation to trigger 3458 if the input data length is zero bytes. */ 3459 __IOM uint32_t HASH_CUR_LEN_0; /*!< (@ 0x000007CC) Bits [31:0] of the number of bytes that have 3460 been digested so far. */ 3461 __IOM uint32_t HASH_CUR_LEN_1; /*!< (@ 0x000007D0) Bits [63:32] of the number of bytes that have 3462 been digested so far. */ 3463 __IM uint32_t RESERVED5[2]; 3464 __IM uint32_t HASH_HW_FLAGS; /*!< (@ 0x000007DC) Hardware configuration of the HASH engine. Reset 3465 value holds the supported features. */ 3466 __IM uint32_t RESERVED6; 3467 __OM uint32_t HASH_SW_RESET; /*!< (@ 0x000007E4) Reset the HASH engine. */ 3468 __IOM uint32_t HASH_ENDIANNESS; /*!< (@ 0x000007E8) Configure the endianness of HASH data and padding 3469 generation. */ 3470 } NRF_CC_HASH_Type; /*!< Size = 2028 (0x7ec) */ 3471 3472 3473 3474 /* =========================================================================================================================== */ 3475 /* ================ CC_HOST_RGF_S ================ */ 3476 /* =========================================================================================================================== */ 3477 3478 3479 /** 3480 * @brief CRYPTOCELL HOST register interface (CC_HOST_RGF_S) 3481 */ 3482 3483 typedef struct { /*!< (@ 0x50845000) CC_HOST_RGF_S Structure */ 3484 __IM uint32_t RESERVED[640]; 3485 __IM uint32_t IRR; /*!< (@ 0x00000A00) Interrupt request register. Each bit of this 3486 register holds the interrupt status of a 3487 single interrupt source. If corresponding 3488 IMR bit is unmasked, an interrupt is generated. */ 3489 __IOM uint32_t IMR; /*!< (@ 0x00000A04) Interrupt mask register. Each bit of this register 3490 holds the mask of a single interrupt source. */ 3491 __OM uint32_t ICR; /*!< (@ 0x00000A08) Interrupt clear register. Writing a 1 bit into 3492 a field in this register will clear the 3493 corresponding bit in IRR. */ 3494 __IOM uint32_t ENDIANNESS; /*!< (@ 0x00000A0C) This register defines the endianness of the Host-accessible 3495 registers, and can only be written once. */ 3496 __IM uint32_t RESERVED1[5]; 3497 __IM uint32_t HOST_SIGNATURE; /*!< (@ 0x00000A24) This register holds the CRYPTOCELL subsystem 3498 signature. See reset value. */ 3499 __IM uint32_t HOST_BOOT; /*!< (@ 0x00000A28) Hardware configuration of the CRYPTOCELL subsystem. 3500 Reset value holds the supported features. */ 3501 __IM uint32_t RESERVED2[20]; 3502 __IM uint32_t HOST_CC_IS_IDLE; /*!< (@ 0x00000A7C) Idle state register for the CRYPTOCELL subsystem. */ 3503 __IOM uint32_t HOST_POWERDOWN; /*!< (@ 0x00000A80) This register start the power-down sequence. */ 3504 } NRF_CC_HOST_RGF_Type; /*!< Size = 2692 (0xa84) */ 3505 3506 3507 3508 /* =========================================================================================================================== */ 3509 /* ================ CC_MISC_S ================ */ 3510 /* =========================================================================================================================== */ 3511 3512 3513 /** 3514 * @brief CRYPTOCELL MISC interface (CC_MISC_S) 3515 */ 3516 3517 typedef struct { /*!< (@ 0x50845000) CC_MISC_S Structure */ 3518 __IM uint32_t RESERVED[516]; 3519 __OM uint32_t AES_CLK; /*!< (@ 0x00000810) Clock control for the AES engine. */ 3520 __IM uint32_t RESERVED1; 3521 __OM uint32_t HASH_CLK; /*!< (@ 0x00000818) Clock control for the HASH engine. */ 3522 __OM uint32_t PKA_CLK; /*!< (@ 0x0000081C) Clock control for the PKA engine. */ 3523 __OM uint32_t DMA_CLK; /*!< (@ 0x00000820) Clock control for the DMA engines. */ 3524 __IM uint32_t CLK_STATUS; /*!< (@ 0x00000824) CRYPTOCELL clocks status register. */ 3525 __IM uint32_t RESERVED2[12]; 3526 __OM uint32_t CHACHA_CLK; /*!< (@ 0x00000858) Clock control for the CHACHA engine. */ 3527 } NRF_CC_MISC_Type; /*!< Size = 2140 (0x85c) */ 3528 3529 3530 3531 /* =========================================================================================================================== */ 3532 /* ================ CC_PKA_S ================ */ 3533 /* =========================================================================================================================== */ 3534 3535 3536 /** 3537 * @brief CRYPTOCELL PKA engine (CC_PKA_S) 3538 */ 3539 3540 typedef struct { /*!< (@ 0x50845000) CC_PKA_S Structure */ 3541 __IOM uint32_t MEMORY_MAP[32]; /*!< (@ 0x00000000) Description collection: Register for mapping 3542 the virtual register R[n] to a physical 3543 address in the PKA SRAM. */ 3544 __IOM uint32_t OPCODE; /*!< (@ 0x00000080) Operation code to be executed by the PKA engine. 3545 Writing to this register triggers the PKA 3546 operation. */ 3547 __IOM uint32_t N_NP_T0_T1_ADDR; /*!< (@ 0x00000084) This register defines the N, Np, T0, and T1 virtual 3548 register index. */ 3549 __IM uint32_t PKA_STATUS; /*!< (@ 0x00000088) This register holds the status for the PKA pipeline. */ 3550 __OM uint32_t PKA_SW_RESET; /*!< (@ 0x0000008C) Reset the PKA engine. */ 3551 __IOM uint32_t PKA_L[8]; /*!< (@ 0x00000090) Description collection: This register holds the 3552 operands bit size. */ 3553 __IM uint32_t PKA_PIPE; /*!< (@ 0x000000B0) Status register indicating if the PKA pipeline 3554 is ready to receive a new OPCODE. */ 3555 __IM uint32_t PKA_DONE; /*!< (@ 0x000000B4) Status register indicating if the PKA operation 3556 has been completed. */ 3557 __IM uint32_t RESERVED[3]; 3558 __IM uint32_t PKA_VERSION; /*!< (@ 0x000000C4) PKA engine HW version. Reset value holds the 3559 version. */ 3560 __IM uint32_t RESERVED1[3]; 3561 __OM uint32_t PKA_SRAM_WADDR; /*!< (@ 0x000000D4) Start address in PKA SRAM for subsequent write 3562 transactions. */ 3563 __OM uint32_t PKA_SRAM_WDATA; /*!< (@ 0x000000D8) Write data to PKA SRAM. Writing to this register 3564 triggers a DMA transaction writing data 3565 into PKA SRAM. The DMA address offset is 3566 automatically incremented during write. */ 3567 __IM uint32_t PKA_SRAM_RDATA; /*!< (@ 0x000000DC) Read data from PKA SRAM. Reading from this register 3568 triggers a DMA transaction read data from 3569 PKA SRAM. The DMA address offset is automatically 3570 incremented during read. */ 3571 __OM uint32_t PKA_SRAM_WCLEAR; /*!< (@ 0x000000E0) Register for clearing PKA SRAM write buffer. */ 3572 __OM uint32_t PKA_SRAM_RADDR; /*!< (@ 0x000000E4) Start address in PKA SRAM for subsequent read 3573 transactions. */ 3574 } NRF_CC_PKA_Type; /*!< Size = 232 (0xe8) */ 3575 3576 3577 3578 /* =========================================================================================================================== */ 3579 /* ================ CC_RNG_S ================ */ 3580 /* =========================================================================================================================== */ 3581 3582 3583 /** 3584 * @brief CRYPTOCELL RNG engine (CC_RNG_S) 3585 */ 3586 3587 typedef struct { /*!< (@ 0x50845000) CC_RNG_S Structure */ 3588 __IM uint32_t RESERVED[64]; 3589 __IOM uint32_t RNG_IMR; /*!< (@ 0x00000100) Interrupt mask register. Each bit of this register 3590 holds the mask of a single interrupt source. */ 3591 __IM uint32_t RNG_ISR; /*!< (@ 0x00000104) Interrupt status register. Each bit of this register 3592 holds the interrupt status of a single interrupt 3593 source. If corresponding RNG_IMR bit is 3594 unmasked, an interrupt is generated. */ 3595 __OM uint32_t RNG_ICR; /*!< (@ 0x00000108) Interrupt clear register. Writing a 1 bit into 3596 a field in this register will clear the 3597 corresponding bit in RNG_ISR. */ 3598 __IOM uint32_t TRNG_CONFIG; /*!< (@ 0x0000010C) TRNG ring oscillator length configuration */ 3599 __IM uint32_t TRNG_VALID; /*!< (@ 0x00000110) This register indicates if TRNG entropy collection 3600 is valid. */ 3601 __IM uint32_t EHR_DATA[6]; /*!< (@ 0x00000114) Description collection: The entropy holding registers 3602 (EHR) hold 192-bits random data collected 3603 by the TRNG. The initial EHR_DATA[0] register 3604 holds the least significant bits [31:0] 3605 of the random data value. */ 3606 __IOM uint32_t NOISE_SOURCE; /*!< (@ 0x0000012C) This register controls the ring oscillator circuit 3607 used as a noise source. */ 3608 __IOM uint32_t SAMPLE_CNT; /*!< (@ 0x00000130) Sample count defining the number of CPU clock 3609 cycles between two consecutive noise source 3610 samples. */ 3611 __IOM uint32_t AUTOCORR_STATISTIC; /*!< (@ 0x00000134) Statistics counter for autocorrelation test activations. 3612 Statistics collection is stopped if one 3613 of the counters reach its limit of all ones. */ 3614 __IOM uint32_t TRNG_DEBUG; /*!< (@ 0x00000138) Debug register for the TRNG. This register is 3615 used to bypass TRNG tests in hardware. */ 3616 __IM uint32_t RESERVED1; 3617 __OM uint32_t RNG_SW_RESET; /*!< (@ 0x00000140) Reset the RNG engine. */ 3618 __IM uint32_t RESERVED2[29]; 3619 __IM uint32_t RNG_BUSY; /*!< (@ 0x000001B8) Status register for RNG engine activity. */ 3620 __OM uint32_t TRNG_RESET; /*!< (@ 0x000001BC) Reset the TRNG, including internal counter of 3621 collected bits and registers EHR_DATA and 3622 TRNG_VALID. */ 3623 __IM uint32_t RNG_HW_FLAGS; /*!< (@ 0x000001C0) Hardware configuration of RNG engine. Reset value 3624 holds the supported features. */ 3625 __OM uint32_t RNG_CLK; /*!< (@ 0x000001C4) Control clock for the RNG engine. */ 3626 __IOM uint32_t RNG_DMA; /*!< (@ 0x000001C8) Writing to this register enables the RNG DMA 3627 engine. */ 3628 __IOM uint32_t RNG_DMA_ROSC_LEN; /*!< (@ 0x000001CC) This register defines which ring oscillator length 3629 configuration should be used when using 3630 the RNG DMA engine. */ 3631 __IOM uint32_t RNG_DMA_SRAM_ADDR; /*!< (@ 0x000001D0) This register defines the start address in TRNG 3632 SRAM for the TRNG data to be collected by 3633 the RNG DMA engine. */ 3634 __IOM uint32_t RNG_DMA_SAMPLES_NUM; /*!< (@ 0x000001D4) This register defines the number of 192-bits 3635 samples that the RNG DMA engine collects 3636 per run. */ 3637 __IOM uint32_t RNG_WATCHDOG_VAL; /*!< (@ 0x000001D8) This register defines the maximum number of CPU 3638 clock cycles per TRNG collection of 192-bits 3639 samples. If the number of cycles for a collection 3640 exceeds this threshold the WATCHDOG interrupt 3641 is triggered. */ 3642 __IM uint32_t RNG_DMA_BUSY; /*!< (@ 0x000001DC) Status register for RNG DMA engine activity. */ 3643 } NRF_CC_RNG_Type; /*!< Size = 480 (0x1e0) */ 3644 3645 3646 3647 /* =========================================================================================================================== */ 3648 /* ================ CC_RNG_SRAM_S ================ */ 3649 /* =========================================================================================================================== */ 3650 3651 3652 /** 3653 * @brief CRYPTOCELL RNG SRAM interface (CC_RNG_SRAM_S) 3654 */ 3655 3656 typedef struct { /*!< (@ 0x50845000) CC_RNG_SRAM_S Structure */ 3657 __IM uint32_t RESERVED[960]; 3658 __IOM uint32_t SRAM_DATA; /*!< (@ 0x00000F00) Read/Write data from RNG SRAM */ 3659 __OM uint32_t SRAM_ADDR; /*!< (@ 0x00000F04) First address given to RNG SRAM DMA for read/write 3660 transactions from/to RNG SRAM. */ 3661 __IM uint32_t SRAM_DATA_READY; /*!< (@ 0x00000F08) RNG SRAM DMA engine is ready to read/write from/to 3662 RNG SRAM. */ 3663 } NRF_CC_RNG_SRAM_Type; /*!< Size = 3852 (0xf0c) */ 3664 3665 3666 3667 /* =========================================================================================================================== */ 3668 /* ================ VMC_NS ================ */ 3669 /* =========================================================================================================================== */ 3670 3671 3672 /** 3673 * @brief Volatile Memory controller 0 (VMC_NS) 3674 */ 3675 3676 typedef struct { /*!< (@ 0x40081000) VMC_NS Structure */ 3677 __IM uint32_t RESERVED[384]; 3678 __IOM VMC_RAM_Type RAM[8]; /*!< (@ 0x00000600) Unspecified */ 3679 } NRF_VMC_Type; /*!< Size = 1664 (0x680) */ 3680 3681 3682 /** @} */ /* End of group Device_Peripheral_peripherals */ 3683 3684 3685 /* =========================================================================================================================== */ 3686 /* ================ Device Specific Peripheral Address Map ================ */ 3687 /* =========================================================================================================================== */ 3688 3689 3690 /** @addtogroup Device_Peripheral_peripheralAddr 3691 * @{ 3692 */ 3693 3694 #define NRF_CACHEDATA_S_BASE 0x00F00000UL 3695 #define NRF_CACHEINFO_S_BASE 0x00F08000UL 3696 #define NRF_FICR_S_BASE 0x00FF0000UL 3697 #define NRF_UICR_S_BASE 0x00FF8000UL 3698 #define NRF_CTI_S_BASE 0xE0042000UL 3699 #define NRF_TAD_S_BASE 0xE0080000UL 3700 #define NRF_DCNF_NS_BASE 0x40000000UL 3701 #define NRF_FPU_NS_BASE 0x40000000UL 3702 #define NRF_DCNF_S_BASE 0x50000000UL 3703 #define NRF_FPU_S_BASE 0x50000000UL 3704 #define NRF_CACHE_S_BASE 0x50001000UL 3705 #define NRF_SPU_S_BASE 0x50003000UL 3706 #define NRF_OSCILLATORS_NS_BASE 0x40004000UL 3707 #define NRF_REGULATORS_NS_BASE 0x40004000UL 3708 #define NRF_OSCILLATORS_S_BASE 0x50004000UL 3709 #define NRF_REGULATORS_S_BASE 0x50004000UL 3710 #define NRF_CLOCK_NS_BASE 0x40005000UL 3711 #define NRF_POWER_NS_BASE 0x40005000UL 3712 #define NRF_RESET_NS_BASE 0x40005000UL 3713 #define NRF_CLOCK_S_BASE 0x50005000UL 3714 #define NRF_POWER_S_BASE 0x50005000UL 3715 #define NRF_RESET_S_BASE 0x50005000UL 3716 #define NRF_CTRLAP_NS_BASE 0x40006000UL 3717 #define NRF_CTRLAP_S_BASE 0x50006000UL 3718 #define NRF_SPIM0_NS_BASE 0x40008000UL 3719 #define NRF_SPIS0_NS_BASE 0x40008000UL 3720 #define NRF_TWIM0_NS_BASE 0x40008000UL 3721 #define NRF_TWIS0_NS_BASE 0x40008000UL 3722 #define NRF_UARTE0_NS_BASE 0x40008000UL 3723 #define NRF_SPIM0_S_BASE 0x50008000UL 3724 #define NRF_SPIS0_S_BASE 0x50008000UL 3725 #define NRF_TWIM0_S_BASE 0x50008000UL 3726 #define NRF_TWIS0_S_BASE 0x50008000UL 3727 #define NRF_UARTE0_S_BASE 0x50008000UL 3728 #define NRF_SPIM1_NS_BASE 0x40009000UL 3729 #define NRF_SPIS1_NS_BASE 0x40009000UL 3730 #define NRF_TWIM1_NS_BASE 0x40009000UL 3731 #define NRF_TWIS1_NS_BASE 0x40009000UL 3732 #define NRF_UARTE1_NS_BASE 0x40009000UL 3733 #define NRF_SPIM1_S_BASE 0x50009000UL 3734 #define NRF_SPIS1_S_BASE 0x50009000UL 3735 #define NRF_TWIM1_S_BASE 0x50009000UL 3736 #define NRF_TWIS1_S_BASE 0x50009000UL 3737 #define NRF_UARTE1_S_BASE 0x50009000UL 3738 #define NRF_SPIM4_NS_BASE 0x4000A000UL 3739 #define NRF_SPIM4_S_BASE 0x5000A000UL 3740 #define NRF_SPIM2_NS_BASE 0x4000B000UL 3741 #define NRF_SPIS2_NS_BASE 0x4000B000UL 3742 #define NRF_TWIM2_NS_BASE 0x4000B000UL 3743 #define NRF_TWIS2_NS_BASE 0x4000B000UL 3744 #define NRF_UARTE2_NS_BASE 0x4000B000UL 3745 #define NRF_SPIM2_S_BASE 0x5000B000UL 3746 #define NRF_SPIS2_S_BASE 0x5000B000UL 3747 #define NRF_TWIM2_S_BASE 0x5000B000UL 3748 #define NRF_TWIS2_S_BASE 0x5000B000UL 3749 #define NRF_UARTE2_S_BASE 0x5000B000UL 3750 #define NRF_SPIM3_NS_BASE 0x4000C000UL 3751 #define NRF_SPIS3_NS_BASE 0x4000C000UL 3752 #define NRF_TWIM3_NS_BASE 0x4000C000UL 3753 #define NRF_TWIS3_NS_BASE 0x4000C000UL 3754 #define NRF_UARTE3_NS_BASE 0x4000C000UL 3755 #define NRF_SPIM3_S_BASE 0x5000C000UL 3756 #define NRF_SPIS3_S_BASE 0x5000C000UL 3757 #define NRF_TWIM3_S_BASE 0x5000C000UL 3758 #define NRF_TWIS3_S_BASE 0x5000C000UL 3759 #define NRF_UARTE3_S_BASE 0x5000C000UL 3760 #define NRF_GPIOTE0_S_BASE 0x5000D000UL 3761 #define NRF_SAADC_NS_BASE 0x4000E000UL 3762 #define NRF_SAADC_S_BASE 0x5000E000UL 3763 #define NRF_TIMER0_NS_BASE 0x4000F000UL 3764 #define NRF_TIMER0_S_BASE 0x5000F000UL 3765 #define NRF_TIMER1_NS_BASE 0x40010000UL 3766 #define NRF_TIMER1_S_BASE 0x50010000UL 3767 #define NRF_TIMER2_NS_BASE 0x40011000UL 3768 #define NRF_TIMER2_S_BASE 0x50011000UL 3769 #define NRF_RTC0_NS_BASE 0x40014000UL 3770 #define NRF_RTC0_S_BASE 0x50014000UL 3771 #define NRF_RTC1_NS_BASE 0x40015000UL 3772 #define NRF_RTC1_S_BASE 0x50015000UL 3773 #define NRF_DPPIC_NS_BASE 0x40017000UL 3774 #define NRF_DPPIC_S_BASE 0x50017000UL 3775 #define NRF_WDT0_NS_BASE 0x40018000UL 3776 #define NRF_WDT0_S_BASE 0x50018000UL 3777 #define NRF_WDT1_NS_BASE 0x40019000UL 3778 #define NRF_WDT1_S_BASE 0x50019000UL 3779 #define NRF_COMP_NS_BASE 0x4001A000UL 3780 #define NRF_LPCOMP_NS_BASE 0x4001A000UL 3781 #define NRF_COMP_S_BASE 0x5001A000UL 3782 #define NRF_LPCOMP_S_BASE 0x5001A000UL 3783 #define NRF_EGU0_NS_BASE 0x4001B000UL 3784 #define NRF_EGU0_S_BASE 0x5001B000UL 3785 #define NRF_EGU1_NS_BASE 0x4001C000UL 3786 #define NRF_EGU1_S_BASE 0x5001C000UL 3787 #define NRF_EGU2_NS_BASE 0x4001D000UL 3788 #define NRF_EGU2_S_BASE 0x5001D000UL 3789 #define NRF_EGU3_NS_BASE 0x4001E000UL 3790 #define NRF_EGU3_S_BASE 0x5001E000UL 3791 #define NRF_EGU4_NS_BASE 0x4001F000UL 3792 #define NRF_EGU4_S_BASE 0x5001F000UL 3793 #define NRF_EGU5_NS_BASE 0x40020000UL 3794 #define NRF_EGU5_S_BASE 0x50020000UL 3795 #define NRF_PWM0_NS_BASE 0x40021000UL 3796 #define NRF_PWM0_S_BASE 0x50021000UL 3797 #define NRF_PWM1_NS_BASE 0x40022000UL 3798 #define NRF_PWM1_S_BASE 0x50022000UL 3799 #define NRF_PWM2_NS_BASE 0x40023000UL 3800 #define NRF_PWM2_S_BASE 0x50023000UL 3801 #define NRF_PWM3_NS_BASE 0x40024000UL 3802 #define NRF_PWM3_S_BASE 0x50024000UL 3803 #define NRF_PDM0_NS_BASE 0x40026000UL 3804 #define NRF_PDM0_S_BASE 0x50026000UL 3805 #define NRF_I2S0_NS_BASE 0x40028000UL 3806 #define NRF_I2S0_S_BASE 0x50028000UL 3807 #define NRF_IPC_NS_BASE 0x4002A000UL 3808 #define NRF_IPC_S_BASE 0x5002A000UL 3809 #define NRF_QSPI_NS_BASE 0x4002B000UL 3810 #define NRF_QSPI_S_BASE 0x5002B000UL 3811 #define NRF_NFCT_NS_BASE 0x4002D000UL 3812 #define NRF_NFCT_S_BASE 0x5002D000UL 3813 #define NRF_GPIOTE1_NS_BASE 0x4002F000UL 3814 #define NRF_MUTEX_NS_BASE 0x40030000UL 3815 #define NRF_MUTEX_S_BASE 0x50030000UL 3816 #define NRF_QDEC0_NS_BASE 0x40033000UL 3817 #define NRF_QDEC0_S_BASE 0x50033000UL 3818 #define NRF_QDEC1_NS_BASE 0x40034000UL 3819 #define NRF_QDEC1_S_BASE 0x50034000UL 3820 #define NRF_USBD_NS_BASE 0x40036000UL 3821 #define NRF_USBD_S_BASE 0x50036000UL 3822 #define NRF_USBREGULATOR_NS_BASE 0x40037000UL 3823 #define NRF_USBREGULATOR_S_BASE 0x50037000UL 3824 #define NRF_KMU_NS_BASE 0x40039000UL 3825 #define NRF_NVMC_NS_BASE 0x40039000UL 3826 #define NRF_KMU_S_BASE 0x50039000UL 3827 #define NRF_NVMC_S_BASE 0x50039000UL 3828 #define NRF_P0_NS_BASE 0x40842500UL 3829 #define NRF_P1_NS_BASE 0x40842800UL 3830 #define NRF_P0_S_BASE 0x50842500UL 3831 #define NRF_P1_S_BASE 0x50842800UL 3832 #define NRF_CRYPTOCELL_S_BASE 0x50844000UL 3833 #define NRF_CC_AES_S_BASE 0x50845000UL 3834 #define NRF_CC_AHB_S_BASE 0x50845000UL 3835 #define NRF_CC_AO_S_BASE 0x50845000UL 3836 #define NRF_CC_CHACHA_S_BASE 0x50845000UL 3837 #define NRF_CC_CTL_S_BASE 0x50845000UL 3838 #define NRF_CC_DIN_S_BASE 0x50845000UL 3839 #define NRF_CC_DOUT_S_BASE 0x50845000UL 3840 #define NRF_CC_GHASH_S_BASE 0x50845000UL 3841 #define NRF_CC_HASH_S_BASE 0x50845000UL 3842 #define NRF_CC_HOST_RGF_S_BASE 0x50845000UL 3843 #define NRF_CC_MISC_S_BASE 0x50845000UL 3844 #define NRF_CC_PKA_S_BASE 0x50845000UL 3845 #define NRF_CC_RNG_S_BASE 0x50845000UL 3846 #define NRF_CC_RNG_SRAM_S_BASE 0x50845000UL 3847 #define NRF_VMC_NS_BASE 0x40081000UL 3848 #define NRF_VMC_S_BASE 0x50081000UL 3849 3850 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 3851 3852 3853 /* =========================================================================================================================== */ 3854 /* ================ Peripheral declaration ================ */ 3855 /* =========================================================================================================================== */ 3856 3857 3858 /** @addtogroup Device_Peripheral_declaration 3859 * @{ 3860 */ 3861 3862 #define NRF_CACHEDATA_S ((NRF_CACHEDATA_Type*) NRF_CACHEDATA_S_BASE) 3863 #define NRF_CACHEINFO_S ((NRF_CACHEINFO_Type*) NRF_CACHEINFO_S_BASE) 3864 #define NRF_FICR_S ((NRF_FICR_Type*) NRF_FICR_S_BASE) 3865 #define NRF_UICR_S ((NRF_UICR_Type*) NRF_UICR_S_BASE) 3866 #define NRF_CTI_S ((NRF_CTI_Type*) NRF_CTI_S_BASE) 3867 #define NRF_TAD_S ((NRF_TAD_Type*) NRF_TAD_S_BASE) 3868 #define NRF_DCNF_NS ((NRF_DCNF_Type*) NRF_DCNF_NS_BASE) 3869 #define NRF_FPU_NS ((NRF_FPU_Type*) NRF_FPU_NS_BASE) 3870 #define NRF_DCNF_S ((NRF_DCNF_Type*) NRF_DCNF_S_BASE) 3871 #define NRF_FPU_S ((NRF_FPU_Type*) NRF_FPU_S_BASE) 3872 #define NRF_CACHE_S ((NRF_CACHE_Type*) NRF_CACHE_S_BASE) 3873 #define NRF_SPU_S ((NRF_SPU_Type*) NRF_SPU_S_BASE) 3874 #define NRF_OSCILLATORS_NS ((NRF_OSCILLATORS_Type*) NRF_OSCILLATORS_NS_BASE) 3875 #define NRF_REGULATORS_NS ((NRF_REGULATORS_Type*) NRF_REGULATORS_NS_BASE) 3876 #define NRF_OSCILLATORS_S ((NRF_OSCILLATORS_Type*) NRF_OSCILLATORS_S_BASE) 3877 #define NRF_REGULATORS_S ((NRF_REGULATORS_Type*) NRF_REGULATORS_S_BASE) 3878 #define NRF_CLOCK_NS ((NRF_CLOCK_Type*) NRF_CLOCK_NS_BASE) 3879 #define NRF_POWER_NS ((NRF_POWER_Type*) NRF_POWER_NS_BASE) 3880 #define NRF_RESET_NS ((NRF_RESET_Type*) NRF_RESET_NS_BASE) 3881 #define NRF_CLOCK_S ((NRF_CLOCK_Type*) NRF_CLOCK_S_BASE) 3882 #define NRF_POWER_S ((NRF_POWER_Type*) NRF_POWER_S_BASE) 3883 #define NRF_RESET_S ((NRF_RESET_Type*) NRF_RESET_S_BASE) 3884 #define NRF_CTRLAP_NS ((NRF_CTRLAPPERI_Type*) NRF_CTRLAP_NS_BASE) 3885 #define NRF_CTRLAP_S ((NRF_CTRLAPPERI_Type*) NRF_CTRLAP_S_BASE) 3886 #define NRF_SPIM0_NS ((NRF_SPIM_Type*) NRF_SPIM0_NS_BASE) 3887 #define NRF_SPIS0_NS ((NRF_SPIS_Type*) NRF_SPIS0_NS_BASE) 3888 #define NRF_TWIM0_NS ((NRF_TWIM_Type*) NRF_TWIM0_NS_BASE) 3889 #define NRF_TWIS0_NS ((NRF_TWIS_Type*) NRF_TWIS0_NS_BASE) 3890 #define NRF_UARTE0_NS ((NRF_UARTE_Type*) NRF_UARTE0_NS_BASE) 3891 #define NRF_SPIM0_S ((NRF_SPIM_Type*) NRF_SPIM0_S_BASE) 3892 #define NRF_SPIS0_S ((NRF_SPIS_Type*) NRF_SPIS0_S_BASE) 3893 #define NRF_TWIM0_S ((NRF_TWIM_Type*) NRF_TWIM0_S_BASE) 3894 #define NRF_TWIS0_S ((NRF_TWIS_Type*) NRF_TWIS0_S_BASE) 3895 #define NRF_UARTE0_S ((NRF_UARTE_Type*) NRF_UARTE0_S_BASE) 3896 #define NRF_SPIM1_NS ((NRF_SPIM_Type*) NRF_SPIM1_NS_BASE) 3897 #define NRF_SPIS1_NS ((NRF_SPIS_Type*) NRF_SPIS1_NS_BASE) 3898 #define NRF_TWIM1_NS ((NRF_TWIM_Type*) NRF_TWIM1_NS_BASE) 3899 #define NRF_TWIS1_NS ((NRF_TWIS_Type*) NRF_TWIS1_NS_BASE) 3900 #define NRF_UARTE1_NS ((NRF_UARTE_Type*) NRF_UARTE1_NS_BASE) 3901 #define NRF_SPIM1_S ((NRF_SPIM_Type*) NRF_SPIM1_S_BASE) 3902 #define NRF_SPIS1_S ((NRF_SPIS_Type*) NRF_SPIS1_S_BASE) 3903 #define NRF_TWIM1_S ((NRF_TWIM_Type*) NRF_TWIM1_S_BASE) 3904 #define NRF_TWIS1_S ((NRF_TWIS_Type*) NRF_TWIS1_S_BASE) 3905 #define NRF_UARTE1_S ((NRF_UARTE_Type*) NRF_UARTE1_S_BASE) 3906 #define NRF_SPIM4_NS ((NRF_SPIM_Type*) NRF_SPIM4_NS_BASE) 3907 #define NRF_SPIM4_S ((NRF_SPIM_Type*) NRF_SPIM4_S_BASE) 3908 #define NRF_SPIM2_NS ((NRF_SPIM_Type*) NRF_SPIM2_NS_BASE) 3909 #define NRF_SPIS2_NS ((NRF_SPIS_Type*) NRF_SPIS2_NS_BASE) 3910 #define NRF_TWIM2_NS ((NRF_TWIM_Type*) NRF_TWIM2_NS_BASE) 3911 #define NRF_TWIS2_NS ((NRF_TWIS_Type*) NRF_TWIS2_NS_BASE) 3912 #define NRF_UARTE2_NS ((NRF_UARTE_Type*) NRF_UARTE2_NS_BASE) 3913 #define NRF_SPIM2_S ((NRF_SPIM_Type*) NRF_SPIM2_S_BASE) 3914 #define NRF_SPIS2_S ((NRF_SPIS_Type*) NRF_SPIS2_S_BASE) 3915 #define NRF_TWIM2_S ((NRF_TWIM_Type*) NRF_TWIM2_S_BASE) 3916 #define NRF_TWIS2_S ((NRF_TWIS_Type*) NRF_TWIS2_S_BASE) 3917 #define NRF_UARTE2_S ((NRF_UARTE_Type*) NRF_UARTE2_S_BASE) 3918 #define NRF_SPIM3_NS ((NRF_SPIM_Type*) NRF_SPIM3_NS_BASE) 3919 #define NRF_SPIS3_NS ((NRF_SPIS_Type*) NRF_SPIS3_NS_BASE) 3920 #define NRF_TWIM3_NS ((NRF_TWIM_Type*) NRF_TWIM3_NS_BASE) 3921 #define NRF_TWIS3_NS ((NRF_TWIS_Type*) NRF_TWIS3_NS_BASE) 3922 #define NRF_UARTE3_NS ((NRF_UARTE_Type*) NRF_UARTE3_NS_BASE) 3923 #define NRF_SPIM3_S ((NRF_SPIM_Type*) NRF_SPIM3_S_BASE) 3924 #define NRF_SPIS3_S ((NRF_SPIS_Type*) NRF_SPIS3_S_BASE) 3925 #define NRF_TWIM3_S ((NRF_TWIM_Type*) NRF_TWIM3_S_BASE) 3926 #define NRF_TWIS3_S ((NRF_TWIS_Type*) NRF_TWIS3_S_BASE) 3927 #define NRF_UARTE3_S ((NRF_UARTE_Type*) NRF_UARTE3_S_BASE) 3928 #define NRF_GPIOTE0_S ((NRF_GPIOTE_Type*) NRF_GPIOTE0_S_BASE) 3929 #define NRF_SAADC_NS ((NRF_SAADC_Type*) NRF_SAADC_NS_BASE) 3930 #define NRF_SAADC_S ((NRF_SAADC_Type*) NRF_SAADC_S_BASE) 3931 #define NRF_TIMER0_NS ((NRF_TIMER_Type*) NRF_TIMER0_NS_BASE) 3932 #define NRF_TIMER0_S ((NRF_TIMER_Type*) NRF_TIMER0_S_BASE) 3933 #define NRF_TIMER1_NS ((NRF_TIMER_Type*) NRF_TIMER1_NS_BASE) 3934 #define NRF_TIMER1_S ((NRF_TIMER_Type*) NRF_TIMER1_S_BASE) 3935 #define NRF_TIMER2_NS ((NRF_TIMER_Type*) NRF_TIMER2_NS_BASE) 3936 #define NRF_TIMER2_S ((NRF_TIMER_Type*) NRF_TIMER2_S_BASE) 3937 #define NRF_RTC0_NS ((NRF_RTC_Type*) NRF_RTC0_NS_BASE) 3938 #define NRF_RTC0_S ((NRF_RTC_Type*) NRF_RTC0_S_BASE) 3939 #define NRF_RTC1_NS ((NRF_RTC_Type*) NRF_RTC1_NS_BASE) 3940 #define NRF_RTC1_S ((NRF_RTC_Type*) NRF_RTC1_S_BASE) 3941 #define NRF_DPPIC_NS ((NRF_DPPIC_Type*) NRF_DPPIC_NS_BASE) 3942 #define NRF_DPPIC_S ((NRF_DPPIC_Type*) NRF_DPPIC_S_BASE) 3943 #define NRF_WDT0_NS ((NRF_WDT_Type*) NRF_WDT0_NS_BASE) 3944 #define NRF_WDT0_S ((NRF_WDT_Type*) NRF_WDT0_S_BASE) 3945 #define NRF_WDT1_NS ((NRF_WDT_Type*) NRF_WDT1_NS_BASE) 3946 #define NRF_WDT1_S ((NRF_WDT_Type*) NRF_WDT1_S_BASE) 3947 #define NRF_COMP_NS ((NRF_COMP_Type*) NRF_COMP_NS_BASE) 3948 #define NRF_LPCOMP_NS ((NRF_LPCOMP_Type*) NRF_LPCOMP_NS_BASE) 3949 #define NRF_COMP_S ((NRF_COMP_Type*) NRF_COMP_S_BASE) 3950 #define NRF_LPCOMP_S ((NRF_LPCOMP_Type*) NRF_LPCOMP_S_BASE) 3951 #define NRF_EGU0_NS ((NRF_EGU_Type*) NRF_EGU0_NS_BASE) 3952 #define NRF_EGU0_S ((NRF_EGU_Type*) NRF_EGU0_S_BASE) 3953 #define NRF_EGU1_NS ((NRF_EGU_Type*) NRF_EGU1_NS_BASE) 3954 #define NRF_EGU1_S ((NRF_EGU_Type*) NRF_EGU1_S_BASE) 3955 #define NRF_EGU2_NS ((NRF_EGU_Type*) NRF_EGU2_NS_BASE) 3956 #define NRF_EGU2_S ((NRF_EGU_Type*) NRF_EGU2_S_BASE) 3957 #define NRF_EGU3_NS ((NRF_EGU_Type*) NRF_EGU3_NS_BASE) 3958 #define NRF_EGU3_S ((NRF_EGU_Type*) NRF_EGU3_S_BASE) 3959 #define NRF_EGU4_NS ((NRF_EGU_Type*) NRF_EGU4_NS_BASE) 3960 #define NRF_EGU4_S ((NRF_EGU_Type*) NRF_EGU4_S_BASE) 3961 #define NRF_EGU5_NS ((NRF_EGU_Type*) NRF_EGU5_NS_BASE) 3962 #define NRF_EGU5_S ((NRF_EGU_Type*) NRF_EGU5_S_BASE) 3963 #define NRF_PWM0_NS ((NRF_PWM_Type*) NRF_PWM0_NS_BASE) 3964 #define NRF_PWM0_S ((NRF_PWM_Type*) NRF_PWM0_S_BASE) 3965 #define NRF_PWM1_NS ((NRF_PWM_Type*) NRF_PWM1_NS_BASE) 3966 #define NRF_PWM1_S ((NRF_PWM_Type*) NRF_PWM1_S_BASE) 3967 #define NRF_PWM2_NS ((NRF_PWM_Type*) NRF_PWM2_NS_BASE) 3968 #define NRF_PWM2_S ((NRF_PWM_Type*) NRF_PWM2_S_BASE) 3969 #define NRF_PWM3_NS ((NRF_PWM_Type*) NRF_PWM3_NS_BASE) 3970 #define NRF_PWM3_S ((NRF_PWM_Type*) NRF_PWM3_S_BASE) 3971 #define NRF_PDM0_NS ((NRF_PDM_Type*) NRF_PDM0_NS_BASE) 3972 #define NRF_PDM0_S ((NRF_PDM_Type*) NRF_PDM0_S_BASE) 3973 #define NRF_I2S0_NS ((NRF_I2S_Type*) NRF_I2S0_NS_BASE) 3974 #define NRF_I2S0_S ((NRF_I2S_Type*) NRF_I2S0_S_BASE) 3975 #define NRF_IPC_NS ((NRF_IPC_Type*) NRF_IPC_NS_BASE) 3976 #define NRF_IPC_S ((NRF_IPC_Type*) NRF_IPC_S_BASE) 3977 #define NRF_QSPI_NS ((NRF_QSPI_Type*) NRF_QSPI_NS_BASE) 3978 #define NRF_QSPI_S ((NRF_QSPI_Type*) NRF_QSPI_S_BASE) 3979 #define NRF_NFCT_NS ((NRF_NFCT_Type*) NRF_NFCT_NS_BASE) 3980 #define NRF_NFCT_S ((NRF_NFCT_Type*) NRF_NFCT_S_BASE) 3981 #define NRF_GPIOTE1_NS ((NRF_GPIOTE_Type*) NRF_GPIOTE1_NS_BASE) 3982 #define NRF_MUTEX_NS ((NRF_MUTEX_Type*) NRF_MUTEX_NS_BASE) 3983 #define NRF_MUTEX_S ((NRF_MUTEX_Type*) NRF_MUTEX_S_BASE) 3984 #define NRF_QDEC0_NS ((NRF_QDEC_Type*) NRF_QDEC0_NS_BASE) 3985 #define NRF_QDEC0_S ((NRF_QDEC_Type*) NRF_QDEC0_S_BASE) 3986 #define NRF_QDEC1_NS ((NRF_QDEC_Type*) NRF_QDEC1_NS_BASE) 3987 #define NRF_QDEC1_S ((NRF_QDEC_Type*) NRF_QDEC1_S_BASE) 3988 #define NRF_USBD_NS ((NRF_USBD_Type*) NRF_USBD_NS_BASE) 3989 #define NRF_USBD_S ((NRF_USBD_Type*) NRF_USBD_S_BASE) 3990 #define NRF_USBREGULATOR_NS ((NRF_USBREG_Type*) NRF_USBREGULATOR_NS_BASE) 3991 #define NRF_USBREGULATOR_S ((NRF_USBREG_Type*) NRF_USBREGULATOR_S_BASE) 3992 #define NRF_KMU_NS ((NRF_KMU_Type*) NRF_KMU_NS_BASE) 3993 #define NRF_NVMC_NS ((NRF_NVMC_Type*) NRF_NVMC_NS_BASE) 3994 #define NRF_KMU_S ((NRF_KMU_Type*) NRF_KMU_S_BASE) 3995 #define NRF_NVMC_S ((NRF_NVMC_Type*) NRF_NVMC_S_BASE) 3996 #define NRF_P0_NS ((NRF_GPIO_Type*) NRF_P0_NS_BASE) 3997 #define NRF_P1_NS ((NRF_GPIO_Type*) NRF_P1_NS_BASE) 3998 #define NRF_P0_S ((NRF_GPIO_Type*) NRF_P0_S_BASE) 3999 #define NRF_P1_S ((NRF_GPIO_Type*) NRF_P1_S_BASE) 4000 #define NRF_CRYPTOCELL_S ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_S_BASE) 4001 #define NRF_CC_AES_S ((NRF_CC_AES_Type*) NRF_CC_AES_S_BASE) 4002 #define NRF_CC_AHB_S ((NRF_CC_AHB_Type*) NRF_CC_AHB_S_BASE) 4003 #define NRF_CC_AO_S ((NRF_CC_AO_Type*) NRF_CC_AO_S_BASE) 4004 #define NRF_CC_CHACHA_S ((NRF_CC_CHACHA_Type*) NRF_CC_CHACHA_S_BASE) 4005 #define NRF_CC_CTL_S ((NRF_CC_CTL_Type*) NRF_CC_CTL_S_BASE) 4006 #define NRF_CC_DIN_S ((NRF_CC_DIN_Type*) NRF_CC_DIN_S_BASE) 4007 #define NRF_CC_DOUT_S ((NRF_CC_DOUT_Type*) NRF_CC_DOUT_S_BASE) 4008 #define NRF_CC_GHASH_S ((NRF_CC_GHASH_Type*) NRF_CC_GHASH_S_BASE) 4009 #define NRF_CC_HASH_S ((NRF_CC_HASH_Type*) NRF_CC_HASH_S_BASE) 4010 #define NRF_CC_HOST_RGF_S ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_S_BASE) 4011 #define NRF_CC_MISC_S ((NRF_CC_MISC_Type*) NRF_CC_MISC_S_BASE) 4012 #define NRF_CC_PKA_S ((NRF_CC_PKA_Type*) NRF_CC_PKA_S_BASE) 4013 #define NRF_CC_RNG_S ((NRF_CC_RNG_Type*) NRF_CC_RNG_S_BASE) 4014 #define NRF_CC_RNG_SRAM_S ((NRF_CC_RNG_SRAM_Type*) NRF_CC_RNG_SRAM_S_BASE) 4015 #define NRF_VMC_NS ((NRF_VMC_Type*) NRF_VMC_NS_BASE) 4016 #define NRF_VMC_S ((NRF_VMC_Type*) NRF_VMC_S_BASE) 4017 4018 /** @} */ /* End of group Device_Peripheral_declaration */ 4019 4020 4021 #ifdef __cplusplus 4022 } 4023 #endif 4024 4025 #endif /* NRF5340_APPLICATION_H */ 4026 4027 4028 /** @} */ /* End of group nrf5340_application */ 4029 4030 /** @} */ /* End of group Nordic Semiconductor */ 4031
