1 /* 2 * Copyright (c) 2022 ITE. 3 * Copyright 2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _HDMITX_H_ 9 #define _HDMITX_H_ 10 11 typedef enum 12 { 13 PCLK_LOW = 0, 14 PCLK_MEDIUM, 15 PCLK_HIGH 16 } VIDEOPCLKLEVEL; 17 18 #define DDC_FIFO_MAXREQ (0x20U) 19 #define MAX_AUDDES_COUNT (0x04U) 20 21 #define SIZEOF_CSCMTX (21U) 22 23 enum AUDIO_INTERFACES 24 { 25 AUDIO_IF_I2S = 1U, 26 AUDIO_IF_SPDIF = 2U, 27 AUDIO_IF_TDM = 3U, 28 }; 29 30 typedef union _tag_DCSUPPORT 31 { 32 struct 33 { 34 uint8_t DVI_Dual : 1; 35 uint8_t Rsvd : 2; 36 uint8_t DC_Y444 : 1; 37 uint8_t DC_30Bit : 1; 38 uint8_t DC_36Bit : 1; 39 uint8_t DC_48Bit : 1; 40 uint8_t SUPPORT_AI : 1; 41 } info; 42 uint8_t uc; 43 } DCSUPPORT; 44 45 typedef union _LATENCY_SUPPORT 46 { 47 struct 48 { 49 uint8_t Rsvd : 6; 50 uint8_t I_Latency_Present : 1; 51 uint8_t Latency_Present : 1; 52 } info; 53 uint8_t uc; 54 } LATENCY_SUPPORT; 55 56 typedef union 57 { 58 struct 59 { 60 uint8_t FL_FR : 1; 61 uint8_t LFE : 1; 62 uint8_t FC : 1; 63 uint8_t RL_RR : 1; 64 uint8_t RC : 1; 65 uint8_t FLC_FRC : 1; 66 uint8_t RLC_RRC : 1; 67 uint8_t Reserve : 1; 68 uint8_t Unuse[2]; 69 } s; 70 uint8_t uc[3]; 71 } SPK_ALLOC; 72 73 typedef union 74 { 75 struct 76 { 77 uint8_t channel : 3; 78 uint8_t AudioFormatCode : 4; 79 uint8_t Rsrv1 : 1; 80 81 uint8_t b32KHz : 1; 82 uint8_t b44_1KHz : 1; 83 uint8_t b48KHz : 1; 84 uint8_t b88_2KHz : 1; 85 uint8_t b96KHz : 1; 86 uint8_t b176_4KHz : 1; 87 uint8_t b192KHz : 1; 88 uint8_t Rsrv2 : 1; 89 uint8_t ucCode; 90 } s; 91 uint8_t uc[3]; 92 } AUDDESCRIPTOR; 93 94 typedef struct _RX_CAP 95 { 96 uint8_t VideoMode; 97 uint8_t NativeVDOMode; 98 uint8_t VDOMode[8]; 99 uint8_t AUDDesCount; 100 AUDDESCRIPTOR AUDDes[MAX_AUDDES_COUNT]; 101 uint8_t PA[2]; 102 uint32_t IEEEOUI; 103 DCSUPPORT dc; 104 uint8_t MaxTMDSClock; 105 LATENCY_SUPPORT lsupport; 106 SPK_ALLOC SpeakerAllocBlk; 107 uint8_t ValidCEA : 1; 108 uint8_t ValidHDMI : 1; 109 uint8_t Valid3D : 1; 110 } RX_CAP; 111 112 typedef struct 113 { 114 uint8_t offset; 115 uint8_t invAndMask; 116 uint8_t OrMask; 117 } RegSetTable_t; 118 119 #define NRTXRCLK (0x01U) /* true:set TRCLK by self */ 120 #define FORCE_TXCLK_STABLE (0x01U) 121 #define STABLE_LINEPIEXELCNT_SENSITIVITY (0x01U) 122 #define RCLK_FREQ_SEL (0x01U) /* false: 10MHz(div1); true: 20 MHz(OSSDIV2) */ 123 #define FORCE_TX_CLK_STABLE (0x01U) 124 #define FORCE_TX_VID_STABLE (0x01U) 125 #define V_SYNC_POL (0x00U) /* 0: active low; 1: active high */ 126 #define H_SYNC_POL (0x00U) /* 0: active low; 1: active high */ 127 128 #define HDMI_TX_PCLK_DIV2 (false) 129 130 #define REG_TX_SW_RST 0x04 131 #define B_TX_ENTEST (1U << 7U) 132 #define B_TX_REF_RST_HDMITX (1U << 5U) 133 #define B_TX_AREF_RST (1U << 4U) 134 #define B_HDMITX_VID_RST (1U << 3U) 135 #define B_HDMITX_AUD_RST (1U << 2U) 136 #define B_TX_HDMI_RST (1U << 1U) 137 #define B_TX_HDCP_RST_HDMITX (1U << 0U) 138 139 #define REG_TX_AFE_DRV_CTRL 0x61 140 #define B_TX_AFE_DRV_PWD (1U << 5U) 141 #define B_TX_AFE_DRV_RST (1U << 4U) 142 143 #define HDMI_TX_GENERAL_REG04 (0x04U) 144 145 #define HDMI_TX_GENERAL_REG05 (0x05U) 146 #define HDMI_TX_GENERAL_REG05_REGINTPOL_SHIFT (0x07U) 147 #define HDMI_TX_GENERAL_REG05_REGINTPOL_MASK (HDMI_TX_GENERAL_REG05_REGINTPOL(0x01U)) 148 #define HDMI_TX_GENERAL_REG05_REGINTPOL(N) ((N) << HDMI_TX_GENERAL_REG05_REGINTPOL_SHIFT) 149 #define HDMI_TX_GENERAL_REG05_REGINTIOMODE_SHIFT (0x06U) 150 #define HDMI_TX_GENERAL_REG05_REGINTIOMODE_MASK (HDMI_TX_GENERAL_REG05_REGINTIOMODE(0x01U)) 151 #define HDMI_TX_GENERAL_REG05_REGINTIOMODE(N) ((N) << HDMI_TX_GENERAL_REG05_REGINTIOMODE_SHIFT) 152 153 /* Interrupt Flags */ 154 #define HDMI_TX_INT_FLAGS_REG06 (0x06U) 155 #define HDMI_TX_INT_FLAGS_REG06_RInt_HPDStus_SHIFT (0x00U) 156 #define HDMI_TX_INT_FLAGS_REG06_RInt_HPDStus_MASK (HDMI_TX_INT_FLAGS_REG06_RInt_HPDStus(0x01U)) 157 #define HDMI_TX_INT_FLAGS_REG06_RInt_HPDStus(N) ((N) << HDMI_TX_INT_FLAGS_REG06_RInt_HPDStus_SHIFT) 158 #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCBusHang_SHIFT (0x02U) 159 #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCBusHang_MASK (HDMI_TX_INT_FLAGS_REG06_RInt_DDCBusHang(0x01U)) 160 #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCBusHang(N) ((N) << HDMI_TX_INT_FLAGS_REG06_RInt_DDCBusHang_SHIFT) 161 #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCFIFOErr_SHIFT (0x04U) 162 #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCFIFOErr_MASK (HDMI_TX_INT_FLAGS_REG06_RInt_DDCFIFOErr(0x01U)) 163 #define HDMI_TX_INT_FLAGS_REG06_RInt_DDCFIFOErr(N) ((N) << HDMI_TX_INT_FLAGS_REG06_RInt_DDCFIFOErr_SHIFT) 164 #define HDMI_TX_INT_FLAGS_REG06_RInt_AudioOvFlwStus_SHIFT (0x07U) 165 #define HDMI_TX_INT_FLAGS_REG06_RInt_AudioOvFlwStus_MASK (HDMI_TX_INT_FLAGS_REG06_RInt_AudioOvFlwStus(0x01U)) 166 #define HDMI_TX_INT_FLAGS_REG06_RInt_AudioOvFlwStus(N) ((N) << HDMI_TX_INT_FLAGS_REG06_RInt_AudioOvFlwStus_SHIFT) 167 #define HDMI_TX_INT_FLAGS_REG08 (0x08U) 168 #define HDMI_TX_INT_FLAGS_REG08_RInt_PktAVIStus_SHIFT (0x00U) 169 #define HDMI_TX_INT_FLAGS_REG08_RInt_PktAVIStus_MASK (HDMI_TX_INT_FLAGS_REG08_RInt_PktAVIStus(0x01U)) 170 #define HDMI_TX_INT_FLAGS_REG08_RInt_PktAVIStus(N) ((N) << HDMI_TX_INT_FLAGS_REG08_RInt_PktAVIStus_SHIFT) 171 #define HDMI_TX_INT_FLAGS_REG08_RInt_VidStableStus_SHIFT (0x04U) 172 #define HDMI_TX_INT_FLAGS_REG08_RInt_VidStableStus_MASK (HDMI_TX_INT_FLAGS_REG08_RInt_VidStableStus(0x01U)) 173 #define HDMI_TX_INT_FLAGS_REG08_RInt_VidStableStus(N) ((N) << HDMI_TX_INT_FLAGS_REG08_RInt_VidStableStus_SHIFT) 174 175 /* Interrupt Mask Registers */ 176 #define HDMI_TX_INT_MASK_REG09 (0x09U) 177 #define HDMI_TX_INT_MASK_REG09_REG_AudioOvFlw_SHIFT (0x07U) 178 #define HDMI_TX_INT_MASK_REG09_REG_AudioOvFlw_MASK (HDMI_TX_INT_MASK_REG09_REG_AudioOvFlw(0x01U)) 179 #define HDMI_TX_INT_MASK_REG09_REG_AudioOvFlw(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_AudioOvFlw_SHIFT) 180 #define HDMI_TX_INT_MASK_REG09_REG_DDCNoACK_SHIFT (0x05U) 181 #define HDMI_TX_INT_MASK_REG09_REG_DDCNoACK_MASK (HDMI_TX_INT_MASK_REG09_REG_DDCNoACK(0x01U)) 182 #define HDMI_TX_INT_MASK_REG09_REG_DDCNoACK(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_DDCNoACK_SHIFT) 183 #define HDMI_TX_INT_MASK_REG09_REG_DDCFIFOErr_SHIFT (0x04U) 184 #define HDMI_TX_INT_MASK_REG09_REG_DDCFIFOErr_MASK (HDMI_TX_INT_MASK_REG09_REG_DDCFIFOErr(0x01U)) 185 #define HDMI_TX_INT_MASK_REG09_REG_DDCFIFOErr(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_DDCFIFOErr_SHIFT) 186 #define HDMI_TX_INT_MASK_REG09_REG_DDCBusHang_SHIFT (0x02U) 187 #define HDMI_TX_INT_MASK_REG09_REG_DDCBusHang_MASK (HDMI_TX_INT_MASK_REG09_REG_DDCBusHang(0x01U)) 188 #define HDMI_TX_INT_MASK_REG09_REG_DDCBusHang(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_DDCBusHang_SHIFT) 189 #define HDMI_TX_INT_MASK_REG09_REG_RxSEN_SHIFT (0x01U) 190 #define HDMI_TX_INT_MASK_REG09_REG_RxSEN_MASK (HDMI_TX_INT_MASK_REG09_REG_RxSEN(0x01U)) 191 #define HDMI_TX_INT_MASK_REG09_REG_RxSEN(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_RxSEN_SHIFT) 192 #define HDMI_TX_INT_MASK_REG09_REG_HPD_SHIFT (0x00U) 193 #define HDMI_TX_INT_MASK_REG09_REG_HPD_MASK (HDMI_TX_INT_MASK_REG09_REG_HPD(0x01U)) 194 #define HDMI_TX_INT_MASK_REG09_REG_HPD(N) ((N) << HDMI_TX_INT_MASK_REG09_REG_HPD_SHIFT) 195 196 #define HDMI_TX_INT_MASK_REG0B (0x0BU) 197 #define HDMI_TX_INT_MASK_REG0B_REG_VidStable_SHIFT (0x03U) 198 #define HDMI_TX_INT_MASK_REG0B_REG_VidStable_MASK (HDMI_TX_INT_MASK_REG0B_REG_VidStable(0x01U)) 199 #define HDMI_TX_INT_MASK_REG0B_REG_VidStable(N) ((N) << HDMI_TX_INT_MASK_REG0B_REG_VidStable_SHIFT) 200 201 /* Interrupt Clear */ 202 #define HDMI_TX_INT_CLEAR_REG0C (0x0CU) 203 #define HDMI_TX_INT_CLEAR_REG0D (0x0DU) 204 205 #define HDMI_TX_SYS_STATUS_REG0E (0x0EU) 206 #define HDMI_TX_SYS_STATUS_REG0E_RHPDetect_SHIFT (0x06U) 207 #define HDMI_TX_SYS_STATUS_REG0E_RHPDetect_MASK (HDMI_TX_SYS_STATUS_REG0E_RHPDetect(0x01U)) 208 #define HDMI_TX_SYS_STATUS_REG0E_RHPDetect(N) ((N) << HDMI_TX_SYS_STATUS_REG0E_RHPDetect_SHIFT) 209 #define HDMI_TX_SYS_STATUS_REG0E_TxVidStable_SHIFT (0x04U) 210 #define HDMI_TX_SYS_STATUS_REG0E_TxVidStable_MASK (HDMI_TX_SYS_STATUS_REG0E_TxVidStable(0x01U)) 211 #define HDMI_TX_SYS_STATUS_REG0E_TxVidStable(N) ((N) << HDMI_TX_SYS_STATUS_REG0E_TxVidStable_SHIFT) 212 #define HDMI_TX_SYS_STATUS_REG0E_Reg_AudCTSClr_SHIFT (0x01U) 213 #define HDMI_TX_SYS_STATUS_REG0E_Reg_AudCTSClr_MASK (HDMI_TX_SYS_STATUS_REG0E_Reg_AudCTSClr(0x01U)) 214 #define HDMI_TX_SYS_STATUS_REG0E_Reg_AudCTSClr(N) ((N) << HDMI_TX_SYS_STATUS_REG0E_Reg_AudCTSClr_SHIFT) 215 #define HDMI_TX_SYS_STATUS_REG0E_Reg_IntActDone_SHIFT (0x00U) 216 #define HDMI_TX_SYS_STATUS_REG0E_Reg_IntActDone_MASK (HDMI_TX_SYS_STATUS_REG0E_Reg_IntActDone(0x01U)) 217 #define HDMI_TX_SYS_STATUS_REG0E_Reg_IntActDone(N) ((N) << HDMI_TX_SYS_STATUS_REG0E_Reg_IntActDone_SHIFT) 218 219 #define HDMI_TX_SYS_STATUS_REG0F (0x0FU) 220 #define HDMI_TX_SYS_STATUS_REG0F_REGBANKSEL_SHIFT (0x00U) 221 #define HDMI_TX_SYS_STATUS_REG0F_REGBANKSEL_MASK (HDMI_TX_SYS_STATUS_REG0F_REGBANKSEL(0x03U)) 222 #define HDMI_TX_SYS_STATUS_REG0F_REGBANKSEL(N) ((N) << HDMI_TX_SYS_STATUS_REG0F_REGBANKSEL_SHIFT) 223 224 #define HDMI_TX_SYS_DDC_CTRL_REG10 (0x10U) 225 #define HDMI_TX_SYS_DDC_CTRL_REG10_Reg_MasterSel_SHIFT (0x00U) 226 #define HDMI_TX_SYS_DDC_CTRL_REG10_Reg_MasterSel_MASK (HDMI_TX_SYS_DDC_CTRL_REG10_Reg_MasterSel(0x01U)) 227 #define HDMI_TX_SYS_DDC_CTRL_REG10_Reg_MasterSel(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG10_Reg_MasterSel_SHIFT) 228 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSDA_SHIFT (0x01U) 229 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSDA_MASK (HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSDA(0x01U)) 230 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSDA(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSDA_SHIFT) 231 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSCL_SHIFT (0x02U) 232 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSCL_MASK (HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSCL(0x01U)) 233 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSCL(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDCSCL_SHIFT) 234 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDC_SHIFT (0x03U) 235 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDC_MASK (HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDC(0x01U)) 236 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDC(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG10_REGSoftDDC_SHIFT) 237 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGGenCLKPulse_SHIFT (0x04U) 238 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGGenCLKPulse_MASK (HDMI_TX_SYS_DDC_CTRL_REG10_REGGenCLKPulse(0x0FU)) 239 #define HDMI_TX_SYS_DDC_CTRL_REG10_REGGenCLKPulse(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG10_REGGenCLKPulse_SHIFT) 240 241 #define HDMI_TX_SYS_DDC_CTRL_REG11 (0x11U) 242 #define HDMI_TX_SYS_DDC_CTRL_REG11_RDDC_HEADER_SHIFT (0x00U) 243 #define HDMI_TX_SYS_DDC_CTRL_REG11_RDDC_HEADER_MASK (HDMI_TX_SYS_DDC_CTRL_REG11_RDDC_HEADER(0xFFU)) 244 #define HDMI_TX_SYS_DDC_CTRL_REG11_RDDC_HEADER(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG11_RDDC_HEADER_SHIFT) 245 /* RDDC_Header[7:0]: PC DDC request slave address */ 246 #define HDMI_TX_DDC_HDCP_ADDR (0x74U) 247 #define HDMI_TX_DDC_EDID_ADDR (0xA0U) 248 249 #define HDMI_TX_SYS_DDC_CTRL_REG12 (0x12U) 250 #define HDMI_TX_SYS_DDC_CTRL_REG12_RDDC_ReqOffSet_SHIFT (0x00U) 251 #define HDMI_TX_SYS_DDC_CTRL_REG12_RDDC_ReqOffSet_MASK (HDMI_TX_SYS_DDC_CTRL_REG12_RDDC_ReqOffSet(0xFFU)) 252 #define HDMI_TX_SYS_DDC_CTRL_REG12_RDDC_ReqOffSet(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG12_RDDC_ReqOffSet_SHIFT) 253 254 #define HDMI_TX_SYS_DDC_CTRL_REG13 (0x13U) 255 #define HDMI_TX_SYS_DDC_CTRL_REG13_RDDC_ReqByte_SHIFT (0x00U) 256 #define HDMI_TX_SYS_DDC_CTRL_REG13_RDDC_ReqByte_MASK (HDMI_TX_SYS_DDC_CTRL_REG13_RDDC_ReqByte(0xFFU)) 257 #define HDMI_TX_SYS_DDC_CTRL_REG13_RDDC_ReqByte(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG13_RDDC_ReqByte_SHIFT) 258 259 #define HDMI_TX_SYS_DDC_CTRL_REG14 (0x14U) 260 #define HDMI_TX_SYS_DDC_CTRL_REG14_RDDC_Segment_SHIFT (0x00U) 261 #define HDMI_TX_SYS_DDC_CTRL_REG14_RDDC_Segment_MASK (HDMI_TX_SYS_DDC_CTRL_REG14_RDDC_Segment(0xFFU)) 262 #define HDMI_TX_SYS_DDC_CTRL_REG14_RDDC_Segment(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG14_RDDC_Segment_SHIFT) 263 264 #define HDMI_TX_SYS_DDC_CTRL_REG15 (0x15U) 265 #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_SHIFT (0x00U) 266 #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_MASK (HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(0x0FU)) 267 #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_EDID_read HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(0x03U) 268 #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_DDC_FIFO_clear HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(0x09U) 269 #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_GenerateSCL_clock_pulse HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(0x0AU) 270 #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_Abort_DDC_CMD HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(0x0FU) 271 #define HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG15_RDDC_Req_SHIFT) 272 273 #define HDMI_TX_SYS_DDC_CTRL_REG16 (0x16U) 274 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_Done_SHIFT (0x07U) 275 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_Done_MASK (HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_Done(0x01U)) 276 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_Done(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_Done_SHIFT) 277 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_NoACK_SHIFT (0x05U) 278 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_NoACK_MASK (HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_NoACK(0x01U)) 279 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_NoACK(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_NoACK_SHIFT) 280 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_WaitBus_SHIFT (0x04U) 281 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_WaitBus_MASK (HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_WaitBus(0x01U)) 282 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_WaitBus(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_WaitBus_SHIFT) 283 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_ArbiLose_SHIFT (0x03U) 284 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_ArbiLose_MASK (HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_ArbiLose(0x01U)) 285 #define HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_ArbiLose(N) \ 286 ((N) << HDMI_TX_SYS_DDC_CTRL_REG16_RDDC_Status_ArbiLose_SHIFT) 287 288 #define HDMI_TX_SYS_DDC_CTRL_REG17 (0x17U) 289 #define HDMI_TX_SYS_DDC_CTRL_REG17_RDDC_ReadFIFO_SHIFT (0x00U) 290 #define HDMI_TX_SYS_DDC_CTRL_REG17_RDDC_ReadFIFO_MASK (HDMI_TX_SYS_DDC_CTRL_REG17_RDDC_ReadFIFO(0xFFU)) 291 #define HDMI_TX_SYS_DDC_CTRL_REG17_RDDC_ReadFIFO(N) ((N) << HDMI_TX_SYS_DDC_CTRL_REG17_RDDC_ReadFIFO_SHIFT) 292 293 /* HDMI TX Clock Control */ 294 #define HDMI_TX_CLOCK_CONTROL_REG58 (0x58U) 295 #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKSamp_SHIFT (0x07U) 296 #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKSamp_MASK (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKSamp(0x01U)) 297 #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKSamp(N) ((N) << HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKSamp_SHIFT) 298 #define HDMI_TX_CLOCK_CONTROL_REG58_REGAutoOSCLK_SHIFT (0x04U) 299 #define HDMI_TX_CLOCK_CONTROL_REG58_REGAutoOSCLK_MASK (HDMI_TX_CLOCK_CONTROL_REG58_REGAutoOSCLK(0x01U)) 300 #define HDMI_TX_CLOCK_CONTROL_REG58_REGAutoOSCLK(N) ((N) << HDMI_TX_CLOCK_CONTROL_REG58_REGAutoOSCLK_SHIFT) 301 #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_SHIFT (0x00U) 302 #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_MASK (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(0x03U)) 303 #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(N) ((N) << HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_SHIFT) 304 #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_1x128Fs (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(0x00U)) 305 #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_2x128Fs (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(0x01U)) 306 #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_4x128Fs (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(0x02U)) 307 #define HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq_8x128Fs (HDMI_TX_CLOCK_CONTROL_REG58_REGMCLKFreq(0x03U)) 308 309 #define HDMI_TX_CLOCK_CONTROL_REG5D (0x5DU) 310 311 #define HDMI_TX_CLOCK_CONTROL_REG5F (0x5FU) 312 #define HDMI_TX_CLOCK_CONTROL_REG5F_OSFreqLock_SHIFT (0x05U) 313 #define HDMI_TX_CLOCK_CONTROL_REG5F_OSFreqLock_MASK (HDMI_TX_CLOCK_CONTROL_REG5F_OSFreqLock(0x01U)) 314 #define HDMI_TX_CLOCK_CONTROL_REG5F_OSFreqLock(N) ((N) << HDMI_TX_CLOCK_CONTROL_REG5F_OSFreqLock_SHIFT) 315 316 /* Input Data Format Registers */ 317 #define HDMI_TX_INPUT_DATA_FORMAT_REG70 (0x70U) 318 #define HDMI_TX_INPUT_DATA_FORMAT_REG70_Reg_PCLKDiv2_SHIFT (0x05U) 319 #define HDMI_TX_INPUT_DATA_FORMAT_REG70_Reg_PCLKDiv2_MASK (HDMI_TX_INPUT_DATA_FORMAT_REG70_Reg_PCLKDiv2(0x01U)) 320 #define HDMI_TX_INPUT_DATA_FORMAT_REG70_Reg_PCLKDiv2(N) ((N) << HDMI_TX_INPUT_DATA_FORMAT_REG70_Reg_PCLKDiv2_SHIFT) 321 322 #define HDMI_TX_INPUT_DATA_FORMAT_REG72 (0x72U) 323 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_SHIFT (0x00U) 324 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_MASK (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel(0x03U)) 325 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel(N) ((N) << HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_SHIFT) 326 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_BYPASS (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel(0x00U)) 327 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_RGB2YUV (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel(0x02U)) 328 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel_YUV2RGB (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_CSCSel(0x03U)) 329 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_DNFREE_GO_SHIFT (0x05U) 330 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_DNFREE_GO_MASK (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_DNFREE_GO(0x01U)) 331 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_DNFREE_GO(N) ((N) << HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_DNFREE_GO_SHIFT) 332 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER_SHIFT (0x06U) 333 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER_MASK (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER(0x01U)) 334 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER(N) \ 335 ((N) << HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_UDFILTER_SHIFT) 336 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_SHIFT (0x07U) 337 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_MASK (HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER(0x01U)) 338 #define HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER(N) ((N) << HDMI_TX_INPUT_DATA_FORMAT_REG72_Reg_EN_DITHER_SHIFT) 339 340 /* Color Space Conversion */ 341 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG73 (0x73U) 342 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG73_Reg_YoffSet_SHIFT (0x00U) 343 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG73_Reg_YoffSet_MASK (HDMI_TX_COLOR_SPACE_CONVERSION_REG73_Reg_YoffSet(0xFFU)) 344 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG73_Reg_YoffSet(N) \ 345 ((N) << HDMI_TX_COLOR_SPACE_CONVERSION_REG73_Reg_YoffSet_SHIFT) 346 347 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D (0x8DU) 348 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegEnCRCLK_SHIFT (0x00U) 349 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegEnCRCLK_MASK (HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegEnCRCLK(0x01U)) 350 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegEnCRCLK(N) \ 351 ((N) << HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegEnCRCLK_SHIFT) 352 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegCECSlvAdr_SHIFT (0x01U) 353 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegCECSlvAdr_MASK \ 354 (HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegCECSlvAdr(0x7FU)) 355 #define HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegCECSlvAdr(N) \ 356 ((N) << HDMI_TX_COLOR_SPACE_CONVERSION_REG8D_RegCECSlvAdr_SHIFT) 357 #define HDMI_TX_CEC_SLAVE_ADDR (0x4EU) 358 359 /* Pattern Sync/DE Generation */ 360 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90 (0x90U) 361 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE_SHIFT (0x00U) 362 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE_MASK \ 363 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE(0x01U)) 364 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE(N) \ 365 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_GenDE_SHIFT) 366 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol_SHIFT (0x01U) 367 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol_MASK \ 368 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol(0x01U)) 369 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol(N) \ 370 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegHSPol_SHIFT) 371 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol_SHIFT (0x02U) 372 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol_MASK \ 373 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol(0x01U)) 374 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol(N) \ 375 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegVSPol_SHIFT) 376 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegGenSync_SHIFT (0x03U) 377 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegGenSync_MASK \ 378 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegGenSync(0x01U)) 379 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegGenSync(N) \ 380 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_RegGenSync_SHIFT) 381 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal_SHIFT (0x04U) 382 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal_MASK \ 383 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal(0x0FU)) 384 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal(N) \ 385 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG90_Reg_PGHTotal_SHIFT) 386 387 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91 (0x91U) 388 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal_SHIFT (0x00U) 389 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal_MASK \ 390 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal(0xFFU)) 391 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal(N) \ 392 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG91_Reg_PGHTotal_SHIFT) 393 394 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95 (0x95U) 395 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS_SHIFT (0x00U) 396 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS_MASK \ 397 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS(0xFFU)) 398 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS(N) \ 399 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG95_Reg_PGHRS_SHIFT) 400 401 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96 (0x96U) 402 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE_SHIFT (0x00U) 403 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE_MASK \ 404 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE(0xFFU)) 405 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE(N) \ 406 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG96_Reg_PGHRE_SHIFT) 407 408 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97 (0x97U) 409 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE_SHIFT (0x04U) 410 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE_MASK \ 411 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE(0x0FU)) 412 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE(N) \ 413 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRE_SHIFT) 414 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS_SHIFT (0x00U) 415 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS_MASK \ 416 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS(0x0FU)) 417 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS(N) \ 418 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG97_Reg_PGHRS_SHIFT) 419 420 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98 (0x98U) 421 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal_SHIFT (0x00U) 422 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal_MASK \ 423 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal(0xFFU)) 424 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal(N) \ 425 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG98_Reg_PGVTotal_SHIFT) 426 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99 (0x99U) 427 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal_SHIFT (0x00U) 428 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal_MASK \ 429 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal(0xFFU)) 430 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal(N) \ 431 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REG99_Reg_PGVTotal_SHIFT) 432 433 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0 (0xA0U) 434 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS_SHIFT (0x00U) 435 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS_MASK \ 436 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS(0xFFU)) 437 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS(N) \ 438 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA0_Reg_PGVRS_SHIFT) 439 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1 (0xA1U) 440 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE_SHIFT (0x04U) 441 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE_MASK \ 442 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE(0x0FU)) 443 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE(N) \ 444 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRE_SHIFT) 445 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS_SHIFT (0x00U) 446 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS_MASK \ 447 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS(0x0FU)) 448 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS(N) \ 449 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA1_Reg_PGVRS_SHIFT) 450 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2 (0xA2U) 451 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd_SHIFT (0x00U) 452 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd_MASK \ 453 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd(0xFFU)) 454 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd(N) \ 455 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA2_Reg_PGVRS2nd_SHIFT) 456 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3 (0xA3U) 457 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd_SHIFT (0x04U) 458 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd_MASK \ 459 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd(0x0FU)) 460 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd(N) \ 461 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRE2nd_SHIFT) 462 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd_SHIFT (0x00U) 463 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd_MASK \ 464 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd(0x0FU)) 465 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd(N) \ 466 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA3_Reg_PGVRS2nd_SHIFT) 467 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4 (0xA4U) 468 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise_SHIFT (0x00U) 469 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise_MASK \ 470 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise(0xFFU)) 471 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise(N) \ 472 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA4_Reg_PGEn2ndVRRise_SHIFT) 473 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5 (0xA5U) 474 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced_SHIFT (0x04U) 475 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced_MASK \ 476 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced(0x01U)) 477 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced(N) \ 478 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGInterlaced_SHIFT) 479 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn_SHIFT (0x05U) 480 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn_MASK \ 481 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn(0x01U)) 482 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn(N) \ 483 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_DEOnlyIn_SHIFT) 484 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise_SHIFT (0x00U) 485 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise_MASK \ 486 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise(0x0FU)) 487 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise(N) \ 488 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA5_Reg_PGEn2ndVRRise_SHIFT) 489 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6 (0xA6U) 490 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd_SHIFT (0x04U) 491 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd_MASK \ 492 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd(0x0FU)) 493 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd(N) \ 494 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE2nd_SHIFT) 495 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE_SHIFT (0x00U) 496 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE_MASK \ 497 (HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE(0x0FU)) 498 #define HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE(N) \ 499 ((N) << HDMI_TX_PATTERN_SYNC_DE_GENERATION_REGA6_Reg_PGVRE_SHIFT) 500 501 /* Pattern Generator */ 502 #define HDMI_TX_PATTERN_GENERATOR_REGA9 (0xA9U) 503 #define HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM_SHIFT (0x07U) 504 #define HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM_MASK (HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM(0x01U)) 505 #define HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGA9_RegHBPM_SHIFT) 506 507 #define HDMI_TX_PATTERN_GENERATOR_REGB1 (0xB1U) 508 #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE_SHIFT (0x06U) 509 #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE_MASK (HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE(0x01U)) 510 #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRE_SHIFT) 511 #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS_SHIFT (0x04U) 512 #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS_MASK (HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS(0x01U)) 513 #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHRS_SHIFT) 514 #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES_SHIFT (0x00U) 515 #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES_MASK (HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES(0x01U)) 516 #define HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGB1_Reg_PGHDES_SHIFT) 517 #define HDMI_TX_PATTERN_GENERATOR_REGB2 (0xB2U) 518 #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise_SHIFT (0x02U) 519 #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise_MASK \ 520 (HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise(0x01U)) 521 #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise(N) \ 522 ((N) << HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGEn2ndVRRise_SHIFT) 523 524 #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal_SHIFT (0x00U) 525 #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal_MASK (HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal(0x01U)) 526 #define HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGB2_Reg_PGHTotal_SHIFT) 527 528 #define HDMI_TX_PATTERN_GENERATOR_REGBF (0xBFU) 529 #define HDMI_TX_PATTERN_GENERATOR_REGBF_Reg_RBSwap_SHIFT (0x00U) 530 #define HDMI_TX_PATTERN_GENERATOR_REGBF_Reg_RBSwap_MASK (HDMI_TX_PATTERN_GENERATOR_REGBF_Reg_RBSwap(0x01U)) 531 #define HDMI_TX_PATTERN_GENERATOR_REGBF_Reg_RBSwap(N) ((N) << HDMI_TX_PATTERN_GENERATOR_REGBF_Reg_RBSwap_SHIFT) 532 533 /* HDMI Control Registers */ 534 #define HDMI_TX_HDMI_CONTROL_REGC0 (0xC0U) 535 #define HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode_SHIFT (0x00U) 536 #define HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode_MASK (HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode(0x01U)) 537 #define HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode_SHIFT) 538 #define HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode_DVI_MODE (HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode(0x00U)) 539 #define HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode_HDMI_MODE (HDMI_TX_HDMI_CONTROL_REGC0_REGHDMIMode(0x01U)) 540 541 #define HDMI_TX_HDMI_CONTROL_REGC1 (0xC1U) 542 #define HDMI_TX_HDMI_CONTROL_REGC1_REGAVMute_SHIFT (0x00U) 543 #define HDMI_TX_HDMI_CONTROL_REGC1_REGAVMute_MASK (HDMI_TX_HDMI_CONTROL_REGC1_REGAVMute(0x01U)) 544 #define HDMI_TX_HDMI_CONTROL_REGC1_REGAVMute(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC1_REGAVMute_SHIFT) 545 546 #define HDMI_TX_HDMI_CONTROL_REGC5 (0xC5U) 547 #define HDMI_TX_HDMI_CONTROL_REGC5_REGSinglePkt_SHIFT (0x00U) 548 #define HDMI_TX_HDMI_CONTROL_REGC5_REGSinglePkt_MASK (HDMI_TX_HDMI_CONTROL_REGC5_REGSinglePkt(0x01U)) 549 #define HDMI_TX_HDMI_CONTROL_REGC5_REGSinglePkt(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC5_REGSinglePkt_SHIFT) 550 #define HDMI_TX_HDMI_CONTROL_REGC5_REGPktAudNCTSSel_SHIFT (0x01U) 551 #define HDMI_TX_HDMI_CONTROL_REGC5_REGPktAudNCTSSel_MASK (HDMI_TX_HDMI_CONTROL_REGC5_REGPktAudNCTSSel(0x01U)) 552 #define HDMI_TX_HDMI_CONTROL_REGC5_REGPktAudNCTSSel(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC5_REGPktAudNCTSSel_SHIFT) 553 554 #define HDMI_TX_HDMI_CONTROL_REGC6 (0xC6U) 555 #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlRpt_SHIFT (0x01U) 556 #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlRpt_MASK (HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlRpt(0x01U)) 557 #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlRpt(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlRpt_SHIFT) 558 #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlEn_SHIFT (0x00U) 559 #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlEn_MASK (HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlEn(0x01U)) 560 #define HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlEn(N) ((N) << HDMI_TX_HDMI_CONTROL_REGC6_REGPktGenCtrlEn_SHIFT) 561 562 #define HDMI_TX_HDMI_CONTROL_REGCD (0xCDU) 563 #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoRpt_SHIFT (0x01U) 564 #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoRpt_MASK (HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoRpt(0x01U)) 565 #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoRpt(N) ((N) << HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoRpt_SHIFT) 566 #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoEn_SHIFT (0x00U) 567 #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoEn_MASK (HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoEn(0x01U)) 568 #define HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoEn(N) ((N) << HDMI_TX_HDMI_CONTROL_REGCD_REGPktAVIInfoEn_SHIFT) 569 570 #define HDMI_TX_HDMI_CONTROL_REGCE (0xCEU) 571 #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoRpt_SHIFT (0x01U) 572 #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoRpt_MASK (HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoRpt(0x01U)) 573 #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoRpt(N) ((N) << HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoRpt_SHIFT) 574 #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoEn_SHIFT (0x00U) 575 #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoEn_MASK (HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoEn(0x01U)) 576 #define HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoEn(N) ((N) << HDMI_TX_HDMI_CONTROL_REGCE_REGPktAudInfoEn_SHIFT) 577 578 #define HDMI_TX_HDMI_CONTROL_REGD1 (0xD1U) 579 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_SHIFT (0x00U) 580 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_MASK (HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd(0x0FU)) 581 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd(N) ((N) << HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_SHIFT) 582 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable_SHIFT (0x03U) 583 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable_MASK \ 584 (HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable(0x01U)) 585 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable(N) \ 586 ((N) << HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxCLKStable_SHIFT) 587 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable_SHIFT (0x02U) 588 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable_MASK \ 589 (HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable(0x01U)) 590 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable(N) \ 591 ((N) << HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TxVidStable_SHIFT) 592 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_StableLinePixelCntSensitivity_SHIFT (0x01U) 593 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_StableLinePixelCntSensitivity_MASK \ 594 (HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_StableLinePixelCntSensitivity(0x01U)) 595 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_StableLinePixelCntSensitivity(N) \ 596 ((N) << HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_StableLinePixelCntSensitivity_SHIFT) 597 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TimerOfTxClkStableCheck_SHIFT (0x00U) 598 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TimerOfTxClkStableCheck_MASK \ 599 (HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TimerOfTxClkStableCheck(0x01U)) 600 #define HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TimerOfTxClkStableCheck(N) \ 601 ((N) << HDMI_TX_HDMI_CONTROL_REGD1_RegStableDbgMd_TimerOfTxClkStable_SHIFT) 602 603 /* Audio Channel Registers */ 604 #define HDMI_TX_AUDIO_CHANNEL_REGE0 (0xE0U) 605 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_SHIFT (0x06U) 606 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_MASK (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(0x03U)) 607 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_SHIFT) 608 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_16bits (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(0x00U)) 609 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_18bits (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(0x01U)) 610 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_20bits (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(0x02U)) 611 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL_24bits (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSWL(0x03U)) 612 613 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGSPDIFTC_SHIFT (0x05U) 614 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGSPDIFTC_MASK (HDMI_TX_AUDIO_CHANNEL_REGE0_REGSPDIFTC(0x01U)) 615 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGSPDIFTC(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE0_REGSPDIFTC_SHIFT) 616 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel_SHIFT (0x04U) 617 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel(0x01U)) 618 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel_SHIFT) 619 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel_I2S (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel(0x00U)) 620 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel_SPDIF (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudSel(0x01U)) 621 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_SHIFT (0x00U) 622 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_MASK (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(0x0FU)) 623 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_SHIFT) 624 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_Enable_Audio_Source_0 (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(0x01U)) 625 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_Enable_Audio_Source_1 (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(0x02U)) 626 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_Enable_Audio_Source_2 (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(0x04U)) 627 #define HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn_Enable_Audio_Source_3 (HDMI_TX_AUDIO_CHANNEL_REGE0_REGAudioEn(0x08U)) 628 629 #define HDMI_TX_AUDIO_CHANNEL_REGE1 (0xE1U) 630 #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFullPkt_SHIFT (0x06U) 631 #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFullPkt_MASK (HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFullPkt(0x01U)) 632 #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFullPkt(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFullPkt_SHIFT) 633 #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudLatEdge_SHIFT (0x05U) 634 #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudLatEdge_MASK (HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudLatEdge(0x01U)) 635 #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudLatEdge(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudLatEdge_SHIFT) 636 #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFmt_SHIFT (0x00U) 637 #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFmt_MASK (HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFmt(0x1FU)) 638 #define HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFmt(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE1_REGAudFmt_SHIFT) 639 640 #define HDMI_TX_AUDIO_CHANNEL_REGE2 (0xE2U) 641 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo3Sel_SHIFT (0x06U) 642 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo3Sel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo3Sel(0x03U)) 643 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo3Sel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo3Sel_SHIFT) 644 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo2Sel_SHIFT (0x04U) 645 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo2Sel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo2Sel(0x03U)) 646 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo2Sel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo2Sel_SHIFT) 647 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo1Sel_SHIFT (0x02U) 648 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo1Sel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo1Sel(0x03U)) 649 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo1Sel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo1Sel_SHIFT) 650 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo0Sel_SHIFT (0x00U) 651 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo0Sel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo0Sel(0x03U)) 652 #define HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo0Sel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE2_REGFifo0Sel_SHIFT) 653 654 #define HDMI_TX_AUDIO_CHANNEL_REGE3 (0xE3U) 655 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGAudMulCh_SHIFT (0x07U) 656 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGAudMulCh_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGAudMulCh(0x01U)) 657 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGAudMulCh(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGAudMulCh_SHIFT) 658 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGPktZeroCTS_SHIFT (0x06U) 659 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGPktZeroCTS_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGPktZeroCTS(0x01U)) 660 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGPktZeroCTS(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGPktZeroCTS_SHIFT) 661 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGChStSel_SHIFT (0x04U) 662 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGChStSel_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGChStSel(0x01U)) 663 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGChStSel(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGChStSel_SHIFT) 664 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS3RLChg_SHIFT (0x03U) 665 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS3RLChg_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGS3RLChg(0x01U)) 666 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS3RLChg(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGS3RLChg_SHIFT) 667 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS2RLChg_SHIFT (0x02U) 668 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS2RLChg_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGS2RLChg(0x01U)) 669 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS2RLChg(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGS2RLChg_SHIFT) 670 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS1RLChg_SHIFT (0x01U) 671 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS1RLChg_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGS1RLChg(0x01U)) 672 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS1RLChg(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGS1RLChg_SHIFT) 673 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS0RLChg_SHIFT (0x00U) 674 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS0RLChg_MASK (HDMI_TX_AUDIO_CHANNEL_REGE3_REGS0RLChg(0x01U)) 675 #define HDMI_TX_AUDIO_CHANNEL_REGE3_REGS0RLChg(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE3_REGS0RLChg_SHIFT) 676 677 #define HDMI_TX_AUDIO_CHANNEL_REGE4 (0xE4U) 678 #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudSPxFlat_SHIFT (0x04U) 679 #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudSPxFlat_MASK (HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudSPxFlat(0x0FU)) 680 #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudSPxFlat(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudSPxFlat_SHIFT) 681 #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudErr2Flat_SHIFT (0x03U) 682 #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudErr2Flat_MASK (HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudErr2Flat(0x01U)) 683 #define HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudErr2Flat(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE4_REGAudErr2Flat_SHIFT) 684 685 #define HDMI_TX_AUDIO_CHANNEL_REGE5 (0xE5U) 686 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegForceASCLKDiv_SHIFT (0x07U) 687 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegForceASCLKDiv_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_RegForceASCLKDiv(0x01U)) 688 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegForceASCLKDiv(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_RegForceASCLKDiv_SHIFT) 689 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegTDMCh_SHIFT (0x05U) 690 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegTDMCh_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_RegTDMCh(0x03U)) 691 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegTDMCh(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_RegTDMCh_SHIFT) 692 #define HDMI_TX_AUDIO_CHANNEL_REGE5_SpdifCompFit_SHIFT (0x04U) 693 #define HDMI_TX_AUDIO_CHANNEL_REGE5_SpdifCompFit_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_SpdifCompFit(0x01U)) 694 #define HDMI_TX_AUDIO_CHANNEL_REGE5_SpdifCompFit(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_SpdifCompFit_SHIFT) 695 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegAudHBR_SHIFT (0x03U) 696 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegAudHBR_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_RegAudHBR(0x01U)) 697 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegAudHBR(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_RegAudHBR_SHIFT) 698 #define HDMI_TX_AUDIO_CHANNEL_REGE5_Reg1BAud_SHIFT (0x01U) 699 #define HDMI_TX_AUDIO_CHANNEL_REGE5_Reg1BAud_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_Reg1BAud(0x01U)) 700 #define HDMI_TX_AUDIO_CHANNEL_REGE5_Reg1BAud(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_Reg1BAud_SHIFT) 701 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegEnTDM_SHIFT (0x00U) 702 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegEnTDM_MASK (HDMI_TX_AUDIO_CHANNEL_REGE5_RegEnTDM(0x01U)) 703 #define HDMI_TX_AUDIO_CHANNEL_REGE5_RegEnTDM(N) ((N) << HDMI_TX_AUDIO_CHANNEL_REGE5_RegEnTDM_SHIFT) 704 705 /* Registers in Bank 1 */ 706 #define HDMI_TX_REGPktAudCTS0 (0x30U) // 7:0 707 #define HDMI_TX_REGPktAudCTS1 (0x31U) // 15:8 708 #define HDMI_TX_REGPktAudCTS2 (0x32U) // 19:16 709 #define HDMI_TX_REGPktAudN0 (0x33U) // 7:0 710 #define HDMI_TX_REGPktAudN1 (0x34U) // 15:8 711 #define HDMI_TX_REGPktAudN2 (0x35U) // 19:16 712 #define HDMI_TX_REGPktAudCTSCnt0 (0x35U) // 3:0 713 #define HDMI_TX_REGPktAudCTSCnt1 (0x36U) // 11:4 714 #define HDMI_TX_REGPktAudCTSCnt2 (0x37U) // 19:12 715 #define HDMI_TX_AVIINFO_DB1 (0x58U) 716 #define HDMI_TX_AVIINFO_SUM (0x5DU) 717 718 #define HDMI_TX_PKT_AUDINFO_CC (0x68U) // [2:0] 719 #define HDMI_TX_PKT_AUDINFO_SF (0x69U) // [4:2] 720 #define HDMI_TX_PKT_AUDINFO_CA (0x6BU) // [7:0] 721 #define HDMI_TX_PKT_AUDINFO_DM_LSV (0x6CU) // [7][6:3] 722 #define HDMI_TX_PKT_AUDINFO_SUM (0x6DU) // [7:0] 723 724 #define HDMI_TX_AUDCHST_MODE (0x91U) 725 #define HDMI_TX_AUDCHST_CAT (0x92U) 726 #define HDMI_TX_AUDCHST_SRCNUM (0x93U) 727 #define HDMI_TX_AUD0CHST_CHTNUM (0x94U) 728 #define HDMI_TX_AUDCHST_CA_FS (0x98U) 729 #define HDMI_TX_AUDCHST_OFS_WL (0x99U) 730 731 #define HDMITX_MAX_DEV_COUNT 1 732 733 /////////////////////////////////////////////////////////////////////// 734 // Output Mode Type 735 /////////////////////////////////////////////////////////////////////// 736 737 #define RES_ASPEC_4x3 0 738 #define RES_ASPEC_16x9 1 739 #define F_MODE_REPT_NO 0 740 #define F_MODE_REPT_TWICE 1 741 #define F_MODE_REPT_QUATRO 3 742 #define F_MODE_CSC_ITU601 0 743 #define F_MODE_CSC_ITU709 1 744 745 #define TIMER_LOOP_LEN 10 746 #define MS(x) (((x) + (TIMER_LOOP_LEN - 1)) / TIMER_LOOP_LEN); // for timer loop 747 748 // #define SUPPORT_AUDI_AudSWL 16 // Jeilin case. 749 #define SUPPORT_AUDI_AudSWL 24 // Jeilin case. 750 751 #if (SUPPORT_AUDI_AudSWL == 16) 752 #define CHTSTS_SWCODE 0x02U 753 #elif (SUPPORT_AUDI_AudSWL == 18) 754 #define CHTSTS_SWCODE 0x04U 755 #elif (SUPPORT_AUDI_AudSWL == 20) 756 #define CHTSTS_SWCODE 0x03U 757 #else 758 #define CHTSTS_SWCODE 0x0BU 759 #endif 760 761 void HDMITX_DevLoopProc(display_handle_t *handle); 762 void HDMITX_VideoReset(display_handle_t *handle); 763 void HDMITX_LoadRegSetting(display_handle_t *handle, RegSetTable_t *table, uint32_t table_sz); 764 #endif // _HDMITX_H_ 765
