1 /* 2 * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_H 8 #define ARCH_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * MIDR bit definitions 14 ******************************************************************************/ 15 #define MIDR_IMPL_MASK U(0xff) 16 #define MIDR_IMPL_SHIFT U(24) 17 #define MIDR_VAR_SHIFT U(20) 18 #define MIDR_VAR_BITS U(4) 19 #define MIDR_REV_SHIFT U(0) 20 #define MIDR_REV_BITS U(4) 21 #define MIDR_PN_MASK U(0xfff) 22 #define MIDR_PN_SHIFT U(4) 23 24 /******************************************************************************* 25 * MPIDR macros 26 ******************************************************************************/ 27 #define MPIDR_MT_MASK (U(1) << 24) 28 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 29 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 30 #define MPIDR_AFFINITY_BITS U(8) 31 #define MPIDR_AFFLVL_MASK U(0xff) 32 #define MPIDR_AFFLVL_SHIFT U(3) 33 #define MPIDR_AFF0_SHIFT U(0) 34 #define MPIDR_AFF1_SHIFT U(8) 35 #define MPIDR_AFF2_SHIFT U(16) 36 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 37 #define MPIDR_AFFINITY_MASK U(0x00ffffff) 38 #define MPIDR_AFFLVL0 U(0) 39 #define MPIDR_AFFLVL1 U(1) 40 #define MPIDR_AFFLVL2 U(2) 41 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 42 43 #define MPIDR_AFFLVL0_VAL(mpidr) \ 44 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 45 #define MPIDR_AFFLVL1_VAL(mpidr) \ 46 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 47 #define MPIDR_AFFLVL2_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL3_VAL(mpidr) U(0) 50 51 #define MPIDR_AFF_ID(mpid, n) \ 52 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 53 54 #define MPID_MASK (MPIDR_MT_MASK |\ 55 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\ 56 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\ 57 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 58 59 /* 60 * An invalid MPID. This value can be used by functions that return an MPID to 61 * indicate an error. 62 */ 63 #define INVALID_MPID U(0xFFFFFFFF) 64 65 /* 66 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 67 * add one while using this macro to define array sizes. 68 */ 69 #define MPIDR_MAX_AFFLVL U(2) 70 71 /* Data Cache set/way op type defines */ 72 #define DC_OP_ISW U(0x0) 73 #define DC_OP_CISW U(0x1) 74 #if ERRATA_A53_827319 75 #define DC_OP_CSW DC_OP_CISW 76 #else 77 #define DC_OP_CSW U(0x2) 78 #endif 79 80 /******************************************************************************* 81 * Generic timer memory mapped registers & offsets 82 ******************************************************************************/ 83 #define CNTCR_OFF U(0x000) 84 /* Counter Count Value Lower register */ 85 #define CNTCVL_OFF U(0x008) 86 /* Counter Count Value Upper register */ 87 #define CNTCVU_OFF U(0x00C) 88 #define CNTFID_OFF U(0x020) 89 90 #define CNTCR_EN (U(1) << 0) 91 #define CNTCR_HDBG (U(1) << 1) 92 #define CNTCR_FCREQ(x) ((x) << 8) 93 94 /******************************************************************************* 95 * System register bit definitions 96 ******************************************************************************/ 97 /* CLIDR definitions */ 98 #define LOUIS_SHIFT U(21) 99 #define LOC_SHIFT U(24) 100 #define CLIDR_FIELD_WIDTH U(3) 101 102 /* CSSELR definitions */ 103 #define LEVEL_SHIFT U(1) 104 105 /* ID_DFR0_EL1 definitions */ 106 #define ID_DFR0_COPTRC_SHIFT U(12) 107 #define ID_DFR0_COPTRC_MASK U(0xf) 108 #define ID_DFR0_COPTRC_SUPPORTED U(1) 109 #define ID_DFR0_COPTRC_LENGTH U(4) 110 #define ID_DFR0_TRACEFILT_SHIFT U(28) 111 #define ID_DFR0_TRACEFILT_MASK U(0xf) 112 #define ID_DFR0_TRACEFILT_SUPPORTED U(1) 113 #define ID_DFR0_TRACEFILT_LENGTH U(4) 114 115 /* ID_DFR1_EL1 definitions */ 116 #define ID_DFR1_MTPMU_SHIFT U(0) 117 #define ID_DFR1_MTPMU_MASK U(0xf) 118 #define ID_DFR1_MTPMU_SUPPORTED U(1) 119 120 /* ID_MMFR4 definitions */ 121 #define ID_MMFR4_CNP_SHIFT U(12) 122 #define ID_MMFR4_CNP_LENGTH U(4) 123 #define ID_MMFR4_CNP_MASK U(0xf) 124 125 #define ID_MMFR4_CCIDX_SHIFT U(24) 126 #define ID_MMFR4_CCIDX_LENGTH U(4) 127 #define ID_MMFR4_CCIDX_MASK U(0xf) 128 129 /* ID_PFR0 definitions */ 130 #define ID_PFR0_AMU_SHIFT U(20) 131 #define ID_PFR0_AMU_LENGTH U(4) 132 #define ID_PFR0_AMU_MASK U(0xf) 133 #define ID_PFR0_AMU_NOT_SUPPORTED U(0x0) 134 #define ID_PFR0_AMU_V1 U(0x1) 135 #define ID_PFR0_AMU_V1P1 U(0x2) 136 137 #define ID_PFR0_DIT_SHIFT U(24) 138 #define ID_PFR0_DIT_LENGTH U(4) 139 #define ID_PFR0_DIT_MASK U(0xf) 140 #define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT) 141 142 /* ID_PFR1 definitions */ 143 #define ID_PFR1_VIRTEXT_SHIFT U(12) 144 #define ID_PFR1_VIRTEXT_MASK U(0xf) 145 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 146 & ID_PFR1_VIRTEXT_MASK) 147 #define ID_PFR1_GENTIMER_SHIFT U(16) 148 #define ID_PFR1_GENTIMER_MASK U(0xf) 149 #define ID_PFR1_GIC_SHIFT U(28) 150 #define ID_PFR1_GIC_MASK U(0xf) 151 #define ID_PFR1_SEC_SHIFT U(4) 152 #define ID_PFR1_SEC_MASK U(0xf) 153 #define ID_PFR1_ELx_ENABLED U(1) 154 155 /* SCTLR definitions */ 156 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \ 157 (U(1) << 3)) 158 #if ARM_ARCH_MAJOR == 7 159 #define SCTLR_RES1 SCTLR_RES1_DEF 160 #else 161 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11)) 162 #endif 163 #define SCTLR_M_BIT (U(1) << 0) 164 #define SCTLR_A_BIT (U(1) << 1) 165 #define SCTLR_C_BIT (U(1) << 2) 166 #define SCTLR_CP15BEN_BIT (U(1) << 5) 167 #define SCTLR_ITD_BIT (U(1) << 7) 168 #define SCTLR_Z_BIT (U(1) << 11) 169 #define SCTLR_I_BIT (U(1) << 12) 170 #define SCTLR_V_BIT (U(1) << 13) 171 #define SCTLR_RR_BIT (U(1) << 14) 172 #define SCTLR_NTWI_BIT (U(1) << 16) 173 #define SCTLR_NTWE_BIT (U(1) << 18) 174 #define SCTLR_WXN_BIT (U(1) << 19) 175 #define SCTLR_UWXN_BIT (U(1) << 20) 176 #define SCTLR_EE_BIT (U(1) << 25) 177 #define SCTLR_TRE_BIT (U(1) << 28) 178 #define SCTLR_AFE_BIT (U(1) << 29) 179 #define SCTLR_TE_BIT (U(1) << 30) 180 #define SCTLR_DSSBS_BIT (U(1) << 31) 181 #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \ 182 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT) 183 184 /* SDCR definitions */ 185 #define SDCR_SPD(x) ((x) << 14) 186 #define SDCR_SPD_LEGACY U(0x0) 187 #define SDCR_SPD_DISABLE U(0x2) 188 #define SDCR_SPD_ENABLE U(0x3) 189 #define SDCR_SCCD_BIT (U(1) << 23) 190 #define SDCR_TTRF_BIT (U(1) << 19) 191 #define SDCR_SPME_BIT (U(1) << 17) 192 #define SDCR_RESET_VAL U(0x0) 193 #define SDCR_MTPME_BIT (U(1) << 28) 194 195 /* HSCTLR definitions */ 196 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 197 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 198 (U(1) << 11) | (U(1) << 4) | (U(1) << 3)) 199 200 #define HSCTLR_M_BIT (U(1) << 0) 201 #define HSCTLR_A_BIT (U(1) << 1) 202 #define HSCTLR_C_BIT (U(1) << 2) 203 #define HSCTLR_CP15BEN_BIT (U(1) << 5) 204 #define HSCTLR_ITD_BIT (U(1) << 7) 205 #define HSCTLR_SED_BIT (U(1) << 8) 206 #define HSCTLR_I_BIT (U(1) << 12) 207 #define HSCTLR_WXN_BIT (U(1) << 19) 208 #define HSCTLR_EE_BIT (U(1) << 25) 209 #define HSCTLR_TE_BIT (U(1) << 30) 210 211 /* CPACR definitions */ 212 #define CPACR_FPEN(x) ((x) << 20) 213 #define CPACR_FP_TRAP_PL0 UL(0x1) 214 #define CPACR_FP_TRAP_ALL UL(0x2) 215 #define CPACR_FP_TRAP_NONE UL(0x3) 216 217 /* SCR definitions */ 218 #define SCR_TWE_BIT (UL(1) << 13) 219 #define SCR_TWI_BIT (UL(1) << 12) 220 #define SCR_SIF_BIT (UL(1) << 9) 221 #define SCR_HCE_BIT (UL(1) << 8) 222 #define SCR_SCD_BIT (UL(1) << 7) 223 #define SCR_NET_BIT (UL(1) << 6) 224 #define SCR_AW_BIT (UL(1) << 5) 225 #define SCR_FW_BIT (UL(1) << 4) 226 #define SCR_EA_BIT (UL(1) << 3) 227 #define SCR_FIQ_BIT (UL(1) << 2) 228 #define SCR_IRQ_BIT (UL(1) << 1) 229 #define SCR_NS_BIT (UL(1) << 0) 230 #define SCR_VALID_BIT_MASK U(0x33ff) 231 #define SCR_RESET_VAL U(0x0) 232 233 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) 234 235 /* HCR definitions */ 236 #define HCR_TGE_BIT (U(1) << 27) 237 #define HCR_AMO_BIT (U(1) << 5) 238 #define HCR_IMO_BIT (U(1) << 4) 239 #define HCR_FMO_BIT (U(1) << 3) 240 #define HCR_RESET_VAL U(0x0) 241 242 /* CNTHCTL definitions */ 243 #define CNTHCTL_RESET_VAL U(0x0) 244 #define PL1PCEN_BIT (U(1) << 1) 245 #define PL1PCTEN_BIT (U(1) << 0) 246 247 /* CNTKCTL definitions */ 248 #define PL0PTEN_BIT (U(1) << 9) 249 #define PL0VTEN_BIT (U(1) << 8) 250 #define PL0PCTEN_BIT (U(1) << 0) 251 #define PL0VCTEN_BIT (U(1) << 1) 252 #define EVNTEN_BIT (U(1) << 2) 253 #define EVNTDIR_BIT (U(1) << 3) 254 #define EVNTI_SHIFT U(4) 255 #define EVNTI_MASK U(0xf) 256 257 /* HCPTR definitions */ 258 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff)) 259 #define TCPAC_BIT (U(1) << 31) 260 #define TAM_SHIFT U(30) 261 #define TAM_BIT (U(1) << TAM_SHIFT) 262 #define TTA_BIT (U(1) << 20) 263 #define TCP11_BIT (U(1) << 11) 264 #define TCP10_BIT (U(1) << 10) 265 #define HCPTR_RESET_VAL HCPTR_RES1 266 267 /* VTTBR defintions */ 268 #define VTTBR_RESET_VAL ULL(0x0) 269 #define VTTBR_VMID_MASK ULL(0xff) 270 #define VTTBR_VMID_SHIFT U(48) 271 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 272 #define VTTBR_BADDR_SHIFT U(0) 273 274 /* HDCR definitions */ 275 #define HDCR_MTPME_BIT (U(1) << 28) 276 #define HDCR_HLP_BIT (U(1) << 26) 277 #define HDCR_HPME_BIT (U(1) << 7) 278 #define HDCR_RESET_VAL U(0x0) 279 280 /* HSTR definitions */ 281 #define HSTR_RESET_VAL U(0x0) 282 283 /* CNTHP_CTL definitions */ 284 #define CNTHP_CTL_RESET_VAL U(0x0) 285 286 /* NSACR definitions */ 287 #define NSASEDIS_BIT (U(1) << 15) 288 #define NSTRCDIS_BIT (U(1) << 20) 289 #define NSACR_CP11_BIT (U(1) << 11) 290 #define NSACR_CP10_BIT (U(1) << 10) 291 #define NSACR_IMP_DEF_MASK (U(0x7) << 16) 292 #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT) 293 #define NSACR_RESET_VAL U(0x0) 294 295 /* CPACR definitions */ 296 #define ASEDIS_BIT (U(1) << 31) 297 #define TRCDIS_BIT (U(1) << 28) 298 #define CPACR_CP11_SHIFT U(22) 299 #define CPACR_CP10_SHIFT U(20) 300 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\ 301 (U(0x3) << CPACR_CP10_SHIFT)) 302 #define CPACR_RESET_VAL U(0x0) 303 304 /* FPEXC definitions */ 305 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8)) 306 #define FPEXC_EN_BIT (U(1) << 30) 307 #define FPEXC_RESET_VAL FPEXC_RES1 308 309 /* SPSR/CPSR definitions */ 310 #define SPSR_FIQ_BIT (U(1) << 0) 311 #define SPSR_IRQ_BIT (U(1) << 1) 312 #define SPSR_ABT_BIT (U(1) << 2) 313 #define SPSR_AIF_SHIFT U(6) 314 #define SPSR_AIF_MASK U(0x7) 315 316 #define SPSR_E_SHIFT U(9) 317 #define SPSR_E_MASK U(0x1) 318 #define SPSR_E_LITTLE U(0) 319 #define SPSR_E_BIG U(1) 320 321 #define SPSR_T_SHIFT U(5) 322 #define SPSR_T_MASK U(0x1) 323 #define SPSR_T_ARM U(0) 324 #define SPSR_T_THUMB U(1) 325 326 #define SPSR_MODE_SHIFT U(0) 327 #define SPSR_MODE_MASK U(0x7) 328 329 #define SPSR_SSBS_BIT BIT_32(23) 330 331 #define DISABLE_ALL_EXCEPTIONS \ 332 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) 333 334 #define CPSR_DIT_BIT (U(1) << 21) 335 /* 336 * TTBCR definitions 337 */ 338 #define TTBCR_EAE_BIT (U(1) << 31) 339 340 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28) 341 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28) 342 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28) 343 344 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26) 345 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26) 346 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26) 347 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26) 348 349 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24) 350 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24) 351 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24) 352 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24) 353 354 #define TTBCR_EPD1_BIT (U(1) << 23) 355 #define TTBCR_A1_BIT (U(1) << 22) 356 357 #define TTBCR_T1SZ_SHIFT U(16) 358 #define TTBCR_T1SZ_MASK U(0x7) 359 #define TTBCR_TxSZ_MIN U(0) 360 #define TTBCR_TxSZ_MAX U(7) 361 362 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12) 363 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 364 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 365 366 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10) 367 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10) 368 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10) 369 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10) 370 371 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8) 372 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8) 373 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8) 374 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8) 375 376 #define TTBCR_EPD0_BIT (U(1) << 7) 377 #define TTBCR_T0SZ_SHIFT U(0) 378 #define TTBCR_T0SZ_MASK U(0x7) 379 380 /* 381 * HTCR definitions 382 */ 383 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23)) 384 385 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12) 386 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12) 387 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12) 388 389 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10) 390 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10) 391 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10) 392 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10) 393 394 #define HTCR_RGN0_INNER_NC (U(0x0) << 8) 395 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8) 396 #define HTCR_RGN0_INNER_WT (U(0x2) << 8) 397 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8) 398 399 #define HTCR_T0SZ_SHIFT U(0) 400 #define HTCR_T0SZ_MASK U(0x7) 401 402 #define MODE_RW_SHIFT U(0x4) 403 #define MODE_RW_MASK U(0x1) 404 #define MODE_RW_32 U(0x1) 405 406 #define MODE32_SHIFT U(0) 407 #define MODE32_MASK U(0x1f) 408 #define MODE32_usr U(0x10) 409 #define MODE32_fiq U(0x11) 410 #define MODE32_irq U(0x12) 411 #define MODE32_svc U(0x13) 412 #define MODE32_mon U(0x16) 413 #define MODE32_abt U(0x17) 414 #define MODE32_hyp U(0x1a) 415 #define MODE32_und U(0x1b) 416 #define MODE32_sys U(0x1f) 417 418 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 419 420 #define SPSR_MODE32(mode, isa, endian, aif) \ 421 ( \ 422 ( \ 423 (MODE_RW_32 << MODE_RW_SHIFT) | \ 424 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 425 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 426 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 427 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) \ 428 ) & \ 429 (~(SPSR_SSBS_BIT)) \ 430 ) 431 432 /* 433 * TTBR definitions 434 */ 435 #define TTBR_CNP_BIT ULL(0x1) 436 437 /* 438 * CTR definitions 439 */ 440 #define CTR_CWG_SHIFT U(24) 441 #define CTR_CWG_MASK U(0xf) 442 #define CTR_ERG_SHIFT U(20) 443 #define CTR_ERG_MASK U(0xf) 444 #define CTR_DMINLINE_SHIFT U(16) 445 #define CTR_DMINLINE_WIDTH U(4) 446 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1)) 447 #define CTR_L1IP_SHIFT U(14) 448 #define CTR_L1IP_MASK U(0x3) 449 #define CTR_IMINLINE_SHIFT U(0) 450 #define CTR_IMINLINE_MASK U(0xf) 451 452 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 453 454 /* PMCR definitions */ 455 #define PMCR_N_SHIFT U(11) 456 #define PMCR_N_MASK U(0x1f) 457 #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT) 458 #define PMCR_LP_BIT (U(1) << 7) 459 #define PMCR_LC_BIT (U(1) << 6) 460 #define PMCR_DP_BIT (U(1) << 5) 461 #define PMCR_RESET_VAL U(0x0) 462 463 /******************************************************************************* 464 * Definitions of register offsets, fields and macros for CPU system 465 * instructions. 466 ******************************************************************************/ 467 468 #define TLBI_ADDR_SHIFT U(0) 469 #define TLBI_ADDR_MASK U(0xFFFFF000) 470 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 471 472 /******************************************************************************* 473 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 474 * system level implementation of the Generic Timer. 475 ******************************************************************************/ 476 #define CNTCTLBASE_CNTFRQ U(0x0) 477 #define CNTNSAR U(0x4) 478 #define CNTNSAR_NS_SHIFT(x) (x) 479 480 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 481 #define CNTACR_RPCT_SHIFT U(0x0) 482 #define CNTACR_RVCT_SHIFT U(0x1) 483 #define CNTACR_RFRQ_SHIFT U(0x2) 484 #define CNTACR_RVOFF_SHIFT U(0x3) 485 #define CNTACR_RWVT_SHIFT U(0x4) 486 #define CNTACR_RWPT_SHIFT U(0x5) 487 488 /******************************************************************************* 489 * Definitions of register offsets and fields in the CNTBaseN Frame of the 490 * system level implementation of the Generic Timer. 491 ******************************************************************************/ 492 /* Physical Count register. */ 493 #define CNTPCT_LO U(0x0) 494 /* Counter Frequency register. */ 495 #define CNTBASEN_CNTFRQ U(0x10) 496 /* Physical Timer CompareValue register. */ 497 #define CNTP_CVAL_LO U(0x20) 498 /* Physical Timer Control register. */ 499 #define CNTP_CTL U(0x2c) 500 501 /* Physical timer control register bit fields shifts and masks */ 502 #define CNTP_CTL_ENABLE_SHIFT 0 503 #define CNTP_CTL_IMASK_SHIFT 1 504 #define CNTP_CTL_ISTATUS_SHIFT 2 505 506 #define CNTP_CTL_ENABLE_MASK U(1) 507 #define CNTP_CTL_IMASK_MASK U(1) 508 #define CNTP_CTL_ISTATUS_MASK U(1) 509 510 /* MAIR macros */ 511 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) 512 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3))) 513 514 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ 515 #define SCR p15, 0, c1, c1, 0 516 #define SCTLR p15, 0, c1, c0, 0 517 #define ACTLR p15, 0, c1, c0, 1 518 #define SDCR p15, 0, c1, c3, 1 519 #define MPIDR p15, 0, c0, c0, 5 520 #define MIDR p15, 0, c0, c0, 0 521 #define HVBAR p15, 4, c12, c0, 0 522 #define VBAR p15, 0, c12, c0, 0 523 #define MVBAR p15, 0, c12, c0, 1 524 #define NSACR p15, 0, c1, c1, 2 525 #define CPACR p15, 0, c1, c0, 2 526 #define DCCIMVAC p15, 0, c7, c14, 1 527 #define DCCMVAC p15, 0, c7, c10, 1 528 #define DCIMVAC p15, 0, c7, c6, 1 529 #define DCCISW p15, 0, c7, c14, 2 530 #define DCCSW p15, 0, c7, c10, 2 531 #define DCISW p15, 0, c7, c6, 2 532 #define CTR p15, 0, c0, c0, 1 533 #define CNTFRQ p15, 0, c14, c0, 0 534 #define ID_MMFR4 p15, 0, c0, c2, 6 535 #define ID_DFR0 p15, 0, c0, c1, 2 536 #define ID_DFR1 p15, 0, c0, c3, 5 537 #define ID_PFR0 p15, 0, c0, c1, 0 538 #define ID_PFR1 p15, 0, c0, c1, 1 539 #define MAIR0 p15, 0, c10, c2, 0 540 #define MAIR1 p15, 0, c10, c2, 1 541 #define TTBCR p15, 0, c2, c0, 2 542 #define TTBR0 p15, 0, c2, c0, 0 543 #define TTBR1 p15, 0, c2, c0, 1 544 #define TLBIALL p15, 0, c8, c7, 0 545 #define TLBIALLH p15, 4, c8, c7, 0 546 #define TLBIALLIS p15, 0, c8, c3, 0 547 #define TLBIMVA p15, 0, c8, c7, 1 548 #define TLBIMVAA p15, 0, c8, c7, 3 549 #define TLBIMVAAIS p15, 0, c8, c3, 3 550 #define TLBIMVAHIS p15, 4, c8, c3, 1 551 #define BPIALLIS p15, 0, c7, c1, 6 552 #define BPIALL p15, 0, c7, c5, 6 553 #define ICIALLU p15, 0, c7, c5, 0 554 #define HSCTLR p15, 4, c1, c0, 0 555 #define HCR p15, 4, c1, c1, 0 556 #define HCPTR p15, 4, c1, c1, 2 557 #define HSTR p15, 4, c1, c1, 3 558 #define CNTHCTL p15, 4, c14, c1, 0 559 #define CNTKCTL p15, 0, c14, c1, 0 560 #define VPIDR p15, 4, c0, c0, 0 561 #define VMPIDR p15, 4, c0, c0, 5 562 #define ISR p15, 0, c12, c1, 0 563 #define CLIDR p15, 1, c0, c0, 1 564 #define CSSELR p15, 2, c0, c0, 0 565 #define CCSIDR p15, 1, c0, c0, 0 566 #define CCSIDR2 p15, 1, c0, c0, 2 567 #define HTCR p15, 4, c2, c0, 2 568 #define HMAIR0 p15, 4, c10, c2, 0 569 #define ATS1CPR p15, 0, c7, c8, 0 570 #define ATS1HR p15, 4, c7, c8, 0 571 #define DBGOSDLR p14, 0, c1, c3, 4 572 573 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 574 #define HDCR p15, 4, c1, c1, 1 575 #define PMCR p15, 0, c9, c12, 0 576 #define CNTHP_TVAL p15, 4, c14, c2, 0 577 #define CNTHP_CTL p15, 4, c14, c2, 1 578 579 /* AArch32 coproc registers for 32bit MMU descriptor support */ 580 #define PRRR p15, 0, c10, c2, 0 581 #define NMRR p15, 0, c10, c2, 1 582 #define DACR p15, 0, c3, c0, 0 583 584 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ 585 #define ICC_IAR1 p15, 0, c12, c12, 0 586 #define ICC_IAR0 p15, 0, c12, c8, 0 587 #define ICC_EOIR1 p15, 0, c12, c12, 1 588 #define ICC_EOIR0 p15, 0, c12, c8, 1 589 #define ICC_HPPIR1 p15, 0, c12, c12, 2 590 #define ICC_HPPIR0 p15, 0, c12, c8, 2 591 #define ICC_BPR1 p15, 0, c12, c12, 3 592 #define ICC_BPR0 p15, 0, c12, c8, 3 593 #define ICC_DIR p15, 0, c12, c11, 1 594 #define ICC_PMR p15, 0, c4, c6, 0 595 #define ICC_RPR p15, 0, c12, c11, 3 596 #define ICC_CTLR p15, 0, c12, c12, 4 597 #define ICC_MCTLR p15, 6, c12, c12, 4 598 #define ICC_SRE p15, 0, c12, c12, 5 599 #define ICC_HSRE p15, 4, c12, c9, 5 600 #define ICC_MSRE p15, 6, c12, c12, 5 601 #define ICC_IGRPEN0 p15, 0, c12, c12, 6 602 #define ICC_IGRPEN1 p15, 0, c12, c12, 7 603 #define ICC_MGRPEN1 p15, 6, c12, c12, 7 604 605 /* 64 bit system register defines The format is: coproc, opt1, CRm */ 606 #define TTBR0_64 p15, 0, c2 607 #define TTBR1_64 p15, 1, c2 608 #define CNTVOFF_64 p15, 4, c14 609 #define VTTBR_64 p15, 6, c2 610 #define CNTPCT_64 p15, 0, c14 611 #define HTTBR_64 p15, 4, c2 612 #define CNTHP_CVAL_64 p15, 6, c14 613 #define PAR_64 p15, 0, c7 614 615 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ 616 #define ICC_SGI1R_EL1_64 p15, 0, c12 617 #define ICC_ASGI1R_EL1_64 p15, 1, c12 618 #define ICC_SGI0R_EL1_64 p15, 2, c12 619 620 /******************************************************************************* 621 * Definitions of MAIR encodings for device and normal memory 622 ******************************************************************************/ 623 /* 624 * MAIR encodings for device memory attributes. 625 */ 626 #define MAIR_DEV_nGnRnE U(0x0) 627 #define MAIR_DEV_nGnRE U(0x4) 628 #define MAIR_DEV_nGRE U(0x8) 629 #define MAIR_DEV_GRE U(0xc) 630 631 /* 632 * MAIR encodings for normal memory attributes. 633 * 634 * Cache Policy 635 * WT: Write Through 636 * WB: Write Back 637 * NC: Non-Cacheable 638 * 639 * Transient Hint 640 * NTR: Non-Transient 641 * TR: Transient 642 * 643 * Allocation Policy 644 * RA: Read Allocate 645 * WA: Write Allocate 646 * RWA: Read and Write Allocate 647 * NA: No Allocation 648 */ 649 #define MAIR_NORM_WT_TR_WA U(0x1) 650 #define MAIR_NORM_WT_TR_RA U(0x2) 651 #define MAIR_NORM_WT_TR_RWA U(0x3) 652 #define MAIR_NORM_NC U(0x4) 653 #define MAIR_NORM_WB_TR_WA U(0x5) 654 #define MAIR_NORM_WB_TR_RA U(0x6) 655 #define MAIR_NORM_WB_TR_RWA U(0x7) 656 #define MAIR_NORM_WT_NTR_NA U(0x8) 657 #define MAIR_NORM_WT_NTR_WA U(0x9) 658 #define MAIR_NORM_WT_NTR_RA U(0xa) 659 #define MAIR_NORM_WT_NTR_RWA U(0xb) 660 #define MAIR_NORM_WB_NTR_NA U(0xc) 661 #define MAIR_NORM_WB_NTR_WA U(0xd) 662 #define MAIR_NORM_WB_NTR_RA U(0xe) 663 #define MAIR_NORM_WB_NTR_RWA U(0xf) 664 665 #define MAIR_NORM_OUTER_SHIFT U(4) 666 667 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 668 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 669 670 /* PAR fields */ 671 #define PAR_F_SHIFT U(0) 672 #define PAR_F_MASK ULL(0x1) 673 #define PAR_ADDR_SHIFT U(12) 674 #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */ 675 676 /******************************************************************************* 677 * Definitions for system register interface to AMU for FEAT_AMUv1 678 ******************************************************************************/ 679 #define AMCR p15, 0, c13, c2, 0 680 #define AMCFGR p15, 0, c13, c2, 1 681 #define AMCGCR p15, 0, c13, c2, 2 682 #define AMUSERENR p15, 0, c13, c2, 3 683 #define AMCNTENCLR0 p15, 0, c13, c2, 4 684 #define AMCNTENSET0 p15, 0, c13, c2, 5 685 #define AMCNTENCLR1 p15, 0, c13, c3, 0 686 #define AMCNTENSET1 p15, 0, c13, c3, 1 687 688 /* Activity Monitor Group 0 Event Counter Registers */ 689 #define AMEVCNTR00 p15, 0, c0 690 #define AMEVCNTR01 p15, 1, c0 691 #define AMEVCNTR02 p15, 2, c0 692 #define AMEVCNTR03 p15, 3, c0 693 694 /* Activity Monitor Group 0 Event Type Registers */ 695 #define AMEVTYPER00 p15, 0, c13, c6, 0 696 #define AMEVTYPER01 p15, 0, c13, c6, 1 697 #define AMEVTYPER02 p15, 0, c13, c6, 2 698 #define AMEVTYPER03 p15, 0, c13, c6, 3 699 700 /* Activity Monitor Group 1 Event Counter Registers */ 701 #define AMEVCNTR10 p15, 0, c4 702 #define AMEVCNTR11 p15, 1, c4 703 #define AMEVCNTR12 p15, 2, c4 704 #define AMEVCNTR13 p15, 3, c4 705 #define AMEVCNTR14 p15, 4, c4 706 #define AMEVCNTR15 p15, 5, c4 707 #define AMEVCNTR16 p15, 6, c4 708 #define AMEVCNTR17 p15, 7, c4 709 #define AMEVCNTR18 p15, 0, c5 710 #define AMEVCNTR19 p15, 1, c5 711 #define AMEVCNTR1A p15, 2, c5 712 #define AMEVCNTR1B p15, 3, c5 713 #define AMEVCNTR1C p15, 4, c5 714 #define AMEVCNTR1D p15, 5, c5 715 #define AMEVCNTR1E p15, 6, c5 716 #define AMEVCNTR1F p15, 7, c5 717 718 /* Activity Monitor Group 1 Event Type Registers */ 719 #define AMEVTYPER10 p15, 0, c13, c14, 0 720 #define AMEVTYPER11 p15, 0, c13, c14, 1 721 #define AMEVTYPER12 p15, 0, c13, c14, 2 722 #define AMEVTYPER13 p15, 0, c13, c14, 3 723 #define AMEVTYPER14 p15, 0, c13, c14, 4 724 #define AMEVTYPER15 p15, 0, c13, c14, 5 725 #define AMEVTYPER16 p15, 0, c13, c14, 6 726 #define AMEVTYPER17 p15, 0, c13, c14, 7 727 #define AMEVTYPER18 p15, 0, c13, c15, 0 728 #define AMEVTYPER19 p15, 0, c13, c15, 1 729 #define AMEVTYPER1A p15, 0, c13, c15, 2 730 #define AMEVTYPER1B p15, 0, c13, c15, 3 731 #define AMEVTYPER1C p15, 0, c13, c15, 4 732 #define AMEVTYPER1D p15, 0, c13, c15, 5 733 #define AMEVTYPER1E p15, 0, c13, c15, 6 734 #define AMEVTYPER1F p15, 0, c13, c15, 7 735 736 /* AMCNTENSET0 definitions */ 737 #define AMCNTENSET0_Pn_SHIFT U(0) 738 #define AMCNTENSET0_Pn_MASK U(0xffff) 739 740 /* AMCNTENSET1 definitions */ 741 #define AMCNTENSET1_Pn_SHIFT U(0) 742 #define AMCNTENSET1_Pn_MASK U(0xffff) 743 744 /* AMCNTENCLR0 definitions */ 745 #define AMCNTENCLR0_Pn_SHIFT U(0) 746 #define AMCNTENCLR0_Pn_MASK U(0xffff) 747 748 /* AMCNTENCLR1 definitions */ 749 #define AMCNTENCLR1_Pn_SHIFT U(0) 750 #define AMCNTENCLR1_Pn_MASK U(0xffff) 751 752 /* AMCR definitions */ 753 #define AMCR_CG1RZ_SHIFT U(17) 754 #define AMCR_CG1RZ_BIT (ULL(1) << AMCR_CG1RZ_SHIFT) 755 756 /* AMCFGR definitions */ 757 #define AMCFGR_NCG_SHIFT U(28) 758 #define AMCFGR_NCG_MASK U(0xf) 759 #define AMCFGR_N_SHIFT U(0) 760 #define AMCFGR_N_MASK U(0xff) 761 762 /* AMCGCR definitions */ 763 #define AMCGCR_CG0NC_SHIFT U(0) 764 #define AMCGCR_CG0NC_MASK U(0xff) 765 #define AMCGCR_CG1NC_SHIFT U(8) 766 #define AMCGCR_CG1NC_MASK U(0xff) 767 768 /******************************************************************************* 769 * Definitions for DynamicIQ Shared Unit registers 770 ******************************************************************************/ 771 #define CLUSTERPWRDN p15, 0, c15, c3, 6 772 773 /* CLUSTERPWRDN register definitions */ 774 #define DSU_CLUSTER_PWR_OFF 0 775 #define DSU_CLUSTER_PWR_ON 1 776 #define DSU_CLUSTER_PWR_MASK U(1) 777 778 #endif /* ARCH_H */ 779
