1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 19 #ifndef B91_BT_BUFFER_H_ 20 #define B91_BT_BUFFER_H_ 21 22 /********************* ACL connection LinkLayer TX & RX data FIFO allocation, Begin *******************************/ 23 #define ACL_CONN_MAX_RX_OCTETS 251 24 #define ACL_SLAVE_MAX_TX_OCTETS 251 25 #define ACL_MASTER_MAX_TX_OCTETS 251 26 27 /** 28 * @brief LE_ACL_Data_Packet_Length, refer to BLE SPEC "7.8.2 LE Read Buffer Size command" 29 * usage limitation: 30 * 1. only used for BLE controller project 31 * 2. must be an integer multiple of 4, such as 32,80,200... 32 * 3. must greater than maximum of ACL_SLAVE_MAX_TX_OCTETS, ACL_MASTER_MAX_TX_OCTETS 33 * 4. can not exceed 252(for maximum tx_octets when DLE used) 34 */ 35 #define LE_ACL_DATA_PACKET_LENGTH (252) 36 37 #define ACL_RX_FIFO_SIZE CAL_LL_ACL_RX_FIFO_SIZE(ACL_CONN_MAX_RX_OCTETS) 38 #define ACL_RX_FIFO_NUM 8 39 40 #define ACL_SLAVE_TX_FIFO_SIZE CAL_LL_ACL_TX_FIFO_SIZE(ACL_SLAVE_MAX_TX_OCTETS) 41 #define ACL_SLAVE_TX_FIFO_NUM 9 42 43 #define ACL_MASTER_TX_FIFO_SIZE CAL_LL_ACL_TX_FIFO_SIZE(ACL_MASTER_MAX_TX_OCTETS) 44 #define ACL_MASTER_TX_FIFO_NUM 9 45 46 extern u8 app_acl_rxfifo[]; 47 extern u8 app_acl_mstTxfifo[]; 48 extern u8 app_acl_slvTxfifo[]; 49 50 /***************************** HCI TX & RX data FIFO allocation, Begin *********************************************/ 51 #define HCI_MAX_TX_SIZE 251 52 53 #define HCI_TX_FIFO_SIZE HCI_FIFO_SIZE(HCI_MAX_TX_SIZE) 54 #define HCI_TX_FIFO_NUM 8 55 56 #define HCI_RX_FIFO_SIZE HCI_FIFO_SIZE(ACL_CONN_MAX_RX_OCTETS) 57 #define HCI_RX_FIFO_NUM 8 58 59 #define HCI_RX_ACL_FIFO_SIZE CALCULATE_HCI_ACL_DATA_FIFO_SIZE(LE_ACL_DATA_PACKET_LENGTH) 60 #define HCI_RX_ACL_FIFO_NUM 8 61 62 extern u8 app_hci_rxfifo[]; 63 extern u8 app_hci_txfifo[]; 64 extern u8 app_hci_rxAclfifo[]; 65 66 #endif /* B91_BT_BUFFER_H_ */ 67
