1 /**************************************************************************//** 2 * @file hbi_reg.h 3 * @version V1.00 4 * @brief HBI register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __HBI_REG_H__ 10 #define __HBI_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup Hyper Bus Interface Controller (HBI) 23 Memory Mapped Structure for HBI Controller 24 @{ */ 25 typedef struct 26 { 27 28 29 /** 30 * @var HBI_T::CMD 31 * Offset: 0x00 HyperBus Command and Status Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[3:0] |HYPCMD |HyperBus Command and Status 36 * | | |Write 37 * | | |0001 = Reset HyperRAM. 38 * | | |0010 = Read HyperRAM regsiter (16-Bit, Read Data[15:0]. 39 * | | |0101 = Exit From Hybrid Sleep and deep power down. 40 * | | |0111 = Write HyperRAM regsiter (16-Bit, Write Data[15:0]. 41 * | | |1000 = Read 1 word (Read Data[15:0]) from HyperRAM. 42 * | | |1001 = Read 2 word (Read Data[31:0]) from HyperRAM. 43 * | | |1100 = Write 1 Byte (Write Data[7:0]) to HyperRAM. 44 * | | |1101 = Write 2 Bytes (Write Data[15:0]) to HyperRAM. 45 * | | |1110 = Write 3 Byte (Write Data[23:0]) to HyperRAM. 46 * | | |1111 = Write 4 Byte (Write Data[31:0]) to HyperRAM. 47 * | | |Other value = reserved. 48 * | | |Read 49 * | | |0000 = HyperBus interface is Idle. 50 * | | |Other value = HyperBus interface is busy. 51 * | | |Note: When an operation is Done, the read value automatically return to 4'b0000. 52 * @var HBI_T::CONFIG 53 * Offset: 0x04 HyperBus Configuration Register 54 * --------------------------------------------------------------------------------------------------- 55 * |Bits |Field |Descriptions 56 * | :----: | :----: | :---- | 57 * |[1:0] |CSST |Chip Select Setup Time to Next CK Rising Edge 58 * | | |This field indicates the setup time between the chip select and the next CK rising edge 59 * | | |00 = 1.5 HCLK cycles. 60 * | | |01 = 2.5 HCLK cycles. 61 * | | |10 = 3.5 HCLK cycles. 62 * | | |11 = 4.5 HCLK cycles. 63 * |[5:2] |ACCT |Initial Access Time 64 * | | |This field indicates the initial access cycles of the Hyper Bus transaction 65 * | | |0000 = 5 CK cycles. 66 * | | |0001 = 6 CK cycles. 67 * | | |0010 = 7 CK cycles. 68 * | | |1110 = 3 CK cycles. 69 * | | |1111 = 4 CK cycles. 70 * | | |Others = Reserved. 71 * | | |Note: This field must be set to the same value as 72 * | | |initial Latency in HyperRAM Configuration Register 0. 73 * |[7:6] |CSH |Chip Select Hold Time After CK Falling Edge 74 * | | |This field indicates the hold time between the last CK falling edge and chip select 75 * | | |00 = 0.5 HCLK cycles. 76 * | | |01 = 1.5 HCLK cycles. 77 * | | |10 = 2.5 HCLK cycles. 78 * | | |11 = 3.5 HCLK cycles. 79 * |[11:8] |CSHI |Chip Select High between Transaction 80 * | | |This field indicates the inactive period between two Hyper Bus transactions 81 * | | |0000 = 1 HCLK cycle. 82 * | | |0001 = 2 HCLK cycles. 83 * | | |0010 = 3 HCLK cycles. 84 * | | |0011 = 4 HCLK cycles. 85 * | | |... 86 * | | |1111 = 16 HCLK cycles. 87 * | | |Note : This field must meet the HyperRAM device specification of tCSHI. 88 * |[13:12] |BGSIZE |Burst Group Size 89 * | | |This field indicates the burst length on the Hyper Bus transaction 90 * | | |00 = 128 Bytes. 91 * | | |01 = 64 Bytes. 92 * | | |10 = 16 Bytes. 93 * | | |11 = 32 Bytes. 94 * | | |Note : This field must be set to the same value as Burst Length? in HyperRAM Configuration Regsiter 0. 95 * |[14] |ENDIAN |Endian Condition on the Hyper Bus Data Pipe 96 * | | |0 = Little-Endian. 97 * | | | Byte A = Bits[7:0] of a 16-Bit ..........word 98 * | | | Byte B = Bits[15:8] of a 16-Bit ..........word 99 * | | |1 = Big-Endia. 100 * | | | Byte A = Bits[15:8] of a 16-Bit ..........word 101 * | | | Byte B = Bits[7:0] of a 16-Bit ..........word 102 * |[15] |CKDIV |Hyper Bus Clock Divider 103 * | | | 0 = Hyper Bus Clock rate is HCLK/2. 104 * | | | 1 = Hyper Bus Clock rate is HCLK/4. 105 * |[26:16] |CSMAXLT |Chip Select Maximum Low Time 106 * | | | This field indicates the maximum Low period of the chip select (CS#) in one transaction 107 * | | | 00000000000 = 1 HCLK cycle. 108 * | | | 00000000001 = 2 HCLK cycles. 109 * | | | 00000000010 = 3 HCLK cycles. 110 * | | | 00000000011 = 4 HCLK cycles. 111 * | | | ... 112 * | | | 01011101100 = 749 HCLK cycles (3.9us @192 MHz). 113 * | | | ... 114 * | | | 11111111110 = 2047 HCLK cycles. 115 * | | | 11111111111 = 2048 HCLK cycles. 116 * | | | Note: This field inidcates the timing of HyperRAM Chip Select specification so that it has to relative the frequency of HCLK and the CLKDIV (HBI_CONFIG[15]). 117 * @var HBI_T::ADR 118 * Offset: 0x08 HyperBus Byte Address access Register 119 * --------------------------------------------------------------------------------------------------- 120 * |Bits |Field |Descriptions 121 * | :----: | :----: | :---- | 122 * |[31:0] |HBI_ADR |HyperBus Byte Address 123 * | | |Memory Space Range: 124 * | | | 0x0000_0000 ~ 0x01FF_FFFF 125 * | | |Register Space Range: 126 * | | | 0X0000_0000 = Identification Register 0 127 * | | | 0X0000_0002 = Identification Register 1 128 * | | | 0X0000_1000 = Configuration Register 0 129 * | | | 0X0000_1002 = Configuration Register 1 130 * | | |Note: 131 * | | |1. It is "Byte" address, not "word" address 132 * | | |2. Up to 32M Bytes of memory space is supported. 133 * @var HBI_T::WDATA 134 * Offset: 0x0C HyperBus 32-Bits Write Data Register 135 * --------------------------------------------------------------------------------------------------- 136 * |Bits |Field |Descriptions 137 * | :----: | :----: | :---- | 138 * |[31:0] |WDATA |HyperBus 32-Bits Write Data 139 * | | |To write 1 Byte to HyperRAM, Byte 0 (Data[7:0]) is used 140 * | | |To write 2 Bytes to HyperRAM, Byte 1~0 (Data[15:0]) is used 141 * | | |To write 3 Bytes to HyperRAM, Byte 2~0 (Data[23:0]) is used 142 * | | |To write 4 Bytes to HyperRAM, Byte 3~ (Data[31:0]) is used 143 * @var HBI_T::RDATA 144 * Offset: 0x10 HyperBus 32-Bits Read Data Register 145 * --------------------------------------------------------------------------------------------------- 146 * |Bits |Field |Descriptions 147 * | :----: | :----: | :---- | 148 * |[31:0] |RDATA |HyperBus 32-Bits Read Data 149 * | | |32-Bits Data for HyperBus Read 150 * | | |Note: The data order is depened on the ENDIAN (HBI_CONFIG[14]). Refer to 1.1.5.4 for detail information. 151 * @var HBI_T::INTEN 152 * Offset: 0x14 HyperBus Interrupt Enable Register 153 * --------------------------------------------------------------------------------------------------- 154 * |Bits |Field |Descriptions 155 * | :----: | :----: | :---- | 156 * |[0] |OPINTEN |HyperBus Operation Done Interrupt Enable 157 * | | |0 = Operation done interrupt is Disab led. 158 * | | |1 = Operation done interrupt is Enabled. 159 * @var HBI_T::INTSTS 160 * Offset: 0x18 HyperBus Interrupt Status Register 161 * --------------------------------------------------------------------------------------------------- 162 * |Bits |Field |Descriptions 163 * | :----: | :----: | :---- | 164 * |[0] |OPDONE |HyperBus Operation Done Interrupt 165 * | | |0 = HyperBus operation is busy. 166 * | | |1 = HyperBus operation is done. 167 */ 168 __IO uint32_t CMD ; /*!< [0x0000] HyperBus Command and Status Register */ 169 __IO uint32_t CONFIG; /*!< [0x0004] HyperBus Configuration Register */ 170 __IO uint32_t ADR; /*!< [0x0008] HyperBus Byte Address access Register */ 171 __IO uint32_t WDATA; /*!< [0x000C] HyperBus 32-Bits Write Data Register */ 172 __IO uint32_t RDATA; /*!< [0x0010] HyperBus 32-Bits Read Data Register */ 173 __IO uint32_t INTEN; /*!< [0x0014] HyperBus Interrupt Enable Register */ 174 __IO uint32_t INTSTS; /*!< [0x0018] HyperBus Interrupt Status Register */ 175 } HBI_T; 176 177 /** 178 @addtogroup HBI_CONST HBI Bit Field Definition 179 Constant Definitions for HBI Controller 180 @{ */ 181 182 #define HBI_CMD_HYPCMD_Pos (0) /*!< HBI_T::CMD: HYPCMD Position */ 183 #define HBI_CMD_HYPCMD_Msk (0xful << HBI_CMD_HYPCMD_Pos) /*!< HBI_T::CMD: HYPCMD Mask */ 184 185 #define HBI_CONFIG_CSST_Pos (0) /*!< HBI_T::CONFIG: CSST Position */ 186 #define HBI_CONFIG_CSST_Msk (0x3ul << HBI_CONFIG_CSST_Pos) /*!< HBI_T::CONFIG: CSST Mask */ 187 188 #define HBI_CONFIG_ACCT_Pos (2) /*!< HBI_T::CONFIG: ACCT Position */ 189 #define HBI_CONFIG_ACCT_Msk (0xful << HBI_CONFIG_ACCT_Pos) /*!< HBI_T::CONFIG: ACCT Mask */ 190 191 #define HBI_CONFIG_CSH_Pos (6) /*!< HBI_T::CONFIG: CSH Position */ 192 #define HBI_CONFIG_CSH_Msk (0x3ul << HBI_CONFIG_CSH_Pos) /*!< HBI_T::CONFIG: CSH Mask */ 193 194 #define HBI_CONFIG_CSHI_Pos (8) /*!< HBI_T::CONFIG: CSHI Position */ 195 #define HBI_CONFIG_CSHI_Msk (0xful << HBI_CONFIG_CSHI_Pos) /*!< HBI_T::CONFIG: CSHI Mask */ 196 197 #define HBI_CONFIG_BGSIZE_Pos (12) /*!< HBI_T::CONFIG: BGSIZE Position */ 198 #define HBI_CONFIG_BGSIZE_Msk (0x3ul << HBI_CONFIG_BGSIZE_Pos) /*!< HBI_T::CONFIG: BGSIZE Mask */ 199 200 #define HBI_CONFIG_ENDIAN_Pos (14) /*!< HBI_T::CONFIG: ENDIAN Position */ 201 #define HBI_CONFIG_ENDIAN_Msk (0x1ul << HBI_CONFIG_ENDIAN_Pos) /*!< HBI_T::CONFIG: ENDIAN Mask */ 202 203 #define HBI_CONFIG_CKDIV_Pos (15) /*!< HBI_T::CONFIG: CKDIV Position */ 204 #define HBI_CONFIG_CKDIV_Msk (0x1ul << HBI_CONFIG_CKDIV_Pos) /*!< HBI_T::CONFIG: CKDIV Mask */ 205 206 #define HBI_CONFIG_CSMAXLT_Pos (16) /*!< HBI_T::CONFIG: CSMAXLT Position */ 207 #define HBI_CONFIG_CSMAXLT_Msk (0x7fful << HBI_CONFIG_CSMAXLT_Pos) /*!< HBI_T::CONFIG: CSMAXLT Mask */ 208 209 #define HBI_ADR_ADR_Pos (0) /*!< HBI_T::ADR: ADR Position */ 210 #define HBI_ADR_ADR_Msk (0xfffffffful << HBI_ADR_ADR_Pos) /*!< HBI_T::ADR: ADR Mask */ 211 212 #define HBI_WDATA_WDATA_Pos (0) /*!< HBI_T::WDATA: WDATA Position */ 213 #define HBI_WDATA_WDATA_Msk (0xfffffffful << HBI_WDATA_WDATA_Pos) /*!< HBI_T::WDATA: WDATA Mask */ 214 215 #define HBI_RDATA_RDATA_Pos (0) /*!< HBI_T::RDATA: RDATA Position */ 216 #define HBI_RDATA_RDATA_Msk (0xfffffffful << HBI_RDATA_RDATA_Pos) /*!< HBI_T::RDATA: RDATA Mask */ 217 218 #define HBI_INTEN_OPINTEN_Pos (0) /*!< HBI_T::INTEN: OPINTEN Position */ 219 #define HBI_INTEN_OPINTEN_Msk (0x1ul << HBI_INTEN_OPINTEN_Pos) /*!< HBI_T::INTEN: OPINTEN Mask */ 220 221 #define HBI_INTSTS_OPDONE_Pos (0) /*!< HBI_T::INTSTS: OPDONE Position */ 222 #define HBI_INTSTS_OPDONE_Msk (0x1ul << HBI_INTSTS_OPDONE_Pos) /*!< HBI_T::INTSTS: OPDONE Mask */ 223 224 225 /**@}*/ /* HBI_CONST */ 226 /**@}*/ /* end of HBI register group */ 227 /**@}*/ /* end of REGISTER group */ 228 229 #if defined ( __CC_ARM ) 230 #pragma no_anon_unions 231 #endif 232 233 #endif /* __HBI_REG_H__ */ 234
