1 /** 2 ****************************************************************************** 3 * @file stm32f3xx_hal_sdadc.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the SDADC 6 * firmware library. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2016 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software is licensed under terms that can be found in the LICENSE file 14 * in the root directory of this software component. 15 * If no LICENSE file comes with this software, it is provided AS-IS. 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32F3xx_SDADC_H 22 #define __STM32F3xx_SDADC_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #if defined(SDADC1) || defined(SDAD2) || defined(SDADC3) 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "stm32f3xx_hal_def.h" 32 33 /** @addtogroup STM32F3xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup SDADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup SDADC_Exported_Types SDADC Exported Types 43 * @{ 44 */ 45 46 47 /** 48 * @brief HAL SDADC States definition 49 */ 50 typedef enum 51 { 52 HAL_SDADC_STATE_RESET = 0x00U, /*!< SDADC not initialized */ 53 HAL_SDADC_STATE_READY = 0x01U, /*!< SDADC initialized and ready for use */ 54 HAL_SDADC_STATE_CALIB = 0x02U, /*!< SDADC calibration in progress */ 55 HAL_SDADC_STATE_REG = 0x03U, /*!< SDADC regular conversion in progress */ 56 HAL_SDADC_STATE_INJ = 0x04U, /*!< SDADC injected conversion in progress */ 57 HAL_SDADC_STATE_REG_INJ = 0x05U, /*!< SDADC regular and injected conversions in progress */ 58 HAL_SDADC_STATE_ERROR = 0xFFU, /*!< SDADC state error */ 59 }HAL_SDADC_StateTypeDef; 60 61 /** 62 * @brief SDADC Init Structure definition 63 */ 64 typedef struct 65 { 66 uint32_t IdleLowPowerMode; /*!< Specifies if SDADC can enter in power down or standby when idle. 67 This parameter can be a value of @ref SDADC_Idle_Low_Power_Mode */ 68 uint32_t FastConversionMode; /*!< Specifies if Fast conversion mode is enabled or not. 69 This parameter can be a value of @ref SDADC_Fast_Conv_Mode */ 70 uint32_t SlowClockMode; /*!< Specifies if slow clock mode is enabled or not. 71 This parameter can be a value of @ref SDADC_Slow_Clock_Mode */ 72 uint32_t ReferenceVoltage; /*!< Specifies the reference voltage. 73 Note: This parameter is common to all SDADC instances. 74 This parameter can be a value of @ref SDADC_Reference_Voltage */ 75 }SDADC_InitTypeDef; 76 77 /** 78 * @brief SDADC handle Structure definition 79 */ 80 typedef struct __SDADC_HandleTypeDef 81 { 82 SDADC_TypeDef *Instance; /*!< SDADC registers base address */ 83 SDADC_InitTypeDef Init; /*!< SDADC init parameters */ 84 DMA_HandleTypeDef *hdma; /*!< SDADC DMA Handle parameters */ 85 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 86 uint32_t InjectedContMode; /*!< Injected conversion continuous mode */ 87 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 88 uint32_t InjConvRemaining; /*!< Injected conversion remaining */ 89 uint32_t RegularTrigger; /*!< Current trigger used for regular conversion */ 90 uint32_t InjectedTrigger; /*!< Current trigger used for injected conversion */ 91 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 92 uint32_t RegularMultimode; /*!< current type of regular multimode */ 93 uint32_t InjectedMultimode; /*!< Current type of injected multimode */ 94 HAL_SDADC_StateTypeDef State; /*!< SDADC state */ 95 uint32_t ErrorCode; /*!< SDADC Error code */ 96 #if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1) 97 void (* ConvHalfCpltCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC half regular conversion complete callback */ 98 void (* ConvCpltCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC regular conversion complete callback */ 99 void (* InjectedConvHalfCpltCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC half injected conversion complete callback */ 100 void (* InjectedConvCpltCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC injected conversion complete callback */ 101 void (* CalibrationCpltCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC calibration callback */ 102 void (* ErrorCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC error callback */ 103 void (* MspInitCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC Msp Init callback */ 104 void (* MspDeInitCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC Msp DeInit callback */ 105 #endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */ 106 }SDADC_HandleTypeDef; 107 108 /** 109 * @brief SDADC Configuration Register Parameter Structure 110 */ 111 typedef struct 112 { 113 uint32_t InputMode; /*!< Specifies the input mode (single ended, differential...) 114 This parameter can be any value of @ref SDADC_InputMode */ 115 uint32_t Gain; /*!< Specifies the gain setting. 116 This parameter can be any value of @ref SDADC_Gain */ 117 uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2U). 118 This parameter can be any value of @ref SDADC_CommonMode */ 119 uint32_t Offset; /*!< Specifies the 12-bit offset value. 120 This parameter can be any value lower or equal to 0x00000FFFU */ 121 }SDADC_ConfParamTypeDef; 122 123 #if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1) 124 /** 125 * @brief HAL SDADC Callback ID enumeration definition 126 */ 127 typedef enum 128 { 129 HAL_SDADC_CONVERSION_HALF_CB_ID = 0x00U, /*!< SDADC half regular conversion complete callback ID */ 130 HAL_SDADC_CONVERSION_COMPLETE_CB_ID = 0x01U, /*!< SDADC regular conversion complete callback ID */ 131 HAL_SDADC_INJ_CONVERSION_HALF_CB_ID = 0x02U, /*!< SDADC half injected conversion complete callback ID */ 132 HAL_SDADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x03U, /*!< SDADC injected conversion complete callback ID */ 133 HAL_SDADC_CALIBRATION_COMPLETE_CB_ID = 0x04U, /*!< SDADC calibration callback ID */ 134 HAL_SDADC_ERROR_CB_ID = 0x05U, /*!< SDADC error callback ID */ 135 HAL_SDADC_MSPINIT_CB_ID = 0x06U, /*!< SDADC Msp Init callback ID */ 136 HAL_SDADC_MSPDEINIT_CB_ID = 0x07U /*!< SDADC Msp DeInit callback ID */ 137 } HAL_SDADC_CallbackIDTypeDef; 138 139 /** 140 * @brief HAL SDADC Callback pointer definition 141 */ 142 typedef void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< pointer to a SDADC callback function */ 143 144 #endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */ 145 146 /** 147 * @} 148 */ 149 150 /* Exported constants --------------------------------------------------------*/ 151 152 /** @defgroup SDADC_Exported_Constants SDADC Exported Constants 153 * @{ 154 */ 155 156 /** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode 157 * @{ 158 */ 159 #define SDADC_LOWPOWER_NONE (0x00000000UL) 160 #define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI 161 #define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI 162 /** 163 * @} 164 */ 165 166 /** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode 167 * @{ 168 */ 169 #define SDADC_FAST_CONV_DISABLE (0x00000000UL) 170 #define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST 171 /** 172 * @} 173 */ 174 175 /** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode 176 * @{ 177 */ 178 #define SDADC_SLOW_CLOCK_DISABLE (0x00000000UL) 179 #define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK 180 /** 181 * @} 182 */ 183 184 /** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage 185 * @{ 186 */ 187 #define SDADC_VREF_EXT (0x00000000UL) /*!< The reference voltage is forced externally using VREF pin */ 188 #define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0 /*!< The reference voltage is forced internally to 1.22V VREFINT */ 189 #define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1 /*!< The reference voltage is forced internally to 1.8V VREFINT */ 190 #define SDADC_VREF_VDDA SDADC_CR1_REFV /*!< The reference voltage is forced internally to VDDA */ 191 /** 192 * @} 193 */ 194 195 /** @defgroup SDADC_ConfIndex SDADC Configuration Index 196 * @{ 197 */ 198 199 #define SDADC_CONF_INDEX_0 (0x00000000UL) /*!< Configuration 0 Register selected */ 200 #define SDADC_CONF_INDEX_1 (0x00000001U) /*!< Configuration 1 Register selected */ 201 #define SDADC_CONF_INDEX_2 (0x00000002U) /*!< Configuration 2 Register selected */ 202 /** 203 * @} 204 */ 205 206 /** @defgroup SDADC_InputMode SDADC Input Mode 207 * @{ 208 */ 209 #define SDADC_INPUT_MODE_DIFF (0x00000000UL) /*!< Conversions are executed in differential mode */ 210 #define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0 /*!< Conversions are executed in single ended offset mode */ 211 #define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0 /*!< Conversions are executed in single ended zero-volt reference mode */ 212 /** 213 * @} 214 */ 215 216 /** @defgroup SDADC_Gain SDADC Gain 217 * @{ 218 */ 219 #define SDADC_GAIN_1 (0x00000000UL) /*!< Gain equal to 1U */ 220 #define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2U */ 221 #define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4U */ 222 #define SDADC_GAIN_8 (0x00300000U) /*!< Gain equal to 8U */ 223 #define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16U */ 224 #define SDADC_GAIN_32 (0x00500000U) /*!< Gain equal to 32U */ 225 #define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1U/2U */ 226 /** 227 * @} 228 */ 229 230 /** @defgroup SDADC_CommonMode SDADC Common Mode 231 * @{ 232 */ 233 #define SDADC_COMMON_MODE_VSSA (0x00000000UL) /*!< Select SDADC VSSA as common mode */ 234 #define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */ 235 #define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */ 236 /** 237 * @} 238 */ 239 240 241 242 /** @defgroup SDADC_Channel_Selection SDADC Channel Selection 243 * @{ 244 */ 245 246 /* SDADC Channels ------------------------------------------------------------*/ 247 /* The SDADC channels are defined as follows: 248 - in 16-bit LSB the channel mask is set 249 - in 16-bit MSB the channel number is set 250 e.g. for channel 5 definition: 251 - the channel mask is 0x00000020 (bit 5 is set) 252 - the channel number 5 is 0x00050000 253 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ 254 #define SDADC_CHANNEL_0 (0x00000001UL) 255 #define SDADC_CHANNEL_1 (0x00010002UL) 256 #define SDADC_CHANNEL_2 (0x00020004UL) 257 #define SDADC_CHANNEL_3 (0x00030008UL) 258 #define SDADC_CHANNEL_4 (0x00040010UL) 259 #define SDADC_CHANNEL_5 (0x00050020UL) 260 #define SDADC_CHANNEL_6 (0x00060040UL) 261 #define SDADC_CHANNEL_7 (0x00070080UL) 262 #define SDADC_CHANNEL_8 (0x00080100UL) 263 /** 264 * @} 265 */ 266 267 /** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence 268 * @{ 269 */ 270 #define SDADC_CALIBRATION_SEQ_1 (0x00000000UL) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */ 271 #define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0 /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */ 272 #define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1 /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */ 273 /** 274 * @} 275 */ 276 277 /** @defgroup SDADC_ContinuousMode SDADC Continuous Mode 278 * @{ 279 */ 280 #define SDADC_CONTINUOUS_CONV_OFF (0x00000000UL) /*!< Conversion are not continuous */ 281 #define SDADC_CONTINUOUS_CONV_ON (0x00000001UL) /*!< Conversion are continuous */ 282 /** 283 * @} 284 */ 285 286 /** @defgroup SDADC_Trigger SDADC Trigger 287 * @{ 288 */ 289 #define SDADC_SOFTWARE_TRIGGER (0x00000000UL) /*!< Software trigger */ 290 #define SDADC_SYNCHRONOUS_TRIGGER (0x00000001UL) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */ 291 #define SDADC_EXTERNAL_TRIGGER (0x00000002UL) /*!< External trigger */ 292 /** 293 * @} 294 */ 295 296 /** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger 297 * @{ 298 */ 299 #define SDADC_EXT_TRIG_TIM13_CC1 (0x00000000UL) /*!< Trigger source for SDADC1 */ 300 #define SDADC_EXT_TRIG_TIM14_CC1 (0x00000100UL) /*!< Trigger source for SDADC1 */ 301 #define SDADC_EXT_TRIG_TIM16_CC1 (0x00000000UL) /*!< Trigger source for SDADC3 */ 302 #define SDADC_EXT_TRIG_TIM17_CC1 (0x00000000UL) /*!< Trigger source for SDADC2 */ 303 #define SDADC_EXT_TRIG_TIM12_CC1 (0x00000100UL) /*!< Trigger source for SDADC2 */ 304 #define SDADC_EXT_TRIG_TIM12_CC2 (0x00000100UL) /*!< Trigger source for SDADC3 */ 305 #define SDADC_EXT_TRIG_TIM15_CC2 (0x00000200UL) /*!< Trigger source for SDADC1 */ 306 #define SDADC_EXT_TRIG_TIM2_CC3 (0x00000200UL) /*!< Trigger source for SDADC2 */ 307 #define SDADC_EXT_TRIG_TIM2_CC4 (0x00000200UL) /*!< Trigger source for SDADC3 */ 308 #define SDADC_EXT_TRIG_TIM3_CC1 (0x00000300UL) /*!< Trigger source for SDADC1 */ 309 #define SDADC_EXT_TRIG_TIM3_CC2 (0x00000300UL) /*!< Trigger source for SDADC2 */ 310 #define SDADC_EXT_TRIG_TIM3_CC3 (0x00000300UL) /*!< Trigger source for SDADC3 */ 311 #define SDADC_EXT_TRIG_TIM4_CC1 (0x00000400UL) /*!< Trigger source for SDADC1 */ 312 #define SDADC_EXT_TRIG_TIM4_CC2 (0x00000400UL) /*!< Trigger source for SDADC2 */ 313 #define SDADC_EXT_TRIG_TIM4_CC3 (0x00000400UL) /*!< Trigger source for SDADC3 */ 314 #define SDADC_EXT_TRIG_TIM19_CC2 (0x00000500UL) /*!< Trigger source for SDADC1 */ 315 #define SDADC_EXT_TRIG_TIM19_CC3 (0x00000500UL) /*!< Trigger source for SDADC2 */ 316 #define SDADC_EXT_TRIG_TIM19_CC4 (0x00000500UL) /*!< Trigger source for SDADC3 */ 317 #define SDADC_EXT_TRIG_EXTI11 (0x00000700UL) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */ 318 #define SDADC_EXT_TRIG_EXTI15 (0x00000600UL) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */ 319 /** 320 * @} 321 */ 322 323 /** @defgroup SDADC_ExtTriggerEdge SDADC External Trigger Edge 324 * @{ 325 */ 326 #define SDADC_EXT_TRIG_RISING_EDGE SDADC_CR2_JEXTEN_0 /*!< External rising edge */ 327 #define SDADC_EXT_TRIG_FALLING_EDGE SDADC_CR2_JEXTEN_1 /*!< External falling edge */ 328 #define SDADC_EXT_TRIG_BOTH_EDGES SDADC_CR2_JEXTEN /*!< External rising and falling edges */ 329 /** 330 * @} 331 */ 332 333 /** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay 334 * @{ 335 */ 336 #define SDADC_INJECTED_DELAY_NONE (0x00000000UL) /*!< No delay on injected conversion */ 337 #define SDADC_INJECTED_DELAY SDADC_CR2_JDS /*!< Delay on injected conversion */ 338 /** 339 * @} 340 */ 341 342 /** @defgroup SDADC_MultimodeType SDADC Multimode Type 343 * @{ 344 */ 345 #define SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000UL) /*!< Get conversion values for SDADC1 and SDADC2 */ 346 #define SDADC_MULTIMODE_SDADC1_SDADC3 (0x00000001U) /*!< Get conversion values for SDADC1 and SDADC3 */ 347 /** 348 * @} 349 */ 350 351 /** @defgroup SDADC_ErrorCode SDADC Error Code 352 * @{ 353 */ 354 #define SDADC_ERROR_NONE (0x00000000UL) /*!< No error */ 355 #define SDADC_ERROR_REGULAR_OVERRUN (0x00000001UL) /*!< Overrun occurs during regular conversion */ 356 #define SDADC_ERROR_INJECTED_OVERRUN (0x00000002UL) /*!< Overrun occurs during injected conversion */ 357 #define SDADC_ERROR_DMA (0x00000003UL) /*!< DMA error occurs */ 358 #if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1) 359 #define SDADC_ERROR_INVALID_CALLBACK (0x00000004UL) /*!< Invalid Callback error */ 360 #endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */ 361 /** 362 * @} 363 */ 364 365 /** @defgroup SDADC_interrupts_definition SDADC interrupts definition 366 * @{ 367 */ 368 #define SDADC_IT_EOCAL SDADC_CR1_EOCALIE /*!< End of calibration interrupt enable */ 369 #define SDADC_IT_JEOC SDADC_CR1_JEOCIE /*!< Injected end of conversion interrupt enable */ 370 #define SDADC_IT_JOVR SDADC_CR1_JOVRIE /*!< Injected data overrun interrupt enable */ 371 #define SDADC_IT_REOC SDADC_CR1_REOCIE /*!< Regular end of conversion interrupt enable */ 372 #define SDADC_IT_ROVR SDADC_CR1_ROVRIE /*!< Regular data overrun interrupt enable */ 373 /** 374 * @} 375 */ 376 377 /** @defgroup SDADC_flags_definition SDADC flags definition 378 * @{ 379 */ 380 #define SDADC_FLAG_EOCAL SDADC_ISR_EOCALF /*!< End of calibration flag */ 381 #define SDADC_FLAG_JEOC SDADC_ISR_JEOCF /*!< End of injected conversion flag */ 382 #define SDADC_FLAG_JOVR SDADC_ISR_JOVRF /*!< Injected conversion overrun flag */ 383 #define SDADC_FLAG_REOC SDADC_ISR_REOCF /*!< End of regular conversion flag */ 384 #define SDADC_FLAG_ROVR SDADC_ISR_ROVRF /*!< Regular conversion overrun flag */ 385 /** 386 * @} 387 */ 388 389 /** 390 * @} 391 */ 392 393 /* Exported macros -----------------------------------------------------------*/ 394 /** @defgroup SDADC_Exported_Macros SDADC Exported Macros 395 * @{ 396 */ 397 398 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 399 /* final user. */ 400 401 /** @brief Enable the ADC end of conversion interrupt. 402 * @param __HANDLE__ ADC handle 403 * @param __INTERRUPT__ ADC Interrupt 404 * This parameter can be any combination of the following values: 405 * @arg SDADC_IT_EOCAL: End of calibration interrupt enable 406 * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable 407 * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable 408 * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable 409 * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable 410 * @retval None 411 */ 412 #define __HAL_SDADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 413 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 414 415 /** @brief Disable the ADC end of conversion interrupt. 416 * @param __HANDLE__ ADC handle 417 * @param __INTERRUPT__ ADC Interrupt 418 * This parameter can be any combination of the following values: 419 * @arg SDADC_IT_EOCAL: End of calibration interrupt enable 420 * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable 421 * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable 422 * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable 423 * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable 424 * @retval None 425 */ 426 #define __HAL_SDADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 427 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__))) 428 429 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 430 * @param __HANDLE__ ADC handle 431 * @param __INTERRUPT__ ADC interrupt source to check 432 * This parameter can be any combination of the following values: 433 * @arg SDADC_IT_EOCAL: End of calibration interrupt enable 434 * @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable 435 * @arg SDADC_IT_JOVR: Injected data overrun interrupt enable 436 * @arg SDADC_IT_REOC: Regular end of conversion interrupt enable 437 * @arg SDADC_IT_ROVR: Regular data overrun interrupt enable 438 * @retval State of interruption (SET or RESET) 439 */ 440 #define __HAL_SDADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 441 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) 442 443 /** @brief Get the selected ADC's flag status. 444 * @param __HANDLE__ ADC handle 445 * @param __FLAG__ ADC flag 446 * This parameter can be any combination of the following values: 447 * @arg SDADC_FLAG_EOCAL: End of calibration flag 448 * @arg SDADC_FLAG_JEOC: End of injected conversion flag 449 * @arg SDADC_FLAG_JOVR: Injected conversion overrun flag 450 * @arg SDADC_FLAG_REOC: End of regular conversion flag 451 * @arg SDADC_FLAG_ROVR: Regular conversion overrun flag 452 * @retval None 453 */ 454 #define __HAL_SDADC_GET_FLAG(__HANDLE__, __FLAG__) \ 455 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 456 457 /** @brief Clear the ADC's pending flags 458 * @param __HANDLE__ ADC handle 459 * @param __FLAG__ ADC flag 460 * This parameter can be any combination of the following values: 461 * @arg SDADC_FLAG_EOCAL: End of calibration flag 462 * @arg SDADC_FLAG_JEOC: End of injected conversion flag 463 * @arg SDADC_FLAG_JOVR: Injected conversion overrun flag 464 * @arg SDADC_FLAG_REOC: End of regular conversion flag 465 * @arg SDADC_FLAG_ROVR: Regular conversion overrun flag 466 * @retval None 467 */ 468 #define __HAL_SDADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 469 (CLEAR_BIT((__HANDLE__)->Instance->ISR, (__FLAG__))) 470 471 /** @brief Reset SDADC handle state 472 * @param __HANDLE__ SDADC handle. 473 * @retval None 474 */ 475 #if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1) 476 #define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) \ 477 do{ \ 478 (__HANDLE__)->State = HAL_SDADC_STATE_RESET; \ 479 (__HANDLE__)->MspInitCallback = NULL; \ 480 (__HANDLE__)->MspDeInitCallback = NULL; \ 481 } while(0) 482 #else 483 #define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) \ 484 ((__HANDLE__)->State = HAL_SDADC_STATE_RESET) 485 #endif 486 487 /** 488 * @} 489 */ 490 491 /* Private macros ------------------------------------------------------------*/ 492 /** @defgroup SDADC_Private_Macros SDADC Private Macros 493 * @{ 494 */ 495 496 #define IS_SDADC_LOWPOWER_MODE(LOWPOWER) (((LOWPOWER) == SDADC_LOWPOWER_NONE) || \ 497 ((LOWPOWER) == SDADC_LOWPOWER_POWERDOWN) || \ 498 ((LOWPOWER) == SDADC_LOWPOWER_STANDBY)) 499 500 #define IS_SDADC_FAST_CONV_MODE(FAST) (((FAST) == SDADC_FAST_CONV_DISABLE) || \ 501 ((FAST) == SDADC_FAST_CONV_ENABLE)) 502 503 #define IS_SDADC_SLOW_CLOCK_MODE(MODE) (((MODE) == SDADC_SLOW_CLOCK_DISABLE) || \ 504 ((MODE) == SDADC_SLOW_CLOCK_ENABLE)) 505 506 #define IS_SDADC_VREF(VREF) (((VREF) == SDADC_VREF_EXT) || \ 507 ((VREF) == SDADC_VREF_VREFINT1) || \ 508 ((VREF) == SDADC_VREF_VREFINT2) || \ 509 ((VREF) == SDADC_VREF_VDDA)) 510 511 #define IS_SDADC_CONF_INDEX(CONF) (((CONF) == SDADC_CONF_INDEX_0) || \ 512 ((CONF) == SDADC_CONF_INDEX_1) || \ 513 ((CONF) == SDADC_CONF_INDEX_2)) 514 515 #define IS_SDADC_INPUT_MODE(MODE) (((MODE) == SDADC_INPUT_MODE_DIFF) || \ 516 ((MODE) == SDADC_INPUT_MODE_SE_OFFSET) || \ 517 ((MODE) == SDADC_INPUT_MODE_SE_ZERO_REFERENCE)) 518 519 #define IS_SDADC_GAIN(GAIN) (((GAIN) == SDADC_GAIN_1) || \ 520 ((GAIN) == SDADC_GAIN_2) || \ 521 ((GAIN) == SDADC_GAIN_4) || \ 522 ((GAIN) == SDADC_GAIN_8) || \ 523 ((GAIN) == SDADC_GAIN_16) || \ 524 ((GAIN) == SDADC_GAIN_32) || \ 525 ((GAIN) == SDADC_GAIN_1_2)) 526 527 #define IS_SDADC_COMMON_MODE(MODE) (((MODE) == SDADC_COMMON_MODE_VSSA) || \ 528 ((MODE) == SDADC_COMMON_MODE_VDDA_2) || \ 529 ((MODE) == SDADC_COMMON_MODE_VDDA)) 530 531 #define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFFU) 532 533 /* Just one channel of the 9 channels can be selected for regular conversion */ 534 #define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0) || \ 535 ((CHANNEL) == SDADC_CHANNEL_1) || \ 536 ((CHANNEL) == SDADC_CHANNEL_2) || \ 537 ((CHANNEL) == SDADC_CHANNEL_3) || \ 538 ((CHANNEL) == SDADC_CHANNEL_4) || \ 539 ((CHANNEL) == SDADC_CHANNEL_5) || \ 540 ((CHANNEL) == SDADC_CHANNEL_6) || \ 541 ((CHANNEL) == SDADC_CHANNEL_7) || \ 542 ((CHANNEL) == SDADC_CHANNEL_8)) 543 544 /* Any or all of the 9 channels can be selected for injected conversion */ 545 #define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU)) 546 547 548 #define IS_SDADC_CALIB_SEQUENCE(SEQUENCE) (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1) || \ 549 ((SEQUENCE) == SDADC_CALIBRATION_SEQ_2) || \ 550 ((SEQUENCE) == SDADC_CALIBRATION_SEQ_3)) 551 552 #define IS_SDADC_CONTINUOUS_MODE(MODE) (((MODE) == SDADC_CONTINUOUS_CONV_OFF) || \ 553 ((MODE) == SDADC_CONTINUOUS_CONV_ON)) 554 555 556 #define IS_SDADC_REGULAR_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \ 557 ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER)) 558 559 #define IS_SDADC_INJECTED_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \ 560 ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER) || \ 561 ((TRIGGER) == SDADC_EXTERNAL_TRIGGER)) 562 563 564 #define IS_SDADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == SDADC_EXT_TRIG_TIM13_CC1) || \ 565 ((INJTRIG) == SDADC_EXT_TRIG_TIM14_CC1) || \ 566 ((INJTRIG) == SDADC_EXT_TRIG_TIM16_CC1) || \ 567 ((INJTRIG) == SDADC_EXT_TRIG_TIM17_CC1) || \ 568 ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC1) || \ 569 ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC2) || \ 570 ((INJTRIG) == SDADC_EXT_TRIG_TIM15_CC2) || \ 571 ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC3) || \ 572 ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC4) || \ 573 ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC1) || \ 574 ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC2) || \ 575 ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC3) || \ 576 ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC1) || \ 577 ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC2) || \ 578 ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC3) || \ 579 ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC2) || \ 580 ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC3) || \ 581 ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC4) || \ 582 ((INJTRIG) == SDADC_EXT_TRIG_EXTI11) || \ 583 ((INJTRIG) == SDADC_EXT_TRIG_EXTI15)) 584 585 #define IS_SDADC_EXT_TRIG_EDGE(TRIGGER) (((TRIGGER) == SDADC_EXT_TRIG_RISING_EDGE) || \ 586 ((TRIGGER) == SDADC_EXT_TRIG_FALLING_EDGE) || \ 587 ((TRIGGER) == SDADC_EXT_TRIG_BOTH_EDGES)) 588 589 590 #define IS_SDADC_INJECTED_DELAY(DELAY) (((DELAY) == SDADC_INJECTED_DELAY_NONE) || \ 591 ((DELAY) == SDADC_INJECTED_DELAY)) 592 593 #define IS_SDADC_MULTIMODE_TYPE(TYPE) (((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC2) || \ 594 ((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC3)) 595 /** 596 * @} 597 */ 598 599 /* Exported functions --------------------------------------------------------*/ 600 /** @addtogroup SDADC_Exported_Functions SDADC Exported Functions 601 * @{ 602 */ 603 604 /** @addtogroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions 605 * @{ 606 */ 607 608 /* Initialization and de-initialization functions *****************************/ 609 HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef *hsdadc); 610 HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef *hsdadc); 611 void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc); 612 void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc); 613 614 #if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1) 615 /* Callbacks Register/UnRegister functions ***********************************/ 616 HAL_StatusTypeDef HAL_SDADC_RegisterCallback(SDADC_HandleTypeDef *sdhadc, HAL_SDADC_CallbackIDTypeDef CallbackID, pSDADC_CallbackTypeDef pCallback); 617 HAL_StatusTypeDef HAL_SDADC_UnRegisterCallback(SDADC_HandleTypeDef *sdhadc, HAL_SDADC_CallbackIDTypeDef CallbackID); 618 #endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */ 619 620 /** 621 * @} 622 */ 623 624 /** @addtogroup SDADC_Exported_Functions_Group2 peripheral control functions 625 * @{ 626 */ 627 628 /* Peripheral Control functions ***********************************************/ 629 HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc, 630 uint32_t ConfIndex, 631 SDADC_ConfParamTypeDef* ConfParamStruct); 632 HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc, 633 uint32_t Channel, 634 uint32_t ConfIndex); 635 HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc, 636 uint32_t Channel, 637 uint32_t ContinuousMode); 638 HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc, 639 uint32_t Channel, 640 uint32_t ContinuousMode); 641 HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc, 642 uint32_t InjectedExtTrigger, 643 uint32_t ExtTriggerEdge); 644 HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc, 645 uint32_t InjectedDelay); 646 HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger); 647 HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger); 648 HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType); 649 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType); 650 651 /** 652 * @} 653 */ 654 655 /** @addtogroup SDADC_Exported_Functions_Group3 Input and Output operation functions 656 * @{ 657 */ 658 659 /* IO operation functions *****************************************************/ 660 HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence); 661 HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence); 662 663 HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc); 664 HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc); 665 HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length); 666 HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc); 667 HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc); 668 HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc); 669 670 HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc); 671 HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc); 672 HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length); 673 HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc); 674 HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc); 675 HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc); 676 677 HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length); 678 HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc); 679 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length); 680 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc); 681 682 uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc); 683 uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel); 684 uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc); 685 uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc); 686 687 void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc); 688 689 HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout); 690 HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout); 691 HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout); 692 693 void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc); 694 void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc); 695 void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc); 696 void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc); 697 void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc); 698 void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc); 699 700 /** 701 * @} 702 */ 703 704 /** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions 705 * @{ 706 */ 707 708 /* Peripheral State and Error functions ***************************************/ 709 HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc); 710 uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc); 711 712 /* Private functions ---------------------------------------------------------*/ 713 714 /** 715 * @} 716 */ 717 718 /** 719 * @} 720 */ 721 722 /** 723 * @} 724 */ 725 726 /** 727 * @} 728 */ 729 730 #endif /* SDADC1 || SDAD2 || SDADC3 */ 731 732 #ifdef __cplusplus 733 } 734 #endif 735 736 #endif /*__STM32F3xx_SDADC_H */ 737
