1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_rcc.c
4 * @author MCD Application Team
5 * @brief RCC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Reset and Clock Control (RCC) peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 *
11 ******************************************************************************
12 * @attention
13 *
14 * Copyright (c) 2019 STMicroelectronics.
15 * All rights reserved.
16 *
17 * This software is licensed under terms that can be found in the LICENSE file
18 * in the root directory of this software component.
19 * If no LICENSE file comes with this software, it is provided AS-IS.
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### RCC specific features #####
25 ==============================================================================
26 [..]
27 After reset the device is running from Internal High Speed oscillator
28 (HSI 64MHz) and all peripherals are off except
29 internal SRAM1, SRAM2, SRAM3 and PWR
30 (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses;
31 all peripherals mapped on these buses are running at HSI speed.
32 (+) The clock for all peripherals is switched off, except the SRAM
33
34 [..]
35 Once the device started from reset, the user application has to:
36 (+) Configure the clock source to be used to drive the MPU, AXI and MCU
37 (if the application needs higher frequency/performance)
38 (+) Configure the AHB and APB buses pre-scalers
39 (+) Enable the clock for the peripheral(s) to be used
40 (+) Configure the clock kernel source(s) for peripherals which clocks are not
41 derived from Bus clocks
42
43 @endverbatim
44 ******************************************************************************
45 */
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32mp1xx_hal.h"
49
50 /** @addtogroup STM32MP1xx_HAL_Driver
51 * @{
52 */
53
54 /** @defgroup RCC RCC
55 * @brief RCC HAL module driver
56 * @{
57 */
58
59 #ifdef HAL_RCC_MODULE_ENABLED
60
61 /* Private typedef -----------------------------------------------------------*/
62 /* Private define ------------------------------------------------------------*/
63 #define LSE_MASK (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_DIGBYP)
64 #define HSE_MASK (RCC_OCENSETR_HSEON | RCC_OCENSETR_HSEBYP | RCC_OCENSETR_DIGBYP)
65 /* Private macro -------------------------------------------------------------*/
66 /* Private variables ---------------------------------------------------------*/
67 /* Private function prototypes -----------------------------------------------*/
68 /** @defgroup RCC_Private_Function_Prototypes RCC Private Functions Prototypes
69 * @{
70 */
71 HAL_StatusTypeDef RCC_MPUConfig(RCC_MPUInitTypeDef *RCC_MPUInitStruct);
72 HAL_StatusTypeDef RCC_AXISSConfig(RCC_AXISSInitTypeDef *RCC_AXISSInitStruct);
73 HAL_StatusTypeDef RCC_MCUConfig(RCC_MCUInitTypeDef *MCUInitStruct);
74 /**
75 * @}
76 */
77
78 /* Exported functions ---------------------------------------------------------*/
79
80 /** @defgroup RCC_Exported_Functions RCC Exported Functions
81 * @{
82 */
83
84 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
85 * @brief Initialization and Configuration functions
86 *
87 @verbatim
88 ===============================================================================
89 ##### Initialization and de-initialization functions #####
90 ===============================================================================
91 [..]
92 This section provides functions allowing to configure the internal/external oscillators
93 (HSE, HSI, LSE,CSI, LSI) PLL, HSECSS, LSECSS and MCO and the System busses clocks (
94 MPUSS,AXISS, MCUSS, AHB[1:4], AHB[5:6], APB1, APB2, APB3, APB4 and APB5).
95
96 [..] Internal/external clock and PLL configuration
97 (#) HSI (high-speed internal), 64 MHz factory-trimmed RC used directly or through
98 the PLL as System clock source.
99
100 (#) CSI is a low-power RC oscillator which can be used directly as system clock, peripheral
101 clock, or PLL input.But even with frequency calibration, is less accurate than an
102 external crystal oscillator or ceramic resonator.
103
104 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
105 clock source.
106
107 (#) HSE (high-speed external), 4 to 48 MHz crystal oscillator used directly or
108 through the PLL as System clock source. Can be used also as RTC clock source.
109
110 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
111
112 (#) PLL , The RCC features four independent PLLs (clocked by HSI , HSE or CSI),
113 featuring three different output clocks and able to work either in integer, Fractional or
114 Spread Sprectum mode.
115 (++) PLL1, which is used to provide clock to the A7 sub-system
116 (++) PLL2, which is used to provide clock to the AXI sub-system, DDR and GPU
117 (++) PLL3, which is used to provide clock to the MCU sub-system and to generate the kernel
118 clock for peripherals.
119 (++) PLL4, which is used to generate the kernel clock for peripherals.
120
121
122 (#) HSECSS (HSE Clock security system), once enabled and if a HSE clock failure occurs
123 HSECSS will generate a system reset, and protect sensitive data of the BKPSRAM
124
125 (#) LSECSS (LSE Clock security system), once enabled and if a LSE clock failure occurs
126 (++) The clock provided to the RTC is disabled immediately by the hardware
127 (++) A failure event is generated (rcc_lsecss_fail). This event is connected to the TAMP
128 block, allowing to wake up from Standby, and allowing the protection of backup
129 registers and BKPSRAM
130 (++) An interrupt flag (LSECSSF) is activated in order to generate an interrupt to the
131 MCU or MPU if needed.
132
133 (#) MCO1 (micro controller clock output), used to output HSI, HSE, CSI,LSI or LSE clock
134 (through a configurable pre-scaler).
135
136 (#) MCO2 (micro controller clock output), used to output MPUSS, AXISS, MCUSS, PLL4(PLL4_P),
137 HSE, or HSI clock (through a configurable pre-scaler).
138
139
140 [..] Sub-system clock configuration
141
142 (#) The MPUDIV divider located into RCC MPU Clock Divider Register (RCC_MPCKDIVR) can be used
143 to adjust dynamically the clock for the MPU.
144
145 (#) The AXIDIV divider located into RCC AXI Clock Divider Register (RCC_AXIDIVR) can be used
146 to adjust dynamically the clock for the AXI matrix. The value of this divider also impacts
147 the clock frequency of AHB5, AHB6, APB4 and APB5.
148
149 (#) The APB4DIV divider located into RCC APB4 Clock Divider Register (RCC_APB4DIVR) can be used
150 to adjust dynamically the clock for the APB4 bridge.
151
152 (#) In the same way, the APB5DIV divider located into RCC APB5 Clock Divider Register
153 (RCC_APB5DIVR), can be used to adjust dynamically the clock for the APB5 bridge.
154
155 (#) In the MCU clock tree, the MCUDIV divider located into RCC MCU Clock Divider Register
156 (RCC_MCUDIVR), can be used to adjust dynamically the clock for the MCU. The value of
157 this divider also impacts the clock frequency of AHB bridges, APB1, APB2 and APB3.
158
159 (#) The APB1DIV divider located into RCC APB1 Clock Divider Register (RCC_APB1DIVR), can be used
160 to adjust dynamically the clock for the APB1 bridge. Similar implementation is available for
161 APB2 and APB3.
162
163 @endverbatim
164 * @{
165 */
166
167 /**
168 * @brief Resets the RCC clock configuration to the default reset state.
169 * @note The default reset state of the clock configuration is given below:
170 * - HSI ON and used as system clock source
171 * - HSE, PLL1, PLL2 and PLL3 and PLL4 OFF
172 * - AHB, APB Bus pre-scaler set to 1.
173 * - MCO1 and MCO2 OFF
174 * - All interrupts disabled (except Wake-up from CSTOP Interrupt Enable)
175 * @note This function doesn't modify the configuration of the
176 * - Peripheral clocks
177 * - LSI, LSE and RTC clock
178 * - HSECSS and LSECSS
179 * @retval None
180 */
HAL_RCC_DeInit(void)181 HAL_StatusTypeDef HAL_RCC_DeInit(void)
182 {
183 uint32_t tickstart;
184
185 /* Set HSION bit to enable HSI oscillator */
186 SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSION);
187
188 /* Get Start Tick*/
189 tickstart = HAL_GetTick();
190
191 /* Wait till HSI is ready */
192 while ((RCC->OCRDYR & RCC_OCRDYR_HSIRDY) == 0U)
193 {
194 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
195 {
196 return HAL_TIMEOUT;
197 }
198 }
199
200 /* Reset MCO1 Configuration Register */
201 CLEAR_REG(RCC->MCO1CFGR);
202
203 /* Reset MCO2 Configuration Register */
204 CLEAR_REG(RCC->MCO2CFGR);
205
206 /* Reset MPU Clock Selection Register */
207 MODIFY_REG(RCC->MPCKSELR, (RCC_MPCKSELR_MPUSRC), 0U);
208
209 /* Reset AXI Sub-System Clock Selection Register */
210 MODIFY_REG(RCC->ASSCKSELR, (RCC_ASSCKSELR_AXISSRC), 0U);
211
212 /* Reset MCU Sub-System Clock Selection Register */
213 MODIFY_REG(RCC->MSSCKSELR, (RCC_MSSCKSELR_MCUSSRC), 0U);
214
215 /* Reset RCC MPU Clock Divider Register */
216 MODIFY_REG(RCC->MPCKDIVR, (RCC_MPCKDIVR_MPUDIV), RCC_MPCKDIVR_MPUDIV_0);
217
218 /* Reset RCC AXI Clock Divider Register */
219 MODIFY_REG(RCC->AXIDIVR, (RCC_AXIDIVR_AXIDIV), 0U);
220
221 /* Reset RCC APB4 Clock Divider Register */
222 MODIFY_REG(RCC->APB4DIVR, (RCC_APB4DIVR_APB4DIV), 0U);
223
224 /* Reset RCC APB5 Clock Divider Register */
225 MODIFY_REG(RCC->APB5DIVR, (RCC_APB5DIVR_APB5DIV), 0U);
226
227 /* Reset RCC MCU Clock Divider Register */
228 MODIFY_REG(RCC->MCUDIVR, (RCC_MCUDIVR_MCUDIV), 0U);
229
230 /* Reset RCC APB1 Clock Divider Register */
231 MODIFY_REG(RCC->APB1DIVR, (RCC_APB1DIVR_APB1DIV), 0U);
232
233 /* Reset RCC APB2 Clock Divider Register */
234 MODIFY_REG(RCC->APB2DIVR, (RCC_APB2DIVR_APB2DIV), 0U);
235
236 /* Reset RCC APB3 Clock Divider Register */
237 MODIFY_REG(RCC->APB3DIVR, (RCC_APB3DIVR_APB3DIV), 0U);
238
239 /* Disable PLL1 outputs */
240 CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN | RCC_PLL1CR_DIVQEN |
241 RCC_PLL1CR_DIVREN);
242
243 /* Get Start Tick*/
244 tickstart = HAL_GetTick();
245
246 /* Disable PLL1 */
247 CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_PLLON);
248
249 /* Wait till PLL is disabled */
250 while ((RCC->PLL1CR & RCC_PLL1CR_PLL1RDY) != 0U)
251 {
252 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
253 {
254 return HAL_TIMEOUT;
255 }
256 }
257
258 /* Clear remaining SSCG_CTRL bit */
259 CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_SSCG_CTRL);
260
261 /* Disable PLL2 outputs */
262 CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_DIVPEN | RCC_PLL2CR_DIVQEN |
263 RCC_PLL2CR_DIVREN);
264
265 /* Get Start Tick*/
266 tickstart = HAL_GetTick();
267
268 /* Disable PLL2 */
269 CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_PLLON);
270
271 /* Wait till PLL is disabled */
272 while ((RCC->PLL2CR & RCC_PLL2CR_PLL2RDY) != 0U)
273 {
274 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
275 {
276 return HAL_TIMEOUT;
277 }
278 }
279
280 /* Clear remaining SSCG_CTRL bit */
281 CLEAR_BIT(RCC->PLL2CR, RCC_PLL2CR_SSCG_CTRL);
282
283 /* Disable PLL3 outputs */
284 CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_DIVPEN | RCC_PLL3CR_DIVQEN |
285 RCC_PLL3CR_DIVREN);
286
287 /* Get Start Tick*/
288 tickstart = HAL_GetTick();
289
290 /* Disable PLL3 */
291 CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_PLLON);
292
293 /* Wait till PLL is disabled */
294 while ((RCC->PLL3CR & RCC_PLL3CR_PLL3RDY) != 0U)
295 {
296 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
297 {
298 return HAL_TIMEOUT;
299 }
300 }
301
302 /* Clear remaining SSCG_CTRL bit */
303 CLEAR_BIT(RCC->PLL3CR, RCC_PLL3CR_SSCG_CTRL);
304
305 /* Disable PLL4 outputs */
306 CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_DIVPEN | RCC_PLL4CR_DIVQEN |
307 RCC_PLL4CR_DIVREN);
308
309 /* Get Start Tick*/
310 tickstart = HAL_GetTick();
311
312 /* Disable PLL4 */
313 CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_PLLON);
314
315 /* Wait till PLL is disabled */
316 while ((RCC->PLL4CR & RCC_PLL4CR_PLL4RDY) != 0U)
317 {
318 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
319 {
320 return HAL_TIMEOUT;
321 }
322 }
323
324 /* Clear remaining SSCG_CTRL bit */
325 CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL);
326
327 /* Reset PLL 1 and 2 Ref. Clock Selection Register */
328 MODIFY_REG(RCC->RCK12SELR, (RCC_RCK12SELR_PLL12SRC), 0U);
329
330 /* Reset RCC PLL 3 Ref. Clock Selection Register */
331 MODIFY_REG(RCC->RCK3SELR, (RCC_RCK3SELR_PLL3SRC), 0U);
332
333 /* Reset PLL4 Ref. Clock Selection Register */
334 MODIFY_REG(RCC->RCK4SELR, (RCC_RCK4SELR_PLL4SRC), 0U);
335
336 /* Reset RCC PLL1 Configuration Register 1 */
337 WRITE_REG(RCC->PLL1CFGR1, 0x00010031U);
338
339 /* Reset RCC PLL1 Configuration Register 2 */
340 WRITE_REG(RCC->PLL1CFGR2, 0x00010100U);
341
342 /* Reset RCC PLL1 Fractional Register */
343 CLEAR_REG(RCC->PLL1FRACR);
344
345 /* Reset RCC PLL1 Clock Spreading Generator Register */
346 CLEAR_REG(RCC->PLL1CSGR);
347
348 /* Reset RCC PLL2 Configuration Register 1 */
349 WRITE_REG(RCC->PLL2CFGR1, 0x00010063U);
350
351 /* Reset RCC PLL2 Configuration Register 2 */
352 WRITE_REG(RCC->PLL2CFGR2, 0x00010101U);
353
354 /* Reset RCC PLL2 Fractional Register */
355 CLEAR_REG(RCC->PLL2FRACR);
356
357 /* Reset RCC PLL2 Clock Spreading Generator Register */
358 CLEAR_REG(RCC->PLL2CSGR);
359
360 /* Reset RCC PLL3 Configuration Register 1 */
361 WRITE_REG(RCC->PLL3CFGR1, 0x00010031U);
362
363 /* Reset RCC PLL3 Configuration Register 2 */
364 WRITE_REG(RCC->PLL3CFGR2, 0x00010101U);
365
366 /* Reset RCC PLL3 Fractional Register */
367 CLEAR_REG(RCC->PLL3FRACR);
368
369 /* Reset RCC PLL3 Clock Spreading Generator Register */
370 CLEAR_REG(RCC->PLL3CSGR);
371
372 /* Reset RCC PLL4 Configuration Register 1 */
373 WRITE_REG(RCC->PLL4CFGR1, 0x00010031U);
374
375 /* Reset RCC PLL4 Configuration Register 2 */
376 WRITE_REG(RCC->PLL4CFGR2, 0x00000000U);
377
378 /* Reset RCC PLL4 Fractional Register */
379 CLEAR_REG(RCC->PLL4FRACR);
380
381 /* Reset RCC PLL4 Clock Spreading Generator Register */
382 CLEAR_REG(RCC->PLL4CSGR);
383
384 /* Reset HSIDIV once PLLs are off */
385 CLEAR_BIT(RCC->HSICFGR, RCC_HSICFGR_HSIDIV);
386
387 /* Get Start Tick*/
388 tickstart = HAL_GetTick();
389
390 /* Wait till HSIDIV is ready */
391 while ((RCC->OCRDYR & RCC_OCRDYR_HSIDIVRDY) == 0U)
392 {
393 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
394 {
395 return HAL_TIMEOUT;
396 }
397 }
398
399 /* Reset HSITRIM value */
400 CLEAR_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM);
401
402 /* Reset the Oscillator Enable Control registers */
403 WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSIKERON | RCC_OCENCLRR_CSION |
404 RCC_OCENCLRR_CSIKERON | RCC_OCENCLRR_DIGBYP | RCC_OCENCLRR_HSEON |
405 RCC_OCENCLRR_HSEKERON | RCC_OCENCLRR_HSEBYP);
406
407 /* Clear LSION bit */
408 CLEAR_BIT(RCC->RDLSICR, RCC_RDLSICR_LSION);
409
410 /* Reset CSITRIM value */
411 CLEAR_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM);
412
413 #ifdef CORE_CA7
414 /* Reset RCC Clock Source Interrupt Enable Register */
415 CLEAR_BIT(RCC->MP_CIER, (RCC_MP_CIER_LSIRDYIE | RCC_MP_CIER_LSERDYIE |
416 RCC_MP_CIER_HSIRDYIE | RCC_MP_CIER_HSERDYIE | RCC_MP_CIER_CSIRDYIE |
417 RCC_MP_CIER_PLL1DYIE | RCC_MP_CIER_PLL2DYIE | RCC_MP_CIER_PLL3DYIE |
418 RCC_MP_CIER_PLL4DYIE | RCC_MP_CIER_LSECSSIE | RCC_MP_CIER_WKUPIE));
419
420 /* Clear all RCC MPU interrupt flags */
421 SET_BIT(RCC->MP_CIFR, (RCC_MP_CIFR_LSIRDYF | RCC_MP_CIFR_LSERDYF |
422 RCC_MP_CIFR_HSIRDYF | RCC_MP_CIFR_HSERDYF | RCC_MP_CIFR_CSIRDYF |
423 RCC_MP_CIFR_PLL1DYF | RCC_MP_CIFR_PLL2DYF | RCC_MP_CIFR_PLL3DYF |
424 RCC_MP_CIFR_PLL4DYF | RCC_MP_CIFR_LSECSSF | RCC_MP_CIFR_WKUPF));
425
426 /* Clear all RCC MPU Reset Flags */
427 SET_BIT(RCC->MP_RSTSCLRR, (RCC_MP_RSTSCLRR_MPUP1RSTF |
428 RCC_MP_RSTSCLRR_MPUP0RSTF | RCC_MP_RSTSCLRR_CSTDBYRSTF |
429 RCC_MP_RSTSCLRR_STDBYRSTF | RCC_MP_RSTSCLRR_IWDG2RSTF |
430 RCC_MP_RSTSCLRR_IWDG1RSTF | RCC_MP_RSTSCLRR_MCSYSRSTF |
431 RCC_MP_RSTSCLRR_MPSYSRSTF | RCC_MP_RSTSCLRR_VCORERSTF |
432 RCC_MP_RSTSCLRR_HCSSRSTF | RCC_MP_RSTSCLRR_PADRSTF |
433 RCC_MP_RSTSCLRR_BORRSTF | RCC_MP_RSTSCLRR_PORRSTF));
434 #endif
435
436 #ifdef CORE_CM4
437 /* Reset RCC Clock Source Interrupt Enable Register */
438 CLEAR_BIT(RCC->MC_CIER, (RCC_MC_CIER_LSIRDYIE | RCC_MC_CIER_LSERDYIE |
439 RCC_MC_CIER_HSIRDYIE | RCC_MC_CIER_HSERDYIE | RCC_MC_CIER_CSIRDYIE |
440 RCC_MC_CIER_PLL1DYIE | RCC_MC_CIER_PLL2DYIE | RCC_MC_CIER_PLL3DYIE |
441 RCC_MC_CIER_PLL4DYIE | RCC_MC_CIER_LSECSSIE | RCC_MC_CIER_WKUPIE));
442
443 /* Clear all RCC MCU interrupt flags */
444 SET_BIT(RCC->MC_CIFR, (RCC_MC_CIFR_LSIRDYF | RCC_MC_CIFR_LSERDYF |
445 RCC_MC_CIFR_HSIRDYF | RCC_MC_CIFR_HSERDYF | RCC_MC_CIFR_CSIRDYF |
446 RCC_MC_CIFR_PLL1DYF | RCC_MC_CIFR_PLL2DYF | RCC_MC_CIFR_PLL3DYF |
447 RCC_MC_CIFR_PLL4DYF | RCC_MC_CIFR_LSECSSF | RCC_MC_CIFR_WKUPF));
448
449 /* Clear all RCC MCU Reset Flags */
450 SET_BIT(RCC->MC_RSTSCLRR, RCC_MC_RSTSCLRR_WWDG1RSTF |
451 RCC_MC_RSTSCLRR_IWDG2RSTF | RCC_MC_RSTSCLRR_IWDG1RSTF |
452 RCC_MC_RSTSCLRR_MCSYSRSTF | RCC_MC_RSTSCLRR_MPSYSRSTF |
453 RCC_MC_RSTSCLRR_MCURSTF | RCC_MC_RSTSCLRR_VCORERSTF |
454 RCC_MC_RSTSCLRR_HCSSRSTF | RCC_MC_RSTSCLRR_PADRSTF |
455 RCC_MC_RSTSCLRR_BORRSTF | RCC_MC_RSTSCLRR_PORRSTF);
456 #endif
457
458 /* Update the SystemCoreClock global variable */
459 SystemCoreClock = HSI_VALUE;
460
461 /* Adapt Systick interrupt period */
462 if (HAL_InitTick(uwTickPrio) != HAL_OK)
463 {
464 return HAL_ERROR;
465 }
466
467 return HAL_OK;
468 }
469
470 /**
471 * @brief Initializes the RCC Oscillators according to the specified parameters in the
472 * RCC_OscInitTypeDef.
473 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
474 * contains the configuration information for the RCC Oscillators.
475 * @note The PLL is not disabled when used as system clock.
476 * @retval HAL status
477 */
HAL_RCC_OscConfig(RCC_OscInitTypeDef * RCC_OscInitStruct)478 __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
479 {
480 uint32_t tickstart;
481 HAL_StatusTypeDef result = HAL_OK;
482
483 /* Check Null pointer */
484 if (RCC_OscInitStruct == NULL)
485 {
486 return HAL_ERROR;
487 }
488
489 /* Check the parameters */
490 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
491 /*------------------------------- HSE Configuration ------------------------*/
492 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
493 {
494 /* Check the parameters */
495 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
496 /* When the HSE is used somewhere in the system it will not be disabled */
497 if (IS_HSE_IN_USE())
498 {
499 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
500 {
501 return HAL_ERROR;
502 }
503 }
504 else
505 {
506 /* Configure HSE oscillator */
507 result = HAL_RCC_HSEConfig(RCC_OscInitStruct->HSEState);
508 if (result != HAL_OK)
509 {
510 return result;
511 }
512 }
513 }
514 /*----------------------------- HSI Configuration --------------------------*/
515 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
516 {
517 /* Check the parameters */
518 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
519 assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
520 assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDivValue));
521
522 /* When the HSI is used as system clock it will not disabled */
523 if (IS_HSI_IN_USE())
524 {
525 /* When HSI is used as system clock it will not disabled */
526 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
527 {
528 return HAL_ERROR;
529 }
530 /* Otherwise, just the calibration is allowed */
531 else
532 {
533 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
534 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
535
536 /* It is not allowed to change HSIDIV if HSI is currently used as
537 * reference clock for a PLL
538 */
539 if (((__HAL_RCC_GET_PLL12_SOURCE() != RCC_PLL12SOURCE_HSI) ||
540 ((!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY)) &&
541 ((!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY))))) &&
542 ((__HAL_RCC_GET_PLL3_SOURCE() != RCC_PLL3SOURCE_HSI) ||
543 (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY))) &&
544 ((__HAL_RCC_GET_PLL4_SOURCE() != RCC_PLL4SOURCE_HSI) ||
545 (!__HAL_RCC_GET_FLAG(RCC_FLAG_PLL4RDY))))
546 {
547 /* Update HSIDIV value */
548 __HAL_RCC_HSI_DIV(RCC_OscInitStruct->HSIDivValue);
549
550 /* Get Start Tick*/
551 tickstart = HAL_GetTick();
552
553 /* Wait till HSIDIV is ready */
554 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) == RESET)
555 {
556 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
557 {
558 return HAL_TIMEOUT;
559 }
560 }
561 }
562
563 /* Update the SystemCoreClock global variable */
564 SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq();
565
566 /* Adapt Systick interrupt period */
567 if (HAL_InitTick(uwTickPrio) != HAL_OK)
568 {
569 return HAL_ERROR;
570 }
571 }
572 }
573 else
574 {
575 /* Check the HSI State */
576 if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
577 {
578 /* Enable the Internal High Speed oscillator (HSI). */
579 __HAL_RCC_HSI_ENABLE();
580
581 /* Get Start Tick*/
582 tickstart = HAL_GetTick();
583
584 /* Wait till HSI is ready */
585 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
586 {
587 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
588 {
589 return HAL_TIMEOUT;
590 }
591 }
592
593 /* Update HSIDIV value */
594 __HAL_RCC_HSI_DIV(RCC_OscInitStruct->HSIDivValue);
595
596 /* Get Start Tick*/
597 tickstart = HAL_GetTick();
598
599 /* Wait till HSIDIV is ready */
600 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) == RESET)
601 {
602 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
603 {
604 return HAL_TIMEOUT;
605 }
606 }
607
608 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
609 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
610 }
611 else
612 {
613 /* Disable the Internal High Speed oscillator (HSI). */
614 __HAL_RCC_HSI_DISABLE();
615
616 /* Get Start Tick*/
617 tickstart = HAL_GetTick();
618
619 /* Wait till HSI is ready */
620 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
621 {
622 if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
623 {
624 return HAL_TIMEOUT;
625 }
626 }
627 }
628 }
629 }
630 /*----------------------------- CSI Configuration --------------------------*/
631 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
632 {
633 /* Check the parameters */
634 assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
635 assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
636
637 /* When the CSI is used as system clock it will not disabled */
638 if (IS_CSI_IN_USE())
639 {
640 /* When CSI is used as system clock it will not disabled */
641 if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
642 {
643 return HAL_ERROR;
644 }
645 /* Otherwise, just the calibration is allowed */
646 else
647 {
648 /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
649 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
650 }
651 }
652 else
653 {
654 /* Check the CSI State */
655 if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
656 {
657 /* Enable the Internal High Speed oscillator (CSI). */
658 __HAL_RCC_CSI_ENABLE();
659
660 /* Get Start Tick*/
661 tickstart = HAL_GetTick();
662
663 /* Wait till CSI is ready */
664 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET)
665 {
666 if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
667 {
668 return HAL_TIMEOUT;
669 }
670 }
671
672 /* Adjusts the Internal High Speed oscillator (CSI) calibration value.*/
673 __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
674 }
675 else
676 {
677 /* Disable the Internal High Speed oscillator (CSI). */
678 __HAL_RCC_CSI_DISABLE();
679
680 /* Get Start Tick*/
681 tickstart = HAL_GetTick();
682
683 /* Wait till CSI is ready */
684 while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != RESET)
685 {
686 if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
687 {
688 return HAL_TIMEOUT;
689 }
690 }
691 }
692 }
693 }
694 /*------------------------------ LSI Configuration -------------------------*/
695 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
696 {
697 /* Check the parameters */
698 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
699
700 /* Check the LSI State */
701 if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
702 {
703 /* Enable the Internal Low Speed oscillator (LSI). */
704 __HAL_RCC_LSI_ENABLE();
705
706 /* Get Start Tick*/
707 tickstart = HAL_GetTick();
708
709 /* Wait till LSI is ready */
710 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
711 {
712 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
713 {
714 return HAL_TIMEOUT;
715 }
716 }
717 }
718 else
719 {
720 /* Disable the Internal Low Speed oscillator (LSI). */
721 __HAL_RCC_LSI_DISABLE();
722
723 /* Get Start Tick*/
724 tickstart = HAL_GetTick();
725
726 /* Wait till LSI is ready */
727 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
728 {
729 if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
730 {
731 return HAL_TIMEOUT;
732 }
733 }
734 }
735 }
736
737 /*------------------------------ LSE Configuration -------------------------*/
738 if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
739 {
740 /* Check the parameters */
741 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
742
743 /* Enable write access to Backup domain */
744 SET_BIT(PWR->CR1, PWR_CR1_DBP);
745
746 /* Wait for Backup domain Write protection disable */
747 tickstart = HAL_GetTick();
748
749 while ((PWR->CR1 & PWR_CR1_DBP) == RESET)
750 {
751 if ((HAL_GetTick() - tickstart) > DBP_TIMEOUT_VALUE)
752 {
753 return HAL_TIMEOUT;
754 }
755 }
756
757 result = HAL_RCC_LSEConfig(RCC_OscInitStruct->LSEState);
758 if (result != HAL_OK)
759 {
760 return result;
761 }
762
763 } /* Close LSE Configuration */
764
765 /*-------------------------------- PLL Configuration -----------------------*/
766
767 /* Configure PLL1 */
768 result = RCC_PLL1_Config(&(RCC_OscInitStruct->PLL));
769 if (result != HAL_OK)
770 {
771 return result;
772 }
773
774 /* Configure PLL2 */
775 result = RCCEx_PLL2_Config(&(RCC_OscInitStruct->PLL2));
776 if (result != HAL_OK)
777 {
778 return result;
779 }
780
781 /* Configure PLL3 */
782 result = RCCEx_PLL3_Config(&(RCC_OscInitStruct->PLL3));
783 if (result != HAL_OK)
784 {
785 return result;
786 }
787
788 /* Configure PLL4 */
789 result = RCCEx_PLL4_Config(&(RCC_OscInitStruct->PLL4));
790 if (result != HAL_OK)
791 {
792 return result;
793 }
794
795 return HAL_OK;
796 }
797
798
799 /**
800 * @brief Initializes the RCC HSE Oscillator according to the specified
801 * parameter State
802 * @note Beware HSE oscillator is not used as clock before using this function.
803 * If this is the case, you have to select another source clock for item
804 * using HSE then change the HSE state (Eg.: disable it).
805 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
806 * @note This function reset the CSSON bit, so if the clock security system(CSS)
807 * was previously enabled you have to enable it again after calling this
808 * function.
809 * @param State contains the configuration for the RCC HSE Oscillator.
810 * This parameter can be one of the following values:
811 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator
812 * @arg RCC_HSE_ON: turn ON the HSE oscillator using an external
813 * crystal/ceramic resonator
814 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external
815 * clock using a low-swing analog signal provided to OSC_IN
816 * @arg RCC_HSE_BYPASS_DIG: HSE oscillator bypassed with external
817 * clock using a full-swing digital signal provided to OSC_IN
818 * @retval HAL status
819 */
HAL_RCC_HSEConfig(uint32_t State)820 HAL_StatusTypeDef HAL_RCC_HSEConfig(uint32_t State)
821 {
822 uint32_t tickstart;
823
824 /* Check parameter */
825 assert_param(IS_RCC_HSE(State));
826
827 /* Disable HSEON before configuring the HSE --------------*/
828 WRITE_REG(RCC->OCENCLRR, RCC_OCENCLRR_HSEON);
829
830 /* Get Start Tick*/
831 tickstart = HAL_GetTick();
832
833 /* Wait till HSE is disabled */
834 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
835 {
836 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
837 {
838 return HAL_TIMEOUT;
839 }
840 }
841
842 /* Clear remaining bits */
843 WRITE_REG(RCC->OCENCLRR, (RCC_OCENCLRR_DIGBYP | RCC_OCENSETR_HSEBYP));
844
845 /* Enable HSE if needed ---------------------------------------*/
846 if (State != RCC_HSE_OFF)
847 {
848 if (State == RCC_HSE_BYPASS)
849 {
850 SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEBYP);
851 }
852 else if (State == RCC_HSE_BYPASS_DIG)
853 {
854 SET_BIT(RCC->OCENSETR, RCC_OCENCLRR_DIGBYP);
855 SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEBYP);
856 }
857
858 /* Enable oscillator */
859 SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSEON);
860
861 /* Get Start Tick*/
862 tickstart = HAL_GetTick();
863
864 /* Wait till HSE is ready */
865 while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
866 {
867 if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
868 {
869 return HAL_TIMEOUT;
870 }
871 }
872 }
873
874 return HAL_OK;
875 }
876
877 /**
878 * @brief Initializes the RCC External Low Speed oscillator (LSE) according
879 * to the specified parameter State
880 * @note Beware LSE oscillator is not used as clock before using this function.
881 * If this is the case, you have to select another source clock for item
882 * using LSE then change the LSE state (Eg.: disable it).
883 * @note As the LSE is in the Backup domain and write access is denied to
884 * this domain after reset, you have to enable write access using
885 * HAL_PWR_EnableBkUpAccess() function (set PWR_CR1_DBP bit) before
886 * to configure the LSE (to be done once after reset).
887 * @param State contains the configuration for the RCC LSE Oscillator
888 * This parameter can be one of the following values:
889 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator
890 * @arg RCC_LSE_ON: turn ON the LSE oscillator using an external
891 * crystal/ceramic resonator
892 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
893 * using a low-swing analog signal provided to OSC32_IN
894 * @arg RCC_LSE_BYPASS_DIG: LSE oscillator bypassed with external
895 * clock using a full-swing digital signal provided to OSC32_IN
896 * @retval HAL status
897 */
HAL_RCC_LSEConfig(uint32_t State)898 HAL_StatusTypeDef HAL_RCC_LSEConfig(uint32_t State)
899 {
900 uint32_t tickstart;
901
902 /* Check parameter */
903 assert_param(IS_RCC_LSE(State));
904
905 /* Turning LSE off is needed before configuring */
906 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
907
908 /* Get Start Tick*/
909 tickstart = HAL_GetTick();
910
911 /* Wait till LSE is disabled */
912 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
913 {
914 if ((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
915 {
916 return HAL_TIMEOUT;
917 }
918 }
919
920 /* Clear remaining bits */
921 CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEBYP | RCC_BDCR_DIGBYP));
922
923 /* Enable LSE if needed */
924 if (State != RCC_LSE_OFF)
925 {
926 if (State == RCC_LSE_BYPASS)
927 {
928 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
929 }
930 else if (State == RCC_LSE_BYPASS_DIG)
931 {
932 SET_BIT(RCC->BDCR, RCC_BDCR_DIGBYP);
933 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
934 }
935
936 /* Enable oscillator */
937 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
938
939 /* Get Start Tick*/
940 tickstart = HAL_GetTick();
941
942 /* Wait till LSE is ready */
943 while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
944 {
945 if ((HAL_GetTick() - tickstart) > LSE_TIMEOUT_VALUE)
946 {
947 return HAL_TIMEOUT;
948 }
949 }
950 } /* Enable LSE if needed */
951
952 return HAL_OK;
953 }
954
RCC_PLL1_Config(RCC_PLLInitTypeDef * pll1)955 HAL_StatusTypeDef RCC_PLL1_Config(RCC_PLLInitTypeDef *pll1)
956 {
957 uint32_t tickstart;
958
959 /* Check the parameters */
960 assert_param(IS_RCC_PLL(pll1->PLLState));
961 if ((pll1->PLLState) != RCC_PLL_NONE)
962 {
963 /* Check if the PLL is used as system clock or not (MPU, MCU, AXISS)*/
964 if (!__IS_PLL1_IN_USE()) /* If not used then */
965 {
966 if ((pll1->PLLState) == RCC_PLL_ON)
967 {
968 /* Check the parameters */
969 assert_param(IS_RCC_PLLMODE(pll1->PLLMODE));
970 assert_param(IS_RCC_PLL12SOURCE(pll1->PLLSource));
971 assert_param(IS_RCC_PLLM1_VALUE(pll1->PLLM));
972 if (pll1->PLLMODE == RCC_PLL_FRACTIONAL)
973 {
974 assert_param(IS_RCC_PLLN1_FRAC_VALUE(pll1->PLLN));
975 }
976 else
977 {
978 assert_param(IS_RCC_PLLN1_INT_VALUE(pll1->PLLN));
979 }
980 assert_param(IS_RCC_PLLP1_VALUE(pll1->PLLP));
981 assert_param(IS_RCC_PLLQ1_VALUE(pll1->PLLQ));
982 assert_param(IS_RCC_PLLR1_VALUE(pll1->PLLR));
983
984 /*Disable the post-dividers*/
985 __HAL_RCC_PLL1CLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR);
986 /* Disable the main PLL. */
987 __HAL_RCC_PLL1_DISABLE();
988
989 /* Get Start Tick*/
990 tickstart = HAL_GetTick();
991
992 /* Wait till PLL is ready */
993 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) != RESET)
994 {
995 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
996 {
997 return HAL_TIMEOUT;
998 }
999 }
1000
1001
1002 /*The PLL configuration below must be done before enabling the PLL:
1003 -Selection of PLL clock entry (HSI or HSE)
1004 -Frequency input range (PLLxRGE)
1005 -Division factors (DIVMx, DIVNx, DIVPx, DIVQx & DIVRx)
1006 Once the PLL is enabled, these parameters can not be changed.
1007 If the User wants to change the PLL parameters he must disable the concerned PLL (PLLxON=0) and wait for the
1008 PLLxRDY flag to be at 0.
1009 The PLL configuration below can be done at any time:
1010 -Enable/Disable of output clock dividers (DIVPxEN, DIVQxEN & DIVRxEN)
1011 -Fractional Division Enable (PLLxFRACNEN)
1012 -Fractional Division factor (FRACNx)*/
1013
1014 /* Do not change pll src if already in use */
1015 if (__IS_PLL2_IN_USE())
1016 {
1017 if (pll1->PLLSource != __HAL_RCC_GET_PLL12_SOURCE())
1018 {
1019 return HAL_ERROR;
1020 }
1021 }
1022 else
1023 {
1024 /* Configure PLL1 and PLL2 clock source */
1025 __HAL_RCC_PLL12_SOURCE(pll1->PLLSource);
1026 }
1027
1028 /* Wait till PLL SOURCE is ready */
1029 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL12SRCRDY) == RESET)
1030 {
1031 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
1032 {
1033 return HAL_TIMEOUT;
1034 }
1035 }
1036
1037 /* Configure the PLL1 multiplication and division factors. */
1038 __HAL_RCC_PLL1_CONFIG(
1039 pll1->PLLM,
1040 pll1->PLLN,
1041 pll1->PLLP,
1042 pll1->PLLQ,
1043 pll1->PLLR);
1044
1045
1046 /* Configure the Fractional Divider */
1047 __HAL_RCC_PLL1FRACV_DISABLE(); /*Set FRACLE to '0' */
1048 /* In integer or clock spreading mode the application shall ensure that a 0 is loaded into the SDM */
1049 if ((pll1->PLLMODE == RCC_PLL_SPREAD_SPECTRUM) || (pll1->PLLMODE == RCC_PLL_INTEGER))
1050 {
1051 /* Do not use the fractional divider */
1052 __HAL_RCC_PLL1FRACV_CONFIG(0U); /* Set FRACV to '0' */
1053 }
1054 else
1055 {
1056 /* Configure PLL PLL1FRACV in fractional mode*/
1057 __HAL_RCC_PLL1FRACV_CONFIG(pll1->PLLFRACV);
1058 }
1059 __HAL_RCC_PLL1FRACV_ENABLE(); /* Set FRACLE to 1 */
1060
1061
1062 /* Configure the Spread Control */
1063 if (pll1->PLLMODE == RCC_PLL_SPREAD_SPECTRUM)
1064 {
1065 assert_param(IS_RCC_INC_STEP(pll1->INC_STEP));
1066 assert_param(IS_RCC_SSCG_MODE(pll1->SSCG_MODE));
1067 assert_param(IS_RCC_RPDFN_DIS(pll1->RPDFN_DIS));
1068 assert_param(IS_RCC_TPDFN_DIS(pll1->TPDFN_DIS));
1069 assert_param(IS_RCC_MOD_PER(pll1->MOD_PER));
1070
1071 __HAL_RCC_PLL1CSGCONFIG(pll1->MOD_PER, pll1->TPDFN_DIS, pll1->RPDFN_DIS,
1072 pll1->SSCG_MODE, pll1->INC_STEP);
1073
1074 __HAL_RCC_PLL1_SSMODE_ENABLE();
1075 }
1076 else
1077 {
1078 __HAL_RCC_PLL1_SSMODE_DISABLE();
1079 }
1080
1081 /* Enable the PLL1. */
1082 __HAL_RCC_PLL1_ENABLE();
1083
1084 /* Get Start Tick*/
1085 tickstart = HAL_GetTick();
1086
1087 /* Wait till PLL is ready */
1088 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) == RESET)
1089 {
1090 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
1091 {
1092 return HAL_TIMEOUT;
1093 }
1094 }
1095 /* Enable post-dividers */
1096 __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR);
1097 }
1098 else
1099 {
1100 /*Disable the post-dividers*/
1101 __HAL_RCC_PLL1CLKOUT_DISABLE(RCC_PLL1_DIVP | RCC_PLL1_DIVQ | RCC_PLL1_DIVR);
1102 /* Disable the PLL1. */
1103 __HAL_RCC_PLL1_DISABLE();
1104
1105 /* Get Start Tick*/
1106 tickstart = HAL_GetTick();
1107
1108 /* Wait till PLL is ready */
1109 while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) != RESET)
1110 {
1111 if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
1112 {
1113 return HAL_TIMEOUT;
1114 }
1115 }
1116 }
1117 }
1118 else
1119 {
1120 return HAL_ERROR;
1121 }
1122 }
1123 return HAL_OK;
1124
1125 }
1126
1127
1128
1129 /**
1130 * @brief Initializes the MPU,AXI, AHB and APB busses clocks according to the specified
1131 * parameters in the RCC_ClkInitStruct.
1132 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
1133 * contains the configuration information for the RCC peripheral.
1134 *
1135 * @note The SystemCoreClock CCSIS variable is used to store System Clock Frequency
1136 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
1137 *
1138 * @note The HSI is used (enabled by hardware) as system clock source after
1139 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
1140 * of failure of the HSE used directly or indirectly as system clock
1141 * (if the Clock Security System CSS is enabled).
1142 *
1143 * @note A switch from one clock source to another occurs only if the target
1144 * clock source is ready (clock stable after startup delay or PLL locked).
1145 * If a clock source which is not yet ready is selected, the switch will
1146 * occur when the clock source will be ready.
1147 *
1148 * @note Depending on the device voltage range, the software has to set correctly
1149 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
1150 * (for more details refer to section above "Initialization/de-initialization functions")
1151 * @retval None
1152 */
HAL_RCC_ClockConfig(RCC_ClkInitTypeDef * RCC_ClkInitStruct)1153 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct)
1154 {
1155
1156 HAL_StatusTypeDef status = HAL_OK;
1157 uint32_t tickstart;
1158
1159 /* Check Null pointer */
1160 if (RCC_ClkInitStruct == NULL)
1161 {
1162 return HAL_ERROR;
1163 }
1164
1165 assert_param(IS_RCC_CLOCKTYPETYPE(RCC_ClkInitStruct->ClockType));
1166
1167 /* Configure MPU block if needed */
1168 if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_MPU) == RCC_CLOCKTYPE_MPU)
1169 {
1170 status = RCC_MPUConfig(&(RCC_ClkInitStruct->MPUInit));
1171 if (status != HAL_OK)
1172 {
1173 return status;
1174 }
1175 }
1176
1177 /* Configure AXISS block if needed */
1178 if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_ACLK) == RCC_CLOCKTYPE_ACLK)
1179 {
1180 status = RCC_AXISSConfig(&(RCC_ClkInitStruct->AXISSInit));
1181 if (status != HAL_OK)
1182 {
1183 return status;
1184 }
1185 }
1186
1187 /* Configure MCU block if needed */
1188 if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
1189 {
1190 status = RCC_MCUConfig(&(RCC_ClkInitStruct->MCUInit));
1191 if (status != HAL_OK)
1192 {
1193 return status;
1194 }
1195 }
1196
1197 /* Configure APB4 divisor if needed */
1198 if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK4) == RCC_CLOCKTYPE_PCLK4)
1199 {
1200 assert_param(IS_RCC_APB4DIV(RCC_ClkInitStruct->APB4_Div));
1201 /* Set APB4 division factor */
1202 __HAL_RCC_APB4_DIV(RCC_ClkInitStruct->APB4_Div);
1203
1204 /* Get Start Tick*/
1205 tickstart = HAL_GetTick();
1206
1207 /* Wait till APB4 is ready */
1208 while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB4DIVRDY) == RESET)
1209 {
1210 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1211 {
1212 return HAL_TIMEOUT;
1213 }
1214 }
1215 }
1216
1217 /* Configure APB5 divisor if needed */
1218 if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK5) == RCC_CLOCKTYPE_PCLK5)
1219 {
1220 assert_param(IS_RCC_APB5DIV(RCC_ClkInitStruct->APB5_Div));
1221 /* Set APB5 division factor */
1222 __HAL_RCC_APB5_DIV(RCC_ClkInitStruct->APB5_Div);
1223
1224 /* Get Start Tick*/
1225 tickstart = HAL_GetTick();
1226
1227 /* Wait till APB5 is ready */
1228 while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB5DIVRDY) == RESET)
1229 {
1230 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1231 {
1232 return HAL_TIMEOUT;
1233 }
1234 }
1235 }
1236
1237 /* Configure APB1 divisor if needed */
1238 if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
1239 {
1240 assert_param(IS_RCC_APB1DIV(RCC_ClkInitStruct->APB1_Div));
1241 /* Set APB1 division factor */
1242 __HAL_RCC_APB1_DIV(RCC_ClkInitStruct->APB1_Div);
1243
1244 /* Get Start Tick*/
1245 tickstart = HAL_GetTick();
1246
1247 /* Wait till APB1 is ready */
1248 while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB1DIVRDY) == RESET)
1249 {
1250 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1251 {
1252 return HAL_TIMEOUT;
1253 }
1254 }
1255 }
1256
1257 /* Configure APB2 divisor if needed */
1258 if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
1259 {
1260 assert_param(IS_RCC_APB2DIV(RCC_ClkInitStruct->APB2_Div));
1261 /* Set APB2 division factor */
1262 __HAL_RCC_APB2_DIV(RCC_ClkInitStruct->APB2_Div);
1263
1264 /* Get Start Tick*/
1265 tickstart = HAL_GetTick();
1266
1267 /* Wait till APB2 is ready */
1268 while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB2DIVRDY) == RESET)
1269 {
1270 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1271 {
1272 return HAL_TIMEOUT;
1273 }
1274 }
1275 }
1276
1277 /* Configure APB3 divisor if needed */
1278 if ((RCC_ClkInitStruct->ClockType & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3)
1279 {
1280 assert_param(IS_RCC_APB3DIV(RCC_ClkInitStruct->APB3_Div));
1281 /* Set APB3 division factor */
1282 __HAL_RCC_APB3_DIV(RCC_ClkInitStruct->APB3_Div);
1283
1284 /* Get Start Tick*/
1285 tickstart = HAL_GetTick();
1286
1287 /* Wait till APB3 is ready */
1288 while (__HAL_RCC_GET_FLAG(RCC_FLAG_APB3DIVRDY) == RESET)
1289 {
1290 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1291 {
1292 return HAL_TIMEOUT;
1293 }
1294 }
1295 }
1296
1297 return HAL_OK;
1298 }
1299
RCC_MPUConfig(RCC_MPUInitTypeDef * RCC_MPUInitStruct)1300 HAL_StatusTypeDef RCC_MPUConfig(RCC_MPUInitTypeDef *RCC_MPUInitStruct)
1301 {
1302 uint32_t tickstart;
1303
1304 assert_param(IS_RCC_MPUSOURCE(RCC_MPUInitStruct->MPU_Clock));
1305
1306 /* Ensure clock source is ready*/
1307 switch (RCC_MPUInitStruct->MPU_Clock)
1308 {
1309 case (RCC_MPUSOURCE_HSI):
1310 {
1311 /* Check the HSI ready flag */
1312 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
1313 {
1314 return HAL_ERROR;
1315 }
1316 break;
1317 }
1318
1319 case (RCC_MPUSOURCE_HSE):
1320 {
1321 /* Check the HSE ready flag */
1322 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
1323 {
1324 return HAL_ERROR;
1325 }
1326 break;
1327 }
1328
1329 case (RCC_MPUSOURCE_PLL1):
1330 {
1331 /* Check the PLL1 ready flag */
1332 if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) == RESET)
1333 {
1334 return HAL_ERROR;
1335 }
1336 break;
1337 }
1338
1339 case (RCC_MPUSOURCE_MPUDIV):
1340 {
1341 assert_param(IS_RCC_MPUDIV(RCC_MPUInitStruct->MPU_Div));
1342
1343 /* Check the PLL1 ready flag (as PLL1_P is the MPUDIV source */
1344 if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL1RDY) == RESET)
1345 {
1346 return HAL_ERROR;
1347 }
1348
1349 /* Set MPU division factor */
1350 __HAL_RCC_MPU_DIV(RCC_MPUInitStruct->MPU_Div);
1351
1352 break;
1353 }
1354
1355 default:
1356 /* This case is impossible */
1357 return HAL_ERROR;
1358 break;
1359 }
1360
1361 /* Set MPU clock source */
1362 __HAL_RCC_MPU_SOURCE(RCC_MPUInitStruct->MPU_Clock);
1363
1364 /* Get Start Tick*/
1365 tickstart = HAL_GetTick();
1366
1367 /* Wait till MPU is ready */
1368 while (__HAL_RCC_GET_FLAG(RCC_FLAG_MPUSRCRDY) == RESET)
1369 {
1370 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1371 {
1372 return HAL_TIMEOUT;
1373 }
1374 }
1375 #ifdef CORE_CA7
1376 /* Update the SystemCoreClock global variable */
1377 SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq();
1378
1379 /* Configure the source of time base considering new system clocks settings*/
1380 HAL_InitTick(uwTickPrio);
1381 #endif
1382
1383 return HAL_OK;
1384 }
1385
1386
RCC_AXISSConfig(RCC_AXISSInitTypeDef * RCC_AXISSInitStruct)1387 HAL_StatusTypeDef RCC_AXISSConfig(RCC_AXISSInitTypeDef *RCC_AXISSInitStruct)
1388 {
1389 uint32_t tickstart;
1390
1391 assert_param(IS_RCC_AXISSOURCE(RCC_AXISSInitStruct->AXI_Clock));
1392 assert_param(IS_RCC_AXIDIV(RCC_AXISSInitStruct->AXI_Div));
1393
1394 /* Ensure clock source is ready*/
1395 switch (RCC_AXISSInitStruct->AXI_Clock)
1396 {
1397 case (RCC_AXISSOURCE_HSI):
1398 {
1399 /* Check the HSI ready flag */
1400 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
1401 {
1402 return HAL_ERROR;
1403 }
1404 break;
1405 }
1406
1407 case (RCC_AXISSOURCE_HSE):
1408 {
1409 /* Check the HSI ready flag */
1410 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
1411 {
1412 return HAL_ERROR;
1413 }
1414 break;
1415 }
1416
1417 case (RCC_AXISSOURCE_PLL2):
1418 {
1419 /* Check the HSI ready flag */
1420 if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
1421 {
1422 return HAL_ERROR;
1423 }
1424 break;
1425 }
1426
1427 default:
1428 break;
1429
1430 }
1431
1432 /* Set AXISS clock source */
1433 __HAL_RCC_AXISS_SOURCE(RCC_AXISSInitStruct->AXI_Clock);
1434
1435 if (RCC_AXISSInitStruct->AXI_Clock != RCC_AXISSOURCE_OFF)
1436 {
1437 /* Get Start Tick*/
1438 tickstart = HAL_GetTick();
1439
1440 /* Wait till AXISS is ready */
1441 while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) == RESET)
1442 {
1443 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1444 {
1445 return HAL_TIMEOUT;
1446 }
1447 }
1448 }
1449 else
1450 {
1451 // RCC_AXISSOURCE_OFF case
1452 /* Get Start Tick*/
1453 tickstart = HAL_GetTick();
1454
1455 /* Wait till AXISS is ready */
1456 while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXISSRCRDY) != RESET)
1457 {
1458 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1459 {
1460 return HAL_TIMEOUT;
1461 }
1462 }
1463 }
1464
1465 /* Set AXISS division factor */
1466 __HAL_RCC_AXI_DIV(RCC_AXISSInitStruct->AXI_Div);
1467
1468 /* Get Start Tick*/
1469 tickstart = HAL_GetTick();
1470
1471 /* Wait till AXISS is ready */
1472 while (__HAL_RCC_GET_FLAG(RCC_FLAG_AXIDIVRDY) == RESET)
1473 {
1474 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1475 {
1476 return HAL_TIMEOUT;
1477 }
1478 }
1479
1480 return HAL_OK;
1481 }
1482
1483
RCC_MCUConfig(RCC_MCUInitTypeDef * MCUInitStruct)1484 HAL_StatusTypeDef RCC_MCUConfig(RCC_MCUInitTypeDef *MCUInitStruct)
1485 {
1486 uint32_t tickstart;
1487
1488 assert_param(IS_RCC_MCUSSOURCE(MCUInitStruct->MCU_Clock));
1489 assert_param(IS_RCC_MCUDIV(MCUInitStruct->MCU_Div));
1490
1491 /* Ensure clock source is ready*/
1492 switch (MCUInitStruct->MCU_Clock)
1493 {
1494 case (RCC_MCUSSOURCE_HSI):
1495 {
1496 /* Check the HSI ready flag */
1497 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
1498 {
1499 return HAL_ERROR;
1500 }
1501 break;
1502 }
1503
1504 case (RCC_MCUSSOURCE_HSE):
1505 {
1506 /* Check the HSE ready flag */
1507 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
1508 {
1509 return HAL_ERROR;
1510 }
1511 break;
1512 }
1513
1514 case (RCC_MCUSSOURCE_CSI):
1515 {
1516 /* Check the HSI ready flag */
1517 if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET)
1518 {
1519 return HAL_ERROR;
1520 }
1521 break;
1522 }
1523
1524 case (RCC_MCUSSOURCE_PLL3):
1525 {
1526 /* Check the HSI ready flag */
1527 if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == RESET)
1528 {
1529 return HAL_ERROR;
1530 }
1531 break;
1532 }
1533
1534 default:
1535 break;
1536
1537 }
1538
1539 /* Set MCU clock source */
1540 __HAL_RCC_MCU_SOURCE(MCUInitStruct->MCU_Clock);
1541
1542 /* Get Start Tick*/
1543 tickstart = HAL_GetTick();
1544
1545 /* Wait till MCU is ready */
1546
1547 while (__HAL_RCC_GET_FLAG(RCC_FLAG_MCUSSRCRDY) == RESET)
1548 {
1549 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1550 {
1551 return HAL_TIMEOUT;
1552 }
1553 }
1554
1555 #ifdef CORE_CM4
1556 /* Update the SystemCoreClock global variable */
1557 SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq();
1558
1559 /* Configure the source of time base considering new system clocks settings*/
1560 HAL_InitTick(uwTickPrio);
1561 #endif
1562
1563 /* Set MCU division factor */
1564 __HAL_RCC_MCU_DIV(MCUInitStruct->MCU_Div);
1565
1566 /* Get Start Tick*/
1567 tickstart = HAL_GetTick();
1568
1569 /* Wait till MCU is ready */
1570 while (__HAL_RCC_GET_FLAG(RCC_FLAG_MCUDIVRDY) == RESET)
1571 {
1572 if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
1573 {
1574 return HAL_TIMEOUT;
1575 }
1576 }
1577 #ifdef CORE_CM4
1578 /* Update the SystemCoreClock global variable */
1579 SystemCoreClock = HAL_RCC_GetSystemCoreClockFreq();
1580
1581 /* Configure the source of time base considering new system clocks settings*/
1582 HAL_InitTick(uwTickPrio);
1583 #endif
1584
1585 return HAL_OK;
1586 }
1587
1588 /**
1589 * @}
1590 */
1591
1592 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
1593 * @brief RCC clocks control functions
1594 *
1595 @verbatim
1596 ===============================================================================
1597 ##### Peripheral Control functions #####
1598 ===============================================================================
1599 [..]
1600 This subsection provides a set of functions allowing to control the RCC Clocks
1601 frequencies.
1602 @endverbatim
1603 * @{
1604 */
1605
1606 /**
1607 * @brief Selects the clock source to output on MCO1 pin or on MCO2 pin
1608 * @note BSP_MCO_Init shall be called before to configure output pins depending on the board
1609 * @param RCC_MCOx: specifies the output direction for the clock source.
1610 * This parameter can be one of the following values:
1611 * @arg RCC_MCO1: Clock source to output on MCO1
1612 * @arg RCC_MCO2: Clock source to output on MCO2
1613 * @param RCC_MCOSource: specifies the clock source to output.
1614 * This parameter can be one of the following values:
1615 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 clock entry
1616 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 clock entry
1617 * @arg RCC_MCO1SOURCE_CSI: CSI clock selected as MCO1 clock entry
1618 * @arg RCC_MCO1SOURCE_LSI: LSI clock selected as MCO1 clock entry
1619 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 clock entry
1620 * @arg RCC_MCO2SOURCE_MPU: MPU clock selected as MCO2 clock entry
1621 * @arg RCC_MCO2SOURCE_AXI: AXI clock selected as MCO2 clock entry
1622 * @arg RCC_MCO2SOURCE_MCU: MCU clock selected as MCO2 clock entry
1623 * @arg RCC_MCO2SOURCE_PLL4: PLL4 clock selected as MCO2 clock entry
1624 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 clock entry
1625 * @arg RCC_MCO2SOURCE_HSI: HSI clock selected as MCO2 clock entry
1626 *
1627 * @param RCC_MCODiv: specifies the MCOx prescaler.
1628 * This parameter can be one of the following values:
1629 * @arg RCC_MCODIV_1 up to RCC_MCODIV_16 : divider applied to MCOx clock
1630 * @retval None
1631 */
HAL_RCC_MCOConfig(uint32_t RCC_MCOx,uint32_t RCC_MCOSource,uint32_t RCC_MCODiv)1632 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
1633 {
1634 /* Check the parameters */
1635 assert_param(IS_RCC_MCO(RCC_MCOx));
1636 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
1637 /* RCC_MCO1 */
1638 if (RCC_MCOx == RCC_MCO1)
1639 {
1640 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
1641
1642 /* Configure MCO1 */
1643 __HAL_RCC_MCO1_CONFIGURE(RCC_MCOSource, RCC_MCODiv);
1644
1645 /* Enable MCO1 output */
1646 __HAL_RCC_MCO1_ENABLE();
1647 }
1648 else
1649 {
1650 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
1651
1652 /* Configure MCO2 */
1653 __HAL_RCC_MCO2_CONFIGURE(RCC_MCOSource, RCC_MCODiv);
1654
1655 /* Enable MCO2 output */
1656 __HAL_RCC_MCO2_ENABLE();
1657 }
1658 }
1659
1660
1661 /**
1662 * @brief Enables the HSE Clock Security System.
1663 * @note If a failure is detected on the HSE:
1664 * - The RCC generates a system reset (nreset). The flag HCSSRSTF is set in order to
1665 * allow the application to identify the reset root cause.
1666 * - A failure event is generated (rcc_hsecss_fail). This event is connected to the TAMP
1667 * block, allowing the protection of backup registers and BKPSRAM.
1668 *
1669 * @note HSECSSON can be activated even when the HSEON is set to ‘0’. The CSS on HSE will be
1670 * enabled by the hardware when the HSE is enabled and ready, and HSECSSON is set to ‘1’.
1671 *
1672 * @note The HSECSS is disabled when the HSE is disabled (i.e. when the system is STOP or
1673 * STANDBY).
1674 *
1675 * @note It is not possible to clear the bit HSECSSON by software.
1676 *
1677 * @note The bit HSECSSON will be cleared by the hardware when a system reset occurs or when
1678 the system enters in STANDBY mode
1679 * @retval None
1680 */
HAL_RCC_EnableHSECSS(void)1681 void HAL_RCC_EnableHSECSS(void)
1682 {
1683 SET_BIT(RCC->OCENSETR, RCC_OCENSETR_HSECSSON);
1684 }
1685
1686 /**
1687 * @brief Configures the RCC_OscInitStruct according to the internal
1688 * RCC configuration registers.
1689 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
1690 * will be configured.
1691 * @retval None
1692 */
HAL_RCC_GetOscConfig(RCC_OscInitTypeDef * RCC_OscInitStruct)1693 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
1694 {
1695
1696 /* Set all possible values for the Oscillator type parameter ---------------*/
1697 RCC_OscInitStruct->OscillatorType =
1698 RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI |
1699 RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
1700
1701 /* Get the HSE configuration -----------------------------------------------*/
1702 if ((RCC->OCENSETR & RCC_OCENSETR_HSEBYP) == RCC_OCENSETR_HSEBYP)
1703 {
1704 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
1705 }
1706 else if ((RCC->OCENSETR & RCC_OCENSETR_HSEON) == RCC_OCENSETR_HSEON)
1707 {
1708 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
1709 }
1710 else
1711 {
1712 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
1713 }
1714
1715 /* Get the CSI configuration -----------------------------------------------*/
1716 if ((RCC->OCENSETR & RCC_OCENSETR_CSION) == RCC_OCENSETR_CSION)
1717 {
1718 RCC_OscInitStruct->CSIState = RCC_CSI_ON;
1719 }
1720 else
1721 {
1722 RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
1723 }
1724
1725 RCC_OscInitStruct->CSICalibrationValue =
1726 (uint32_t)((RCC->CSICFGR & RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1727
1728
1729 /* Get the HSI configuration -----------------------------------------------*/
1730 if ((RCC->OCENSETR & RCC_OCENSETR_HSION) == RCC_OCENSETR_HSION)
1731 {
1732 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
1733 }
1734 else
1735 {
1736 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
1737 }
1738
1739 RCC_OscInitStruct->HSICalibrationValue =
1740 (uint32_t)((RCC->HSICFGR & RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1741
1742
1743 /* Get the LSE configuration -----------------------------------------------*/
1744 if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
1745 {
1746 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
1747 }
1748 else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
1749 {
1750 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
1751 }
1752 else
1753 {
1754 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
1755 }
1756
1757 /* Get the LSI configuration -----------------------------------------------*/
1758 if ((RCC->RDLSICR & RCC_RDLSICR_LSION) == RCC_RDLSICR_LSION)
1759 {
1760 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
1761 }
1762 else
1763 {
1764 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
1765 }
1766
1767
1768 /* Get the PLL1 configuration -----------------------------------------------*/
1769 if ((RCC->PLL1CR & RCC_PLL1CR_PLLON) == RCC_PLL1CR_PLLON)
1770 {
1771 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
1772 }
1773 else
1774 {
1775 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
1776 }
1777
1778 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRC);
1779 RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVM1) >> RCC_PLL1CFGR1_DIVM1_Pos) + 1;
1780 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVN) >> RCC_PLL1CFGR1_DIVN_Pos) + 1;
1781 RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVR) >> RCC_PLL1CFGR2_DIVR_Pos) + 1;
1782 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVP) >> RCC_PLL1CFGR2_DIVP_Pos) + 1;
1783 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVQ) >> RCC_PLL1CFGR2_DIVQ_Pos) + 1;
1784 RCC_OscInitStruct->PLL.PLLFRACV = (uint32_t)((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACV) >> RCC_PLL1FRACR_FRACV_Pos);
1785
1786 if ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACV) == 0)
1787 {
1788 if ((RCC->PLL1CR & RCC_PLL1CR_SSCG_CTRL) == RCC_PLL1CR_SSCG_CTRL)
1789 {
1790 //SSMODE enabled
1791 RCC_OscInitStruct->PLL.PLLMODE = RCC_PLL_SPREAD_SPECTRUM;
1792 }
1793 else
1794 {
1795 RCC_OscInitStruct->PLL.PLLMODE = RCC_PLL_INTEGER;
1796 }
1797 }
1798 else
1799 {
1800 RCC_OscInitStruct->PLL.PLLMODE = RCC_PLL_FRACTIONAL;
1801 }
1802
1803 RCC_OscInitStruct->PLL.MOD_PER = (uint32_t)(RCC->PLL1CSGR & RCC_PLL1CSGR_MOD_PER);
1804 RCC_OscInitStruct->PLL.TPDFN_DIS = (uint32_t)(RCC->PLL1CSGR & RCC_PLL1CSGR_TPDFN_DIS);
1805 RCC_OscInitStruct->PLL.RPDFN_DIS = (uint32_t)(RCC->PLL1CSGR & RCC_PLL1CSGR_RPDFN_DIS);
1806 RCC_OscInitStruct->PLL.SSCG_MODE = (uint32_t)(RCC->PLL1CSGR & RCC_PLL1CSGR_SSCG_MODE);
1807 RCC_OscInitStruct->PLL.INC_STEP = (uint32_t)((RCC->PLL1CSGR & RCC_PLL1CSGR_INC_STEP) >> RCC_PLL1CSGR_INC_STEP_Pos);
1808
1809
1810 /* Get the PLL2 configuration -----------------------------------------------*/
1811 if ((RCC->PLL2CR & RCC_PLL2CR_PLLON) == RCC_PLL2CR_PLLON)
1812 {
1813 RCC_OscInitStruct->PLL2.PLLState = RCC_PLL_ON;
1814 }
1815 else
1816 {
1817 RCC_OscInitStruct->PLL2.PLLState = RCC_PLL_OFF;
1818 }
1819
1820 RCC_OscInitStruct->PLL2.PLLSource = (uint32_t)(RCC->RCK12SELR & RCC_RCK12SELR_PLL12SRC);
1821 RCC_OscInitStruct->PLL2.PLLM = (uint32_t)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVM2) >> RCC_PLL2CFGR1_DIVM2_Pos) + 1;
1822 RCC_OscInitStruct->PLL2.PLLN = (uint32_t)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVN) >> RCC_PLL2CFGR1_DIVN_Pos) + 1;
1823 RCC_OscInitStruct->PLL2.PLLR = (uint32_t)((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVR) >> RCC_PLL2CFGR2_DIVR_Pos) + 1;
1824 RCC_OscInitStruct->PLL2.PLLP = (uint32_t)((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVP) >> RCC_PLL2CFGR2_DIVP_Pos) + 1;
1825 RCC_OscInitStruct->PLL2.PLLQ = (uint32_t)((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVQ) >> RCC_PLL2CFGR2_DIVQ_Pos) + 1;
1826 RCC_OscInitStruct->PLL2.PLLFRACV = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACV) >> RCC_PLL2FRACR_FRACV_Pos);
1827
1828 if ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACV) == 0)
1829 {
1830 if ((RCC->PLL2CR & RCC_PLL2CR_SSCG_CTRL) == RCC_PLL2CR_SSCG_CTRL)
1831 {
1832 //SSMODE enabled
1833 RCC_OscInitStruct->PLL2.PLLMODE = RCC_PLL_SPREAD_SPECTRUM;
1834 }
1835 else
1836 {
1837 RCC_OscInitStruct->PLL2.PLLMODE = RCC_PLL_INTEGER;
1838 }
1839 }
1840 else
1841 {
1842 RCC_OscInitStruct->PLL2.PLLMODE = RCC_PLL_FRACTIONAL;
1843 }
1844
1845 RCC_OscInitStruct->PLL2.MOD_PER = (uint32_t)(RCC->PLL2CSGR & RCC_PLL2CSGR_MOD_PER);
1846 RCC_OscInitStruct->PLL2.TPDFN_DIS = (uint32_t)(RCC->PLL2CSGR & RCC_PLL2CSGR_TPDFN_DIS);
1847 RCC_OscInitStruct->PLL2.RPDFN_DIS = (uint32_t)(RCC->PLL2CSGR & RCC_PLL2CSGR_RPDFN_DIS);
1848 RCC_OscInitStruct->PLL2.SSCG_MODE = (uint32_t)(RCC->PLL2CSGR & RCC_PLL2CSGR_SSCG_MODE);
1849 RCC_OscInitStruct->PLL2.INC_STEP = (uint32_t)((RCC->PLL2CSGR & RCC_PLL2CSGR_INC_STEP) >> RCC_PLL2CSGR_INC_STEP_Pos);
1850
1851
1852 /* Get the PLL3 configuration -----------------------------------------------*/
1853 if ((RCC->PLL3CR & RCC_PLL3CR_PLLON) == RCC_PLL3CR_PLLON)
1854 {
1855 RCC_OscInitStruct->PLL3.PLLState = RCC_PLL_ON;
1856 }
1857 else
1858 {
1859 RCC_OscInitStruct->PLL3.PLLState = RCC_PLL_OFF;
1860 }
1861
1862 RCC_OscInitStruct->PLL3.PLLSource = (uint32_t)(RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC);
1863 RCC_OscInitStruct->PLL3.PLLM = (uint32_t)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1;
1864 RCC_OscInitStruct->PLL3.PLLN = (uint32_t)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) >> RCC_PLL3CFGR1_DIVN_Pos) + 1;
1865 RCC_OscInitStruct->PLL3.PLLR = (uint32_t)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVR) >> RCC_PLL3CFGR2_DIVR_Pos) + 1;
1866 RCC_OscInitStruct->PLL3.PLLP = (uint32_t)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) >> RCC_PLL3CFGR2_DIVP_Pos) + 1;
1867 RCC_OscInitStruct->PLL3.PLLQ = (uint32_t)((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVQ) >> RCC_PLL3CFGR2_DIVQ_Pos) + 1;
1868 RCC_OscInitStruct->PLL3.PLLRGE = (uint32_t)(RCC->PLL3CFGR1 & RCC_PLL3CFGR1_IFRGE);
1869 RCC_OscInitStruct->PLL3.PLLFRACV = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> RCC_PLL3FRACR_FRACV_Pos);
1870
1871 if ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) == 0)
1872 {
1873 if ((RCC->PLL3CR & RCC_PLL3CR_SSCG_CTRL) == RCC_PLL3CR_SSCG_CTRL)
1874 {
1875 //SSMODE enabled
1876 RCC_OscInitStruct->PLL3.PLLMODE = RCC_PLL_SPREAD_SPECTRUM;
1877 }
1878 else
1879 {
1880 RCC_OscInitStruct->PLL3.PLLMODE = RCC_PLL_INTEGER;
1881 }
1882 }
1883 else
1884 {
1885 RCC_OscInitStruct->PLL3.PLLMODE = RCC_PLL_FRACTIONAL;
1886 }
1887
1888 RCC_OscInitStruct->PLL3.MOD_PER = (uint32_t)(RCC->PLL3CSGR & RCC_PLL3CSGR_MOD_PER);
1889 RCC_OscInitStruct->PLL3.TPDFN_DIS = (uint32_t)(RCC->PLL3CSGR & RCC_PLL3CSGR_TPDFN_DIS);
1890 RCC_OscInitStruct->PLL3.RPDFN_DIS = (uint32_t)(RCC->PLL3CSGR & RCC_PLL3CSGR_RPDFN_DIS);
1891 RCC_OscInitStruct->PLL3.SSCG_MODE = (uint32_t)(RCC->PLL3CSGR & RCC_PLL3CSGR_SSCG_MODE);
1892 RCC_OscInitStruct->PLL3.INC_STEP = (uint32_t)((RCC->PLL3CSGR & RCC_PLL3CSGR_INC_STEP) >> RCC_PLL3CSGR_INC_STEP_Pos);
1893
1894 /* Get the PLL4 configuration -----------------------------------------------*/
1895 if ((RCC->PLL4CR & RCC_PLL4CR_PLLON) == RCC_PLL4CR_PLLON)
1896 {
1897 RCC_OscInitStruct->PLL4.PLLState = RCC_PLL_ON;
1898 }
1899 else
1900 {
1901 RCC_OscInitStruct->PLL4.PLLState = RCC_PLL_OFF;
1902 }
1903
1904 RCC_OscInitStruct->PLL4.PLLSource = (uint32_t)(RCC->RCK4SELR & RCC_RCK4SELR_PLL4SRC);
1905 RCC_OscInitStruct->PLL4.PLLM = (uint32_t)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVM4) >> RCC_PLL4CFGR1_DIVM4_Pos) + 1;
1906 RCC_OscInitStruct->PLL4.PLLN = (uint32_t)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVN) >> RCC_PLL4CFGR1_DIVN_Pos) + 1;
1907 RCC_OscInitStruct->PLL4.PLLR = (uint32_t)((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVR) >> RCC_PLL4CFGR2_DIVR_Pos) + 1;
1908 RCC_OscInitStruct->PLL4.PLLP = (uint32_t)((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVP) >> RCC_PLL4CFGR2_DIVP_Pos) + 1;
1909 RCC_OscInitStruct->PLL4.PLLQ = (uint32_t)((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVQ) >> RCC_PLL4CFGR2_DIVQ_Pos) + 1;
1910 RCC_OscInitStruct->PLL4.PLLRGE = (uint32_t)(RCC->PLL4CFGR1 & RCC_PLL4CFGR1_IFRGE);
1911 RCC_OscInitStruct->PLL4.PLLFRACV = (uint32_t)((RCC->PLL4FRACR & RCC_PLL4FRACR_FRACV) >> RCC_PLL4FRACR_FRACV_Pos);
1912
1913 if ((RCC->PLL4FRACR & RCC_PLL4FRACR_FRACV) == 0)
1914 {
1915 if ((RCC->PLL4CR & RCC_PLL4CR_SSCG_CTRL) == RCC_PLL4CR_SSCG_CTRL)
1916 {
1917 //SSMODE enabled
1918 RCC_OscInitStruct->PLL4.PLLMODE = RCC_PLL_SPREAD_SPECTRUM;
1919 }
1920 else
1921 {
1922 RCC_OscInitStruct->PLL4.PLLMODE = RCC_PLL_INTEGER;
1923 }
1924 }
1925 else
1926 {
1927 RCC_OscInitStruct->PLL4.PLLMODE = RCC_PLL_FRACTIONAL;
1928 }
1929
1930 RCC_OscInitStruct->PLL4.MOD_PER = (uint32_t)(RCC->PLL4CSGR & RCC_PLL4CSGR_MOD_PER);
1931 RCC_OscInitStruct->PLL4.TPDFN_DIS = (uint32_t)(RCC->PLL4CSGR & RCC_PLL4CSGR_TPDFN_DIS);
1932 RCC_OscInitStruct->PLL4.RPDFN_DIS = (uint32_t)(RCC->PLL4CSGR & RCC_PLL4CSGR_RPDFN_DIS);
1933 RCC_OscInitStruct->PLL4.SSCG_MODE = (uint32_t)(RCC->PLL4CSGR & RCC_PLL4CSGR_SSCG_MODE);
1934 RCC_OscInitStruct->PLL4.INC_STEP = (uint32_t)((RCC->PLL4CSGR & RCC_PLL4CSGR_INC_STEP) >> RCC_PLL4CSGR_INC_STEP_Pos);
1935
1936 }
1937
1938 /**
1939 * @brief Configures the RCC_ClkInitStruct according to the internal
1940 * RCC configuration registers.
1941 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
1942 * will be configured.
1943 * @param pFLatency: Pointer on the Flash Latency.
1944 * @retval None
1945 */
HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef * RCC_ClkInitStruct,uint32_t * pFLatency)1946 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
1947 {
1948 /* Prevent unused argument compilation warning */
1949 UNUSED(pFLatency);
1950
1951 /* Set all possible values for the Clock type parameter --------------------*/
1952 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_MPU | RCC_CLOCKTYPE_ACLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK4 |
1953 RCC_CLOCKTYPE_PCLK5 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
1954
1955 RCC_ClkInitStruct->MPUInit.MPU_Clock = __HAL_RCC_GET_MPU_SOURCE();
1956 RCC_ClkInitStruct->MPUInit.MPU_Div = __HAL_RCC_GET_MPU_DIV();
1957
1958 RCC_ClkInitStruct->AXISSInit.AXI_Clock = __HAL_RCC_GET_AXIS_SOURCE();
1959 RCC_ClkInitStruct->AXISSInit.AXI_Div = __HAL_RCC_GET_AXI_DIV();
1960
1961 RCC_ClkInitStruct->MCUInit.MCU_Clock = __HAL_RCC_GET_MCU_SOURCE();
1962 RCC_ClkInitStruct->MCUInit.MCU_Div = __HAL_RCC_GET_MCU_DIV();
1963
1964 RCC_ClkInitStruct->APB1_Div = __HAL_RCC_GET_APB1_DIV();
1965 RCC_ClkInitStruct->APB2_Div = __HAL_RCC_GET_APB2_DIV();
1966 RCC_ClkInitStruct->APB3_Div = __HAL_RCC_GET_APB3_DIV();
1967 RCC_ClkInitStruct->APB4_Div = __HAL_RCC_GET_APB4_DIV();
1968 RCC_ClkInitStruct->APB5_Div = __HAL_RCC_GET_APB5_DIV();
1969 }
1970
1971
1972 /**
1973 * @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency
1974 * @note The PLL1 clock frequencies computed by this function is not the real
1975 * frequency in the chip. It is calculated based on the predefined
1976 * constant and the selected clock source:
1977 * @note The function returns values based on HSE_VALUE or HSI_VALUE Value multiplied/divided by the PLL factors.
1978 * @note This function can be used by the user application to compute the
1979 * baud-rate for the communication peripherals or configure other parameters.
1980 *
1981 * @note Each time PLL1CLK changes, this function must be called to update the
1982 * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect.
1983 * @param PLL1_Clocks structure.
1984 * @retval None
1985 */
HAL_RCC_GetPLL1ClockFreq(PLL1_ClocksTypeDef * PLL1_Clocks)1986 __weak void HAL_RCC_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
1987 {
1988 uint32_t pllsource = 0U, pll1m = 1U, pll1fracen = 0U, hsivalue = 0U;
1989 float fracn1, pll1vco = 0;
1990
1991 pllsource = __HAL_RCC_GET_PLL12_SOURCE();
1992 pll1m = ((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVM1) >> RCC_PLL1CFGR1_DIVM1_Pos) + 1U;
1993 pll1fracen = (RCC->PLL1FRACR & RCC_PLL1FRACR_FRACLE) >> RCC_PLL1FRACR_FRACLE_Pos;
1994 fracn1 = (float)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACV) >> RCC_PLL1FRACR_FRACV_Pos));
1995 pll1vco = (float)((float)((RCC->PLL1CFGR1 & RCC_PLL1CFGR1_DIVN) + 1U) + (fracn1 / (float)0x2000)); //Intermediary value
1996 switch (pllsource)
1997 {
1998 case RCC_PLL12SOURCE_HSI: /* HSI used as PLL clock source */
1999
2000 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
2001 {
2002 hsivalue = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2003 pll1vco *= (float)(hsivalue / pll1m);
2004 }
2005 else
2006 {
2007 pll1vco *= (float)(HSI_VALUE / pll1m);
2008 }
2009 break;
2010
2011 case RCC_PLL12SOURCE_HSE: /* HSE used as PLL clock source */
2012 pll1vco *= (float)(HSE_VALUE / pll1m);
2013 break;
2014
2015 case RCC_PLL12SOURCE_OFF: /* No clock source for PLL */
2016 pll1vco = 0;
2017 break;
2018
2019 default:
2020 pll1vco = 0;
2021 break;
2022 }
2023
2024 PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(pll1vco / ((float)(((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVP) >> RCC_PLL1CFGR2_DIVP_Pos) + 1U)));
2025 PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(pll1vco / ((float)(((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVQ) >> RCC_PLL1CFGR2_DIVQ_Pos) + 1U)));
2026 PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(pll1vco / ((float)(((RCC->PLL1CFGR2 & RCC_PLL1CFGR2_DIVR) >> RCC_PLL1CFGR2_DIVR_Pos) + 1U)));
2027 }
2028
2029
2030 /**
2031 * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency
2032 * @note The PLL2 clock frequencies computed by this function is not the real
2033 * frequency in the chip. It is calculated based on the predefined
2034 * constant and the selected clock source:
2035 * @note The function returns values based on HSE_VALUE or HSI_VALUE Value multiplied/divided by the PLL factors.
2036 * @note This function can be used by the user application to compute the
2037 * baud-rate for the communication peripherals or configure other parameters.
2038 *
2039 * @note Each time PLL2CLK changes, this function must be called to update the
2040 * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect.
2041 * @param PLL2_Clocks structure.
2042 * @retval None
2043 */
HAL_RCC_GetPLL2ClockFreq(PLL2_ClocksTypeDef * PLL2_Clocks)2044 __weak void HAL_RCC_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
2045 {
2046 uint32_t pllsource = 0U, pll2m = 1U, pll2fracen = 0U, hsivalue = 0U;
2047 float fracn1, pll2vco = 0;
2048
2049 pllsource = __HAL_RCC_GET_PLL12_SOURCE();
2050 pll2m = ((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVM2) >> RCC_PLL2CFGR1_DIVM2_Pos) + 1U;
2051 pll2fracen = (RCC->PLL2FRACR & RCC_PLL2FRACR_FRACLE) >> RCC_PLL2FRACR_FRACLE_Pos;
2052 fracn1 = (float)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACV) >> RCC_PLL2FRACR_FRACV_Pos));
2053 pll2vco = (float)((float)((RCC->PLL2CFGR1 & RCC_PLL2CFGR1_DIVN) + 1U) + (fracn1 / (float)0x2000)); //Intermediary value
2054 switch (pllsource)
2055 {
2056 case RCC_PLL12SOURCE_HSI: /* HSI used as PLL clock source */
2057 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
2058 {
2059 hsivalue = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2060 pll2vco *= (float)(hsivalue / pll2m);
2061 }
2062 else
2063 {
2064 pll2vco *= (float)(HSI_VALUE / pll2m);
2065 }
2066 break;
2067
2068 case RCC_PLL12SOURCE_HSE: /* HSE used as PLL clock source */
2069 pll2vco *= (float)(HSE_VALUE / pll2m);
2070 break;
2071
2072 case RCC_PLL12SOURCE_OFF: /* No clock source for PLL */
2073 pll2vco = 0;
2074 break;
2075
2076 default:
2077 pll2vco = 0;
2078 break;
2079 }
2080
2081 PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(pll2vco / ((float)(((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVP) >> RCC_PLL2CFGR2_DIVP_Pos) + 1U)));
2082 PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(pll2vco / ((float)(((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVQ) >> RCC_PLL2CFGR2_DIVQ_Pos) + 1U)));
2083 PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(pll2vco / ((float)(((RCC->PLL2CFGR2 & RCC_PLL2CFGR2_DIVR) >> RCC_PLL2CFGR2_DIVR_Pos) + 1U)));
2084 }
2085
2086
2087 /**
2088 * @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency
2089 * @note The PLL3 clock frequencies computed by this function is not the real
2090 * frequency in the chip. It is calculated based on the predefined
2091 * constant and the selected clock source:
2092 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
2093 * @note This function can be used by the user application to compute the
2094 * baud-rate for the communication peripherals or configure other parameters.
2095 *
2096 * @note Each time PLL3CLK changes, this function must be called to update the
2097 * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect.
2098 * @param PLL3_Clocks structure.
2099 * @retval None
2100 */
HAL_RCC_GetPLL3ClockFreq(PLL3_ClocksTypeDef * PLL3_Clocks)2101 __weak void HAL_RCC_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
2102 {
2103 uint32_t pllsource = 0, pll3m = 1, pll3fracen = 0, hsivalue = 0;
2104 float fracn1, pll3vco = 0;
2105
2106 pllsource = __HAL_RCC_GET_PLL3_SOURCE();
2107 pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U;
2108 pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> RCC_PLL3FRACR_FRACLE_Pos;
2109 fracn1 = (float)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> RCC_PLL3FRACR_FRACV_Pos));
2110 pll3vco = (float)((float)((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x2000)); //Intermediary value
2111 switch (pllsource)
2112 {
2113 case RCC_PLL3SOURCE_HSI: /* HSI used as PLL clock source */
2114 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
2115 {
2116 hsivalue = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2117 pll3vco *= (float)(hsivalue / pll3m);
2118 }
2119 else
2120 {
2121 pll3vco *= (float)(HSI_VALUE / pll3m);
2122 }
2123 break;
2124
2125 case RCC_PLL3SOURCE_HSE: /* HSE used as PLL clock source */
2126 pll3vco *= (float)(HSE_VALUE / pll3m);
2127 break;
2128
2129
2130
2131 case RCC_PLL3SOURCE_CSI: /* CSI used as PLL clock source */
2132 pll3vco *= (float)(CSI_VALUE / pll3m);
2133 break;
2134
2135 case RCC_PLL3SOURCE_OFF: /* No clock source for PLL */
2136 pll3vco = 0;
2137 break;
2138 }
2139
2140 PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(pll3vco / ((float)(((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) >> RCC_PLL3CFGR2_DIVP_Pos) + 1U)));
2141 PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(pll3vco / ((float)(((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVQ) >> RCC_PLL3CFGR2_DIVQ_Pos) + 1U)));
2142 PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(pll3vco / ((float)(((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVR) >> RCC_PLL3CFGR2_DIVR_Pos) + 1U)));
2143 }
2144
2145
2146 /**
2147 * @brief Returns the PLL4 clock frequencies :PLL4_P_Frequency,PLL4_R_Frequency and PLL4_Q_Frequency
2148 * @note The PLL4 clock frequencies computed by this function is not the real
2149 * frequency in the chip. It is calculated based on the predefined
2150 * constant and the selected clock source:
2151 * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL factors.
2152 * @note This function can be used by the user application to compute the
2153 * baud-rate for the communication peripherals or configure other parameters.
2154 *
2155 * @note Each time PLL4CLK changes, this function must be called to update the
2156 * right PLL4CLK value. Otherwise, any configuration based on this function will be incorrect.
2157 * @param PLL4_Clocks structure.
2158 * @retval None
2159 */
HAL_RCC_GetPLL4ClockFreq(PLL4_ClocksTypeDef * PLL4_Clocks)2160 __weak void HAL_RCC_GetPLL4ClockFreq(PLL4_ClocksTypeDef *PLL4_Clocks)
2161 {
2162 uint32_t pllsource = 0U, pll4m = 1U, pll4fracen = 0U, hsivalue = 0U;
2163 float fracn1, pll4vco = 0;
2164
2165 pllsource = __HAL_RCC_GET_PLL4_SOURCE();
2166 pll4m = ((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVM4) >> RCC_PLL4CFGR1_DIVM4_Pos) + 1U;
2167 pll4fracen = (RCC->PLL4FRACR & RCC_PLL4FRACR_FRACLE) >> RCC_PLL4FRACR_FRACLE_Pos;
2168 fracn1 = (float)(pll4fracen * ((RCC->PLL4FRACR & RCC_PLL4FRACR_FRACV) >> RCC_PLL4FRACR_FRACV_Pos));
2169 pll4vco = (float)((float)((RCC->PLL4CFGR1 & RCC_PLL4CFGR1_DIVN) + 1U) + (fracn1 / (float) 0x2000)); //Intermediary value
2170 switch (pllsource)
2171 {
2172 case RCC_PLL4SOURCE_HSI: /* HSI used as PLL clock source */
2173 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
2174 {
2175 hsivalue = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2176 pll4vco *= (float)(hsivalue / pll4m);
2177 }
2178 else
2179 {
2180 pll4vco *= (float)(HSI_VALUE / pll4m);
2181 }
2182 break;
2183
2184 case RCC_PLL4SOURCE_HSE: /* HSE used as PLL clock source */
2185 pll4vco *= (float)(HSE_VALUE / pll4m);
2186 break;
2187
2188 case RCC_PLL4SOURCE_CSI: /* CSI used as PLL clock source */
2189 pll4vco *= (float)(CSI_VALUE / pll4m);
2190 break;
2191
2192 case RCC_PLL4SOURCE_I2S_CKIN: /* Signal I2S_CKIN used as reference clock */
2193 pll4vco *= (float)(EXTERNAL_CLOCK_VALUE / pll4m);
2194 break;
2195 }
2196
2197 PLL4_Clocks->PLL4_P_Frequency = (uint32_t)(pll4vco / ((float)(((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVP) >> RCC_PLL4CFGR2_DIVP_Pos) + 1U)));
2198 PLL4_Clocks->PLL4_Q_Frequency = (uint32_t)(pll4vco / ((float)(((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVQ) >> RCC_PLL4CFGR2_DIVQ_Pos) + 1U)));
2199 PLL4_Clocks->PLL4_R_Frequency = (uint32_t)(pll4vco / ((float)(((RCC->PLL4CFGR2 & RCC_PLL4CFGR2_DIVR) >> RCC_PLL4CFGR2_DIVR_Pos) + 1U)));
2200 }
2201
2202 /**
2203 * @brief Returns the PCLK1 frequency
2204 * @note Each time PCLK1 changes, this function must be called to update the
2205 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
2206 * @retval PCLK1 frequency
2207 */
HAL_RCC_GetPCLK1Freq(void)2208 uint32_t HAL_RCC_GetPCLK1Freq(void)
2209 {
2210 uint32_t apb1div = 0;
2211
2212 /* Compute PCLK1 frequency ---------------------------*/
2213 apb1div = __HAL_RCC_GET_APB1_DIV();
2214 if (apb1div > RCC_APB1_DIV16)
2215 {
2216 apb1div = RCC_APB1_DIV16;
2217 }
2218
2219 return (HAL_RCC_GetMCUFreq() >> apb1div);
2220 }
2221
2222
2223 /**
2224 * @brief Returns the PCLK2 frequency
2225 * @note Each time PCLK2 changes, this function must be called to update the
2226 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
2227 * @retval PCLK2 frequency
2228 */
HAL_RCC_GetPCLK2Freq(void)2229 uint32_t HAL_RCC_GetPCLK2Freq(void)
2230 {
2231 uint32_t apb2div = 0;
2232
2233 /* Compute PCLK2 frequency ---------------------------*/
2234 apb2div = __HAL_RCC_GET_APB2_DIV();
2235 if (apb2div > RCC_APB2_DIV16)
2236 {
2237 apb2div = RCC_APB2_DIV16;
2238 }
2239
2240 return (HAL_RCC_GetMCUFreq() >> apb2div);
2241 }
2242
2243 /**
2244 * @brief Returns the PCLK3 frequency
2245 * @note Each time PCLK3 changes, this function must be called to update the
2246 * right PCLK3 value. Otherwise, any configuration based on this function will be incorrect.
2247 * @retval PCLK3 frequency
2248 */
HAL_RCC_GetPCLK3Freq(void)2249 uint32_t HAL_RCC_GetPCLK3Freq(void)
2250 {
2251 uint32_t apb3div = 0;
2252
2253 /* Compute PCLK3 frequency ---------------------------*/
2254 apb3div = __HAL_RCC_GET_APB3_DIV();
2255 if (apb3div > RCC_APB3_DIV16)
2256 {
2257 apb3div = RCC_APB3_DIV16;
2258 }
2259
2260 return (HAL_RCC_GetMCUFreq() >> apb3div);
2261 }
2262
2263 /**
2264 * @brief Returns the PCLK4 frequency
2265 * @note Each time PCLK4 changes, this function must be called to update the
2266 * right PCLK4 value. Otherwise, any configuration based on this function will be incorrect.
2267 * @retval PCLK4 frequency
2268 */
HAL_RCC_GetPCLK4Freq(void)2269 uint32_t HAL_RCC_GetPCLK4Freq(void)
2270 {
2271 uint32_t apb4div = 0;
2272
2273 /* Compute PCLK4 frequency ---------------------------*/
2274 apb4div = __HAL_RCC_GET_APB4_DIV();
2275 if (apb4div > RCC_APB4_DIV16)
2276 {
2277 apb4div = RCC_APB4_DIV16;
2278 }
2279
2280 return (HAL_RCC_GetACLKFreq() >> apb4div);
2281 }
2282
2283 /**
2284 * @brief Returns the PCLK5 frequency
2285 * @note Each time PCLK5 changes, this function must be called to update the
2286 * right PCLK5 value. Otherwise, any configuration based on this function will be incorrect.
2287 * @retval PCLK5 frequency
2288 */
HAL_RCC_GetPCLK5Freq(void)2289 uint32_t HAL_RCC_GetPCLK5Freq(void)
2290 {
2291 uint32_t apb5div = 0;
2292
2293 /* Compute PCLK5 frequency ---------------------------*/
2294 apb5div = __HAL_RCC_GET_APB5_DIV();
2295 if (apb5div > RCC_APB5_DIV16)
2296 {
2297 apb5div = RCC_APB5_DIV16;
2298 }
2299
2300 return (HAL_RCC_GetACLKFreq() >> apb5div);
2301 }
2302
2303 /**
2304 * @brief Returns the ACLK frequency
2305 * @note Each time ACLK changes, this function must be called to update the
2306 * right ACLK value. Otherwise, any configuration based on this function will be incorrect.
2307 * @retval ACLK frequency
2308 */
HAL_RCC_GetACLKFreq(void)2309 uint32_t HAL_RCC_GetACLKFreq(void)
2310 {
2311 uint32_t axidiv = 0;
2312
2313 /* Compute ACLK frequency ---------------------------*/
2314 axidiv = __HAL_RCC_GET_AXI_DIV();
2315 if (axidiv > RCC_AXI_DIV4)
2316 {
2317 axidiv = RCC_AXI_DIV4;
2318 }
2319 axidiv += 1;
2320
2321 return HAL_RCC_GetAXISSFreq() / axidiv;
2322 }
2323
2324 /**
2325 * @brief Returns the HCLK5 frequency
2326 * @note Each time HCLK5 changes, this function must be called to update the
2327 * right HCLK5 value. Otherwise, any configuration based on this function will be incorrect.
2328 * @retval HCLK5 frequency
2329 */
HAL_RCC_GetHCLK5Freq(void)2330 uint32_t HAL_RCC_GetHCLK5Freq(void)
2331 {
2332 return HAL_RCC_GetACLKFreq();
2333 }
2334
2335 /**
2336 * @brief Returns the HCLK6 frequency
2337 * @note Each time HCLK6 changes, this function must be called to update the
2338 * right HCLK6 value. Otherwise, any configuration based on this function will be incorrect.
2339 * @retval HCLK6 frequency
2340 */
HAL_RCC_GetHCLK6Freq(void)2341 uint32_t HAL_RCC_GetHCLK6Freq(void)
2342 {
2343 return HAL_RCC_GetACLKFreq();
2344 }
2345
2346 /**
2347 * @brief Returns the HCLK1 frequency
2348 * @note Each time HCLK1 changes, this function must be called to update the
2349 * right HCLK1 value. Otherwise, any configuration based on this function will be incorrect.
2350 * @retval HCLK1 frequency
2351 */
HAL_RCC_GetHCLK1Freq(void)2352 uint32_t HAL_RCC_GetHCLK1Freq(void)
2353 {
2354 return HAL_RCC_GetMCUFreq();
2355 }
2356
2357 /**
2358 * @brief Returns the HCLK2 frequency
2359 * @note Each time HCLK1 changes, this function must be called to update the
2360 * right HCLK1 value. Otherwise, any configuration based on this function will be incorrect.
2361 * @retval HCLK2 frequency
2362 */
HAL_RCC_GetHCLK2Freq(void)2363 uint32_t HAL_RCC_GetHCLK2Freq(void)
2364 {
2365 return HAL_RCC_GetMCUFreq();
2366 }
2367
2368 /**
2369 * @brief Returns the HCLK3 frequency
2370 * @note Each time HCLK3 changes, this function must be called to update the
2371 * right HCLK3 value. Otherwise, any configuration based on this function will be incorrect.
2372 * @retval HCLK3 frequency
2373 */
HAL_RCC_GetHCLK3Freq(void)2374 uint32_t HAL_RCC_GetHCLK3Freq(void)
2375 {
2376 return HAL_RCC_GetMCUFreq();
2377 }
2378
2379 /**
2380 * @brief Returns the HCLK4 frequency
2381 * @note Each time HCLK4 changes, this function must be called to update the
2382 * right HCLK4 value. Otherwise, any configuration based on this function will be incorrect.
2383 * @retval HCLK4 frequency
2384 */
HAL_RCC_GetHCLK4Freq(void)2385 uint32_t HAL_RCC_GetHCLK4Freq(void)
2386 {
2387 return HAL_RCC_GetMCUFreq();
2388 }
2389
2390 /**
2391 * @brief Returns the MLHCLK frequency
2392 * @note Each time MLHCLK changes, this function must be called to update the
2393 * right MLHCLK value. Otherwise, any configuration based on this function will be incorrect.
2394 * @retval HCLK4 frequency
2395 */
HAL_RCC_GetMLHCLKFreq(void)2396 uint32_t HAL_RCC_GetMLHCLKFreq(void)
2397 {
2398 return HAL_RCC_GetMCUFreq();
2399 }
2400
2401
2402 /**
2403 * @brief Returns the MCU frequency
2404 * @note Each time MCU changes, this function must be called to update the
2405 * right MCU value. Otherwise, any configuration based on this function will be incorrect.
2406 * @retval MCU frequency
2407 */
HAL_RCC_GetMCUFreq(void)2408 uint32_t HAL_RCC_GetMCUFreq(void)
2409 {
2410 uint32_t mcudiv = 0;
2411
2412 /* Compute MCU frequency ---------------------------*/
2413 mcudiv = __HAL_RCC_GET_MCU_DIV();
2414 if (mcudiv > RCC_MCU_DIV512)
2415 {
2416 mcudiv = RCC_MCU_DIV512;
2417 }
2418
2419 return HAL_RCC_GetMCUSSFreq() >> mcudiv;
2420 }
2421
2422
2423 /**
2424 * @brief Returns the FCLK frequency
2425 * @note Each time FCLK changes, this function must be called to update the
2426 * right FCLK value. Otherwise, any configuration based on this function will be incorrect.
2427 * @retval FCLK frequency
2428 */
HAL_RCC_GetFCLKFreq(void)2429 uint32_t HAL_RCC_GetFCLKFreq(void)
2430 {
2431 return HAL_RCC_GetMCUFreq();
2432 }
2433
2434 /**
2435 * @brief Returns the CKPER frequency
2436 * @note Each time CKPER changes, this function must be called to update the
2437 * right CKPER value. Otherwise, any configuration based on this function will be incorrect.
2438 * @retval CKPER frequency
2439 */
RCC_GetCKPERFreq(void)2440 uint32_t RCC_GetCKPERFreq(void)
2441 {
2442 uint32_t ckperclocksource = 0, frequency = 0;
2443
2444 ckperclocksource = __HAL_RCC_GET_CKPER_SOURCE();
2445
2446 if (ckperclocksource == RCC_CKPERCLKSOURCE_HSI)
2447 {
2448 /* In Case the main PLL Source is HSI */
2449 frequency = HSI_VALUE;
2450 }
2451
2452 else if (ckperclocksource == RCC_CKPERCLKSOURCE_CSI)
2453 {
2454 /* In Case the main PLL Source is CSI */
2455 frequency = CSI_VALUE;
2456 }
2457
2458 else if (ckperclocksource == RCC_CKPERCLKSOURCE_HSE)
2459 {
2460 /* In Case the main PLL Source is HSE */
2461 frequency = HSE_VALUE;
2462 }
2463 else
2464 {
2465 frequency = 0;
2466 }
2467
2468 return frequency;
2469 }
2470
2471 /**
2472 * @brief Returns the System Core frequency
2473 *
2474 * @note The system frequency computed by this function is not the real
2475 * frequency in the chip. It is calculated based on the predefined
2476 * constants and the selected clock source
2477 * @retval System Core frequency
2478 */
HAL_RCC_GetSystemCoreClockFreq(void)2479 uint32_t HAL_RCC_GetSystemCoreClockFreq(void)
2480 {
2481 #ifdef CORE_CA7
2482 return HAL_RCC_GetMPUSSFreq();
2483 #else /* CORE_CM4 */
2484 return HAL_RCC_GetMCUFreq();
2485 #endif
2486 }
2487
HAL_RCC_GetMPUSSFreq()2488 uint32_t HAL_RCC_GetMPUSSFreq()
2489 {
2490 uint32_t mpussfreq = 0, mpudiv = 0;
2491 PLL1_ClocksTypeDef pll1_clocks;
2492
2493 switch (__HAL_RCC_GET_MPU_SOURCE())
2494 {
2495 case RCC_MPUSOURCE_PLL1:
2496 HAL_RCC_GetPLL1ClockFreq(&pll1_clocks);
2497 mpussfreq = pll1_clocks.PLL1_P_Frequency;
2498 break;
2499
2500 case RCC_MPUSOURCE_MPUDIV:
2501 mpudiv = __HAL_RCC_GET_MPU_DIV();
2502 if (mpudiv == RCC_MPU_DIV_OFF)
2503 {
2504 mpussfreq = 0;
2505 }
2506 else if (mpudiv <= RCC_MPU_DIV16)
2507 {
2508 HAL_RCC_GetPLL1ClockFreq(&pll1_clocks);
2509 mpussfreq = (pll1_clocks.PLL1_P_Frequency >> mpudiv);
2510 }
2511 else
2512 {
2513 HAL_RCC_GetPLL1ClockFreq(&pll1_clocks);
2514 mpussfreq = (pll1_clocks.PLL1_P_Frequency >> 16); /* divided by 16 */
2515 }
2516 break;
2517
2518 case RCC_MPUSOURCE_HSI:
2519 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
2520 {
2521 mpussfreq = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2522 }
2523 else
2524 {
2525 mpussfreq = HSI_VALUE;
2526 }
2527 break;
2528
2529 case RCC_MPUSOURCE_HSE:
2530 mpussfreq = HSE_VALUE;
2531 break;
2532 }
2533
2534 return mpussfreq;
2535 }
2536
2537
HAL_RCC_GetAXISSFreq()2538 uint32_t HAL_RCC_GetAXISSFreq()
2539 {
2540 uint32_t axissfreq = 0;
2541 PLL2_ClocksTypeDef pll2_clocks;
2542
2543 switch (__HAL_RCC_GET_AXIS_SOURCE())
2544 {
2545 case RCC_AXISSOURCE_PLL2:
2546 HAL_RCC_GetPLL2ClockFreq(&pll2_clocks);
2547 axissfreq = pll2_clocks.PLL2_P_Frequency;
2548 break;
2549
2550 case RCC_AXISSOURCE_HSI:
2551 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIVRDY) != 0U)
2552 {
2553 axissfreq = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2554 }
2555 else
2556 {
2557 axissfreq = HSI_VALUE;
2558 }
2559 break;
2560
2561 case RCC_AXISSOURCE_HSE:
2562 axissfreq = HSE_VALUE;
2563 break;
2564
2565 case RCC_AXISSOURCE_OFF:
2566 default:
2567 axissfreq = 0; /* ck_axiss is gated */
2568 break;
2569 }
2570
2571 return axissfreq;
2572 }
2573
HAL_RCC_GetMCUSSFreq()2574 uint32_t HAL_RCC_GetMCUSSFreq()
2575 {
2576 uint32_t mcussfreq = 0;
2577 PLL3_ClocksTypeDef pll3_clocks;
2578
2579 switch (__HAL_RCC_GET_MCU_SOURCE())
2580 {
2581 case RCC_MCUSSOURCE_PLL3:
2582 HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
2583 mcussfreq = pll3_clocks.PLL3_P_Frequency;
2584 break;
2585
2586 case RCC_MCUSSOURCE_HSI:
2587 mcussfreq = (HSI_VALUE >> __HAL_RCC_GET_HSI_DIV());
2588
2589 break;
2590
2591 case RCC_MCUSSOURCE_HSE:
2592 mcussfreq = HSE_VALUE;
2593 break;
2594
2595 case RCC_MCUSSOURCE_CSI:
2596 mcussfreq = CSI_VALUE;
2597 break;
2598 }
2599
2600 return mcussfreq;
2601 }
2602
2603
2604
2605 /**
2606 * @brief This function handles the RCC global interrupt (rcc_mcu_irq/rcc_mpu_irq)
2607 * @note This API should be called under the RCC_Handler().
2608 * @retval None
2609 */
HAL_RCC_IRQHandler(void)2610 void HAL_RCC_IRQHandler(void)
2611 {
2612 #if defined(CORE_CM4)
2613 uint32_t flags = (READ_REG(RCC->MC_CIFR) & RCC_IT_ALL);
2614 #endif /* CORE_CM4 */
2615 #if defined(CORE_CA7)
2616 uint32_t flags = (READ_REG(RCC->MP_CIFR) & RCC_IT_ALL);
2617 #endif
2618 /* Clear the RCC interrupt bits */
2619 __HAL_RCC_CLEAR_IT(flags);
2620
2621 if ((flags & RCC_IT_LSECSS) != RESET)
2622 {
2623 /* Enable write access to Backup domain */
2624 SET_BIT(PWR->CR1, PWR_CR1_DBP);
2625
2626 /* Clear LSECSSON bit */
2627 HAL_RCCEx_DisableLSECSS();
2628 /* Clear LSEON bit */
2629 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2630 }
2631
2632 /* RCC interrupt user callback */
2633 HAL_RCC_Callback(flags);
2634 }
2635
2636
2637 /**
2638 * @brief RCC global interrupt callback
2639 * @param Flags: It contains the flags which were set during the RCC_IRQHandler
2640 * before cleaning them
2641 * @retval None
2642 */
HAL_RCC_Callback(uint32_t Flags)2643 __weak void HAL_RCC_Callback(uint32_t Flags)
2644 {
2645 /* Prevent unused argument compilation warning */
2646 UNUSED(Flags);
2647
2648 /* NOTE : This function Should not be modified, when the callback is needed,
2649 the HAL_RCC_Callback could be implemented in the user file
2650 */
2651 }
2652
2653
2654 /**
2655 * @brief This function handles the RCC Wake up interrupt (rcc_mcu_wkup_irq/rcc_mpu_wkup_irq)
2656 * @note This API should be called under the RCC_WAKEUP_Handler().
2657 * @retval None
2658 */
HAL_RCC_WAKEUP_IRQHandler(void)2659 void HAL_RCC_WAKEUP_IRQHandler(void)
2660 {
2661 /* Check RCC WKUP flag is set */
2662 if (__HAL_RCC_GET_IT(RCC_IT_WKUP) != RESET)
2663 {
2664 /* Clear the RCC WKUP flag bit */
2665 __HAL_RCC_CLEAR_IT(RCC_IT_WKUP);
2666
2667 /* RCC WKUP interrupt user callback */
2668 HAL_RCC_WAKEUP_Callback();
2669 }
2670 }
2671
2672
2673 /**
2674 * @brief RCC WAKEUP interrupt callback
2675 * @retval None
2676 */
HAL_RCC_WAKEUP_Callback(void)2677 __weak void HAL_RCC_WAKEUP_Callback(void)
2678 {
2679 /* NOTE : This function Should not be modified, when the callback is needed,
2680 the HAL_RCC_WAKEUP_Callback could be implemented in the user file
2681 */
2682 }
2683
2684
2685 /**
2686 * @}
2687 */
2688
2689 /**
2690 * @}
2691 */
2692
2693 #endif /* HAL_RCC_MODULE_ENABLED */
2694 /**
2695 * @}
2696 */
2697
2698 /**
2699 * @}
2700 */
2701
