1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_qspi.h 4 * @author MCD Application Team 5 * @brief Header file of QSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_HAL_QSPI_H 38 #define STM32L4xx_HAL_QSPI_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32l4xx_hal_def.h" 46 47 #if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) 48 49 /** @addtogroup STM32L4xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup QSPI 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** @defgroup QSPI_Exported_Types QSPI Exported Types 59 * @{ 60 */ 61 62 /** 63 * @brief QSPI Init structure definition 64 */ 65 typedef struct 66 { 67 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 68 This parameter can be a number between 0 and 255 */ 69 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 70 This parameter can be a value between 1 and 16 */ 71 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 72 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 73 This parameter can be a value of @ref QSPI_SampleShifting */ 74 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 75 required to address the flash memory. The flash capacity can be up to 4GB 76 (addressed using 32 bits) in indirect mode, but the addressable space in 77 memory-mapped mode is limited to 256MB 78 This parameter can be a number between 0 and 31 */ 79 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 80 of clock cycles which the chip select must remain high between commands. 81 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 82 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 83 This parameter can be a value of @ref QSPI_ClockMode */ 84 #if defined(QUADSPI_CR_DFM) 85 uint32_t FlashID; /* Specifies the Flash which will be used, 86 This parameter can be a value of @ref QSPI_Flash_Select */ 87 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 88 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 89 #endif 90 }QSPI_InitTypeDef; 91 92 /** 93 * @brief HAL QSPI State structures definition 94 */ 95 typedef enum 96 { 97 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 98 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 99 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 100 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 101 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 102 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 103 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 104 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 105 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 106 }HAL_QSPI_StateTypeDef; 107 108 /** 109 * @brief QSPI Handle Structure definition 110 */ 111 typedef struct __QSPI_HandleTypeDef 112 { 113 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 114 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 115 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 116 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 117 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 118 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 119 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 120 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 121 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ 122 __IO HAL_LockTypeDef Lock; /* Locking object */ 123 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 124 __IO uint32_t ErrorCode; /* QSPI Error code */ 125 uint32_t Timeout; /* Timeout for the QSPI memory access */ 126 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 127 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 128 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 129 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 130 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 131 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 132 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 133 void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 134 void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 135 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 136 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 137 138 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 139 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 140 #endif 141 }QSPI_HandleTypeDef; 142 143 /** 144 * @brief QSPI Command structure definition 145 */ 146 typedef struct 147 { 148 uint32_t Instruction; /* Specifies the Instruction to be sent 149 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 150 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 151 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 152 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 153 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 154 uint32_t AddressSize; /* Specifies the Address Size 155 This parameter can be a value of @ref QSPI_AddressSize */ 156 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 157 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 158 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 159 This parameter can be a number between 0 and 31 */ 160 uint32_t InstructionMode; /* Specifies the Instruction Mode 161 This parameter can be a value of @ref QSPI_InstructionMode */ 162 uint32_t AddressMode; /* Specifies the Address Mode 163 This parameter can be a value of @ref QSPI_AddressMode */ 164 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 165 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 166 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 167 This parameter can be a value of @ref QSPI_DataMode */ 168 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 169 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 170 until end of memory)*/ 171 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 172 This parameter can be a value of @ref QSPI_DdrMode */ 173 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data 174 output by one half of system clock in DDR mode. 175 Not available on all devices. 176 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 177 uint32_t SIOOMode; /* Specifies the send instruction only once mode 178 This parameter can be a value of @ref QSPI_SIOOMode */ 179 }QSPI_CommandTypeDef; 180 181 /** 182 * @brief QSPI Auto Polling mode configuration structure definition 183 */ 184 typedef struct 185 { 186 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 187 This parameter can be any value between 0 and 0xFFFFFFFF */ 188 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 189 This parameter can be any value between 0 and 0xFFFFFFFF */ 190 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 191 This parameter can be any value between 0 and 0xFFFF */ 192 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 193 This parameter can be any value between 1 and 4 */ 194 uint32_t MatchMode; /* Specifies the method used for determining a match. 195 This parameter can be a value of @ref QSPI_MatchMode */ 196 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 197 This parameter can be a value of @ref QSPI_AutomaticStop */ 198 }QSPI_AutoPollingTypeDef; 199 200 /** 201 * @brief QSPI Memory Mapped mode configuration structure definition 202 */ 203 typedef struct 204 { 205 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 206 This parameter can be any value between 0 and 0xFFFF */ 207 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 208 This parameter can be a value of @ref QSPI_TimeOutActivation */ 209 }QSPI_MemoryMappedTypeDef; 210 211 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 212 /** 213 * @brief HAL QSPI Callback ID enumeration definition 214 */ 215 typedef enum 216 { 217 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 218 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 219 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 220 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 221 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 222 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 223 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ 224 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ 225 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 226 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 227 228 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 229 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 230 }HAL_QSPI_CallbackIDTypeDef; 231 232 /** 233 * @brief HAL QSPI Callback pointer definition 234 */ 235 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 236 #endif 237 /** 238 * @} 239 */ 240 241 /* Exported constants --------------------------------------------------------*/ 242 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 243 * @{ 244 */ 245 246 /** @defgroup QSPI_ErrorCode QSPI Error Code 247 * @{ 248 */ 249 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 250 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 251 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 252 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 253 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 254 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 255 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 256 #endif 257 /** 258 * @} 259 */ 260 261 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 262 * @{ 263 */ 264 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 265 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 266 /** 267 * @} 268 */ 269 270 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 271 * @{ 272 */ 273 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 274 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 275 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 276 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 277 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 278 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 279 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 280 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 281 /** 282 * @} 283 */ 284 285 /** @defgroup QSPI_ClockMode QSPI Clock Mode 286 * @{ 287 */ 288 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 289 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 290 /** 291 * @} 292 */ 293 294 #if defined(QUADSPI_CR_DFM) 295 /** @defgroup QSPI_Flash_Select QSPI Flash Select 296 * @{ 297 */ 298 #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ 299 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ 300 /** 301 * @} 302 */ 303 304 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 305 * @{ 306 */ 307 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ 308 #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ 309 /** 310 * @} 311 */ 312 313 #endif 314 /** @defgroup QSPI_AddressSize QSPI Address Size 315 * @{ 316 */ 317 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 318 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 319 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 320 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 321 /** 322 * @} 323 */ 324 325 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 326 * @{ 327 */ 328 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 329 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 330 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 331 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 332 /** 333 * @} 334 */ 335 336 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 337 * @{ 338 */ 339 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 340 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 341 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 342 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 343 /** 344 * @} 345 */ 346 347 /** @defgroup QSPI_AddressMode QSPI Address Mode 348 * @{ 349 */ 350 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 351 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 352 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 353 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 354 /** 355 * @} 356 */ 357 358 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 359 * @{ 360 */ 361 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 362 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 363 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 364 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 365 /** 366 * @} 367 */ 368 369 /** @defgroup QSPI_DataMode QSPI Data Mode 370 * @{ 371 */ 372 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 373 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 374 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 375 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 376 /** 377 * @} 378 */ 379 380 /** @defgroup QSPI_DdrMode QSPI DDR Mode 381 * @{ 382 */ 383 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 384 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 385 /** 386 * @} 387 */ 388 389 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 390 * @{ 391 */ 392 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 393 #if defined(QUADSPI_CCR_DHHC) 394 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ 395 #endif 396 /** 397 * @} 398 */ 399 400 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 401 * @{ 402 */ 403 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 404 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 405 /** 406 * @} 407 */ 408 409 /** @defgroup QSPI_MatchMode QSPI Match Mode 410 * @{ 411 */ 412 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 413 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 414 /** 415 * @} 416 */ 417 418 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 419 * @{ 420 */ 421 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 422 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 423 /** 424 * @} 425 */ 426 427 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 428 * @{ 429 */ 430 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 431 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 432 /** 433 * @} 434 */ 435 436 /** @defgroup QSPI_Flags QSPI Flags 437 * @{ 438 */ 439 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 440 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 441 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 442 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 443 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 444 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 445 /** 446 * @} 447 */ 448 449 /** @defgroup QSPI_Interrupts QSPI Interrupts 450 * @{ 451 */ 452 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 453 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 454 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 455 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 456 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 457 /** 458 * @} 459 */ 460 461 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 462 * @brief QSPI Timeout definition 463 * @{ 464 */ 465 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 466 /** 467 * @} 468 */ 469 470 /** 471 * @} 472 */ 473 474 /* Exported macros -----------------------------------------------------------*/ 475 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 476 * @{ 477 */ 478 /** @brief Reset QSPI handle state. 479 * @param __HANDLE__ : QSPI handle. 480 * @retval None 481 */ 482 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 483 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 484 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 485 (__HANDLE__)->MspInitCallback = NULL; \ 486 (__HANDLE__)->MspDeInitCallback = NULL; \ 487 } while(0) 488 #else 489 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 490 #endif 491 492 /** @brief Enable the QSPI peripheral. 493 * @param __HANDLE__ : specifies the QSPI Handle. 494 * @retval None 495 */ 496 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 497 498 /** @brief Disable the QSPI peripheral. 499 * @param __HANDLE__ : specifies the QSPI Handle. 500 * @retval None 501 */ 502 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 503 504 /** @brief Enable the specified QSPI interrupt. 505 * @param __HANDLE__ : specifies the QSPI Handle. 506 * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. 507 * This parameter can be one of the following values: 508 * @arg QSPI_IT_TO: QSPI Timeout interrupt 509 * @arg QSPI_IT_SM: QSPI Status match interrupt 510 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 511 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 512 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 513 * @retval None 514 */ 515 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 516 517 518 /** @brief Disable the specified QSPI interrupt. 519 * @param __HANDLE__ : specifies the QSPI Handle. 520 * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. 521 * This parameter can be one of the following values: 522 * @arg QSPI_IT_TO: QSPI Timeout interrupt 523 * @arg QSPI_IT_SM: QSPI Status match interrupt 524 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 525 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 526 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 527 * @retval None 528 */ 529 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 530 531 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 532 * @param __HANDLE__ : specifies the QSPI Handle. 533 * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. 534 * This parameter can be one of the following values: 535 * @arg QSPI_IT_TO: QSPI Timeout interrupt 536 * @arg QSPI_IT_SM: QSPI Status match interrupt 537 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 538 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 539 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 540 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 541 */ 542 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 543 544 /** 545 * @brief Check whether the selected QSPI flag is set or not. 546 * @param __HANDLE__ : specifies the QSPI Handle. 547 * @param __FLAG__ : specifies the QSPI flag to check. 548 * This parameter can be one of the following values: 549 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 550 * @arg QSPI_FLAG_TO: QSPI Timeout flag 551 * @arg QSPI_FLAG_SM: QSPI Status match flag 552 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 553 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 554 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 555 * @retval None 556 */ 557 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 558 559 /** @brief Clears the specified QSPI's flag status. 560 * @param __HANDLE__ : specifies the QSPI Handle. 561 * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set 562 * This parameter can be one of the following values: 563 * @arg QSPI_FLAG_TO: QSPI Timeout flag 564 * @arg QSPI_FLAG_SM: QSPI Status match flag 565 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 566 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 567 * @retval None 568 */ 569 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 570 /** 571 * @} 572 */ 573 574 /* Exported functions --------------------------------------------------------*/ 575 /** @addtogroup QSPI_Exported_Functions 576 * @{ 577 */ 578 579 /** @addtogroup QSPI_Exported_Functions_Group1 580 * @{ 581 */ 582 /* Initialization/de-initialization functions ********************************/ 583 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 584 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 585 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 586 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 587 /** 588 * @} 589 */ 590 591 /** @addtogroup QSPI_Exported_Functions_Group2 592 * @{ 593 */ 594 /* IO operation functions *****************************************************/ 595 /* QSPI IRQ handler method */ 596 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 597 598 /* QSPI indirect mode */ 599 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 600 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 601 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 602 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 603 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 604 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 605 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 606 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 607 608 /* QSPI status flag polling mode */ 609 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 610 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 611 612 /* QSPI memory-mapped mode */ 613 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 614 615 /* Callback functions in non-blocking modes ***********************************/ 616 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 617 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 618 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 619 620 /* QSPI indirect mode */ 621 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 622 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 623 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 624 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 625 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 626 627 /* QSPI status flag polling mode */ 628 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 629 630 /* QSPI memory-mapped mode */ 631 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 632 633 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 634 /* QSPI callback registering/unregistering */ 635 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); 636 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); 637 #endif 638 /** 639 * @} 640 */ 641 642 /** @addtogroup QSPI_Exported_Functions_Group3 643 * @{ 644 */ 645 /* Peripheral Control and State functions ************************************/ 646 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 647 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 648 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 649 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 650 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 651 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 652 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 653 #if defined(QUADSPI_CR_DFM) 654 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); 655 #endif 656 /** 657 * @} 658 */ 659 660 /** 661 * @} 662 */ 663 /* End of exported functions -------------------------------------------------*/ 664 665 /* Private macros ------------------------------------------------------------*/ 666 /** @defgroup QSPI_Private_Macros QSPI Private Macros 667 * @{ 668 */ 669 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 670 671 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U)) 672 673 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 674 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 675 676 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 677 678 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 679 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 680 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 681 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 682 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 683 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 684 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 685 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 686 687 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 688 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 689 690 #if defined(QUADSPI_CR_DFM) 691 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ 692 ((FLASH_ID) == QSPI_FLASH_ID_2)) 693 694 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 695 ((MODE) == QSPI_DUALFLASH_DISABLE)) 696 697 #endif 698 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 699 700 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 701 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 702 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 703 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 704 705 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 706 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 707 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 708 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 709 710 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 711 712 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 713 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 714 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 715 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 716 717 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 718 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 719 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 720 ((MODE) == QSPI_ADDRESS_4_LINES)) 721 722 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 723 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 724 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 725 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 726 727 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 728 ((MODE) == QSPI_DATA_1_LINE) || \ 729 ((MODE) == QSPI_DATA_2_LINES) || \ 730 ((MODE) == QSPI_DATA_4_LINES)) 731 732 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 733 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 734 735 #if defined(QUADSPI_CCR_DHHC) 736 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 737 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 738 739 #else 740 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) 741 742 #endif 743 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 744 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 745 746 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 747 748 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 749 750 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 751 ((MODE) == QSPI_MATCH_MODE_OR)) 752 753 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 754 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 755 756 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 757 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 758 759 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 760 /** 761 * @} 762 */ 763 /* End of private macros -----------------------------------------------------*/ 764 765 /** 766 * @} 767 */ 768 769 /** 770 * @} 771 */ 772 773 #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ 774 775 #ifdef __cplusplus 776 } 777 #endif 778 779 #endif /* STM32L4xx_HAL_QSPI_H */ 780 781 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 782
