1 /* 2 * Copyright (c) 2023 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_FLASH_OSPI_STM32_H_ 8 #define ZEPHYR_DRIVERS_FLASH_OSPI_STM32_H_ 9 10 #if defined(CONFIG_SOC_SERIES_STM32H5X) 11 12 #define NbData DataLength 13 #define AddressSize AddressWidth 14 #define InstructionDtrMode InstructionDTRMode 15 #define AddressDtrMode AddressDTRMode 16 #define DataDtrMode DataDTRMode 17 #define InstructionSize InstructionWidth 18 #define FifoThreshold FifoThresholdByte 19 #define ChipSelectHighTime ChipSelectHighTimeCycle 20 #define FlashId IOSelect 21 #define Match MatchValue 22 #define Mask MatchMask 23 #define Interval IntervalTime 24 #define DeviceSize MemorySize 25 #define DualQuad MemoryMode 26 27 #define OSPI_InitTypeDef XSPI_InitTypeDef 28 #define OSPI_HandleTypeDef XSPI_HandleTypeDef 29 #define OSPI_RegularCmdTypeDef XSPI_RegularCmdTypeDef 30 #define OSPI_AutoPollingTypeDef XSPI_AutoPollingTypeDef 31 32 #define HAL_OSPI_Init HAL_XSPI_Init 33 #define HAL_OSPI_Command HAL_XSPI_Command 34 #define HAL_OSPI_Receive HAL_XSPI_Receive 35 #define HAL_OSPI_Receive_DMA HAL_XSPI_Receive_DMA 36 #define HAL_OSPI_Receive_IT HAL_XSPI_Receive_IT 37 #define HAL_OSPI_Transmit HAL_XSPI_Transmit 38 #define HAL_OSPI_Transmit_DMA HAL_XSPI_Transmit_DMA 39 #define HAL_OSPI_Transmit_IT HAL_XSPI_Transmit_IT 40 #define HAL_OSPI_AutoPolling HAL_XSPI_AutoPolling 41 #define HAL_OSPI_IRQHandler HAL_XSPI_IRQHandler 42 43 #define HAL_OSPI_ErrorCallback HAL_XSPI_ErrorCallback 44 #define HAL_OSPI_CmdCpltCallback HAL_XSPI_CmdCpltCallback 45 #define HAL_OSPI_RxCpltCallback HAL_XSPI_RxCpltCallback 46 #define HAL_OSPI_TxCpltCallback HAL_XSPI_TxCpltCallback 47 #define HAL_OSPI_StatusMatchCallback HAL_XSPI_StatusMatchCallback 48 #define HAL_OSPI_TimeOutCallback HAL_XSPI_TimeOutCallback 49 50 #define HAL_OSPI_ADDRESS_NONE HAL_XSPI_ADDRESS_NONE 51 #define HAL_OSPI_ADDRESS_8_LINES HAL_XSPI_ADDRESS_8_LINES 52 #define HAL_OSPI_ADDRESS_4_LINES HAL_XSPI_ADDRESS_4_LINES 53 #define HAL_OSPI_ADDRESS_2_LINES HAL_XSPI_ADDRESS_2_LINES 54 #define HAL_OSPI_ADDRESS_1_LINE HAL_XSPI_ADDRESS_1_LINE 55 #define HAL_OSPI_ADDRESS_32_BITS HAL_XSPI_ADDRESS_32_BITS 56 #define HAL_OSPI_ADDRESS_24_BITS HAL_XSPI_ADDRESS_24_BITS 57 #define HAL_OSPI_ADDRESS_16_BITS HAL_XSPI_ADDRESS_16_BITS 58 #define HAL_OSPI_ADDRESS_8_BITS HAL_XSPI_ADDRESS_8_BITS 59 #define HAL_OSPI_ADDRESS_DTR_ENABLE HAL_XSPI_ADDRESS_DTR_ENABLE 60 #define HAL_OSPI_ADDRESS_DTR_DISABLE HAL_XSPI_ADDRESS_DTR_DISABLE 61 #define HAL_OSPI_INSTRUCTION_8_LINES HAL_XSPI_INSTRUCTION_8_LINES 62 #define HAL_OSPI_INSTRUCTION_4_LINES HAL_XSPI_INSTRUCTION_4_LINES 63 #define HAL_OSPI_INSTRUCTION_2_LINES HAL_XSPI_INSTRUCTION_2_LINES 64 #define HAL_OSPI_INSTRUCTION_1_LINE HAL_XSPI_INSTRUCTION_1_LINE 65 #define HAL_OSPI_INSTRUCTION_32_BITS HAL_XSPI_INSTRUCTION_32_BITS 66 #define HAL_OSPI_INSTRUCTION_16_BITS HAL_XSPI_INSTRUCTION_16_BITS 67 #define HAL_OSPI_INSTRUCTION_8_BITS HAL_XSPI_INSTRUCTION_8_BITS 68 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE HAL_XSPI_INSTRUCTION_DTR_ENABLE 69 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE HAL_XSPI_INSTRUCTION_DTR_DISABLE 70 71 #define HAL_OSPI_ALTERNATE_BYTES_NONE HAL_XSPI_ALT_BYTES_NONE 72 #define HAL_OSPI_DATA_NONE HAL_XSPI_DATA_NONE 73 #define HAL_OSPI_DATA_8_LINES HAL_XSPI_DATA_8_LINES 74 #define HAL_OSPI_DATA_4_LINES HAL_XSPI_DATA_4_LINES 75 #define HAL_OSPI_DATA_2_LINES HAL_XSPI_DATA_2_LINES 76 #define HAL_OSPI_DATA_1_LINE HAL_XSPI_DATA_1_LINE 77 #define HAL_OSPI_DATA_DTR_ENABLE HAL_XSPI_DATA_DTR_ENABLE 78 #define HAL_OSPI_DATA_DTR_DISABLE HAL_XSPI_DATA_DTR_DISABLE 79 #define HAL_OSPI_DQS_ENABLE HAL_XSPI_DQS_ENABLE 80 #define HAL_OSPI_DQS_DISABLE HAL_XSPI_DQS_DISABLE 81 82 #define HAL_OSPI_MATCH_MODE_AND HAL_XSPI_MATCH_MODE_AND 83 #define HAL_OSPI_SIOO_INST_EVERY_CMD HAL_XSPI_SIOO_INST_EVERY_CMD 84 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE HAL_XSPI_AUTOMATIC_STOP_ENABLE 85 #define HAL_OSPI_OPTYPE_COMMON_CFG HAL_XSPI_OPTYPE_COMMON_CFG 86 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE HAL_XSPI_TIMEOUT_DEFAULT_VALUE 87 88 #define HAL_OSPI_CLOCK_MODE_0 HAL_XSPI_CLOCK_MODE_0 89 #define HAL_OSPI_FLASH_ID_1 HAL_XSPI_SELECT_IO_7_0 90 #define HAL_OSPI_DUALQUAD_DISABLE HAL_XSPI_SINGLE_MEM 91 #define HAL_OSPI_DUALQUAD_ENABLE HAL_XSPI_DUAL_MEM 92 #define HAL_OSPI_SAMPLE_SHIFTING_NONE HAL_XSPI_SAMPLE_SHIFT_NONE 93 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE 94 #define HAL_OSPI_DELAY_BLOCK_USED HAL_XSPI_DELAY_BLOCK_ON 95 #define HAL_OSPI_DELAY_BLOCK_BYPASSED HAL_XSPI_DELAY_BLOCK_BYPASS 96 #define HAL_OSPI_MEMTYPE_MICRON HAL_XSPI_MEMTYPE_MICRON 97 #define HAL_OSPI_MEMTYPE_MACRONIX HAL_XSPI_MEMTYPE_MACRONIX 98 #define HAL_OSPI_DHQC_ENABLE HAL_XSPI_DHQC_ENABLE 99 #define HAL_OSPI_DHQC_DISABLE HAL_XSPI_DHQC_DISABLE 100 #define HAL_OSPI_WRAP_NOT_SUPPORTED HAL_XSPI_WRAP_NOT_SUPPORTED 101 #define HAL_OSPI_FREERUNCLK_DISABLE HAL_XSPI_FREERUNCLK_DISABLE 102 #endif /* CONFIG_SOC_SERIES_STM32H5X */ 103 104 #endif /* ZEPHYR_DRIVERS_FLASH_OSPIH_STM32_H_ */ 105
