1 /** 2 ********************************************************************************************************************** 3 * @file stm32h5xx_hal_i3c.h 4 * @author MCD Application Team 5 * @brief Header file of I3C HAL module. 6 ********************************************************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2022 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ********************************************************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ 20 #ifndef STM32H5xx_HAL_I3C_H 21 #define STM32H5xx_HAL_I3C_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 28 /* Includes ----------------------------------------------------------------------------------------------------------*/ 29 #include "stm32h5xx_hal_def.h" 30 #include "stm32h5xx_ll_i3c.h" 31 32 /** @addtogroup STM32H5xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup I3C 37 * @{ 38 */ 39 40 /* Exported types ----------------------------------------------------------------------------------------------------*/ 41 /** @defgroup I3C_Exported_Types I3C Exported Types 42 * @{ 43 */ 44 /** @defgroup I3C_Init_Structure_definition I3C Init Structure definition 45 * @brief I3C Init Structure definition 46 * @{ 47 */ 48 typedef struct 49 { 50 LL_I3C_CtrlBusConfTypeDef CtrlBusCharacteristic; /*!< Specifies the I3C controller bus characteristic configuration 51 when Controller mode */ 52 53 LL_I3C_TgtBusConfTypeDef TgtBusCharacteristic; /*!< Specifies the I3C target bus characteristic configuration 54 when Target mode */ 55 56 } I3C_InitTypeDef; 57 /** 58 * @} 59 */ 60 61 /** @defgroup I3C_FIFO_Config_Structure_definition I3C FIFO Configuration Structure definition 62 * @brief I3C FIFO configuration structure definition 63 * @{ 64 */ 65 typedef struct 66 { 67 uint32_t RxFifoThreshold; /*!< Specifies the I3C Rx FIFO threshold level. 68 This parameter must be a value of @ref I3C_RX_FIFO_THRESHOLD */ 69 70 uint32_t TxFifoThreshold; /*!< Specifies the I3C Tx FIFO threshold level. 71 This parameter must be a value of @ref I3C_TX_FIFO_THRESHOLD */ 72 73 uint32_t ControlFifo; /*!< Specifies the I3C control FIFO enable/disable state. 74 This parameter is configured only with controller mode and it 75 must be a value of @ref I3C_CONTROL_FIFO_STATE */ 76 77 uint32_t StatusFifo; /*!< Specifies the I3C status FIFO enable/disable state. 78 This parameter is configured only with controller mode and it 79 must be a value of @ref I3C_STATUS_FIFO_STATE */ 80 } I3C_FifoConfTypeDef; 81 /** 82 * @} 83 */ 84 85 /** @defgroup I3C_Controller_Config_Structure_definition I3C Controller Configuration Structure definition 86 * @brief I3C controller configuration structure definition 87 * @{ 88 */ 89 typedef struct 90 { 91 uint8_t DynamicAddr; /*!< Specifies the dynamic address of the controller when goes in target mode. 92 This parameter must be a number between Min_Data=0x00 and Max_Data=0x7F */ 93 94 uint8_t StallTime; /*!< Specifies the controller clock stall time in number of kernel clock cycles. 95 This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF */ 96 97 FunctionalState HotJoinAllowed; /*!< Specifies the Enable/Disable state of the controller Hot Join acknowledgement 98 when receiving a hot join request from target. 99 This parameter can be set to ENABLE or DISABLE */ 100 101 FunctionalState ACKStallState; /*!< Specifies the Enable/Disable state of the controller clock stall 102 on the ACK phase. 103 This parameter can be set to ENABLE or DISABLE */ 104 105 FunctionalState CCCStallState; /*!< Specifies the Enable/Disable state of the controller clock stall on the 106 T bit phase of a CCC communication to allow the target to decode command. 107 This parameter can be set to ENABLE or DISABLE */ 108 109 FunctionalState TxStallState; /*!< Specifies the Enable/Disable state of the controller clock stall on 110 parity phase of data to allow the target to read received data. 111 This parameter can be set to ENABLE or DISABLE */ 112 113 FunctionalState RxStallState; /*!< Specifies the Enable/Disable state of the controller clock stall on the T bit 114 phase of data enable to allow the target to prepare data to be sent. 115 This parameter can be set to ENABLE or DISABLE */ 116 117 FunctionalState HighKeeperSDA; /*!< Specifies the Enable/Disable state of the controller SDA high keeper. 118 This parameter can be set to ENABLE or DISABLE */ 119 } I3C_CtrlConfTypeDef; 120 /** 121 * @} 122 */ 123 124 /** @defgroup I3C_Target_Config_Structure_definition I3C Target Configuration Structure definition 125 * @brief I3C target configuration structure definition 126 * @{ 127 */ 128 typedef struct 129 { 130 uint8_t Identifier; /*!< Specifies the target characteristic ID (MIPI named reference DCR). 131 This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF */ 132 133 uint8_t MIPIIdentifier; /*!< Specifies the bits [12-15] of the 48-provisioned ID 134 (MIPI named reference PID), other 48-provisioned ID are hardcoded. 135 This parameter must be a number between Min_Data=0x00 and Max_Data=0x0F */ 136 137 FunctionalState CtrlRoleRequest; /*!< Specifies the Enable/Disable state of the target authorization request 138 for a second master Chip. 139 This parameter can be set to ENABLE or DISABLE */ 140 141 FunctionalState HotJoinRequest; /*!< Specifies the Enable/Disable state of the target hot join 142 authorization request. 143 This parameter can be set to ENABLE or DISABLE */ 144 145 FunctionalState IBIRequest; /*!< Specifies the Enable/Disable state of the target in Band Interrupt 146 authorization request. 147 This parameter can be set to ENABLE or DISABLE */ 148 149 FunctionalState IBIPayload; /*!< Specifies the Enable/Disable state of sending data payload after 150 an accepted IBI. 151 This parameter can be set to ENABLE or DISABLE */ 152 153 uint32_t IBIPayloadSize; /*!< Specifies the I3C target payload data size. 154 This parameter must be a value of @ref I3C_PAYLOAD_SIZE */ 155 156 uint16_t MaxReadDataSize; /*!< Specifies the numbers of data bytes that the target can read at maximum. 157 This parameter must be a number between Min_Data=0x00 and Max_Data=0xFFFF */ 158 159 uint16_t MaxWriteDataSize; /*!< Specifies the numbers of data bytes that the target can write at maximum. 160 This parameter must be a number between Min_Data=0x00 and Max_Data=0xFFFF */ 161 162 FunctionalState CtrlCapability; /*!< Specifies the Enable/Disable state of the target controller capability. 163 This parameter can be set to ENABLE or DISABLE */ 164 165 FunctionalState GroupAddrCapability; /*!< Specifies the Enable/Disable state of the target support of group address 166 after a controller role hand-off. 167 This parameter can be set to ENABLE or DISABLE */ 168 169 uint32_t DataTurnAroundDuration; /*!< Specifies the I3C target clock-to-data turnaround time. 170 This parameter must be a value of @ref I3C_TURNAROUND_TIME_TSCO */ 171 172 uint8_t MaxReadTurnAround; /*!< Specifies the target maximum read turnaround byte. 173 This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF */ 174 175 uint32_t MaxDataSpeed; /*!< Specifies the I3C target returned GETMXDS CCC format. 176 This parameter must be a value of @ref I3C_GETMXDS_FORMAT */ 177 178 FunctionalState MaxSpeedLimitation; /*!< Specifies the Enable/Disable state of the target max data speed limitation. 179 This parameter can be set to ENABLE or DISABLE */ 180 181 uint32_t HandOffActivityState; /*!< Specifies the I3C target activity state when becoming controller. 182 This parameter must be a value of @ref I3C_HANDOFF_ACTIVITY_STATE */ 183 184 FunctionalState HandOffDelay; /*!< Specifies the Enable/Disable state of the target need of delay to process 185 the controller role hand-off. 186 This parameter can be set to ENABLE or DISABLE */ 187 188 FunctionalState PendingReadMDB; /*!< Specifies the Enable/Disable state of the transmission of a mandatory 189 data bytes indicating a pending read notification for GETCAPR CCC command. 190 This parameter can be set to ENABLE or DISABLE */ 191 } I3C_TgtConfTypeDef; 192 /** 193 * @} 194 */ 195 196 /** @defgroup I3C_Device_Config_Structure_definition I3C Device Configuration Structure definition 197 * @brief I3C device configuration structure definition 198 * @{ 199 */ 200 typedef struct 201 { 202 uint8_t DeviceIndex; /*!< Specifies the index value of the device in the DEVRx register. 203 This parameter must be a number between Min_Data=1 and Max_Data=4 */ 204 205 uint8_t TargetDynamicAddr; /*!< Specifies the dynamic address of the target x (1 to 4) connected on the bus. 206 This parameter must be a number between Min_Data=0x00 and Max_Data=0x7F */ 207 208 FunctionalState IBIAck; /*!< Specifies the Enable/Disable state of the controller's ACK when receiving 209 an IBI from a target x (1 to 4) connected on the bus. 210 This parameter can be set to ENABLE or DISABLE */ 211 212 FunctionalState IBIPayload; /*!< Specifies the Enable/Disable state of the controller's receiving IBI payload 213 after acknowledging an IBI requested from a target x (1 to 4) connected 214 on the bus. 215 This parameter can be set to ENABLE or DISABLE */ 216 217 FunctionalState CtrlRoleReqAck; /*!< Specifies the Enable/Disable state of the controller's ACK when receiving 218 a control request from a target x (1 to 4) connected on the bus. 219 This parameter can be set to ENABLE or DISABLE */ 220 221 FunctionalState CtrlStopTransfer; /*!< Specifies the Enable/Disable state of the controller's stop transfer after 222 receiving an IBI request from a target x (1 to 4) connected on the bus. 223 This parameter can be set to ENABLE or DISABLE */ 224 225 } I3C_DeviceConfTypeDef; 226 /** 227 * @} 228 */ 229 230 /** @defgroup I3C_mode_structure_definition I3C mode structure definition 231 * @brief I3C Mode structure definition 232 * @{ 233 */ 234 typedef enum 235 { 236 HAL_I3C_MODE_NONE = 0x00U, /*!< No I3C communication on going */ 237 HAL_I3C_MODE_CONTROLLER = 0x01U, /*!< I3C communication is in controller Mode */ 238 HAL_I3C_MODE_TARGET = 0x02U, /*!< I3C communication is in target Mode */ 239 240 } HAL_I3C_ModeTypeDef; 241 /** 242 * @} 243 */ 244 245 /** @defgroup HAL_state_structure_definition HAL state structure definition 246 * @brief HAL State structure definition 247 * @{ 248 */ 249 typedef enum 250 { 251 HAL_I3C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ 252 HAL_I3C_STATE_READY = 0x10U, /*!< Peripheral Initialized and ready for use */ 253 HAL_I3C_STATE_BUSY = 0x20U, /*!< An internal process is ongoing */ 254 HAL_I3C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ 255 HAL_I3C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ 256 HAL_I3C_STATE_BUSY_TX_RX = 0x23U, /*!< Data Multiple Transfer process is ongoing */ 257 HAL_I3C_STATE_BUSY_DAA = 0x24U, /*!< Dynamic address assignment process is ongoing */ 258 HAL_I3C_STATE_LISTEN = 0x30U, /*!< Listen process is ongoing */ 259 HAL_I3C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ 260 HAL_I3C_STATE_ERROR = 0xE0U, /*!< Error */ 261 262 } HAL_I3C_StateTypeDef; 263 /** 264 * @} 265 */ 266 267 /** @defgroup I3C_CCCInfoTypeDef_Structure_definition I3C CCCInfoTypeDef Structure definition 268 * @brief I3C CCCInfoTypeDef Structure definition 269 * @{ 270 */ 271 typedef struct 272 { 273 uint32_t DynamicAddrValid; /*!< I3C target Dynamic Address Valid (updated during ENTDAA/RSTDAA/SETNEWDA CCC) 274 This parameter can be Valid=1U or Not Valid=0U */ 275 uint32_t DynamicAddr; /*!< I3C target Dynamic Address (updated during ENTDAA/RSTDAA/SETNEWDA CCC) */ 276 uint32_t MaxWriteLength; /*!< I3C target Maximum Write Length (updated during SETMWL CCC) */ 277 uint32_t MaxReadLength; /*!< I3C target Maximum Read Length (updated during SETMRL CCC) */ 278 uint32_t ResetAction; /*!< I3C target Reset Action level (updated during RSTACT CCC) */ 279 uint32_t ActivityState; /*!< I3C target Activity State (updated during ENTASx CCC) */ 280 uint32_t HotJoinAllowed; /*!< I3C target Hot Join (updated during ENEC/DISEC CCC) 281 This parameter can be Allowed=1U or Not Allowed=0U */ 282 uint32_t InBandAllowed; /*!< I3C target In Band Interrupt (updated during ENEC/DISEC CCC) 283 This parameter can be Allowed=1U or Not Allowed=0U */ 284 uint32_t CtrlRoleAllowed; /*!< I3C target Controller Role Request (updated during ENEC/DISEC CCC) 285 This parameter can be Allowed=1U or Not Allowed=0U */ 286 uint32_t IBICRTgtAddr; /*!< I3C controller receive Target Address during IBI or Controller Role Request event*/ 287 uint32_t IBITgtNbPayload; /*!< I3C controller get Number of Data Payload after an IBI event */ 288 uint32_t IBITgtPayload; /*!< I3C controller receive IBI Payload after an IBI event */ 289 290 } I3C_CCCInfoTypeDef; 291 /** 292 * @} 293 */ 294 295 /** @defgroup I3C_ControlTypeDef_Structure_definition I3C ControlTypeDef Structure definition 296 * @brief I3C ControlTypeDef Structure definition 297 * @{ 298 */ 299 typedef struct 300 { 301 uint32_t *pBuffer; /*!< Pointer to the buffer containing the control or status register values */ 302 uint32_t Size; /*!< The size of pBuffer in words */ 303 304 } I3C_ControlTypeDef; 305 /** 306 * @} 307 */ 308 309 /** @defgroup I3C_DataTypeDef_Structure_definition I3C DataTypeDef Structure definition 310 * @brief I3C DataTypeDef Structure definition 311 * @{ 312 */ 313 typedef struct 314 { 315 uint8_t *pBuffer; /*!< Pointer to the buffer containing all data values to transfer */ 316 uint32_t Size; /*!< The size of pBuffer in bytes */ 317 318 } I3C_DataTypeDef; 319 320 /** 321 * @} 322 */ 323 324 /** @defgroup I3C_CCCTypeDef_Structure_definition I3C CCCTypeDef Structure definition 325 * @brief I3C CCCTypeDef Structure definition 326 * @{ 327 */ 328 typedef struct 329 { 330 uint8_t TargetAddr; /*!< Dynamic or Static target Address */ 331 uint8_t CCC; /*!< CCC value code */ 332 I3C_DataTypeDef CCCBuf; /*!< Contain size of associated data and size of defining byte if any. 333 Contain pointer to CCC associated data */ 334 uint32_t Direction; /*!< CCC read and/or write direction message */ 335 336 } I3C_CCCTypeDef; 337 /** 338 * @} 339 */ 340 341 /** @defgroup I3C_PrivateTypeDef_Structure_definition I3C PrivateTypeDef Structure definition 342 * @brief I3C PrivateTypeDef Structure definition 343 * @{ 344 */ 345 typedef struct 346 { 347 uint8_t TargetAddr; /*!< Dynamic or Static target Address */ 348 I3C_DataTypeDef TxBuf; /*!< Buffer structure containing the data to transmit (little endian) */ 349 I3C_DataTypeDef RxBuf; /*!< Buffer structure containing the data to receive (little endian) */ 350 uint32_t Direction; /*!< Read and/or write message */ 351 352 } I3C_PrivateTypeDef; 353 /** 354 * @} 355 */ 356 357 /** @defgroup I3C_XferTypeDef_Structure_definition I3C XferTypeDef Structure definition 358 * @brief I3C XferTypeDef Structure definition 359 * @{ 360 */ 361 typedef struct 362 { 363 I3C_ControlTypeDef CtrlBuf; /*!< Buffer structure containing the control register values */ 364 I3C_ControlTypeDef StatusBuf; /*!< Buffer structure containing the status register values */ 365 I3C_DataTypeDef TxBuf; /*!< Buffer structure containing the data to transmit */ 366 I3C_DataTypeDef RxBuf; /*!< Buffer structure containing the data to receive */ 367 368 } I3C_XferTypeDef; 369 /** 370 * @} 371 */ 372 373 /** @defgroup I3C_handle_Structure_definition I3C handle Structure definition 374 * @brief I3C handle Structure definition 375 * @{ 376 */ 377 typedef struct __I3C_HandleTypeDef 378 { 379 I3C_TypeDef *Instance; /*!< I3C registers base address */ 380 381 I3C_InitTypeDef Init; /*!< I3C communication parameters */ 382 383 HAL_I3C_ModeTypeDef Mode; /*!< I3C communication mode. 384 This parameter must be a value of 385 @ref I3C_mode_structure_definition */ 386 387 I3C_XferTypeDef *pXferData; /*!< I3C transfer buffers pointer */ 388 389 const I3C_CCCTypeDef *pCCCDesc; /*!< I3C CCC descriptor pointer */ 390 391 const I3C_PrivateTypeDef *pPrivateDesc; /*!< I3C private transfer descriptor pointer */ 392 393 uint32_t ControlXferCount; /*!< I3C counter indicating the remaining 394 control data bytes to write in 395 the control register */ 396 397 uint32_t RxXferCount; /*!< I3C counter indicating the remaining 398 data bytes to receive */ 399 400 uint32_t TxXferCount; /*!< I3C counter indicating the remaining 401 data bytes to transmit */ 402 403 #if defined(HAL_DMA_MODULE_ENABLED) 404 DMA_HandleTypeDef *hdmacr; /*!< I3C control DMA handle parameters */ 405 406 DMA_HandleTypeDef *hdmatx; /*!< I3C Tx DMA handle parameters */ 407 408 DMA_HandleTypeDef *hdmarx; /*!< I3C Rx DMA handle parameters */ 409 410 DMA_HandleTypeDef *hdmasr; /*!< I3C status DMA handle parameters */ 411 #endif /* HAL_DMA_MODULE_ENABLED */ 412 413 HAL_LockTypeDef Lock; /*!< I3C locking object */ 414 415 __IO HAL_I3C_StateTypeDef State; /*!< I3C communication state */ 416 417 __IO HAL_I3C_StateTypeDef PreviousState; /*!< I3C communication previous state */ 418 419 __IO uint32_t ErrorCode; /*!< I3C Error code */ 420 421 HAL_StatusTypeDef(*XferISR)(struct __I3C_HandleTypeDef *hi3c, 422 uint32_t itFlags, 423 uint32_t itSources); /*!< I3C transfer IRQ handler function pointer */ 424 425 void(*ptrTxFunc)(struct __I3C_HandleTypeDef *hi3c); /*!< I3C transmit function pointer */ 426 427 void(*ptrRxFunc)(struct __I3C_HandleTypeDef *hi3c); /*!< I3C receive function pointer */ 428 429 #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) 430 431 void (* CtrlTxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 432 /*!< I3C Controller private data and CCC Tx Transfer complete callback */ 433 434 void (* CtrlRxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 435 /*!< I3C Controller private data and CCC Rx Transfer completed callback */ 436 437 void (* CtrlMultipleXferCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 438 /*!< I3C Controller multiple Direct CCC, I3C private or I2C Transfer completed callback */ 439 440 void (* CtrlDAACpltCallback)(struct __I3C_HandleTypeDef *hi3c); 441 /*!< I3C Controller Dynamic Address Assignment completed callback */ 442 443 void (* TgtReqDynamicAddrCallback)(struct __I3C_HandleTypeDef *hi3c, uint64_t targetPayload); 444 /*!< I3C Controller request dynamic address callback during Dynamic Address Assignment processus */ 445 446 void (* TgtTxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 447 /*!< I3C Target private data Tx Transfer completed callback */ 448 449 void (* TgtRxCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 450 /*!< I3C Target private data Rx Transfer completed callback */ 451 452 void (* TgtHotJoinCallback)(struct __I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress); 453 /*!< I3C Target Hot-Join callback */ 454 455 void (* NotifyCallback)(struct __I3C_HandleTypeDef *hi3c, uint32_t eventId); 456 /*!< I3C Target or Controller asynchronous events callback */ 457 458 void (* ErrorCallback)(struct __I3C_HandleTypeDef *hi3c); 459 /*!< I3C Error callback */ 460 461 void (* AbortCpltCallback)(struct __I3C_HandleTypeDef *hi3c); 462 /*!< I3C Abort complete callback */ 463 464 void (* MspInitCallback)(struct __I3C_HandleTypeDef *hi3c); 465 /*!< I3C Msp Init callback */ 466 467 void (* MspDeInitCallback)(struct __I3C_HandleTypeDef *hi3c); 468 /*!< I3C Msp DeInit callback */ 469 470 #endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ 471 472 } I3C_HandleTypeDef; 473 /** 474 * @} 475 */ 476 477 #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) 478 /** @defgroup HAL_I3C_Callback_ID_definition I3C callback ID definition 479 * @brief HAL I3C callback ID definition 480 * @{ 481 */ 482 typedef enum 483 { 484 /*!< I3C Controller Tx Transfer completed callback ID */ 485 HAL_I3C_CTRL_TX_COMPLETE_CB_ID = 0x00U, 486 /*!< I3C Controller Rx Transfer completed callback ID */ 487 HAL_I3C_CTRL_RX_COMPLETE_CB_ID = 0x01U, 488 /*!< I3C Controller Multiple Transfer completed callback ID */ 489 HAL_I3C_CTRL_MULTIPLE_XFER_COMPLETE_CB_ID = 0x02U, 490 /*!< I3C Controller Dynamic Address Assignment completed callback ID */ 491 HAL_I3C_CTRL_DAA_COMPLETE_CB_ID = 0x03U, 492 /*!< I3C Controller request dynamic address completed callback ID */ 493 HAL_I3C_TGT_REQ_DYNAMIC_ADDR_CB_ID = 0x04U, 494 /*!< I3C Target Tx Transfer completed callback ID */ 495 HAL_I3C_TGT_TX_COMPLETE_CB_ID = 0x05U, 496 /*!< I3C Target Rx Transfer completed callback ID */ 497 HAL_I3C_TGT_RX_COMPLETE_CB_ID = 0x06U, 498 /*!< I3C Target Hot-join notification callback ID */ 499 HAL_I3C_TGT_HOTJOIN_CB_ID = 0x07U, 500 /*!< I3C Target or Controller receive notification callback ID */ 501 HAL_I3C_NOTIFY_CB_ID = 0x08U, 502 /*!< I3C Error callback ID */ 503 HAL_I3C_ERROR_CB_ID = 0x09U, 504 /*!< I3C Abort callback ID */ 505 HAL_I3C_ABORT_CB_ID = 0x0AU, 506 /*!< I3C Msp Init callback ID */ 507 HAL_I3C_MSPINIT_CB_ID = 0x0BU, 508 /*!< I3C Msp DeInit callback ID */ 509 HAL_I3C_MSPDEINIT_CB_ID = 0x0CU 510 511 } HAL_I3C_CallbackIDTypeDef; 512 /** 513 * @} 514 */ 515 516 /** @defgroup HAL_I3C_Callback_Pointer_definition I3C callback Pointer definition 517 * @brief HAL I3C callback pointer definition 518 * @{ 519 */ 520 typedef void (*pI3C_CallbackTypeDef)(I3C_HandleTypeDef *hi3c); 521 typedef void (*pI3C_NotifyCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint32_t notifyId); 522 typedef void (*pI3C_TgtHotJoinCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress); 523 typedef void (*pI3C_TgtReqDynamicAddrCallbackTypeDef)(I3C_HandleTypeDef *hi3c, uint64_t targetPayload); 524 /** 525 * @} 526 */ 527 #endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ 528 529 /** 530 * @} 531 */ 532 533 /* Exported constants ------------------------------------------------------------------------------------------------*/ 534 /** @defgroup I3C_Exported_Constants I3C Exported Constants 535 * @{ 536 */ 537 538 /** @defgroup HAL_I3C_Notification_ID_definition I3C Notification ID definition 539 * @brief HAL I3C Notification ID definition 540 * @{ 541 */ 542 543 #define EVENT_ID_GETACCCR (0x00000001U) 544 /*!< I3C target complete controller-role hand-off (direct GETACCR CCC) event */ 545 #define EVENT_ID_IBIEND (0x00000002U) 546 /*!< I3C target IBI end process event */ 547 #define EVENT_ID_DAU (0x00000004U) 548 /*!< I3C target receive a dynamic address update (ENTDAA/RSTDAA/SETNEWDA CCC) event */ 549 #define EVENT_ID_GETx (0x00000008U) 550 /*!< I3C target receive any direct GETxxx CCC event */ 551 #define EVENT_ID_GETSTATUS (0x00000010U) 552 /*!< I3C target receive get status command (direct GETSTATUS CCC) event */ 553 #define EVENT_ID_SETMWL (0x00000020U) 554 /*!< I3C target receive maximum write length update (direct SETMWL CCC) event */ 555 #define EVENT_ID_SETMRL (0x00000040U) 556 /*!< I3C target receive maximum read length update(direct SETMRL CCC) event */ 557 #define EVENT_ID_RSTACT (0x00000080U) 558 /*!< I3C target detect reset pattern (broadcast or direct RSTACT CCC) event */ 559 #define EVENT_ID_ENTASx (0x00000100U) 560 /*!< I3C target receive activity state update (direct or broadcast ENTASx) event */ 561 #define EVENT_ID_ENEC_DISEC (0x00000200U) 562 /*!< I3C target receive a direct or broadcast ENEC/DISEC CCC event */ 563 #define EVENT_ID_DEFTGTS (0x00000400U) 564 /*!< I3C target receive a broadcast DEFTGTS CCC event */ 565 #define EVENT_ID_DEFGRPA (0x00000800U) 566 /*!< I3C target receive a group addressing (broadcast DEFGRPA CCC) event */ 567 #define EVENT_ID_WKP (0x00001000U) 568 /*!< I3C target wakeup event */ 569 #define EVENT_ID_IBI (0x00002000U) 570 /*!< I3C controller receive IBI event */ 571 #define EVENT_ID_CR (0x00004000U) 572 /*!< I3C controller controller-role request event */ 573 #define EVENT_ID_HJ (0x00008000U) 574 /*!< I3C controller hot-join event */ 575 /** 576 * @} 577 */ 578 579 /** @defgroup I3C_OPTION_DEFINITION OPTION DEFINITION 580 * @note HAL I3C option value coding follow below described bitmap: 581 * b31 582 * 0 : message end type restart 583 * 1 : message end type stop 584 * b30-b29-b28-b27 585 * 0010 : I3C private message 586 * 0011 : direct CCC message 587 * 0110 : broadcast CCC message 588 * 0100 : I2C private message 589 * b4 590 * 0 : message without arbitration header 591 * 1 : message with arbitration header 592 * b0 593 * 0 : message without defining byte 594 * 1 : message with defining byte 595 * 596 * other bits (not used) 597 * @{ 598 */ 599 #define I3C_DIRECT_WITH_DEFBYTE_RESTART (0x18000001U) /*!< Restart between each Direct Command then Stop 600 request for last command. 601 Each Command have an associated defining byte */ 602 #define I3C_DIRECT_WITH_DEFBYTE_STOP (0x98000001U) /*!< Stop between each Direct Command. 603 Each Command have an associated defining byte */ 604 #define I3C_DIRECT_WITHOUT_DEFBYTE_RESTART (0x18000000U) /*!< Restart between each Direct Command then Stop 605 request for last command. 606 Each Command have not an associated defining byte */ 607 #define I3C_DIRECT_WITHOUT_DEFBYTE_STOP (0x98000000U) /*!< Stop between each Direct Command. 608 Each Command have not an associated defining byte */ 609 #define I3C_BROADCAST_WITH_DEFBYTE_RESTART (0x30000001U) /*!< Restart between each Broadcast Command then Stop 610 request for last command. 611 Each Command have an associated defining byte */ 612 #define I3C_BROADCAST_WITH_DEFBYTE_STOP (0xB0000001U) /*!< Stop between each Broadcast Command. 613 Each Command have an associated defining byte */ 614 #define I3C_BROADCAST_WITHOUT_DEFBYTE_RESTART (0x30000000U) /*!< Restart between each Broadcast Command then Stop 615 request for last command. 616 Each Command have not an associated defining byte */ 617 #define I3C_BROADCAST_WITHOUT_DEFBYTE_STOP (0xB0000000U) /*!< Stop between each Broadcast Command. 618 Each Command have not an associated defining byte */ 619 #define I3C_PRIVATE_WITH_ARB_RESTART (0x10000000U) /*!< Restart between each I3C Private message then Stop 620 request for last message. 621 Each Message start with an arbitration header after 622 start bit condition */ 623 #define I3C_PRIVATE_WITH_ARB_STOP (0x90000000U) /*!< Stop between each I3C Private message. 624 Each Message start with an arbitration header after 625 start bit condition */ 626 #define I3C_PRIVATE_WITHOUT_ARB_RESTART (0x10000004U) /*!< Restart between each I3C message then Stop request 627 for last message. 628 Each Message start with Target address after start 629 bit condition */ 630 #define I3C_PRIVATE_WITHOUT_ARB_STOP (0x90000004U) /*!< Stop between each I3C Private message. 631 Each Message start with Target address after 632 start bit condition */ 633 #define I2C_PRIVATE_WITH_ARB_RESTART (0x20000000U) /*!< Restart between each I2C Private message then Stop 634 request for last message. 635 Each Message start with an arbitration header after 636 start bit condition */ 637 #define I2C_PRIVATE_WITH_ARB_STOP (0xA0000000U) /*!< Stop between each I2C Private message. 638 Each Message start with an arbitration header after 639 start bit condition */ 640 #define I2C_PRIVATE_WITHOUT_ARB_RESTART (0x20000004U) /*!< Restart between each I2C message then Stop request 641 for last message. 642 Each Message start with Target address after start 643 bit condition */ 644 #define I2C_PRIVATE_WITHOUT_ARB_STOP (0xA0000004U) /*!< Stop between each I2C Private message. 645 Each Message start with Target address after start 646 bit condition */ 647 /** 648 * @} 649 */ 650 651 /** @defgroup I3C_DYNAMIC_ADDRESS_OPTION_DEFINITION I3C DYNAMIC ADDRESS OPTION DEFINITION 652 * @{ 653 */ 654 #define I3C_RSTDAA_THEN_ENTDAA (0x00000001U) /*!< Initiate a RSTDAA before a ENTDAA procedure */ 655 #define I3C_ONLY_ENTDAA (0x00000002U) /*!< Initiate a ENTDAA without RSTDAA */ 656 /** 657 * @} 658 */ 659 660 /** @defgroup I3C_ERROR_CODE_DEFINITION ERROR CODE DEFINITION 661 * @{ 662 */ 663 #define HAL_I3C_ERROR_NONE (0x00000000U) /*!< No error */ 664 665 #define HAL_I3C_ERROR_CE0 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE0) /*!< Controller detected an illegally 666 formatted CCC */ 667 #define HAL_I3C_ERROR_CE1 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE1) /*!< Controller detected that transmitted data 668 on the bus is different than expected */ 669 #define HAL_I3C_ERROR_CE2 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE2) /*!< Controller detected that broadcast address 670 7'h7E has been nacked */ 671 #define HAL_I3C_ERROR_CE3 (I3C_SER_PERR | LL_I3C_CONTROLLER_ERROR_CE3) /*!< Controller detected that new Controller 672 did not drive the bus after 673 Controller-role handoff */ 674 #define HAL_I3C_ERROR_TE0 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE0) /*!< Target detected an invalid broadcast 675 address */ 676 #define HAL_I3C_ERROR_TE1 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE1) /*!< Target detected an invalid CCC Code */ 677 #define HAL_I3C_ERROR_TE2 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE2) /*!< Target detected a parity error during 678 a write data */ 679 #define HAL_I3C_ERROR_TE3 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE3) /*!< Target detected a parity error on assigned 680 address during dynamic address 681 arbitration */ 682 #define HAL_I3C_ERROR_TE4 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE4) /*!< Target detected 7'h7E missing after Restart 683 during Dynamic Address Assignment 684 procedure */ 685 #define HAL_I3C_ERROR_TE5 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE5) /*!< Target detected an illegally 686 formatted CCC */ 687 #define HAL_I3C_ERROR_TE6 (I3C_SER_PERR | LL_I3C_TARGET_ERROR_TE6) /*!< Target detected that transmitted data on 688 the bus is different than expected */ 689 #define HAL_I3C_ERROR_DATA_HAND_OFF (I3C_SER_DERR) /*!< I3C data error during controller-role hand-off process */ 690 #define HAL_I3C_ERROR_DATA_NACK (I3C_SER_DNACK) /*!< I3C data not acknowledged error */ 691 #define HAL_I3C_ERROR_ADDRESS_NACK (I3C_SER_ANACK) /*!< I3C address not acknowledged error */ 692 #define HAL_I3C_ERROR_COVR (I3C_SER_COVR) /*!< I3C S FIFO Over-Run or C FIFO Under-Run error */ 693 #define HAL_I3C_ERROR_DOVR (I3C_SER_DOVR) /*!< I3C Rx FIFO Over-Run or Tx FIFO Under-Run error */ 694 #define HAL_I3C_ERROR_STALL (I3C_SER_STALL) /*!< I3C SCL stall error */ 695 #define HAL_I3C_ERROR_DMA (0x00010000U) /*!< DMA transfer error */ 696 #define HAL_I3C_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ 697 #define HAL_I3C_ERROR_DMA_PARAM (0x00040000U) /*!< DMA Parameter Error */ 698 #define HAL_I3C_ERROR_INVALID_PARAM (0x00080000U) /*!< Invalid Parameters error */ 699 #define HAL_I3C_ERROR_SIZE (0x00100000U) /*!< I3C size management error */ 700 #define HAL_I3C_ERROR_NOT_ALLOWED (0x00200000U) /*!< I3C operation is not allowed */ 701 #define HAL_I3C_ERROR_DYNAMIC_ADDR (0x00400000U) /*!< I3C dynamic address error */ 702 703 #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) 704 #define HAL_I3C_ERROR_INVALID_CALLBACK (0x00800000U) /*!< Invalid Callback error */ 705 #endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ 706 /** 707 * @} 708 */ 709 710 /** @defgroup I3C_SDA_HOLD_TIME SDA HOLD TIME 711 * @{ 712 */ 713 #define HAL_I3C_SDA_HOLD_TIME_0_5 LL_I3C_SDA_HOLD_TIME_0_5 /*!< SDA hold time equal to 0.5 x ti3cclk */ 714 #define HAL_I3C_SDA_HOLD_TIME_1_5 LL_I3C_SDA_HOLD_TIME_1_5 /*!< SDA hold time equal to 1.5 x ti3cclk */ 715 /** 716 * @} 717 */ 718 719 /** @defgroup I3C_OWN_ACTIVITY_STATE OWN ACTIVITY STATE 720 * @{ 721 */ 722 #define HAL_I3C_OWN_ACTIVITY_STATE_0 LL_I3C_OWN_ACTIVITY_STATE_0 /*!< Own Controller Activity state 0 */ 723 #define HAL_I3C_OWN_ACTIVITY_STATE_1 LL_I3C_OWN_ACTIVITY_STATE_1 /*!< Own Controller Activity state 1 */ 724 #define HAL_I3C_OWN_ACTIVITY_STATE_2 LL_I3C_OWN_ACTIVITY_STATE_2 /*!< Own Controller Activity state 2 */ 725 #define HAL_I3C_OWN_ACTIVITY_STATE_3 LL_I3C_OWN_ACTIVITY_STATE_3 /*!< Own Controller Activity state 3 */ 726 /** 727 * @} 728 */ 729 730 /** @defgroup I3C_RX_FIFO_THRESHOLD RX FIFO THRESHOLD 731 * @{ 732 */ 733 #define HAL_I3C_RXFIFO_THRESHOLD_1_4 LL_I3C_RXFIFO_THRESHOLD_1_4 /*!< Rx Fifo Threshold is 1 byte */ 734 #define HAL_I3C_RXFIFO_THRESHOLD_4_4 LL_I3C_RXFIFO_THRESHOLD_4_4 /*!< Rx Fifo Threshold is 4 bytes */ 735 /** 736 * @} 737 */ 738 739 /** @defgroup I3C_TX_FIFO_THRESHOLD TX FIFO THRESHOLD 740 * @{ 741 */ 742 #define HAL_I3C_TXFIFO_THRESHOLD_1_4 LL_I3C_TXFIFO_THRESHOLD_1_4 /*!< Tx Fifo Threshold is 1 byte */ 743 #define HAL_I3C_TXFIFO_THRESHOLD_4_4 LL_I3C_TXFIFO_THRESHOLD_4_4 /*!< Tx Fifo Threshold is 4 bytes */ 744 /** 745 * @} 746 */ 747 748 /** @defgroup I3C_CONTROL_FIFO_STATE CONTROL FIFO STATE 749 * @{ 750 */ 751 #define HAL_I3C_CONTROLFIFO_DISABLE 0x00000000U /*!< Control FIFO mode disable */ 752 #define HAL_I3C_CONTROLFIFO_ENABLE I3C_CFGR_TMODE /*!< Control FIFO mode enable */ 753 /** 754 * @} 755 */ 756 757 /** @defgroup I3C_STATUS_FIFO_STATE STATUS FIFO STATE 758 * @{ 759 */ 760 #define HAL_I3C_STATUSFIFO_DISABLE 0x00000000U /*!< Status FIFO mode disable */ 761 #define HAL_I3C_STATUSFIFO_ENABLE I3C_CFGR_SMODE /*!< Status FIFO mode enable */ 762 /** 763 * @} 764 */ 765 766 /** @defgroup I3C_DIRECTION DIRECTION 767 * @{ 768 */ 769 #define HAL_I3C_DIRECTION_WRITE LL_I3C_DIRECTION_WRITE /*!< Write transfer */ 770 #define HAL_I3C_DIRECTION_READ LL_I3C_DIRECTION_READ /*!< Read transfer */ 771 #define HAL_I3C_DIRECTION_BOTH (LL_I3C_DIRECTION_READ | 1U) /*!< Read and Write transfer */ 772 /** 773 * @} 774 */ 775 776 /** @defgroup I3C_PAYLOAD_SIZE PAYLOAD SIZE 777 * @{ 778 */ 779 #define HAL_I3C_PAYLOAD_EMPTY LL_I3C_PAYLOAD_EMPTY /*!< Empty payload, no additional data after IBI acknowledge */ 780 #define HAL_I3C_PAYLOAD_1_BYTE LL_I3C_PAYLOAD_1_BYTE /*!< One additional data byte after IBI acknowledge */ 781 #define HAL_I3C_PAYLOAD_2_BYTES LL_I3C_PAYLOAD_2_BYTES /*!< Two additional data bytes after IBI acknowledge */ 782 #define HAL_I3C_PAYLOAD_3_BYTES LL_I3C_PAYLOAD_3_BYTES /*!< Three additional data bytes after IBI acknowledge */ 783 #define HAL_I3C_PAYLOAD_4_BYTES LL_I3C_PAYLOAD_4_BYTES /*!< Four additional data bytes after IBI acknowledge */ 784 /** 785 * @} 786 */ 787 788 /** @defgroup I3C_HANDOFF_ACTIVITY_STATE HANDOFF ACTIVITY STATE 789 * @{ 790 */ 791 #define HAL_I3C_HANDOFF_ACTIVITY_STATE_0 LL_I3C_HANDOFF_ACTIVITY_STATE_0 /*!< Activity state 0 after handoff */ 792 #define HAL_I3C_HANDOFF_ACTIVITY_STATE_1 LL_I3C_HANDOFF_ACTIVITY_STATE_1 /*!< Activity state 1 after handoff */ 793 #define HAL_I3C_HANDOFF_ACTIVITY_STATE_2 LL_I3C_HANDOFF_ACTIVITY_STATE_2 /*!< Activity state 2 after handoff */ 794 #define HAL_I3C_HANDOFF_ACTIVITY_STATE_3 LL_I3C_HANDOFF_ACTIVITY_STATE_3 /*!< Activity state 3 after handoff */ 795 /** 796 * @} 797 */ 798 799 /** @defgroup I3C_GETMXDS_FORMAT GETMXDS FORMAT 800 * @{ 801 */ 802 #define HAL_I3C_GETMXDS_FORMAT_1 LL_I3C_GETMXDS_FORMAT_1 /*!< GETMXDS CCC Format 1 is used, no MaxRdTurn 803 field in response */ 804 #define HAL_I3C_GETMXDS_FORMAT_2_LSB LL_I3C_GETMXDS_FORMAT_2_LSB /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field 805 in response, LSB = RDTURN[7:0] */ 806 #define HAL_I3C_GETMXDS_FORMAT_2_MID LL_I3C_GETMXDS_FORMAT_2_MID /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field 807 in response, Middle byte = RDTURN[7:0] */ 808 #define HAL_I3C_GETMXDS_FORMAT_2_MSB LL_I3C_GETMXDS_FORMAT_2_MSB /*!< GETMXDS CCC Format 2 is used, MaxRdTurn field 809 in response, MSB = RDTURN[7:0] */ 810 /** 811 * @} 812 */ 813 814 /** @defgroup I3C_TURNAROUND_TIME_TSCO TURNAROUND TIME TSCO 815 * @{ 816 */ 817 #define HAL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS LL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS 818 /*!< clock-to-data turnaround time tSCO <= 12ns */ 819 #define HAL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS LL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS 820 /*!< clock-to-data turnaround time tSCO > 12ns */ 821 /** 822 * @} 823 */ 824 825 /** @defgroup I3C_COMMON_INTERRUPT I3C COMMON INTERRUPT 826 * @{ 827 */ 828 #define HAL_I3C_IT_TXFNFIE LL_I3C_IER_TXFNFIE /*!< Tx FIFO not full interrupt enable */ 829 #define HAL_I3C_IT_RXFNEIE LL_I3C_IER_RXFNEIE /*!< Rx FIFO not empty interrupt enable */ 830 #define HAL_I3C_IT_FCIE LL_I3C_IER_FCIE /*!< Frame complete interrupt enable */ 831 #define HAL_I3C_IT_ERRIE LL_I3C_IER_ERRIE /*!< Error interrupt enable */ 832 #define HAL_I3C_ALL_COMMON_ITS (uint32_t)(LL_I3C_IER_TXFNFIE | LL_I3C_IER_RXFNEIE | \ 833 LL_I3C_IER_FCIE | LL_I3C_IER_ERRIE) 834 /** 835 * @} 836 */ 837 838 /** @defgroup I3C_TARGET_INTERRUPT I3C TARGET INTERRUPT 839 * @{ 840 */ 841 #define HAL_I3C_IT_IBIENDIE LL_I3C_IER_IBIENDIE /*!< IBI end interrupt enable */ 842 #define HAL_I3C_IT_CRUPDIE LL_I3C_IER_CRUPDIE /*!< controller-role update interrupt enable */ 843 #define HAL_I3C_IT_WKPIE LL_I3C_IER_WKPIE /*!< wakeup interrupt enable */ 844 #define HAL_I3C_IT_GETIE LL_I3C_IER_GETIE /*!< GETxxx CCC interrupt enable */ 845 #define HAL_I3C_IT_STAIE LL_I3C_IER_STAIE /*!< GETSTATUS CCC interrupt enable */ 846 #define HAL_I3C_IT_DAUPDIE LL_I3C_IER_DAUPDIE /*!< ENTDAA/RSTDAA/SETNEWDA CCC interrupt enable */ 847 #define HAL_I3C_IT_MWLUPDIE LL_I3C_IER_MWLUPDIE /*!< SETMWL CCC interrupt enable */ 848 #define HAL_I3C_IT_MRLUPDIE LL_I3C_IER_MRLUPDIE /*!< SETMRL CCC interrupt enable */ 849 #define HAL_I3C_IT_RSTIE LL_I3C_IER_RSTIE /*!< reset pattern interrupt enable */ 850 #define HAL_I3C_IT_ASUPDIE LL_I3C_IER_ASUPDIE /*!< ENTASx CCC interrupt enable */ 851 #define HAL_I3C_IT_INTUPDIE LL_I3C_IER_INTUPDIE /*!< ENEC/DISEC CCC interrupt enable */ 852 #define HAL_I3C_IT_DEFIE (LL_I3C_IER_DEFIE | LL_I3C_IER_RXFNEIE) 853 /*!< DEFTGTS CCC interrupt enable */ 854 #define HAL_I3C_IT_GRPIE (LL_I3C_IER_GRPIE | LL_I3C_IER_RXFNEIE) 855 /*!< DEFGRPA CCC interrupt enable */ 856 #define HAL_I3C_ALL_TGT_ITS (uint32_t)(LL_I3C_IER_IBIENDIE | LL_I3C_IER_CRUPDIE | LL_I3C_IER_WKPIE | \ 857 LL_I3C_IER_GETIE | LL_I3C_IER_STAIE | LL_I3C_IER_DAUPDIE | \ 858 LL_I3C_IER_MWLUPDIE | LL_I3C_IER_MRLUPDIE | LL_I3C_IER_RSTIE | \ 859 LL_I3C_IER_ASUPDIE | LL_I3C_IER_INTUPDIE | LL_I3C_IER_DEFIE | \ 860 LL_I3C_IER_GRPIE) 861 /** 862 * @} 863 */ 864 865 /** @defgroup I3C_CONTROLLER_INTERRUPT I3C CONTROLLER INTERRUPT 866 * @{ 867 */ 868 #define HAL_I3C_IT_CFNFIE LL_I3C_IER_CFNFIE /*!< Control FIFO not full interrupt enable */ 869 #define HAL_I3C_IT_SFNEIE LL_I3C_IER_SFNEIE /*!< Status FIFO not empty interrupt enable */ 870 #define HAL_I3C_IT_HJIE LL_I3C_IER_HJIE /*!< Hot-join interrupt enable */ 871 #define HAL_I3C_IT_CRIE LL_I3C_IER_CRIE /*!< Controller-role request interrupt enable */ 872 #define HAL_I3C_IT_IBIIE LL_I3C_IER_IBIIE /*!< IBI request interrupt enable */ 873 #define HAL_I3C_IT_RXTGTENDIE LL_I3C_IER_RXTGTENDIE /*!< Target-initiated read end interrupt enable */ 874 #define HAL_I3C_ALL_CTRL_ITS (uint32_t)(LL_I3C_IER_CFNFIE | LL_I3C_IER_SFNEIE | LL_I3C_IER_HJIE | \ 875 LL_I3C_IER_CRIE | LL_I3C_IER_IBIIE | LL_I3C_IER_RXTGTENDIE) 876 /** 877 * @} 878 */ 879 880 /** @defgroup I3C_FLAGS I3C FLAGS 881 * @{ 882 */ 883 #define HAL_I3C_FLAG_CFEF LL_I3C_EVR_CFEF /*!< Control FIFO not empty flag */ 884 #define HAL_I3C_FLAG_TXFEF LL_I3C_EVR_TXFEF /*!< Tx FIFO empty flag */ 885 #define HAL_I3C_FLAG_CFNFF LL_I3C_EVR_CFNFF /*!< Control FIFO not full flag */ 886 #define HAL_I3C_FLAG_SFNEF LL_I3C_EVR_SFNEF /*!< Status FIFO not empty flag */ 887 #define HAL_I3C_FLAG_TXFNFF LL_I3C_EVR_TXFNFF /*!< Tx FIFO not full flag */ 888 #define HAL_I3C_FLAG_RXFNEF LL_I3C_EVR_RXFNEF /*!< Rx FIFO not empty flag */ 889 #define HAL_I3C_FLAG_RXLASTF LL_I3C_EVR_RXLASTF /*!< Last read data byte/word flag */ 890 #define HAL_I3C_FLAG_TXLASTF LL_I3C_EVR_TXLASTF /*!< Last written data byte/word flag */ 891 #define HAL_I3C_FLAG_FCF LL_I3C_EVR_FCF /*!< Frame complete flag */ 892 #define HAL_I3C_FLAG_RXTGTENDF LL_I3C_EVR_RXTGTENDF /*!< Target-initiated read end flag */ 893 #define HAL_I3C_FLAG_ERRF LL_I3C_EVR_ERRF /*!< Error flag */ 894 #define HAL_I3C_FLAG_IBIF LL_I3C_EVR_IBIF /*!< IBI request flag */ 895 #define HAL_I3C_FLAG_IBIENDF LL_I3C_EVR_IBIENDF /*!< IBI end flag */ 896 #define HAL_I3C_FLAG_CRF LL_I3C_EVR_CRF /*!< Controller-role request flag */ 897 #define HAL_I3C_FLAG_CRUPDF LL_I3C_EVR_CRUPDF /*!< Controller-role update flag */ 898 #define HAL_I3C_FLAG_HJF LL_I3C_EVR_HJF /*!< Hot-join flag */ 899 #define HAL_I3C_FLAG_WKPF LL_I3C_EVR_WKPF /*!< Wakeup flag */ 900 #define HAL_I3C_FLAG_GETF LL_I3C_EVR_GETF /*!< GETxxx CCC flag */ 901 #define HAL_I3C_FLAG_STAF LL_I3C_EVR_STAF /*!< Format 1 GETSTATUS CCC flag */ 902 #define HAL_I3C_FLAG_DAUPDF LL_I3C_EVR_DAUPDF /*!< ENTDAA/RSTDAA/SETNEWDA CCC flag */ 903 #define HAL_I3C_FLAG_MWLUPDF LL_I3C_EVR_MWLUPDF /*!< SETMWL CCC flag */ 904 #define HAL_I3C_FLAG_MRLUPDF LL_I3C_EVR_MRLUPDF /*!< SETMRL CCC flag */ 905 #define HAL_I3C_FLAG_RSTF LL_I3C_EVR_RSTF /*!< Reset pattern flag */ 906 #define HAL_I3C_FLAG_ASUPDF LL_I3C_EVR_ASUPDF /*!< ENTASx CCC flag */ 907 #define HAL_I3C_FLAG_INTUPDF LL_I3C_EVR_INTUPDF /*!< ENEC/DISEC CCC flag */ 908 #define HAL_I3C_FLAG_DEFF LL_I3C_EVR_DEFF /*!< DEFTGTS CCC flag */ 909 #define HAL_I3C_FLAG_GRPF LL_I3C_EVR_GRPF /*!< DEFGRPA CCC flag */ 910 /** 911 * @} 912 */ 913 914 /** @defgroup I3C_BCR_IN_PAYLOAD I3C BCR IN PAYLOAD 915 * @{ 916 */ 917 #define HAL_I3C_BCR_IN_PAYLOAD_SHIFT 48 /*!< BCR field in target payload */ 918 /** 919 * @} 920 */ 921 922 /** 923 * @} 924 */ 925 926 /* Exported macros ---------------------------------------------------------------------------------------------------*/ 927 /** @defgroup I3C_Exported_Macros I3C Exported Macros 928 * @{ 929 */ 930 931 /** @brief Reset I3C handle state. 932 * @param __HANDLE__ specifies the I3C Handle. 933 * @retval None 934 */ 935 #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1) 936 #define __HAL_I3C_RESET_HANDLE_STATE(__HANDLE__) do{ \ 937 (__HANDLE__)->State = HAL_I3C_STATE_RESET; \ 938 (__HANDLE__)->MspInitCallback = NULL; \ 939 (__HANDLE__)->MspDeInitCallback = NULL; \ 940 } while(0) 941 #else 942 #define __HAL_I3C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I3C_STATE_RESET) 943 #endif /* USE_HAL_I3C_REGISTER_CALLBACKS */ 944 945 /** @brief Enable the specified I3C interrupt. 946 * @param __HANDLE__ specifies the I3C Handle. 947 * @param __INTERRUPT__ specifies the interrupt source to enable. 948 * This parameter can be one value or a combination of the following group's values: 949 * @arg @ref I3C_CONTROLLER_INTERRUPT 950 * @arg @ref I3C_TARGET_INTERRUPT 951 * @arg @ref I3C_COMMON_INTERRUPT 952 * @retval None 953 */ 954 #define __HAL_I3C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 955 956 /** @brief Disable the specified I3C interrupt. 957 * @param __HANDLE__ specifies the I3C Handle. 958 * @param __INTERRUPT__ specifies the interrupt source to disable. 959 * This parameter can be one value or a combination of the following group's values: 960 * @arg @ref I3C_CONTROLLER_INTERRUPT 961 * @arg @ref I3C_TARGET_INTERRUPT 962 * @arg @ref I3C_COMMON_INTERRUPT 963 * @retval None 964 */ 965 #define __HAL_I3C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 966 967 /** @brief Check whether the specified I3C flag is set or not. 968 * @param __HANDLE__ specifies the I3C Handle. 969 * @param __FLAG__ specifies the flag to check. 970 * This parameter can be one value of the group @arg @ref I3C_FLAGS values. 971 * @retval The new state of __FLAG__ (SET or RESET). 972 */ 973 #define __HAL_I3C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->EVR) &\ 974 (__FLAG__)) == (__FLAG__)) ? SET : RESET) 975 976 /** @brief Get Bus Characterics in payload (64bits) receive during ENTDAA procedure. 977 * @param __PAYLOAD__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. 978 * This parameter must be a number between Min_Data=0x00(uint64_t) and Max_Data=0xFFFFFFFFFFFFFFFFFF. 979 * @retval The value of BCR Return value between Min_Data=0x00 and Max_Data=0xFF. 980 */ 981 #define __HAL_I3C_GET_BCR(__PAYLOAD__) (((uint32_t)((uint64_t)(__PAYLOAD__) >> HAL_I3C_BCR_IN_PAYLOAD_SHIFT)) & \ 982 I3C_BCR_BCR) 983 984 /** @brief Check IBI request capabilities. 985 * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. 986 * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. 987 * @retval The state of IBI request capabilities (ENABLE or DISABLE). 988 */ 989 #define __HAL_I3C_GET_IBI_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR1_Msk) >> I3C_BCR_BCR1_Pos) == 1U) \ 990 ? ENABLE : DISABLE) 991 992 /** @brief Check IBI additional data byte capabilities. 993 * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. 994 * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. 995 * @retval The state of IBI additional data byte capabilities (ENABLE or DISABLE). 996 */ 997 #define __HAL_I3C_GET_IBI_PAYLOAD(__BCR__) (((((__BCR__) & I3C_BCR_BCR2_Msk) >> I3C_BCR_BCR2_Pos) == 1U) \ 998 ? ENABLE : DISABLE) 999 1000 /** @brief Check Controller role request capabilities. 1001 * @param __BCR__ specifies the Bus Characteristics capabilities retrieve during ENTDAA procedure. 1002 * This parameter must be a number between Min_Data=0x00 and Max_Data=0xFF. 1003 * @retval The state of Controller role request capabilities (ENABLE or DISABLE). 1004 */ 1005 #define __HAL_I3C_GET_CR_CAPABLE(__BCR__) (((((__BCR__) & I3C_BCR_BCR6_Msk) >> I3C_BCR_BCR6_Pos) == 1U) \ 1006 ? ENABLE : DISABLE) 1007 1008 /** 1009 * @} 1010 */ 1011 1012 /* Exported functions ------------------------------------------------------------------------------------------------*/ 1013 /** @addtogroup I3C_Exported_Functions 1014 * @{ 1015 */ 1016 1017 /** @addtogroup I3C_Exported_Functions_Group1 Initialization and de-initialization functions. 1018 * @{ 1019 */ 1020 HAL_StatusTypeDef HAL_I3C_Init(I3C_HandleTypeDef *hi3c); 1021 HAL_StatusTypeDef HAL_I3C_DeInit(I3C_HandleTypeDef *hi3c); 1022 void HAL_I3C_MspInit(I3C_HandleTypeDef *hi3c); 1023 void HAL_I3C_MspDeInit(I3C_HandleTypeDef *hi3c); 1024 /** 1025 * @} 1026 */ 1027 1028 /** @addtogroup I3C_Exported_Functions_Group2 Interrupt and callback functions. 1029 * @{ 1030 */ 1031 #if (USE_HAL_I3C_REGISTER_CALLBACKS == 1U) 1032 HAL_StatusTypeDef HAL_I3C_RegisterCallback(I3C_HandleTypeDef *hi3c, 1033 HAL_I3C_CallbackIDTypeDef callbackID, 1034 pI3C_CallbackTypeDef pCallback); 1035 HAL_StatusTypeDef HAL_I3C_RegisterNotifyCallback(I3C_HandleTypeDef *hi3c, 1036 pI3C_NotifyCallbackTypeDef pNotifyCallback); 1037 HAL_StatusTypeDef HAL_I3C_RegisterTgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, 1038 pI3C_TgtReqDynamicAddrCallbackTypeDef pTgtReqAddrCallback); 1039 HAL_StatusTypeDef HAL_I3C_RegisterTgtHotJoinCallback(I3C_HandleTypeDef *hi3c, 1040 pI3C_TgtHotJoinCallbackTypeDef pTgtHotJoinCallback); 1041 HAL_StatusTypeDef HAL_I3C_UnRegisterCallback(I3C_HandleTypeDef *hi3c, HAL_I3C_CallbackIDTypeDef callbackID); 1042 #endif /* USE_HAL_I3C_REGISTER_CALLBACKS == 1U */ 1043 1044 HAL_StatusTypeDef HAL_I3C_ActivateNotification(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, 1045 uint32_t interruptMask); 1046 HAL_StatusTypeDef HAL_I3C_DeactivateNotification(I3C_HandleTypeDef *hi3c, uint32_t interruptMask); 1047 void HAL_I3C_CtrlTxCpltCallback(I3C_HandleTypeDef *hi3c); 1048 void HAL_I3C_CtrlRxCpltCallback(I3C_HandleTypeDef *hi3c); 1049 void HAL_I3C_CtrlMultipleXferCpltCallback(I3C_HandleTypeDef *hi3c); 1050 void HAL_I3C_CtrlDAACpltCallback(I3C_HandleTypeDef *hi3c); 1051 void HAL_I3C_TgtReqDynamicAddrCallback(I3C_HandleTypeDef *hi3c, uint64_t targetPayload); 1052 void HAL_I3C_TgtTxCpltCallback(I3C_HandleTypeDef *hi3c); 1053 void HAL_I3C_TgtRxCpltCallback(I3C_HandleTypeDef *hi3c); 1054 void HAL_I3C_TgtHotJoinCallback(I3C_HandleTypeDef *hi3c, uint8_t dynamicAddress); 1055 void HAL_I3C_NotifyCallback(I3C_HandleTypeDef *hi3c, uint32_t eventId); 1056 void HAL_I3C_AbortCpltCallback(I3C_HandleTypeDef *hi3c); 1057 void HAL_I3C_ErrorCallback(I3C_HandleTypeDef *hi3c); 1058 void HAL_I3C_ER_IRQHandler(I3C_HandleTypeDef *hi3c); 1059 void HAL_I3C_EV_IRQHandler(I3C_HandleTypeDef *hi3c); 1060 /** 1061 * @} 1062 */ 1063 1064 /** @addtogroup I3C_Exported_Functions_Group3 Configuration functions. 1065 * @{ 1066 */ 1067 HAL_StatusTypeDef HAL_I3C_Ctrl_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c, 1068 const LL_I3C_CtrlBusConfTypeDef *pConfig); 1069 HAL_StatusTypeDef HAL_I3C_Tgt_BusCharacteristicConfig(I3C_HandleTypeDef *hi3c, 1070 const LL_I3C_TgtBusConfTypeDef *pConfig); 1071 HAL_StatusTypeDef HAL_I3C_SetConfigFifo(I3C_HandleTypeDef *hi3c, const I3C_FifoConfTypeDef *pConfig); 1072 HAL_StatusTypeDef HAL_I3C_Ctrl_Config(I3C_HandleTypeDef *hi3c, const I3C_CtrlConfTypeDef *pConfig); 1073 HAL_StatusTypeDef HAL_I3C_Tgt_Config(I3C_HandleTypeDef *hi3c, const I3C_TgtConfTypeDef *pConfig); 1074 HAL_StatusTypeDef HAL_I3C_Ctrl_ConfigBusDevices(I3C_HandleTypeDef *hi3c, 1075 const I3C_DeviceConfTypeDef *pDesc, 1076 uint8_t nbDevice); 1077 HAL_StatusTypeDef HAL_I3C_AddDescToFrame(I3C_HandleTypeDef *hi3c, 1078 const I3C_CCCTypeDef *pCCCDesc, 1079 const I3C_PrivateTypeDef *pPrivateDesc, 1080 I3C_XferTypeDef *pXferData, 1081 uint8_t nbFrame, 1082 uint32_t option); 1083 /** 1084 * @} 1085 */ 1086 1087 /** @addtogroup I3C_Exported_Functions_Group4 FIFO Management functions. 1088 * @{ 1089 */ 1090 HAL_StatusTypeDef HAL_I3C_FlushAllFifo(I3C_HandleTypeDef *hi3c); 1091 HAL_StatusTypeDef HAL_I3C_FlushTxFifo(I3C_HandleTypeDef *hi3c); 1092 HAL_StatusTypeDef HAL_I3C_FlushRxFifo(I3C_HandleTypeDef *hi3c); 1093 HAL_StatusTypeDef HAL_I3C_FlushControlFifo(I3C_HandleTypeDef *hi3c); 1094 HAL_StatusTypeDef HAL_I3C_FlushStatusFifo(I3C_HandleTypeDef *hi3c); 1095 HAL_StatusTypeDef HAL_I3C_ClearConfigFifo(I3C_HandleTypeDef *hi3c); 1096 HAL_StatusTypeDef HAL_I3C_GetConfigFifo(I3C_HandleTypeDef *hi3c, I3C_FifoConfTypeDef *pConfig); 1097 /** 1098 * @} 1099 */ 1100 1101 /** @addtogroup I3C_Exported_Functions_Group5 Controller operational functions. 1102 * @{ 1103 */ 1104 /* Controller transmit direct write or a broadcast CCC command APIs */ 1105 HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC(I3C_HandleTypeDef *hi3c, 1106 I3C_XferTypeDef *pXferData, 1107 uint32_t timeout); 1108 HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_IT(I3C_HandleTypeDef *hi3c, 1109 I3C_XferTypeDef *pXferData); 1110 HAL_StatusTypeDef HAL_I3C_Ctrl_TransmitCCC_DMA(I3C_HandleTypeDef *hi3c, 1111 I3C_XferTypeDef *pXferData); 1112 1113 /* Controller transmit direct read CCC command APIs */ 1114 HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC(I3C_HandleTypeDef *hi3c, 1115 I3C_XferTypeDef *pXferData, 1116 uint32_t timeout); 1117 HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_IT(I3C_HandleTypeDef *hi3c, 1118 I3C_XferTypeDef *pXferData); 1119 HAL_StatusTypeDef HAL_I3C_Ctrl_ReceiveCCC_DMA(I3C_HandleTypeDef *hi3c, 1120 I3C_XferTypeDef *pXferData); 1121 1122 /* Controller private write APIs */ 1123 HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit(I3C_HandleTypeDef *hi3c, 1124 I3C_XferTypeDef *pXferData, 1125 uint32_t timeout); 1126 HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_IT(I3C_HandleTypeDef *hi3c, 1127 I3C_XferTypeDef *pXferData); 1128 HAL_StatusTypeDef HAL_I3C_Ctrl_Transmit_DMA(I3C_HandleTypeDef *hi3c, 1129 I3C_XferTypeDef *pXferData); 1130 1131 /* Controller private read APIs */ 1132 HAL_StatusTypeDef HAL_I3C_Ctrl_Receive(I3C_HandleTypeDef *hi3c, 1133 I3C_XferTypeDef *pXferData, 1134 uint32_t timeout); 1135 HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_IT(I3C_HandleTypeDef *hi3c, 1136 I3C_XferTypeDef *pXferData); 1137 HAL_StatusTypeDef HAL_I3C_Ctrl_Receive_DMA(I3C_HandleTypeDef *hi3c, 1138 I3C_XferTypeDef *pXferData); 1139 1140 /* Controller multiple Direct CCC Command, I3C private or I2C transfer APIs */ 1141 HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_IT(I3C_HandleTypeDef *hi3c, 1142 I3C_XferTypeDef *pXferData); 1143 HAL_StatusTypeDef HAL_I3C_Ctrl_MultipleTransfer_DMA(I3C_HandleTypeDef *hi3c, 1144 I3C_XferTypeDef *pXferData); 1145 1146 /* Controller assign dynamic address APIs */ 1147 HAL_StatusTypeDef HAL_I3C_Ctrl_SetDynAddr(I3C_HandleTypeDef *hi3c, uint8_t devAddress); 1148 HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign_IT(I3C_HandleTypeDef *hi3c, uint32_t dynOption); 1149 HAL_StatusTypeDef HAL_I3C_Ctrl_DynAddrAssign(I3C_HandleTypeDef *hi3c, 1150 uint64_t *target_payload, 1151 uint32_t dynOption, 1152 uint32_t timeout); 1153 /* Controller check device ready APIs */ 1154 HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI3C_Ready(I3C_HandleTypeDef *hi3c, 1155 uint8_t devAddress, 1156 uint32_t trials, 1157 uint32_t timeout); 1158 HAL_StatusTypeDef HAL_I3C_Ctrl_IsDeviceI2C_Ready(I3C_HandleTypeDef *hi3c, 1159 uint8_t devAddress, 1160 uint32_t trials, 1161 uint32_t timeout); 1162 /** 1163 * @} 1164 */ 1165 1166 /** @addtogroup I3C_Exported_Functions_Group6 Target operational functions. 1167 * @{ 1168 */ 1169 HAL_StatusTypeDef HAL_I3C_Tgt_Transmit(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout); 1170 HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); 1171 HAL_StatusTypeDef HAL_I3C_Tgt_Transmit_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); 1172 HAL_StatusTypeDef HAL_I3C_Tgt_Receive(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData, uint32_t timeout); 1173 HAL_StatusTypeDef HAL_I3C_Tgt_Receive_IT(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); 1174 HAL_StatusTypeDef HAL_I3C_Tgt_Receive_DMA(I3C_HandleTypeDef *hi3c, I3C_XferTypeDef *pXferData); 1175 HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq(I3C_HandleTypeDef *hi3c, uint32_t timeout); 1176 HAL_StatusTypeDef HAL_I3C_Tgt_ControlRoleReq_IT(I3C_HandleTypeDef *hi3c); 1177 HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq(I3C_HandleTypeDef *hi3c, uint8_t *pAddress, uint32_t timeout); 1178 HAL_StatusTypeDef HAL_I3C_Tgt_HotJoinReq_IT(I3C_HandleTypeDef *hi3c); 1179 HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq(I3C_HandleTypeDef *hi3c, uint8_t *pPayload, uint8_t payloadSize, uint32_t timeout); 1180 HAL_StatusTypeDef HAL_I3C_Tgt_IBIReq_IT(I3C_HandleTypeDef *hi3c, uint8_t *pPayload, uint8_t payloadSize); 1181 /** 1182 * @} 1183 */ 1184 1185 /** @addtogroup I3C_Exported_Functions_Group7 Generic and Common functions. 1186 * @{ 1187 */ 1188 HAL_StatusTypeDef HAL_I3C_Abort_IT(I3C_HandleTypeDef *hi3c); 1189 HAL_I3C_StateTypeDef HAL_I3C_GetState(I3C_HandleTypeDef *hi3c); 1190 HAL_I3C_ModeTypeDef HAL_I3C_GetMode(I3C_HandleTypeDef *hi3c); 1191 uint32_t HAL_I3C_GetError(I3C_HandleTypeDef *hi3c); 1192 HAL_StatusTypeDef HAL_I3C_GetCCCInfo(I3C_HandleTypeDef *hi3c, 1193 uint32_t notifyId, 1194 I3C_CCCInfoTypeDef *pCCCInfo); 1195 /** 1196 * @} 1197 */ 1198 1199 /** 1200 * @} 1201 */ 1202 1203 /* Private constants -------------------------------------------------------------------------------------------------*/ 1204 /** @defgroup I3C_Private_Constants I3C Private Constants 1205 * @{ 1206 */ 1207 1208 /** 1209 * @} 1210 */ 1211 1212 /* Private macros ----------------------------------------------------------------------------------------------------*/ 1213 /** @defgroup I3C_Private_Macro I3C Private Macros 1214 * @{ 1215 */ 1216 #define IS_I3C_MODE(__MODE__) (((__MODE__) == HAL_I3C_MODE_NONE) || \ 1217 ((__MODE__) == HAL_I3C_MODE_CONTROLLER) || \ 1218 ((__MODE__) == HAL_I3C_MODE_TARGET)) 1219 1220 #define IS_I3C_INTERRUPTMASK(__MODE__, __ITMASK__) (((__MODE__) == HAL_I3C_MODE_CONTROLLER) ? \ 1221 ((((__ITMASK__) & HAL_I3C_ALL_CTRL_ITS) != 0x0U) || \ 1222 (((__ITMASK__) & HAL_I3C_ALL_COMMON_ITS) != 0x0U)) : \ 1223 ((((__ITMASK__) & HAL_I3C_ALL_TGT_ITS) != 0x0U) || \ 1224 (((__ITMASK__) & HAL_I3C_ALL_COMMON_ITS) != 0x0U))) 1225 1226 #define IS_I3C_ENTDAA_OPTION(__OPTION__) (((__OPTION__) == I3C_RSTDAA_THEN_ENTDAA) || \ 1227 ((__OPTION__) == I3C_ONLY_ENTDAA)) 1228 1229 #define IS_I3C_SDAHOLDTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_0_5) || \ 1230 ((__VALUE__) == HAL_I3C_SDA_HOLD_TIME_1_5)) 1231 1232 #define IS_I3C_WAITTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_0) || \ 1233 ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_1) || \ 1234 ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_2) || \ 1235 ((__VALUE__) == HAL_I3C_OWN_ACTIVITY_STATE_3)) 1236 1237 #define IS_I3C_TXFIFOTHRESHOLD_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_TXFIFO_THRESHOLD_1_4) || \ 1238 ((__VALUE__) == HAL_I3C_TXFIFO_THRESHOLD_4_4)) 1239 1240 #define IS_I3C_RXFIFOTHRESHOLD_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_RXFIFO_THRESHOLD_1_4) || \ 1241 ((__VALUE__) == HAL_I3C_RXFIFO_THRESHOLD_4_4)) 1242 1243 #define IS_I3C_CONTROLFIFOSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_CONTROLFIFO_DISABLE) || \ 1244 ((__VALUE__) == HAL_I3C_CONTROLFIFO_ENABLE)) 1245 1246 #define IS_I3C_STATUSFIFOSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_STATUSFIFO_DISABLE) || \ 1247 ((__VALUE__) == HAL_I3C_STATUSFIFO_ENABLE)) 1248 1249 #define IS_I3C_DEVICE_VALUE(__VALUE__) (((__VALUE__) >= 1U) && ((__VALUE__) <= 4U)) 1250 1251 #define IS_I3C_DYNAMICADDRESS_VALUE(__VALUE__) ((__VALUE__) <= 0x7FU) 1252 1253 #define IS_I3C_FUNCTIONALSTATE_VALUE(__VALUE__) (((__VALUE__) == DISABLE) || \ 1254 ((__VALUE__) == ENABLE)) 1255 1256 #define IS_I3C_HANDOFFACTIVITYSTATE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_0) || \ 1257 ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_1) || \ 1258 ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_2) || \ 1259 ((__VALUE__) == HAL_I3C_HANDOFF_ACTIVITY_STATE_3)) 1260 1261 #define IS_I3C_TSCOTIME_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_TURNAROUND_TIME_TSCO_LESS_12NS) || \ 1262 ((__VALUE__) == HAL_I3C_TURNAROUND_TIME_TSCO_GREATER_12NS)) 1263 1264 #define IS_I3C_MAXSPEEDDATA_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_1 ) || \ 1265 ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_LSB) || \ 1266 ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_MID) || \ 1267 ((__VALUE__) == HAL_I3C_GETMXDS_FORMAT_2_MSB)) 1268 1269 #define IS_I3C_IBIPAYLOADSIZE_VALUE(__VALUE__) (((__VALUE__) == HAL_I3C_PAYLOAD_EMPTY ) || \ 1270 ((__VALUE__) == HAL_I3C_PAYLOAD_1_BYTE ) || \ 1271 ((__VALUE__) == HAL_I3C_PAYLOAD_2_BYTES) || \ 1272 ((__VALUE__) == HAL_I3C_PAYLOAD_3_BYTES) || \ 1273 ((__VALUE__) == HAL_I3C_PAYLOAD_4_BYTES)) 1274 1275 #define IS_I3C_MIPIIDENTIFIER_VALUE(__VALUE__) ((__VALUE__) <= 0x0FU) 1276 1277 #define IS_I3C_MAXREADTURNARROUND_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU) 1278 1279 #define I3C_CHECK_IT_SOURCE(__IER__, __IT__) ((((__IER__) & (__IT__)) == (__IT__)) ? SET : RESET) 1280 1281 #define I3C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) 1282 1283 #define IS_I3C_DMASOURCEBYTE_VALUE(__VALUE__) ((__VALUE__) == DMA_SRC_DATAWIDTH_BYTE) 1284 1285 #define IS_I3C_DMASOURCEWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_SRC_DATAWIDTH_WORD) 1286 1287 #define IS_I3C_DMADESTINATIONBYTE_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_BYTE) 1288 1289 #define IS_I3C_DMADESTINATIONWORD_VALUE(__VALUE__) ((__VALUE__) == DMA_DEST_DATAWIDTH_WORD) 1290 1291 #define I3C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) 1292 1293 /** 1294 * @} 1295 */ 1296 1297 /* Private functions -------------------------------------------------------------------------------------------------*/ 1298 /** @defgroup I3C_Private_Functions I3C Private Functions 1299 * @{ 1300 */ 1301 /* Private functions are defined in stm32h5xx_hal_i3c.c file */ 1302 /** 1303 * @} 1304 */ 1305 1306 /** 1307 * @} 1308 */ 1309 1310 /** 1311 * @} 1312 */ 1313 1314 #ifdef __cplusplus 1315 } 1316 #endif 1317 1318 #endif /* STM32H5xx_HAL_I3C_H */ 1319
