1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_hrtim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the High Resolution Timer (HRTIM) peripheral:
8 * + HRTIM Initialization
9 * + DLL Calibration Start
10 * + Timer Time Base Unit Configuration
11 * + Simple Time Base Start/Stop
12 * + Simple Time Base Start/Stop Interrupt
13 * + Simple Time Base Start/Stop DMA Request
14 * + Simple Output Compare/PWM Channel Configuration
15 * + Simple Output Compare/PWM Channel Start/Stop Interrupt
16 * + Simple Output Compare/PWM Channel Start/Stop DMA Request
17 * + Simple Input Capture Channel Configuration
18 * + Simple Input Capture Channel Start/Stop Interrupt
19 * + Simple Input Capture Channel Start/Stop DMA Request
20 * + Simple One Pulse Channel Configuration
21 * + Simple One Pulse Channel Start/Stop Interrupt
22 * + HRTIM External Synchronization Configuration
23 * + HRTIM Burst Mode Controller Configuration
24 * + HRTIM Burst Mode Controller Enabling
25 * + HRTIM External Events Conditioning Configuration
26 * + HRTIM Faults Conditioning Configuration
27 * + HRTIM Faults Enabling
28 * + HRTIM ADC trigger Configuration
29 * + Waveform Timer Configuration
30 * + Waveform Event Filtering Configuration
31 * + Waveform Dead Time Insertion Configuration
32 * + Waveform Chopper Mode Configuration
33 * + Waveform Compare Unit Configuration
34 * + Waveform Capture Unit Configuration
35 * + Waveform Output Configuration
36 * + Waveform Counter Start/Stop
37 * + Waveform Counter Start/Stop Interrupt
38 * + Waveform Counter Start/Stop DMA Request
39 * + Waveform Output Enabling
40 * + Waveform Output Level Set/Get
41 * + Waveform Output State Get
42 * + Waveform Burst DMA Operation Configuration
43 * + Waveform Burst DMA Operation Start
44 * + Waveform Timer Counter Software Reset
45 * + Waveform Capture Software Trigger
46 * + Waveform Burst Mode Controller Software Trigger
47 * + Waveform Timer Pre-loadable Registers Update Enabling
48 * + Waveform Timer Pre-loadable Registers Software Update
49 * + Waveform Timer Delayed Protection Status Get
50 * + Waveform Timer Burst Status Get
51 * + Waveform Timer Push-Pull Status Get
52 * + Peripheral State Get
53 *
54 ******************************************************************************
55 * @attention
56 *
57 * Copyright (c) 2019 STMicroelectronics.
58 * All rights reserved.
59 *
60 * This software is licensed under terms that can be found in the LICENSE file
61 * in the root directory of this software component.
62 * If no LICENSE file comes with this software, it is provided AS-IS.
63 *
64 ******************************************************************************
65 @verbatim
66 ==============================================================================
67 ##### Simple mode v.s. waveform mode #####
68 ==============================================================================
69 [..] The HRTIM HAL API is split into 2 categories:
70 (#)Simple functions: these functions allow for using a HRTIM timer as a
71 general purpose timer with high resolution capabilities.
72 HRTIM simple modes are managed through the set of functions named
73 HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
74 to the one defined for the TIM peripheral. When a HRTIM timer operates in
75 simple mode, only a very limited set of HRTIM features are used.
76 Following simple modes are proposed:
77 (++)Output compare mode,
78 (++)PWM output mode,
79 (++)Input capture mode,
80 (++)One pulse mode.
81 (#)Waveform functions: These functions allow taking advantage of the HRTIM
82 flexibility to produce numerous types of control signal. When a HRTIM timer
83 operates in waveform mode, all the HRTIM features are accessible without
84 any restriction. HRTIM waveform modes are managed through the set of
85 functions named HAL_HRTIM_Waveform<Function>
86
87 ==============================================================================
88 ##### How to use this driver #####
89 ==============================================================================
90 [..]
91 (#)Initialize the HRTIM low level resources by implementing the
92 HAL_HRTIM_MspInit() function:
93 (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
94 (##)Connect HRTIM pins to MCU I/Os
95 (+++) Enable the clock for the HRTIM GPIOs using the following
96 function: __HAL_RCC_GPIOx_CLK_ENABLE()
97 (+++) Configure these GPIO pins in Alternate Function mode using
98 HAL_GPIO_Init()
99 (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
100 (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
101 (+++)Initialize the DMA handle
102 (+++)Associate the initialized DMA handle to the appropriate DMA
103 handle of the HRTIM handle using __HAL_LINKDMA()
104 (+++)Initialize the DMA channel using HAL_DMA_Init()
105 (+++)Configure the priority and enable the NVIC for the transfer
106 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
107 and HAL_NVIC_EnableIRQ()
108 (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
109 (+++)Configure the priority and enable the NVIC for the concerned
110 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
111
112 (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
113 structure (field of the HRTIM handle) specifies which global interrupt of
114 whole HRTIM must be enabled (Burst mode period, System fault, Faults).
115 It also contains the HRTIM external synchronization configuration. HRTIM
116 can act as a master (generating a synchronization signal) or as a slave
117 (waiting for a trigger to be synchronized).
118
119 (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
120 calibration is executed periodically and compensate for potential voltage
121 and temperature drifts. DLL calibration period is specified by the
122 CalibrationRate argument.
123
124 (#)HRTIM timers cannot be used until the high resolution unit is ready. This
125 can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
126 HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
127 is still going on when timeout given as argument expires. DLL calibration
128 can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
129 In that case an interrupt is generated when the DLL calibration is completed.
130 Note that as DLL calibration is executed on a periodic basis an interrupt
131 will be generated at the end of every DLL calibration operation
132 (worst case: one interrupt every 14 micro seconds !).
133
134 (#) Configure HRTIM resources shared by all HRTIM timers
135 (##)Burst Mode Controller:
136 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
137 controller: operating mode (continuous or one-shot mode), clock
138 (source, prescaler) , trigger(s), period, idle duration.
139 (##)External Events Conditioning:
140 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
141 external event channel: source, polarity, edge-sensitivity.
142 External event can be used as triggers (timer reset, input
143 capture, burst mode, ADC triggers, delayed protection)
144 They can also be used to set or reset timer outputs. Up to
145 10 event channels are available.
146 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
147 event sampling clock (used for digital filtering).
148 (##)Fault Conditioning:
149 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
150 fault channel: source, polarity, edge-sensitivity. Fault
151 channels are used to disable the outputs in case of an
152 abnormal operation. Up to 6 fault channels are available.
153 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
154 sampling clock (used for digital filtering).
155 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
156 circuitry. By default all fault inputs are disabled.
157 (##)ADC trigger:
158 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
159 the update of the ADC trigger register and the ADC trigger.
160 4 independent triggers are available to start both the regular
161 and the injected sequencers of the 2 ADCs
162
163 (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
164 function must be called whatever the HRTIM timer operating mode is
165 (simple v.s. waveform). It configures mainly:
166 (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
167 (##)The HRTIM timer clock prescaler
168 (##)The HRTIM timer period
169 (##)The HRTIM timer repetition counter
170
171 *** If the HRTIM timer operates in simple mode ***
172 ===================================================
173 [..]
174 (#) Start or Stop simple timers
175 (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
176 HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
177 HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
178 (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
179 HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
180 HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
181 HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
182 (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
183 HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
184 HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
185 HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
186 (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
187 HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
188 HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
189 HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
190 (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
191 HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
192 HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
193
194 *** If the HRTIM timer operates in waveform mode ***
195 ====================================================
196 [..]
197 (#) Completes waveform timer configuration
198 (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
199 operating in wave form mode mainly consists in:
200 (+++)Enabling the HRTIM timer interrupts and DMA requests.
201 (+++)Enabling the half mode for the HRTIM timer.
202 (+++)Defining how the HRTIM timer reacts to external synchronization input.
203 (+++)Enabling the push-pull mode for the HRTIM timer.
204 (+++)Enabling the fault channels for the HRTIM timer.
205 (+++)Enabling the dead-time insertion for the HRTIM timer.
206 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
207 on which the delayed protection are applied).
208 (+++)Specifying the HRTIM timer update and reset triggers.
209 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
210 (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
211 event blanking and windowing circuitry of a HRTIM timer:
212 (+++)Blanking: to mask external events during a defined time period a defined time period
213 (+++)Windowing, to enable external events only during a defined time period
214 (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
215 unit for a HRTIM timer. Allows to generate a couple of
216 complementary signals from a single reference waveform,
217 with programmable delays between active state.
218 (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
219 the high-frequency carrier signal added on top of the timing
220 unit output. Chopper mode can be enabled or disabled for each
221 timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
222 (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
223 controller. Allows having multiple HRTIM registers updated
224 with a single DMA request. The burst DMA operation is started
225 by calling HAL_HRTIM_BurstDMATransfer().
226 (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
227 of a HRTIM timer. This operation consists in setting the
228 compare value and possibly specifying the auto delayed mode
229 for compare units 2 and 4 (allows to have compare events
230 generated relatively to capture events). Note that when auto
231 delayed mode is needed, the capture unit associated to the
232 compare unit must be configured separately.
233 (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
234 of a HRTIM timer. This operation consists in specifying the
235 source(s) triggering the capture (timer register update event,
236 external event, timer output set/reset event, other HRTIM
237 timer related events).
238 (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
239 output mainly consists in:
240 (+++)Setting the output polarity (active high or active low),
241 (+++)Defining the set/reset crossbar for the output,
242 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
243
244 (#) Set waveform timer output(s) level
245 (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
246 active or inactive level. For example, when deadtime insertion
247 is enabled it is necessary to force the output level by software
248 to have the outputs in a complementary state as soon as the RUN mode is entered.
249
250 (#) Enable or Disable waveform timer output(s)
251 (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
252
253 (#) Start or Stop waveform HRTIM timer(s).
254 (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
255 (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
256 (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
257 (#) Burst mode controller enabling:
258 (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
259 burst mode controller.
260
261 (#) Some HRTIM operations can be triggered by software:
262 (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
263 trigs the burst operation.
264 (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
265 capture of the HRTIM timer counter.
266 (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
267 update of the pre-loadable registers of the HRTIM timer
268 (++)HAL_HRTIM_SoftwareReset():calling this function resets the
269 HRTIM timer counter.
270
271 (#) Some functions can be used any time to retrieve HRTIM timer related
272 information
273 (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
274 capture register of the designated capture unit.
275 (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
276 (ACTIVE/INACTIVE) of the designated timer output.
277 (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
278 (IDLE/RUN/FAULT) of the designated timer output.
279 (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
280 (ACTIVE/INACTIVE) of the designated output when the delayed
281 protection was triggered.
282 (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
283 (ACTIVE/INACTIVE) of the burst mode controller.
284 (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
285 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
286 the push-pull status indicates on which output the signal is currently
287 active (e.g signal applied on output 1 and output 2 forced
288 inactive or vice versa).
289 (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
290 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
291 the idle push-pull status indicates during which period the
292 delayed protection request occurred (e.g. protection occurred
293 when the output 1 was active and output 2 forced inactive or
294 vice versa).
295
296 (#) Some functions can be used any time to retrieve actual HRTIM status
297 (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
298
299 *** Callback registration ***
300 =============================
301 [..]
302 The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
303 allows the user to configure dynamically the driver callbacks.
304 Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
305 to register an interrupt callback.
306
307 [..]
308 Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
309 (+) Fault1Callback : Fault 1 interrupt callback function
310 (+) Fault2Callback : Fault 2 interrupt callback function
311 (+) Fault3Callback : Fault 3 interrupt callback function
312 (+) Fault4Callback : Fault 4 interrupt callback function
313 (+) Fault5Callback : Fault 5 interrupt callback function
314 (+) Fault6Callback : Fault 6 interrupt callback function
315 (+) SystemFaultCallback : System fault interrupt callback function
316 (+) DLLCalibrationReadyCallback : DLL Ready interrupt callback function
317 (+) BurstModePeriodCallback : Burst mode period interrupt callback function
318 (+) SynchronizationEventCallback : Sync Input interrupt callback function
319 (+) ErrorCallback : DMA error callback function
320 (+) MspInitCallback : HRTIM MspInit callback function
321 (+) MspDeInitCallback : HRTIM MspInit callback function
322
323 [..]
324 Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
325 (+) RegistersUpdateCallback : Timer x Update interrupt callback function
326 (+) RepetitionEventCallback : Timer x Repetition interrupt callback function
327 (+) Compare1EventCallback : Timer x Compare 1 match interrupt callback function
328 (+) Compare2EventCallback : Timer x Compare 2 match interrupt callback function
329 (+) Compare3EventCallback : Timer x Compare 3 match interrupt callback function
330 (+) Compare4EventCallback : Timer x Compare 4 match interrupt callback function
331 (+) Capture1EventCallback : Timer x Capture 1 interrupts callback function
332 (+) Capture2EventCallback : Timer x Capture 2 interrupts callback function
333 (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
334 (+) CounterResetCallback : Timer x counter reset/roll-over interrupt callback function
335 (+) Output1SetCallback : Timer x output 1 set interrupt callback function
336 (+) Output1ResetCallback : Timer x output 1 reset interrupt callback function
337 (+) Output2SetCallback : Timer x output 2 set interrupt callback function
338 (+) Output2ResetCallback : Timer x output 2 reset interrupt callback function
339 (+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function
340
341 [..]
342 Both functions take as parameters the HAL peripheral handle, the Callback ID
343 and a pointer to the user callback function.
344
345 [..]
346 Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
347 to reset a callback to the default weak function. Both functions take as parameters
348 the HAL peripheral handle and the Callback ID.
349
350 [..]
351 By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
352 all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
353 Exception done for MspInit and MspDeInit functions that are reset to the legacy
354 weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
355 callbacks are null (not registered beforehand). If MspInit or MspDeInit are
356 not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
357 MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
358
359 [..]
360 Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
361 Exception done MspInit/MspDeInit functions that can be registered/unregistered
362 in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
363 (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
364 Then, the user first registers the MspInit/MspDeInit user callbacks
365 using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
366 or HAL_HRTIM_Init() function.
367
368 [..]
369 When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
370 not defined, the callback registration feature is not available and all
371 callbacks are set to the corresponding weak functions.
372
373 @endverbatim
374 ******************************************************************************
375 */
376
377 /* Includes ------------------------------------------------------------------*/
378 #include "stm32g4xx_hal.h"
379
380 /** @addtogroup STM32G4xx_HAL_Driver
381 * @{
382 */
383
384 #ifdef HAL_HRTIM_MODULE_ENABLED
385
386 #if defined(HRTIM1)
387
388 /** @defgroup HRTIM HRTIM
389 * @brief HRTIM HAL module driver
390 * @{
391 */
392
393 /* Private typedef -----------------------------------------------------------*/
394 /* Private define ------------------------------------------------------------*/
395 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
396 * @{
397 */
398 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
399 HRTIM_FLTR_FLT2EN |\
400 HRTIM_FLTR_FLT3EN |\
401 HRTIM_FLTR_FLT4EN | \
402 HRTIM_FLTR_FLT5EN | \
403 HRTIM_FLTR_FLT6EN)
404
405 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
406 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
407 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
408 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
409 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
410 HRTIM_TIMUPDATETRIGGER_TIMER_E |\
411 HRTIM_TIMUPDATETRIGGER_TIMER_F)
412
413 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
414 (HRTIM_FAULTLOCK_READONLY << 8U) | \
415 (HRTIM_FAULTLOCK_READONLY << 16U) | \
416 (HRTIM_FAULTLOCK_READONLY << 24U))
417
418 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
419 (HRTIM_FAULTLOCK_READONLY << 8U))
420 /**
421 * @}
422 */
423
424 /* Private macro -------------------------------------------------------------*/
425 /* Private variables ---------------------------------------------------------*/
426 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
427 * @{
428 */
429 static uint32_t TimerIdxToTimerId[] =
430 {
431 HRTIM_TIMERID_TIMER_A,
432 HRTIM_TIMERID_TIMER_B,
433 HRTIM_TIMERID_TIMER_C,
434 HRTIM_TIMERID_TIMER_D,
435 HRTIM_TIMERID_TIMER_E,
436 HRTIM_TIMERID_TIMER_F,
437 HRTIM_TIMERID_MASTER,
438 };
439 /**
440 * @}
441 */
442
443 /* Private function prototypes -----------------------------------------------*/
444 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
445 * @{
446 */
447 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
448 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
449
450 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
451 uint32_t TimerIdx,
452 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
453
454 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
455 HRTIM_TimerCfgTypeDef * pTimerCfg);
456
457 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
458 uint32_t TimerIdx,
459 HRTIM_TimerCfgTypeDef * pTimerCfg);
460
461 static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim,
462 uint32_t TimerIdx,
463 HRTIM_TimerCtlTypeDef * pTimerCtl);
464
465 static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim,
466 uint32_t TimerIdx,
467 uint32_t pRollOverMode);
468
469
470 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
471 uint32_t TimerIdx,
472 uint32_t CaptureUnit,
473 uint32_t Event);
474
475 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
476 uint32_t TimerIdx,
477 uint32_t Output,
478 HRTIM_OutputCfgTypeDef * pOutputCfg);
479
480 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
481 uint32_t Event,
482 HRTIM_EventCfgTypeDef * pEventCfg);
483
484 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
485 uint32_t TimerIdx,
486 uint32_t Event);
487
488 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
489 uint32_t TimerIdx,
490 uint32_t OCChannel);
491
492 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
493 uint32_t TimerIdx,
494 uint32_t OCChannel);
495
496 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
497 uint32_t TimerIdx);
498
499 static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
500 DMA_HandleTypeDef * hdma);
501
502 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
503 uint32_t TimerIdx);
504
505 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
506
507 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
508
509 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
510 uint32_t TimerIdx);
511
512 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
513
514 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
515
516 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
517
518 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
519 /**
520 * @}
521 */
522
523 /* Exported functions ---------------------------------------------------------*/
524 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
525 * @{
526 */
527
528 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
529 * @brief Initialization and Configuration functions
530 @verbatim
531 ===============================================================================
532 ##### Initialization and Time Base Configuration functions #####
533 ===============================================================================
534 [..] This section provides functions allowing to:
535 (+) Initialize a HRTIM instance
536 (+) De-initialize a HRTIM instance
537 (+) Initialize the HRTIM MSP
538 (+) De-initialize the HRTIM MSP
539 (+) Start the high-resolution unit (start DLL calibration)
540 (+) Check that the high resolution unit is ready (DLL calibration done)
541 (+) Configure the time base unit of a HRTIM timer
542
543 @endverbatim
544 * @{
545 */
546
547 /**
548 * @brief Initialize a HRTIM instance
549 * @param hhrtim pointer to HAL HRTIM handle
550 * @retval HAL status
551 */
HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)552 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
553 {
554 uint8_t timer_idx;
555 uint32_t hrtim_mcr;
556
557 /* Check the HRTIM handle allocation */
558 if(hhrtim == NULL)
559 {
560 return HAL_ERROR;
561 }
562
563 /* Check the parameters */
564 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
565 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
566
567 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
568 if (hhrtim->State == HAL_HRTIM_STATE_RESET)
569 {
570 /* Initialize callback function pointers to their default values */
571 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
572 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
573 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
574 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
575 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
576 hhrtim->Fault6Callback = HAL_HRTIM_Fault6Callback;
577 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
578 hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
579 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
580 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
581 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
582 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
583 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
584 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
585 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
586 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
587 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
588 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
589 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
590 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
591 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
592 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
593 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
594 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
595 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
596 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
597
598 if (hhrtim->MspInitCallback == NULL)
599 {
600 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
601 }
602 }
603 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
604
605 /* Set the HRTIM state */
606 hhrtim->State = HAL_HRTIM_STATE_BUSY;
607
608 /* Initialize the DMA handles */
609 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
610 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
611 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
612 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
613 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
614 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
615 hhrtim->hdmaTimerF = (DMA_HandleTypeDef *)NULL;
616
617 /* HRTIM output synchronization configuration (if required) */
618 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
619 {
620 /* Check parameters */
621 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
622 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
623
624 /* The synchronization output initialization procedure must be done prior
625 to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
626 */
627 if (hhrtim->Instance == HRTIM1)
628 {
629 /* Enable the HRTIM peripheral clock */
630 __HAL_RCC_HRTIM1_CLK_ENABLE();
631 }
632
633 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
634
635 /* Set the event to be sent on the synchronization output */
636 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
637 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
638
639 /* Set the polarity of the synchronization output */
640 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
641 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
642
643 /* Update the HRTIM registers */
644 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
645 }
646
647 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
648 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
649 hhrtim->MspInitCallback(hhrtim);
650 #else
651 HAL_HRTIM_MspInit(hhrtim);
652 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
653
654 /* HRTIM input synchronization configuration (if required) */
655 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
656 {
657 /* Check parameters */
658 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
659
660 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
661
662 /* Set the synchronization input source */
663 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
664 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
665
666 /* Update the HRTIM registers */
667 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
668 }
669
670 /* Initialize the HRTIM state*/
671 hhrtim->State = HAL_HRTIM_STATE_READY;
672
673 /* Initialize the lock status of the HRTIM HAL API */
674 __HAL_UNLOCK(hhrtim);
675
676 /* Initialize timer related parameters */
677 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
678 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
679 timer_idx++)
680 {
681 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
682 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
683 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
684 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
685 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
686 hhrtim->TimerParam[timer_idx].DMASize = 0U;
687 }
688
689 return HAL_OK;
690 }
691
692 /**
693 * @brief De-initialize a HRTIM instance
694 * @param hhrtim pointer to HAL HRTIM handle
695 * @retval HAL status
696 */
HAL_HRTIM_DeInit(HRTIM_HandleTypeDef * hhrtim)697 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
698 {
699 /* Check the HRTIM handle allocation */
700 if(hhrtim == NULL)
701 {
702 return HAL_ERROR;
703 }
704
705 /* Check the parameters */
706 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
707
708 /* Set the HRTIM state */
709 hhrtim->State = HAL_HRTIM_STATE_BUSY;
710
711 /* DeInit the low level hardware */
712 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
713 if (hhrtim->MspDeInitCallback == NULL)
714 {
715 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
716 }
717
718 hhrtim->MspDeInitCallback(hhrtim);
719 #else
720 HAL_HRTIM_MspDeInit(hhrtim);
721 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
722
723 hhrtim->State = HAL_HRTIM_STATE_READY;
724
725 return HAL_OK;
726 }
727
728 /**
729 * @brief MSP initialization for a HRTIM instance
730 * @param hhrtim pointer to HAL HRTIM handle
731 * @retval None
732 */
HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)733 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
734 {
735 /* Prevent unused argument(s) compilation warning */
736 UNUSED(hhrtim);
737
738 /* NOTE: This function should not be modified, when the callback is needed,
739 the HAL_HRTIM_MspInit could be implemented in the user file
740 */
741 }
742
743 /**
744 * @brief MSP de-initialization of a HRTIM instance
745 * @param hhrtim pointer to HAL HRTIM handle
746 * @retval None
747 */
HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)748 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
749 {
750 /* Prevent unused argument(s) compilation warning */
751 UNUSED(hhrtim);
752
753 /* NOTE: This function should not be modified, when the callback is needed,
754 the HAL_HRTIM_MspDeInit could be implemented in the user file
755 */
756 }
757
758 /**
759 * @brief Start the DLL calibration
760 * @param hhrtim pointer to HAL HRTIM handle
761 * @param CalibrationRate DLL calibration period
762 * This parameter can be one of the following values:
763 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
764 * @arg HRTIM_CALIBRATIONRATE_0: Periodic DLL calibration. T=6.168 ms
765 * @arg HRTIM_CALIBRATIONRATE_1: Periodic DLL calibration. T=0.771 ms
766 * @arg HRTIM_CALIBRATIONRATE_2: Periodic DLL calibration. T=0.096 ms
767 * @arg HRTIM_CALIBRATIONRATE_3: Periodic DLL calibration. T=0.012 ms
768 * @retval HAL status
769 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
770 * within the HAL_HRTIM_PollForDLLCalibration function, just before
771 * exiting the function.
772 */
HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,uint32_t CalibrationRate)773 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
774 uint32_t CalibrationRate)
775 {
776 /* Check the parameters */
777 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
778
779 /* Process Locked */
780 __HAL_LOCK(hhrtim);
781
782 hhrtim->State = HAL_HRTIM_STATE_BUSY;
783
784 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
785 {
786 /* One shot DLL calibration */
787 CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
788 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
789 }
790 else
791 {
792 /* Periodic DLL calibration */
793 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
794 MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
795 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
796 }
797
798 /* Set HRTIM state */
799 hhrtim->State = HAL_HRTIM_STATE_READY;
800
801 return HAL_OK;
802 }
803
804 /**
805 * @brief Start the DLL calibration.
806 * DLL ready interrupt is enabled
807 * @param hhrtim pointer to HAL HRTIM handle
808 * @param CalibrationRate DLL calibration period
809 * This parameter can be one of the following values:
810 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
811 * @arg HRTIM_CALIBRATIONRATE_0: Periodic DLL calibration. T=6.168 ms
812 * @arg HRTIM_CALIBRATIONRATE_1: Periodic DLL calibration. T=0.771 ms
813 * @arg HRTIM_CALIBRATIONRATE_2: Periodic DLL calibration. T=0.096 ms
814 * @arg HRTIM_CALIBRATIONRATE_3: Periodic DLL calibration. T=0.012 ms
815 * @retval HAL status
816 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
817 * within the IRQ processing function when processing the DLL ready
818 * interrupt.
819 * @note If this function is called for periodic calibration, the DLLRDY
820 * interrupt is generated every time the calibration completes which
821 * will significantly increases the overall interrupt rate.
822 */
HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t CalibrationRate)823 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
824 uint32_t CalibrationRate)
825 {
826 /* Check the parameters */
827 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
828
829 /* Process Locked */
830 __HAL_LOCK(hhrtim);
831
832 hhrtim->State = HAL_HRTIM_STATE_BUSY;
833
834 /* Enable DLL Ready interrupt flag */
835 __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
836
837 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
838 {
839 /* One shot DLL calibration */
840 CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
841 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
842 }
843 else
844 {
845 /* Periodic DLL calibration */
846 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
847 MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
848 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
849 }
850
851 /* Set HRTIM state */
852 hhrtim->State = HAL_HRTIM_STATE_READY;
853
854 return HAL_OK;
855 }
856
857 /**
858 * @brief Poll the DLL calibration ready flag and returns when the flag is
859 * set (DLL calibration completed) or upon timeout expiration.
860 * @param hhrtim pointer to HAL HRTIM handle
861 * @param Timeout Timeout duration in millisecond
862 * @retval HAL status
863 */
HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,uint32_t Timeout)864 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
865 uint32_t Timeout)
866 {
867 uint32_t tickstart;
868
869 tickstart = HAL_GetTick();
870
871 /* Check End of conversion flag */
872 while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET)
873 {
874 if (Timeout != HAL_MAX_DELAY)
875 {
876 if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
877 {
878 hhrtim->State = HAL_HRTIM_STATE_ERROR;
879 return HAL_TIMEOUT;
880 }
881 }
882 }
883
884 /* Set HRTIM State */
885 hhrtim->State = HAL_HRTIM_STATE_READY;
886
887 /* Process unlocked */
888 __HAL_UNLOCK(hhrtim);
889
890 return HAL_OK;
891 }
892
893 /**
894 * @brief Configure the time base unit of a timer
895 * @param hhrtim pointer to HAL HRTIM handle
896 * @param TimerIdx Timer index
897 * This parameter can be one of the following values:
898 * @arg HRTIM_TIMERINDEX_MASTER for master timer
899 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
900 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
901 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
902 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
903 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
904 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
905 * @param pTimeBaseCfg pointer to the time base configuration structure
906 * @note This function must be called prior starting the timer
907 * @note The time-base unit initialization parameters specify:
908 * The timer counter operating mode (continuous, one shot),
909 * The timer clock prescaler,
910 * The timer period,
911 * The timer repetition counter.
912 * @retval HAL status
913 */
HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)914 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
915 uint32_t TimerIdx,
916 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
917 {
918 /* Check the parameters */
919 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
920 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
921 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
922
923 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
924 {
925 return HAL_BUSY;
926 }
927
928 /* Set the HRTIM state */
929 hhrtim->State = HAL_HRTIM_STATE_BUSY;
930
931 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
932 {
933 /* Configure master timer time base unit */
934 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
935 }
936 else
937 {
938 /* Configure timing unit time base unit */
939 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
940 }
941
942 /* Set HRTIM state */
943 hhrtim->State = HAL_HRTIM_STATE_READY;
944
945 return HAL_OK;
946 }
947
948 /**
949 * @}
950 */
951
952 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
953 * @brief Simple time base mode functions.
954 @verbatim
955 ===============================================================================
956 ##### Simple time base mode functions #####
957 ===============================================================================
958 [..] This section provides functions allowing to:
959 (+) Start simple time base
960 (+) Stop simple time base
961 (+) Start simple time base and enable interrupt
962 (+) Stop simple time base and disable interrupt
963 (+) Start simple time base and enable DMA transfer
964 (+) Stop simple time base and disable DMA transfer
965 -@- When a HRTIM timer operates in simple time base mode, the timer
966 counter counts from 0 to the period value.
967
968 @endverbatim
969 * @{
970 */
971
972 /**
973 * @brief Start the counter of a timer operating in simple time base mode.
974 * @param hhrtim pointer to HAL HRTIM handle
975 * @param TimerIdx Timer index.
976 * This parameter can be one of the following values:
977 * @arg HRTIM_TIMERINDEX_MASTER for master timer
978 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
979 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
980 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
981 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
982 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
983 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
984 * @retval HAL status
985 */
HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)986 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
987 uint32_t TimerIdx)
988 {
989 /* Check the parameters */
990 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
991
992 /* Process Locked */
993 __HAL_LOCK(hhrtim);
994
995 hhrtim->State = HAL_HRTIM_STATE_BUSY;
996
997 /* Enable the timer counter */
998 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
999
1000 hhrtim->State = HAL_HRTIM_STATE_READY;
1001
1002 /* Process Unlocked */
1003 __HAL_UNLOCK(hhrtim);
1004
1005 return HAL_OK;
1006 }
1007
1008 /**
1009 * @brief Stop the counter of a timer operating in simple time base mode.
1010 * @param hhrtim pointer to HAL HRTIM handle
1011 * @param TimerIdx Timer index.
1012 * This parameter can be one of the following values:
1013 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1014 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1015 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1016 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1017 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1018 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1019 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1020 * @retval HAL status
1021 */
HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1022 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
1023 uint32_t TimerIdx)
1024 {
1025 /* Check the parameters */
1026 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1027
1028 /* Process Locked */
1029 __HAL_LOCK(hhrtim);
1030
1031 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1032
1033 /* Disable the timer counter */
1034 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1035
1036 hhrtim->State = HAL_HRTIM_STATE_READY;
1037
1038 /* Process Unlocked */
1039 __HAL_UNLOCK(hhrtim);
1040
1041 return HAL_OK;
1042 }
1043
1044 /**
1045 * @brief Start the counter of a timer operating in simple time base mode
1046 * (Timer repetition interrupt is enabled).
1047 * @param hhrtim pointer to HAL HRTIM handle
1048 * @param TimerIdx Timer index.
1049 * This parameter can be one of the following values:
1050 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1051 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1052 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1053 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1054 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1055 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1056 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1057 * @retval HAL status
1058 */
HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1059 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
1060 uint32_t TimerIdx)
1061 {
1062 /* Check the parameters */
1063 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1064
1065 /* Process Locked */
1066 __HAL_LOCK(hhrtim);
1067
1068 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1069
1070 /* Enable the repetition interrupt */
1071 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1072 {
1073 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
1074 }
1075 else
1076 {
1077 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1078 }
1079
1080 /* Enable the timer counter */
1081 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1082
1083 hhrtim->State = HAL_HRTIM_STATE_READY;
1084
1085 /* Process Unlocked */
1086 __HAL_UNLOCK(hhrtim);
1087
1088 return HAL_OK;
1089 }
1090
1091 /**
1092 * @brief Stop the counter of a timer operating in simple time base mode
1093 * (Timer repetition interrupt is disabled).
1094 * @param hhrtim pointer to HAL HRTIM handle
1095 * @param TimerIdx Timer index.
1096 * This parameter can be one of the following values:
1097 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1098 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1099 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1100 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1101 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1102 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1103 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1104 * @retval HAL status
1105 */
HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1106 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
1107 uint32_t TimerIdx)
1108 {
1109 /* Check the parameters */
1110 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1111
1112 /* Process Locked */
1113 __HAL_LOCK(hhrtim);
1114
1115 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1116
1117 /* Disable the repetition interrupt */
1118 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1119 {
1120 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
1121 }
1122 else
1123 {
1124 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1125 }
1126
1127 /* Disable the timer counter */
1128 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1129
1130 hhrtim->State = HAL_HRTIM_STATE_READY;
1131
1132 /* Process Unlocked */
1133 __HAL_UNLOCK(hhrtim);
1134
1135 return HAL_OK;
1136 }
1137
1138 /**
1139 * @brief Start the counter of a timer operating in simple time base mode
1140 * (Timer repetition DMA request is enabled).
1141 * @param hhrtim pointer to HAL HRTIM handle
1142 * @param TimerIdx Timer index.
1143 * This parameter can be one of the following values:
1144 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1145 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1146 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1147 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1148 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1149 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1150 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1151 * @param SrcAddr DMA transfer source address
1152 * @param DestAddr DMA transfer destination address
1153 * @param Length The length of data items (data size) to be transferred
1154 * from source to destination
1155 */
HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)1156 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1157 uint32_t TimerIdx,
1158 uint32_t SrcAddr,
1159 uint32_t DestAddr,
1160 uint32_t Length)
1161 {
1162 DMA_HandleTypeDef * hdma;
1163
1164 /* Check the parameters */
1165 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1166
1167 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1168 {
1169 return HAL_BUSY;
1170 }
1171 if(hhrtim->State == HAL_HRTIM_STATE_READY)
1172 {
1173 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1174 {
1175 return HAL_ERROR;
1176 }
1177 else
1178 {
1179 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1180 }
1181 }
1182
1183 /* Process Locked */
1184 __HAL_LOCK(hhrtim);
1185
1186 /* Get the timer DMA handler */
1187 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1188
1189 if (hdma == NULL)
1190 {
1191 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1192
1193 /* Process Unlocked */
1194 __HAL_UNLOCK(hhrtim);
1195
1196 return HAL_ERROR;
1197 }
1198
1199 /* Set the DMA transfer completed callback */
1200 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1201 {
1202 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1203 }
1204 else
1205 {
1206 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1207 }
1208
1209 /* Set the DMA error callback */
1210 hdma->XferErrorCallback = HRTIM_DMAError ;
1211
1212 /* Enable the DMA channel */
1213 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1214 {
1215 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1216
1217 /* Process Unlocked */
1218 __HAL_UNLOCK(hhrtim);
1219
1220 return HAL_ERROR;
1221 }
1222
1223 /* Enable the timer repetition DMA request */
1224 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1225 {
1226 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1227 }
1228 else
1229 {
1230 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1231 }
1232
1233 /* Enable the timer counter */
1234 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1235
1236 hhrtim->State = HAL_HRTIM_STATE_READY;
1237
1238 /* Process Unlocked */
1239 __HAL_UNLOCK(hhrtim);
1240
1241 return HAL_OK;
1242 }
1243
1244 /**
1245 * @brief Stop the counter of a timer operating in simple time base mode
1246 * (Timer repetition DMA request is disabled).
1247 * @param hhrtim pointer to HAL HRTIM handle
1248 * @param TimerIdx Timer index.
1249 * This parameter can be one of the following values:
1250 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1251 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1252 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1253 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1254 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1255 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1256 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1257 * @retval HAL status
1258 */
HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)1259 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1260 uint32_t TimerIdx)
1261 {
1262 DMA_HandleTypeDef * hdma;
1263
1264 /* Check the parameters */
1265 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1266
1267 /* Process Locked */
1268 __HAL_LOCK(hhrtim);
1269
1270 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1271 {
1272 hhrtim->State = HAL_HRTIM_STATE_READY;
1273
1274 /* Disable the DMA */
1275 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
1276 {
1277 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1278 }
1279 /* Disable the timer repetition DMA request */
1280 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1281 }
1282 else
1283 {
1284 /* Get the timer DMA handler */
1285 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1286
1287 if (hdma == NULL)
1288 {
1289 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1290 }
1291 else
1292 {
1293 hhrtim->State = HAL_HRTIM_STATE_READY;
1294
1295 /* Disable the DMA */
1296 if (HAL_DMA_Abort(hdma) != HAL_OK)
1297 {
1298 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1299 }
1300
1301 /* Disable the timer repetition DMA request */
1302 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1303 }
1304 }
1305
1306 /* Disable the timer counter */
1307 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1308
1309 /* Process Unlocked */
1310 __HAL_UNLOCK(hhrtim);
1311
1312 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1313 {
1314 return HAL_ERROR;
1315 }
1316 else
1317 {
1318 return HAL_OK;
1319 }
1320 }
1321
1322 /**
1323 * @}
1324 */
1325
1326 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
1327 * @brief Simple output compare functions
1328 @verbatim
1329 ===============================================================================
1330 ##### Simple output compare functions #####
1331 ===============================================================================
1332 [..] This section provides functions allowing to:
1333 (+) Configure simple output channel
1334 (+) Start simple output compare
1335 (+) Stop simple output compare
1336 (+) Start simple output compare and enable interrupt
1337 (+) Stop simple output compare and disable interrupt
1338 (+) Start simple output compare and enable DMA transfer
1339 (+) Stop simple output compare and disable DMA transfer
1340 -@- When a HRTIM timer operates in simple output compare mode
1341 the output level is set to a programmable value when a match
1342 is found between the compare register and the counter.
1343 Compare unit 1 is automatically associated to output 1
1344 Compare unit 2 is automatically associated to output 2
1345 @endverbatim
1346 * @{
1347 */
1348
1349 /**
1350 * @brief Configure an output in simple output compare mode
1351 * @param hhrtim pointer to HAL HRTIM handle
1352 * @param TimerIdx Timer index
1353 * This parameter can be one of the following values:
1354 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1355 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1356 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1357 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1358 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1359 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1360 * @param OCChannel Timer output
1361 * This parameter can be one of the following values:
1362 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1363 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1364 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1365 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1366 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1367 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1368 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1369 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1370 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1371 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1372 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1373 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1374 * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
1375 * @note When the timer operates in simple output compare mode:
1376 * Output 1 is implicitly controlled by the compare unit 1
1377 * Output 2 is implicitly controlled by the compare unit 2
1378 * Output Set/Reset crossbar is set according to the selected output compare mode:
1379 * Toggle: SETxyR = RSTxyR = CMPy
1380 * Active: SETxyR = CMPy, RSTxyR = 0
1381 * Inactive: SETxy =0, RSTxy = CMPy
1382 * @retval HAL status
1383 */
HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,HRTIM_SimpleOCChannelCfgTypeDef * pSimpleOCChannelCfg)1384 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1385 uint32_t TimerIdx,
1386 uint32_t OCChannel,
1387 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
1388 {
1389 uint32_t CompareUnit = (uint32_t)RESET;
1390 HRTIM_OutputCfgTypeDef OutputCfg;
1391
1392 /* Check parameters */
1393 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1394 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1395 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
1396 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1397 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1398
1399 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1400 {
1401 return HAL_BUSY;
1402 }
1403
1404 /* Process Locked */
1405 __HAL_LOCK(hhrtim);
1406
1407 /* Set HRTIM state */
1408 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1409
1410 /* Configure timer compare unit */
1411 switch (OCChannel)
1412 {
1413 case HRTIM_OUTPUT_TA1:
1414 case HRTIM_OUTPUT_TB1:
1415 case HRTIM_OUTPUT_TC1:
1416 case HRTIM_OUTPUT_TD1:
1417 case HRTIM_OUTPUT_TE1:
1418 case HRTIM_OUTPUT_TF1:
1419 {
1420 CompareUnit = HRTIM_COMPAREUNIT_1;
1421 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
1422 break;
1423 }
1424 case HRTIM_OUTPUT_TA2:
1425 case HRTIM_OUTPUT_TB2:
1426 case HRTIM_OUTPUT_TC2:
1427 case HRTIM_OUTPUT_TD2:
1428 case HRTIM_OUTPUT_TE2:
1429 case HRTIM_OUTPUT_TF2:
1430 {
1431 CompareUnit = HRTIM_COMPAREUNIT_2;
1432 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
1433 break;
1434 }
1435 default:
1436 {
1437 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1438
1439 /* Process Unlocked */
1440 __HAL_UNLOCK(hhrtim);
1441
1442 break;
1443 }
1444 }
1445
1446 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1447 {
1448 return HAL_ERROR;
1449 }
1450
1451 /* Configure timer output */
1452 OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
1453 OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
1454 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1455 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1456 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1457 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1458
1459 switch (pSimpleOCChannelCfg->Mode)
1460 {
1461 case HRTIM_BASICOCMODE_TOGGLE:
1462 {
1463 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1464 {
1465 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1466 }
1467 else
1468 {
1469 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1470 }
1471 OutputCfg.ResetSource = OutputCfg.SetSource;
1472 break;
1473 }
1474
1475 case HRTIM_BASICOCMODE_ACTIVE:
1476 {
1477 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1478 {
1479 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1480 }
1481 else
1482 {
1483 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1484 }
1485 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1486 break;
1487 }
1488
1489 case HRTIM_BASICOCMODE_INACTIVE:
1490 {
1491 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1492 {
1493 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1494 }
1495 else
1496 {
1497 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1498 }
1499 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1500 break;
1501 }
1502
1503 default:
1504 {
1505 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1506 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1507
1508 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1509
1510 /* Process Unlocked */
1511 __HAL_UNLOCK(hhrtim);
1512
1513 break;
1514 }
1515 }
1516
1517 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1518 {
1519 return HAL_ERROR;
1520 }
1521
1522 HRTIM_OutputConfig(hhrtim,
1523 TimerIdx,
1524 OCChannel,
1525 &OutputCfg);
1526
1527 /* Set HRTIM state */
1528 hhrtim->State = HAL_HRTIM_STATE_READY;
1529
1530 /* Process Unlocked */
1531 __HAL_UNLOCK(hhrtim);
1532
1533 return HAL_OK;
1534 }
1535
1536 /**
1537 * @brief Start the output compare signal generation on the designed timer output
1538 * @param hhrtim pointer to HAL HRTIM handle
1539 * @param TimerIdx Timer index
1540 * This parameter can be one of the following values:
1541 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1542 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1543 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1544 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1545 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1546 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1547 * @param OCChannel Timer output
1548 * This parameter can be one of the following values:
1549 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1550 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1551 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1552 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1553 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1554 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1555 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1556 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1557 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1558 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1559 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1560 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1561 * @retval HAL status
1562 */
HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1563 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
1564 uint32_t TimerIdx,
1565 uint32_t OCChannel)
1566 {
1567 /* Check the parameters */
1568 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1569
1570 /* Process Locked */
1571 __HAL_LOCK(hhrtim);
1572
1573 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1574
1575 /* Enable the timer output */
1576 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1577
1578 /* Enable the timer counter */
1579 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1580
1581 hhrtim->State = HAL_HRTIM_STATE_READY;
1582
1583 /* Process Unlocked */
1584 __HAL_UNLOCK(hhrtim);
1585
1586 return HAL_OK;
1587 }
1588
1589 /**
1590 * @brief Stop the output compare signal generation on the designed timer output
1591 * @param hhrtim pointer to HAL HRTIM handle
1592 * @param TimerIdx Timer index
1593 * This parameter can be one of the following values:
1594 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1595 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1596 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1597 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1598 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1599 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1600 * @param OCChannel Timer output
1601 * This parameter can be one of the following values:
1602 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1603 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1604 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1605 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1606 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1607 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1608 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1609 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1610 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1611 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1612 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1613 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1614 * @retval HAL status
1615 */
HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1616 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
1617 uint32_t TimerIdx,
1618 uint32_t OCChannel)
1619 {
1620 /* Check the parameters */
1621 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1622
1623 /* Process Locked */
1624 __HAL_LOCK(hhrtim);
1625
1626 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1627
1628 /* Disable the timer output */
1629 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1630
1631 /* Disable the timer counter */
1632 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1633
1634 hhrtim->State = HAL_HRTIM_STATE_READY;
1635
1636 /* Process Unlocked */
1637 __HAL_UNLOCK(hhrtim);
1638
1639 return HAL_OK;
1640 }
1641
1642 /**
1643 * @brief Start the output compare signal generation on the designed timer output
1644 * (Interrupt is enabled (see note note below)).
1645 * @param hhrtim pointer to HAL HRTIM handle
1646 * @param TimerIdx Timer index
1647 * This parameter can be one of the following values:
1648 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1649 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1650 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1651 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1652 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1653 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1654 * @param OCChannel Timer output
1655 * This parameter can be one of the following values:
1656 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1657 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1658 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1659 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1660 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1661 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1662 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1663 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1664 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1665 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1666 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1667 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1668 * @note Interrupt enabling depends on the chosen output compare mode
1669 * Output toggle: compare match interrupt is enabled
1670 * Output set active: output set interrupt is enabled
1671 * Output set inactive: output reset interrupt is enabled
1672 * @retval HAL status
1673 */
HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1674 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
1675 uint32_t TimerIdx,
1676 uint32_t OCChannel)
1677 {
1678 uint32_t interrupt;
1679
1680 /* Check the parameters */
1681 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1682
1683 /* Process Locked */
1684 __HAL_LOCK(hhrtim);
1685
1686 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1687
1688 /* Get the interrupt to enable (depends on the output compare mode) */
1689 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1690
1691 /* Enable the timer output */
1692 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1693
1694 /* Enable the timer interrupt (depends on the output compare mode) */
1695 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1696
1697 /* Enable the timer counter */
1698 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1699
1700 hhrtim->State = HAL_HRTIM_STATE_READY;
1701
1702 /* Process Unlocked */
1703 __HAL_UNLOCK(hhrtim);
1704
1705 return HAL_OK;
1706 }
1707
1708 /**
1709 * @brief Stop the output compare signal generation on the designed timer output
1710 * (Interrupt is disabled).
1711 * @param hhrtim pointer to HAL HRTIM handle
1712 * @param TimerIdx Timer index
1713 * This parameter can be one of the following values:
1714 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1715 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1716 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1717 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1718 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1719 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1720 * @param OCChannel Timer output
1721 * This parameter can be one of the following values:
1722 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1723 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1724 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1725 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1726 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1727 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1728 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1729 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1730 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1731 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1732 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1733 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1734 * @retval HAL status
1735 */
HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1736 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
1737 uint32_t TimerIdx,
1738 uint32_t OCChannel)
1739 {
1740 uint32_t interrupt;
1741
1742 /* Check the parameters */
1743 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1744
1745 /* Process Locked */
1746 __HAL_LOCK(hhrtim);
1747
1748 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1749
1750 /* Disable the timer output */
1751 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1752
1753 /* Get the interrupt to disable (depends on the output compare mode) */
1754 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1755
1756 /* Disable the timer interrupt */
1757 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1758
1759 /* Disable the timer counter */
1760 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1761
1762 hhrtim->State = HAL_HRTIM_STATE_READY;
1763
1764 /* Process Unlocked */
1765 __HAL_UNLOCK(hhrtim);
1766
1767 return HAL_OK;
1768 }
1769
1770 /**
1771 * @brief Start the output compare signal generation on the designed timer output
1772 * (DMA request is enabled (see note below)).
1773 * @param hhrtim pointer to HAL HRTIM handle
1774 * @param TimerIdx Timer index
1775 * This parameter can be one of the following values:
1776 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1777 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1778 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1779 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1780 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1781 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1782 * @param OCChannel Timer output
1783 * This parameter can be one of the following values:
1784 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1785 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1786 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1787 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1788 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1789 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1790 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1791 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1792 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1793 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1794 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1795 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1796 * @param SrcAddr DMA transfer source address
1797 * @param DestAddr DMA transfer destination address
1798 * @param Length The length of data items (data size) to be transferred
1799 * from source to destination
1800 * @note DMA request enabling depends on the chosen output compare mode
1801 * Output toggle: compare match DMA request is enabled
1802 * Output set active: output set DMA request is enabled
1803 * Output set inactive: output reset DMA request is enabled
1804 * @retval HAL status
1805 */
HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)1806 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1807 uint32_t TimerIdx,
1808 uint32_t OCChannel,
1809 uint32_t SrcAddr,
1810 uint32_t DestAddr,
1811 uint32_t Length)
1812 {
1813 DMA_HandleTypeDef * hdma;
1814 uint32_t dma_request;
1815
1816 /* Check the parameters */
1817 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1818
1819 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1820 {
1821 return HAL_BUSY;
1822 }
1823 if(hhrtim->State == HAL_HRTIM_STATE_READY)
1824 {
1825 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1826 {
1827 return HAL_ERROR;
1828 }
1829 else
1830 {
1831 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1832 }
1833 }
1834
1835 /* Process Locked */
1836 __HAL_LOCK(hhrtim);
1837
1838 /* Enable the timer output */
1839 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1840
1841 /* Get the DMA request to enable */
1842 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1843
1844 /* Get the timer DMA handler */
1845 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1846
1847 if (hdma == NULL)
1848 {
1849 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1850
1851 /* Process Unlocked */
1852 __HAL_UNLOCK(hhrtim);
1853
1854 return HAL_ERROR;
1855 }
1856
1857 /* Set the DMA error callback */
1858 hdma->XferErrorCallback = HRTIM_DMAError ;
1859
1860 /* Set the DMA transfer completed callback */
1861 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1862
1863 /* Enable the DMA channel */
1864 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1865 {
1866 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1867
1868 /* Process Unlocked */
1869 __HAL_UNLOCK(hhrtim);
1870
1871 return HAL_ERROR;
1872 }
1873
1874 /* Enable the timer DMA request */
1875 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1876
1877 /* Enable the timer counter */
1878 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1879
1880 hhrtim->State = HAL_HRTIM_STATE_READY;
1881
1882 /* Process Unlocked */
1883 __HAL_UNLOCK(hhrtim);
1884
1885 return HAL_OK;
1886 }
1887
1888 /**
1889 * @brief Stop the output compare signal generation on the designed timer output
1890 * (DMA request is disabled).
1891 * @param hhrtim pointer to HAL HRTIM handle
1892 * @param TimerIdx Timer index
1893 * This parameter can be one of the following values:
1894 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1895 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1896 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1897 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1898 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1899 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1900 * @param OCChannel Timer output
1901 * This parameter can be one of the following values:
1902 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1903 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1904 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1905 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1906 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1907 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1908 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1909 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1910 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1911 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1912 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1913 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1914 * @retval HAL status
1915 */
HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)1916 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1917 uint32_t TimerIdx,
1918 uint32_t OCChannel)
1919 {
1920 uint32_t dma_request;
1921
1922 /* Check the parameters */
1923 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1924
1925 /* Process Locked */
1926 __HAL_LOCK(hhrtim);
1927
1928 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1929
1930 /* Disable the timer output */
1931 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1932
1933 /* Get the timer DMA handler */
1934 /* Disable the DMA */
1935 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
1936 {
1937 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1938
1939 /* Process Unlocked */
1940 __HAL_UNLOCK(hhrtim);
1941
1942 return HAL_ERROR;
1943 }
1944
1945 /* Get the DMA request to disable */
1946 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1947
1948 /* Disable the timer DMA request */
1949 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1950
1951 /* Disable the timer counter */
1952 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1953
1954 hhrtim->State = HAL_HRTIM_STATE_READY;
1955
1956 /* Process Unlocked */
1957 __HAL_UNLOCK(hhrtim);
1958
1959 return HAL_OK;
1960 }
1961
1962 /**
1963 * @}
1964 */
1965
1966 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
1967 * @brief Simple PWM output functions
1968 @verbatim
1969 ===============================================================================
1970 ##### Simple PWM output functions #####
1971 ===============================================================================
1972 [..] This section provides functions allowing to:
1973 (+) Configure simple PWM output channel
1974 (+) Start simple PWM output
1975 (+) Stop simple PWM output
1976 (+) Start simple PWM output and enable interrupt
1977 (+) Stop simple PWM output and disable interrupt
1978 (+) Start simple PWM output and enable DMA transfer
1979 (+) Stop simple PWM output and disable DMA transfer
1980 -@- When a HRTIM timer operates in simple PWM output mode
1981 the output level is set to a programmable value when a match is
1982 found between the compare register and the counter and reset when
1983 the timer period is reached. Duty cycle is determined by the
1984 comparison value.
1985 Compare unit 1 is automatically associated to output 1
1986 Compare unit 2 is automatically associated to output 2
1987 @endverbatim
1988 * @{
1989 */
1990
1991 /**
1992 * @brief Configure an output in simple PWM mode
1993 * @param hhrtim pointer to HAL HRTIM handle
1994 * @param TimerIdx Timer index
1995 * This parameter can be one of the following values:
1996 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1997 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1998 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1999 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2000 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2001 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2002 * @param PWMChannel Timer output
2003 * This parameter can be one of the following values:
2004 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2005 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2006 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2007 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2008 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2009 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2010 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2011 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2012 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2013 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2014 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2015 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2016 * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
2017 * @note When the timer operates in simple PWM output mode:
2018 * Output 1 is implicitly controlled by the compare unit 1
2019 * Output 2 is implicitly controlled by the compare unit 2
2020 * Output Set/Reset crossbar is set as follows:
2021 * Output 1: SETx1R = CMP1, RSTx1R = PER
2022 * Output 2: SETx2R = CMP2, RST2R = PER
2023 * @note When Simple PWM mode is used the registers preload mechanism is
2024 * enabled (otherwise the behavior is not guaranteed).
2025 * @retval HAL status
2026 */
HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,HRTIM_SimplePWMChannelCfgTypeDef * pSimplePWMChannelCfg)2027 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2028 uint32_t TimerIdx,
2029 uint32_t PWMChannel,
2030 HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
2031 {
2032 HRTIM_OutputCfgTypeDef OutputCfg;
2033 uint32_t hrtim_timcr;
2034
2035 /* Check parameters */
2036 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2037 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
2038 assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
2039 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
2040
2041 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2042 {
2043 return HAL_BUSY;
2044 }
2045
2046 /* Process Locked */
2047 __HAL_LOCK(hhrtim);
2048
2049 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2050
2051 /* Configure timer compare unit */
2052 switch (PWMChannel)
2053 {
2054 case HRTIM_OUTPUT_TA1:
2055 case HRTIM_OUTPUT_TB1:
2056 case HRTIM_OUTPUT_TC1:
2057 case HRTIM_OUTPUT_TD1:
2058 case HRTIM_OUTPUT_TE1:
2059 case HRTIM_OUTPUT_TF1:
2060 {
2061 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
2062 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
2063 break;
2064 }
2065
2066 case HRTIM_OUTPUT_TA2:
2067 case HRTIM_OUTPUT_TB2:
2068 case HRTIM_OUTPUT_TC2:
2069 case HRTIM_OUTPUT_TD2:
2070 case HRTIM_OUTPUT_TE2:
2071 case HRTIM_OUTPUT_TF2:
2072 {
2073 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
2074 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
2075 break;
2076 }
2077 default:
2078 {
2079 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
2080 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
2081
2082 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2083
2084 /* Process Unlocked */
2085 __HAL_UNLOCK(hhrtim);
2086
2087 break;
2088 }
2089 }
2090
2091 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2092 {
2093 return HAL_ERROR;
2094 }
2095
2096 /* Configure timer output */
2097 OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
2098 OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1);
2099 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
2100 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
2101 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
2102 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
2103 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
2104
2105 HRTIM_OutputConfig(hhrtim,
2106 TimerIdx,
2107 PWMChannel,
2108 &OutputCfg);
2109
2110 /* Enable the registers preload mechanism */
2111 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
2112 hrtim_timcr |= HRTIM_TIMCR_PREEN;
2113 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
2114
2115 hhrtim->State = HAL_HRTIM_STATE_READY;
2116
2117 /* Process Unlocked */
2118 __HAL_UNLOCK(hhrtim);
2119
2120 return HAL_OK;
2121 }
2122
2123 /**
2124 * @brief Start the PWM output signal generation on the designed timer output
2125 * @param hhrtim pointer to HAL HRTIM handle
2126 * @param TimerIdx Timer index
2127 * This parameter can be one of the following values:
2128 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2129 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2130 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2131 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2132 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2133 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2134 * @param PWMChannel Timer output
2135 * This parameter can be one of the following values:
2136 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2137 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2138 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2139 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2140 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2141 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2142 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2143 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2144 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2145 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2146 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2147 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2148 * @retval HAL status
2149 */
HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2150 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
2151 uint32_t TimerIdx,
2152 uint32_t PWMChannel)
2153 {
2154 /* Check the parameters */
2155 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2156
2157 /* Process Locked */
2158 __HAL_LOCK(hhrtim);
2159
2160 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2161
2162 /* Enable the timer output */
2163 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2164
2165 /* Enable the timer counter */
2166 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2167
2168 hhrtim->State = HAL_HRTIM_STATE_READY;
2169
2170 /* Process Unlocked */
2171 __HAL_UNLOCK(hhrtim);
2172
2173 return HAL_OK;
2174 }
2175
2176 /**
2177 * @brief Stop the PWM output signal generation on the designed timer output
2178 * @param hhrtim pointer to HAL HRTIM handle
2179 * @param TimerIdx Timer index
2180 * This parameter can be one of the following values:
2181 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2182 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2183 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2184 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2185 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2186 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2187 * @param PWMChannel Timer output
2188 * This parameter can be one of the following values:
2189 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2190 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2191 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2192 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2193 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2194 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2195 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2196 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2197 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2198 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2199 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2200 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2201 * @retval HAL status
2202 */
HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2203 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
2204 uint32_t TimerIdx,
2205 uint32_t PWMChannel)
2206 {
2207 /* Check the parameters */
2208 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2209
2210 /* Process Locked */
2211 __HAL_LOCK(hhrtim);
2212
2213 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2214
2215 /* Disable the timer output */
2216 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2217
2218 /* Disable the timer counter */
2219 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2220
2221 hhrtim->State = HAL_HRTIM_STATE_READY;
2222
2223 /* Process Unlocked */
2224 __HAL_UNLOCK(hhrtim);
2225
2226 return HAL_OK;
2227 }
2228
2229 /**
2230 * @brief Start the PWM output signal generation on the designed timer output
2231 * (The compare interrupt is enabled).
2232 * @param hhrtim pointer to HAL HRTIM handle
2233 * @param TimerIdx Timer index
2234 * This parameter can be one of the following values:
2235 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2236 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2237 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2238 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2239 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2240 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2241 * @param PWMChannel Timer output
2242 * This parameter can be one of the following values:
2243 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2244 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2245 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2246 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2247 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2248 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2249 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2250 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2251 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2252 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2253 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2254 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2255 * @retval HAL status
2256 */
HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2257 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
2258 uint32_t TimerIdx,
2259 uint32_t PWMChannel)
2260 {
2261 /* Check the parameters */
2262 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2263
2264 /* Process Locked */
2265 __HAL_LOCK(hhrtim);
2266
2267 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2268
2269 /* Enable the timer output */
2270 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2271
2272 /* Enable the timer interrupt (depends on the PWM output) */
2273 switch (PWMChannel)
2274 {
2275 case HRTIM_OUTPUT_TA1:
2276 case HRTIM_OUTPUT_TB1:
2277 case HRTIM_OUTPUT_TC1:
2278 case HRTIM_OUTPUT_TD1:
2279 case HRTIM_OUTPUT_TE1:
2280 case HRTIM_OUTPUT_TF1:
2281 {
2282 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2283 break;
2284 }
2285
2286 case HRTIM_OUTPUT_TA2:
2287 case HRTIM_OUTPUT_TB2:
2288 case HRTIM_OUTPUT_TC2:
2289 case HRTIM_OUTPUT_TD2:
2290 case HRTIM_OUTPUT_TE2:
2291 case HRTIM_OUTPUT_TF2:
2292 {
2293 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2294 break;
2295 }
2296
2297 default:
2298 {
2299 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2300
2301 /* Process Unlocked */
2302 __HAL_UNLOCK(hhrtim);
2303
2304 break;
2305 }
2306 }
2307
2308 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2309 {
2310 return HAL_ERROR;
2311 }
2312
2313 /* Enable the timer counter */
2314 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2315
2316 hhrtim->State = HAL_HRTIM_STATE_READY;
2317
2318 /* Process Unlocked */
2319 __HAL_UNLOCK(hhrtim);
2320
2321 return HAL_OK;
2322 }
2323
2324 /**
2325 * @brief Stop the PWM output signal generation on the designed timer output
2326 * (The compare interrupt is disabled).
2327 * @param hhrtim pointer to HAL HRTIM handle
2328 * @param TimerIdx Timer index
2329 * This parameter can be one of the following values:
2330 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2331 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2332 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2333 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2334 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2335 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2336 * @param PWMChannel Timer output
2337 * This parameter can be one of the following values:
2338 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2339 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2340 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2341 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2342 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2343 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2344 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2345 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2346 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2347 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2348 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2349 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2350 * @retval HAL status
2351 */
HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2352 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
2353 uint32_t TimerIdx,
2354 uint32_t PWMChannel)
2355 {
2356 /* Check the parameters */
2357 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2358
2359 /* Process Locked */
2360 __HAL_LOCK(hhrtim);
2361
2362 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2363
2364 /* Disable the timer output */
2365 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2366
2367 /* Disable the timer interrupt (depends on the PWM output) */
2368 switch (PWMChannel)
2369 {
2370 case HRTIM_OUTPUT_TA1:
2371 case HRTIM_OUTPUT_TB1:
2372 case HRTIM_OUTPUT_TC1:
2373 case HRTIM_OUTPUT_TD1:
2374 case HRTIM_OUTPUT_TE1:
2375 case HRTIM_OUTPUT_TF1:
2376 {
2377 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2378 break;
2379 }
2380
2381 case HRTIM_OUTPUT_TA2:
2382 case HRTIM_OUTPUT_TB2:
2383 case HRTIM_OUTPUT_TC2:
2384 case HRTIM_OUTPUT_TD2:
2385 case HRTIM_OUTPUT_TE2:
2386 case HRTIM_OUTPUT_TF2:
2387 {
2388 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2389 break;
2390 }
2391
2392 default:
2393 {
2394 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2395
2396 /* Process Unlocked */
2397 __HAL_UNLOCK(hhrtim);
2398
2399 break;
2400 }
2401 }
2402
2403 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2404 {
2405 return HAL_ERROR;
2406 }
2407
2408 /* Disable the timer counter */
2409 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2410
2411 hhrtim->State = HAL_HRTIM_STATE_READY;
2412
2413 /* Process Unlocked */
2414 __HAL_UNLOCK(hhrtim);
2415
2416 return HAL_OK;
2417 }
2418
2419 /**
2420 * @brief Start the PWM output signal generation on the designed timer output
2421 * (The compare DMA request is enabled).
2422 * @param hhrtim pointer to HAL HRTIM handle
2423 * @param TimerIdx Timer index
2424 * This parameter can be one of the following values:
2425 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2426 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2427 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2428 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2429 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2430 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2431 * @param PWMChannel Timer output
2432 * This parameter can be one of the following values:
2433 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2434 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2435 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2436 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2437 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2438 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2439 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2440 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2441 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2442 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2443 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2444 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2445 * @param SrcAddr DMA transfer source address
2446 * @param DestAddr DMA transfer destination address
2447 * @param Length The length of data items (data size) to be transferred
2448 * from source to destination
2449 * @retval HAL status
2450 */
HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)2451 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2452 uint32_t TimerIdx,
2453 uint32_t PWMChannel,
2454 uint32_t SrcAddr,
2455 uint32_t DestAddr,
2456 uint32_t Length)
2457 {
2458 DMA_HandleTypeDef * hdma;
2459
2460 /* Check the parameters */
2461 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2462
2463 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2464 {
2465 return HAL_BUSY;
2466 }
2467 if(hhrtim->State == HAL_HRTIM_STATE_READY)
2468 {
2469 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
2470 {
2471 return HAL_ERROR;
2472 }
2473 else
2474 {
2475 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2476 }
2477 }
2478
2479 /* Process Locked */
2480 __HAL_LOCK(hhrtim);
2481
2482 /* Enable the timer output */
2483 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2484
2485 /* Get the timer DMA handler */
2486 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2487
2488 if (hdma == NULL)
2489 {
2490 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2491
2492 /* Process Unlocked */
2493 __HAL_UNLOCK(hhrtim);
2494
2495 return HAL_ERROR;
2496 }
2497
2498 /* Set the DMA error callback */
2499 hdma->XferErrorCallback = HRTIM_DMAError ;
2500
2501 /* Set the DMA transfer completed callback */
2502 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2503
2504 /* Enable the DMA channel */
2505 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2506 {
2507 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2508
2509 /* Process Unlocked */
2510 __HAL_UNLOCK(hhrtim);
2511
2512 return HAL_ERROR;
2513 }
2514
2515 /* Enable the timer DMA request */
2516 switch (PWMChannel)
2517 {
2518 case HRTIM_OUTPUT_TA1:
2519 case HRTIM_OUTPUT_TB1:
2520 case HRTIM_OUTPUT_TC1:
2521 case HRTIM_OUTPUT_TD1:
2522 case HRTIM_OUTPUT_TE1:
2523 case HRTIM_OUTPUT_TF1:
2524 {
2525 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2526 break;
2527 }
2528
2529 case HRTIM_OUTPUT_TA2:
2530 case HRTIM_OUTPUT_TB2:
2531 case HRTIM_OUTPUT_TC2:
2532 case HRTIM_OUTPUT_TD2:
2533 case HRTIM_OUTPUT_TE2:
2534 case HRTIM_OUTPUT_TF2:
2535 {
2536 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2537 break;
2538 }
2539
2540 default:
2541 {
2542 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2543
2544 /* Process Unlocked */
2545 __HAL_UNLOCK(hhrtim);
2546
2547 break;
2548 }
2549 }
2550
2551 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2552 {
2553 return HAL_ERROR;
2554 }
2555
2556 /* Enable the timer counter */
2557 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2558
2559 hhrtim->State = HAL_HRTIM_STATE_READY;
2560
2561 /* Process Unlocked */
2562 __HAL_UNLOCK(hhrtim);
2563
2564 return HAL_OK;
2565 }
2566
2567 /**
2568 * @brief Stop the PWM output signal generation on the designed timer output
2569 * (The compare DMA request is disabled).
2570 * @param hhrtim pointer to HAL HRTIM handle
2571 * @param TimerIdx Timer index
2572 * This parameter can be one of the following values:
2573 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2574 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2575 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2576 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2577 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2578 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2579 * @param PWMChannel Timer output
2580 * This parameter can be one of the following values:
2581 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2582 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2583 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2584 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2585 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2586 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2587 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2588 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2589 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2590 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2591 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2592 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2593 * @retval HAL status
2594 */
HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t PWMChannel)2595 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2596 uint32_t TimerIdx,
2597 uint32_t PWMChannel)
2598 {
2599 /* Check the parameters */
2600 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2601
2602 /* Process Locked */
2603 __HAL_LOCK(hhrtim);
2604
2605 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2606
2607 /* Disable the timer output */
2608 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2609
2610 /* Get the timer DMA handler */
2611 /* Disable the DMA */
2612 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
2613 {
2614 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2615
2616 /* Process Unlocked */
2617 __HAL_UNLOCK(hhrtim);
2618
2619 return HAL_ERROR;
2620 }
2621
2622 /* Disable the timer DMA request */
2623 switch (PWMChannel)
2624 {
2625 case HRTIM_OUTPUT_TA1:
2626 case HRTIM_OUTPUT_TB1:
2627 case HRTIM_OUTPUT_TC1:
2628 case HRTIM_OUTPUT_TD1:
2629 case HRTIM_OUTPUT_TE1:
2630 case HRTIM_OUTPUT_TF1:
2631 {
2632 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2633 break;
2634 }
2635
2636 case HRTIM_OUTPUT_TA2:
2637 case HRTIM_OUTPUT_TB2:
2638 case HRTIM_OUTPUT_TC2:
2639 case HRTIM_OUTPUT_TD2:
2640 case HRTIM_OUTPUT_TE2:
2641 case HRTIM_OUTPUT_TF2:
2642 {
2643 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2644 break;
2645 }
2646
2647 default:
2648 {
2649 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2650
2651 /* Process Unlocked */
2652 __HAL_UNLOCK(hhrtim);
2653
2654 break;
2655 }
2656 }
2657
2658 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2659 {
2660 return HAL_ERROR;
2661 }
2662
2663 /* Disable the timer counter */
2664 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2665
2666 hhrtim->State = HAL_HRTIM_STATE_READY;
2667
2668 /* Process Unlocked */
2669 __HAL_UNLOCK(hhrtim);
2670
2671 return HAL_OK;
2672 }
2673
2674 /**
2675 * @}
2676 */
2677
2678 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
2679 * @brief Simple input capture functions
2680 @verbatim
2681 ===============================================================================
2682 ##### Simple input capture functions #####
2683 ===============================================================================
2684 [..] This section provides functions allowing to:
2685 (+) Configure simple input capture channel
2686 (+) Start simple input capture
2687 (+) Stop simple input capture
2688 (+) Start simple input capture and enable interrupt
2689 (+) Stop simple input capture and disable interrupt
2690 (+) Start simple input capture and enable DMA transfer
2691 (+) Stop simple input capture and disable DMA transfer
2692 -@- When a HRTIM timer operates in simple input capture mode
2693 the Capture Register (HRTIM_CPT1/2xR) is used to latch the
2694 value of the timer counter counter after a transition detected
2695 on a given external event input.
2696 @endverbatim
2697 * @{
2698 */
2699
2700 /**
2701 * @brief Configure a simple capture
2702 * @param hhrtim pointer to HAL HRTIM handle
2703 * @param TimerIdx Timer index
2704 * This parameter can be one of the following values:
2705 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2706 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2707 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2708 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2709 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2710 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2711 * @param CaptureChannel Capture unit
2712 * This parameter can be one of the following values:
2713 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2714 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2715 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
2716 * @note When the timer operates in simple capture mode the capture is triggered
2717 * by the designated external event and GPIO input is implicitly used as event source.
2718 * The cature can be triggered by a rising edge, a falling edge or both
2719 * edges on event channel.
2720 * @retval HAL status
2721 */
HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,HRTIM_SimpleCaptureChannelCfgTypeDef * pSimpleCaptureChannelCfg)2722 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2723 uint32_t TimerIdx,
2724 uint32_t CaptureChannel,
2725 HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
2726 {
2727 HRTIM_EventCfgTypeDef EventCfg;
2728
2729 /* Check parameters */
2730 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2731 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2732 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2733 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2734 pSimpleCaptureChannelCfg->EventPolarity));
2735 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2736 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2737 pSimpleCaptureChannelCfg->EventFilter));
2738
2739 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2740 {
2741 return HAL_BUSY;
2742 }
2743
2744 /* Process Locked */
2745 __HAL_LOCK(hhrtim);
2746
2747 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2748
2749 /* Configure external event channel */
2750 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2751 EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
2752 EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
2753 EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
2754 EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */
2755
2756 HRTIM_EventConfig(hhrtim,
2757 pSimpleCaptureChannelCfg->Event,
2758 &EventCfg);
2759
2760 /* Memorize capture trigger (will be configured when the capture is started */
2761 HRTIM_CaptureUnitConfig(hhrtim,
2762 TimerIdx,
2763 CaptureChannel,
2764 pSimpleCaptureChannelCfg->Event);
2765
2766 hhrtim->State = HAL_HRTIM_STATE_READY;
2767
2768 /* Process Unlocked */
2769 __HAL_UNLOCK(hhrtim);
2770
2771 return HAL_OK;
2772 }
2773
2774 /**
2775 * @brief Enable a simple capture on the designed capture unit
2776 * @param hhrtim pointer to HAL HRTIM handle
2777 * @param TimerIdx Timer index
2778 * This parameter can be one of the following values:
2779 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2780 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2781 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2782 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2783 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2784 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2785 * @param CaptureChannel Timer output
2786 * This parameter can be one of the following values:
2787 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2788 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2789 * @retval HAL status
2790 * @note The external event triggering the capture is available for all timing
2791 * units. It can be used directly and is active as soon as the timing
2792 * unit counter is enabled.
2793 */
HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2794 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
2795 uint32_t TimerIdx,
2796 uint32_t CaptureChannel)
2797 {
2798 /* Check the parameters */
2799 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2800 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2801
2802 /* Process Locked */
2803 __HAL_LOCK(hhrtim);
2804
2805 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2806
2807 /* Set the capture unit trigger */
2808 switch (CaptureChannel)
2809 {
2810 case HRTIM_CAPTUREUNIT_1:
2811 {
2812 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2813 break;
2814 }
2815
2816 case HRTIM_CAPTUREUNIT_2:
2817 {
2818 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2819 break;
2820 }
2821
2822 default:
2823 {
2824 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2825
2826 /* Process Unlocked */
2827 __HAL_UNLOCK(hhrtim);
2828
2829 break;
2830 }
2831 }
2832
2833 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2834 {
2835 return HAL_ERROR;
2836 }
2837
2838 /* Enable the timer counter */
2839 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2840
2841 hhrtim->State = HAL_HRTIM_STATE_READY;
2842
2843 /* Process Unlocked */
2844 __HAL_UNLOCK(hhrtim);
2845
2846 return HAL_OK;
2847 }
2848
2849 /**
2850 * @brief Disable a simple capture on the designed capture unit
2851 * @param hhrtim pointer to HAL HRTIM handle
2852 * @param TimerIdx Timer index
2853 * This parameter can be one of the following values:
2854 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2855 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2856 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2857 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2858 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2859 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2860 * @param CaptureChannel Timer output
2861 * This parameter can be one of the following values:
2862 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2863 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2864 * @retval HAL status
2865 */
HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2866 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
2867 uint32_t TimerIdx,
2868 uint32_t CaptureChannel)
2869 {
2870 uint32_t hrtim_cpt1cr;
2871 uint32_t hrtim_cpt2cr;
2872
2873 /* Check the parameters */
2874 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2875 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2876
2877 /* Process Locked */
2878 __HAL_LOCK(hhrtim);
2879
2880 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2881
2882 /* Set the capture unit trigger */
2883 switch (CaptureChannel)
2884 {
2885 case HRTIM_CAPTUREUNIT_1:
2886 {
2887 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2888 break;
2889 }
2890
2891 case HRTIM_CAPTUREUNIT_2:
2892 {
2893 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2894 break;
2895 }
2896
2897 default:
2898 {
2899 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2900
2901 /* Process Unlocked */
2902 __HAL_UNLOCK(hhrtim);
2903
2904 break;
2905 }
2906 }
2907
2908 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2909 {
2910 return HAL_ERROR;
2911 }
2912
2913 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2914 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2915
2916 /* Disable the timer counter */
2917 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2918 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2919 {
2920 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2921 }
2922
2923 hhrtim->State = HAL_HRTIM_STATE_READY;
2924
2925 /* Process Unlocked */
2926 __HAL_UNLOCK(hhrtim);
2927
2928 return HAL_OK;
2929 }
2930
2931 /**
2932 * @brief Enable a simple capture on the designed capture unit
2933 * (Capture interrupt is enabled).
2934 * @param hhrtim pointer to HAL HRTIM handle
2935 * @param TimerIdx Timer index
2936 * This parameter can be one of the following values:
2937 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2938 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2939 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2940 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2941 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2942 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2943 * @param CaptureChannel Timer output
2944 * This parameter can be one of the following values:
2945 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2946 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2947 * @retval HAL status
2948 */
HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)2949 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
2950 uint32_t TimerIdx,
2951 uint32_t CaptureChannel)
2952 {
2953 /* Check the parameters */
2954 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2955 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2956
2957 /* Process Locked */
2958 __HAL_LOCK(hhrtim);
2959
2960 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2961
2962 /* Set the capture unit trigger */
2963 switch (CaptureChannel)
2964 {
2965 case HRTIM_CAPTUREUNIT_1:
2966 {
2967 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2968
2969 /* Enable the capture unit 1 interrupt */
2970 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2971 break;
2972 }
2973
2974 case HRTIM_CAPTUREUNIT_2:
2975 {
2976 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2977
2978 /* Enable the capture unit 2 interrupt */
2979 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2980 break;
2981 }
2982
2983 default:
2984 {
2985 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2986
2987 /* Process Unlocked */
2988 __HAL_UNLOCK(hhrtim);
2989
2990 break;
2991 }
2992 }
2993
2994 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2995 {
2996 return HAL_ERROR;
2997 }
2998
2999 /* Enable the timer counter */
3000 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3001
3002 hhrtim->State = HAL_HRTIM_STATE_READY;
3003
3004 /* Process Unlocked */
3005 __HAL_UNLOCK(hhrtim);
3006
3007 return HAL_OK;
3008 }
3009
3010 /**
3011 * @brief Disable a simple capture on the designed capture unit
3012 * (Capture interrupt is disabled).
3013 * @param hhrtim pointer to HAL HRTIM handle
3014 * @param TimerIdx Timer index
3015 * This parameter can be one of the following values:
3016 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3017 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3018 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3019 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3020 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3021 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3022 * @param CaptureChannel Timer output
3023 * This parameter can be one of the following values:
3024 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3025 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3026 * @retval HAL status
3027 */
HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)3028 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
3029 uint32_t TimerIdx,
3030 uint32_t CaptureChannel)
3031 {
3032
3033 uint32_t hrtim_cpt1cr;
3034 uint32_t hrtim_cpt2cr;
3035
3036 /* Check the parameters */
3037 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3038 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3039
3040 /* Process Locked */
3041 __HAL_LOCK(hhrtim);
3042
3043 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3044
3045 /* Set the capture unit trigger */
3046 switch (CaptureChannel)
3047 {
3048 case HRTIM_CAPTUREUNIT_1:
3049 {
3050 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3051
3052 /* Disable the capture unit 1 interrupt */
3053 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
3054 break;
3055 }
3056
3057 case HRTIM_CAPTUREUNIT_2:
3058 {
3059 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3060
3061 /* Disable the capture unit 2 interrupt */
3062 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
3063 break;
3064 }
3065
3066 default:
3067 {
3068 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3069
3070 /* Process Unlocked */
3071 __HAL_UNLOCK(hhrtim);
3072
3073 break;
3074 }
3075 }
3076
3077 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3078 {
3079 return HAL_ERROR;
3080 }
3081
3082 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3083 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3084
3085 /* Disable the timer counter */
3086 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3087 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3088 {
3089 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3090 }
3091
3092 hhrtim->State = HAL_HRTIM_STATE_READY;
3093
3094 /* Process Unlocked */
3095 __HAL_UNLOCK(hhrtim);
3096
3097 return HAL_OK;
3098 }
3099
3100 /**
3101 * @brief Enable a simple capture on the designed capture unit
3102 * (Capture DMA request is enabled).
3103 * @param hhrtim pointer to HAL HRTIM handle
3104 * @param TimerIdx Timer index
3105 * This parameter can be one of the following values:
3106 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3107 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3108 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3109 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3110 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3111 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3112 * @param CaptureChannel Timer output
3113 * This parameter can be one of the following values:
3114 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3115 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3116 * @param SrcAddr DMA transfer source address
3117 * @param DestAddr DMA transfer destination address
3118 * @param Length The length of data items (data size) to be transferred
3119 * from source to destination
3120 * @retval HAL status
3121 */
HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel,uint32_t SrcAddr,uint32_t DestAddr,uint32_t Length)3122 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
3123 uint32_t TimerIdx,
3124 uint32_t CaptureChannel,
3125 uint32_t SrcAddr,
3126 uint32_t DestAddr,
3127 uint32_t Length)
3128 {
3129 DMA_HandleTypeDef * hdma;
3130
3131 /* Check the parameters */
3132 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3133 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3134
3135 /* Process Locked */
3136 __HAL_LOCK(hhrtim);
3137
3138 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3139
3140 /* Get the timer DMA handler */
3141 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
3142
3143 if (hdma == NULL)
3144 {
3145 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3146
3147 /* Process Unlocked */
3148 __HAL_UNLOCK(hhrtim);
3149
3150 return HAL_ERROR;
3151 }
3152
3153 /* Set the DMA error callback */
3154 hdma->XferErrorCallback = HRTIM_DMAError ;
3155
3156 /* Set the DMA transfer completed callback */
3157 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
3158
3159 /* Enable the DMA channel */
3160 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
3161 {
3162 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3163
3164 /* Process Unlocked */
3165 __HAL_UNLOCK(hhrtim);
3166
3167 return HAL_ERROR;
3168 }
3169
3170 switch (CaptureChannel)
3171 {
3172 case HRTIM_CAPTUREUNIT_1:
3173 {
3174 /* Set the capture unit trigger */
3175 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
3176
3177 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3178 break;
3179 }
3180
3181 case HRTIM_CAPTUREUNIT_2:
3182 {
3183 /* Set the capture unit trigger */
3184 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
3185
3186 /* Enable the timer DMA request */
3187 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3188 break;
3189 }
3190
3191 default:
3192 {
3193 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3194
3195 /* Process Unlocked */
3196 __HAL_UNLOCK(hhrtim);
3197
3198 break;
3199 }
3200 }
3201
3202 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3203 {
3204 return HAL_ERROR;
3205 }
3206
3207 /* Enable the timer counter */
3208 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3209
3210 hhrtim->State = HAL_HRTIM_STATE_READY;
3211
3212 /* Process Unlocked */
3213 __HAL_UNLOCK(hhrtim);
3214
3215 return HAL_OK;
3216 }
3217
3218 /**
3219 * @brief Disable a simple capture on the designed capture unit
3220 * (Capture DMA request is disabled).
3221 * @param hhrtim pointer to HAL HRTIM handle
3222 * @param TimerIdx Timer index
3223 * This parameter can be one of the following values:
3224 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3225 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3226 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3227 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3228 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3229 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3230 * @param CaptureChannel Timer output
3231 * This parameter can be one of the following values:
3232 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3233 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3234 * @retval HAL status
3235 */
HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureChannel)3236 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
3237 uint32_t TimerIdx,
3238 uint32_t CaptureChannel)
3239 {
3240
3241 uint32_t hrtim_cpt1cr;
3242 uint32_t hrtim_cpt2cr;
3243
3244 /* Check the parameters */
3245 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3246 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3247
3248 /* Process Locked */
3249 __HAL_LOCK(hhrtim);
3250
3251 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3252
3253 /* Get the timer DMA handler */
3254 /* Disable the DMA */
3255 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
3256 {
3257 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3258
3259 /* Process Unlocked */
3260 __HAL_UNLOCK(hhrtim);
3261
3262 return HAL_ERROR;
3263 }
3264
3265 switch (CaptureChannel)
3266 {
3267 case HRTIM_CAPTUREUNIT_1:
3268 {
3269 /* Reset the capture unit trigger */
3270 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3271
3272 /* Disable the capture unit 1 DMA request */
3273 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3274 break;
3275 }
3276
3277 case HRTIM_CAPTUREUNIT_2:
3278 {
3279 /* Reset the capture unit trigger */
3280 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3281
3282 /* Disable the capture unit 2 DMA request */
3283 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3284 break;
3285 }
3286
3287 default:
3288 {
3289 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3290
3291 /* Process Unlocked */
3292 __HAL_UNLOCK(hhrtim);
3293
3294 break;
3295 }
3296 }
3297
3298 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3299 {
3300 return HAL_ERROR;
3301 }
3302
3303 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3304 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3305
3306 /* Disable the timer counter */
3307 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3308 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3309 {
3310 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3311 }
3312
3313 hhrtim->State = HAL_HRTIM_STATE_READY;
3314
3315 /* Process Unlocked */
3316 __HAL_UNLOCK(hhrtim);
3317
3318 return HAL_OK;
3319 }
3320
3321 /**
3322 * @}
3323 */
3324
3325 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
3326 * @brief Simple one pulse functions
3327 @verbatim
3328 ===============================================================================
3329 ##### Simple one pulse functions #####
3330 ===============================================================================
3331 [..] This section provides functions allowing to:
3332 (+) Configure one pulse channel
3333 (+) Start one pulse generation
3334 (+) Stop one pulse generation
3335 (+) Start one pulse generation and enable interrupt
3336 (+) Stop one pulse generation and disable interrupt
3337 -@- When a HRTIM timer operates in simple one pulse mode
3338 the timer counter is started in response to transition detected
3339 on a given external event input to generate a pulse with a
3340 programmable length after a programmable delay.
3341 @endverbatim
3342 * @{
3343 */
3344
3345 /**
3346 * @brief Configure an output simple one pulse mode
3347 * @param hhrtim pointer to HAL HRTIM handle
3348 * @param TimerIdx Timer index
3349 * This parameter can be one of the following values:
3350 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3351 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3352 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3353 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3354 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3355 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3356 * @param OnePulseChannel Timer output
3357 * This parameter can be one of the following values:
3358 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3359 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3360 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3361 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3362 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3363 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3364 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3365 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3366 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3367 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3368 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3369 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3370 * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
3371 * @note When the timer operates in simple one pulse mode:
3372 * the timer counter is implicitly started by the reset event,
3373 * the reset of the timer counter is triggered by the designated external event
3374 * GPIO input is implicitly used as event source,
3375 * Output 1 is implicitly controlled by the compare unit 1,
3376 * Output 2 is implicitly controlled by the compare unit 2.
3377 * Output Set/Reset crossbar is set as follows:
3378 * Output 1: SETx1R = CMP1, RSTx1R = PER
3379 * Output 2: SETx2R = CMP2, RST2R = PER
3380 * @retval HAL status
3381 * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
3382 * outputs, the reset event related configuration data provided in the
3383 * second call will override the reset event related configuration data
3384 * provided in the first call.
3385 */
HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel,HRTIM_SimpleOnePulseChannelCfgTypeDef * pSimpleOnePulseChannelCfg)3386 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
3387 uint32_t TimerIdx,
3388 uint32_t OnePulseChannel,
3389 HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
3390 {
3391 HRTIM_OutputCfgTypeDef OutputCfg;
3392 HRTIM_EventCfgTypeDef EventCfg;
3393
3394 /* Check parameters */
3395 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3396 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
3397 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
3398 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
3399 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
3400 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
3401 pSimpleOnePulseChannelCfg->EventPolarity));
3402 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
3403 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
3404 pSimpleOnePulseChannelCfg->EventFilter));
3405
3406 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3407 {
3408 return HAL_BUSY;
3409 }
3410
3411 /* Process Locked */
3412 __HAL_LOCK(hhrtim);
3413
3414 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3415
3416 /* Configure timer compare unit */
3417 switch (OnePulseChannel)
3418 {
3419 case HRTIM_OUTPUT_TA1:
3420 case HRTIM_OUTPUT_TB1:
3421 case HRTIM_OUTPUT_TC1:
3422 case HRTIM_OUTPUT_TD1:
3423 case HRTIM_OUTPUT_TE1:
3424 case HRTIM_OUTPUT_TF1:
3425 {
3426 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
3427 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
3428 break;
3429 }
3430
3431 case HRTIM_OUTPUT_TA2:
3432 case HRTIM_OUTPUT_TB2:
3433 case HRTIM_OUTPUT_TC2:
3434 case HRTIM_OUTPUT_TD2:
3435 case HRTIM_OUTPUT_TE2:
3436 case HRTIM_OUTPUT_TF2:
3437 {
3438 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
3439 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
3440 break;
3441 }
3442
3443 default:
3444 {
3445 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
3446 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
3447
3448 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3449
3450 /* Process Unlocked */
3451 __HAL_UNLOCK(hhrtim);
3452
3453 break;
3454 }
3455 }
3456
3457 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3458 {
3459 return HAL_ERROR;
3460 }
3461
3462 /* Configure timer output */
3463 OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
3464 OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
3465 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
3466 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
3467 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
3468 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
3469 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
3470
3471 HRTIM_OutputConfig(hhrtim,
3472 TimerIdx,
3473 OnePulseChannel,
3474 &OutputCfg);
3475
3476 /* Configure external event channel */
3477 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
3478 EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
3479 EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
3480 EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS);
3481 EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */
3482
3483 HRTIM_EventConfig(hhrtim,
3484 pSimpleOnePulseChannelCfg->Event,
3485 &EventCfg);
3486
3487 /* Configure the timer reset register */
3488 HRTIM_TIM_ResetConfig(hhrtim,
3489 TimerIdx,
3490 pSimpleOnePulseChannelCfg->Event);
3491
3492 hhrtim->State = HAL_HRTIM_STATE_READY;
3493
3494 /* Process Unlocked */
3495 __HAL_UNLOCK(hhrtim);
3496
3497 return HAL_OK;
3498 }
3499
3500 /**
3501 * @brief Enable the simple one pulse signal generation on the designed output
3502 * @param hhrtim pointer to HAL HRTIM handle
3503 * @param TimerIdx Timer index
3504 * This parameter can be one of the following values:
3505 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3506 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3507 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3508 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3509 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3510 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3511 * @param OnePulseChannel Timer output
3512 * This parameter can be one of the following values:
3513 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3514 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3515 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3516 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3517 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3518 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3519 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3520 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3521 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3522 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3523 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3524 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3525 * @retval HAL status
3526 */
HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3527 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
3528 uint32_t TimerIdx,
3529 uint32_t OnePulseChannel)
3530 {
3531 /* Check the parameters */
3532 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3533
3534 /* Process Locked */
3535 __HAL_LOCK(hhrtim);
3536
3537 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3538
3539 /* Enable the timer output */
3540 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3541
3542 /* Enable the timer counter */
3543 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3544
3545 hhrtim->State = HAL_HRTIM_STATE_READY;
3546
3547 /* Process Unlocked */
3548 __HAL_UNLOCK(hhrtim);
3549
3550 return HAL_OK;
3551 }
3552
3553 /**
3554 * @brief Disable the simple one pulse signal generation on the designed output
3555 * @param hhrtim pointer to HAL HRTIM handle
3556 * @param TimerIdx Timer index
3557 * This parameter can be one of the following values:
3558 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3559 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3560 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3561 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3562 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3563 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3564 * @param OnePulseChannel Timer output
3565 * This parameter can be one of the following values:
3566 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3567 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3568 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3569 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3570 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3571 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3572 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3573 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3574 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3575 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3576 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3577 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3578 * @retval HAL status
3579 */
HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3580 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
3581 uint32_t TimerIdx,
3582 uint32_t OnePulseChannel)
3583 {
3584 /* Check the parameters */
3585 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3586
3587 /* Process Locked */
3588 __HAL_LOCK(hhrtim);
3589
3590 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3591
3592 /* Disable the timer output */
3593 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3594
3595 /* Disable the timer counter */
3596 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3597
3598 hhrtim->State = HAL_HRTIM_STATE_READY;
3599
3600 /* Process Unlocked */
3601 __HAL_UNLOCK(hhrtim);
3602
3603 return HAL_OK;
3604 }
3605
3606 /**
3607 * @brief Enable the simple one pulse signal generation on the designed output
3608 * (The compare interrupt is enabled (pulse start)).
3609 * @param hhrtim pointer to HAL HRTIM handle
3610 * @param TimerIdx Timer index
3611 * This parameter can be one of the following values:
3612 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3613 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3614 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3615 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3616 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3617 * @arg HRTIM_TIMERINDEX_TIMER_F for timer E
3618 * @param OnePulseChannel Timer output
3619 * This parameter can be one of the following values:
3620 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3621 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3622 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3623 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3624 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3625 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3626 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3627 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3628 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3629 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3630 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3631 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3632 * @retval HAL status
3633 */
HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3634 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
3635 uint32_t TimerIdx,
3636 uint32_t OnePulseChannel)
3637 {
3638 /* Check the parameters */
3639 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3640
3641 /* Process Locked */
3642 __HAL_LOCK(hhrtim);
3643
3644 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3645
3646 /* Enable the timer output */
3647 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3648
3649 /* Enable the timer interrupt (depends on the OnePulse output) */
3650 switch (OnePulseChannel)
3651 {
3652 case HRTIM_OUTPUT_TA1:
3653 case HRTIM_OUTPUT_TB1:
3654 case HRTIM_OUTPUT_TC1:
3655 case HRTIM_OUTPUT_TD1:
3656 case HRTIM_OUTPUT_TE1:
3657 case HRTIM_OUTPUT_TF1:
3658 {
3659 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3660 break;
3661 }
3662
3663 case HRTIM_OUTPUT_TA2:
3664 case HRTIM_OUTPUT_TB2:
3665 case HRTIM_OUTPUT_TC2:
3666 case HRTIM_OUTPUT_TD2:
3667 case HRTIM_OUTPUT_TE2:
3668 case HRTIM_OUTPUT_TF2:
3669 {
3670 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3671 break;
3672 }
3673
3674 default:
3675 {
3676 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3677
3678 /* Process Unlocked */
3679 __HAL_UNLOCK(hhrtim);
3680
3681 break;
3682 }
3683 }
3684
3685 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3686 {
3687 return HAL_ERROR;
3688 }
3689
3690 /* Enable the timer counter */
3691 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3692
3693 hhrtim->State = HAL_HRTIM_STATE_READY;
3694
3695 /* Process Unlocked */
3696 __HAL_UNLOCK(hhrtim);
3697
3698 return HAL_OK;
3699 }
3700
3701 /**
3702 * @brief Disable the simple one pulse signal generation on the designed output
3703 * (The compare interrupt is disabled).
3704 * @param hhrtim pointer to HAL HRTIM handle
3705 * @param TimerIdx Timer index
3706 * This parameter can be one of the following values:
3707 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3708 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3709 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3710 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3711 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3712 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3713 * @param OnePulseChannel Timer output
3714 * This parameter can be one of the following values:
3715 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3716 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3717 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3718 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3719 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3720 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3721 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3722 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3723 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3724 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3725 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3726 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3727 * @retval HAL status
3728 */
HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OnePulseChannel)3729 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
3730 uint32_t TimerIdx,
3731 uint32_t OnePulseChannel)
3732 {
3733 /* Check the parameters */
3734 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3735
3736 /* Process Locked */
3737 __HAL_LOCK(hhrtim);
3738
3739 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3740
3741 /* Disable the timer output */
3742 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3743
3744 /* Disable the timer interrupt (depends on the OnePulse output) */
3745 switch (OnePulseChannel)
3746 {
3747 case HRTIM_OUTPUT_TA1:
3748 case HRTIM_OUTPUT_TB1:
3749 case HRTIM_OUTPUT_TC1:
3750 case HRTIM_OUTPUT_TD1:
3751 case HRTIM_OUTPUT_TE1:
3752 case HRTIM_OUTPUT_TF1:
3753 {
3754 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3755 break;
3756 }
3757
3758 case HRTIM_OUTPUT_TA2:
3759 case HRTIM_OUTPUT_TB2:
3760 case HRTIM_OUTPUT_TC2:
3761 case HRTIM_OUTPUT_TD2:
3762 case HRTIM_OUTPUT_TE2:
3763 case HRTIM_OUTPUT_TF2:
3764 {
3765 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3766 break;
3767 }
3768
3769 default:
3770 {
3771 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3772
3773 /* Process Unlocked */
3774 __HAL_UNLOCK(hhrtim);
3775
3776 break;
3777 }
3778 }
3779
3780 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3781 {
3782 return HAL_ERROR;
3783 }
3784
3785 /* Disable the timer counter */
3786 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3787
3788 hhrtim->State = HAL_HRTIM_STATE_READY;
3789
3790 /* Process Unlocked */
3791 __HAL_UNLOCK(hhrtim);
3792
3793 return HAL_OK;
3794 }
3795
3796 /**
3797 * @}
3798 */
3799
3800 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
3801 * @brief HRTIM configuration functions
3802 @verbatim
3803 ===============================================================================
3804 ##### HRTIM configuration functions #####
3805 ===============================================================================
3806 [..] This section provides functions allowing to configure the HRTIM
3807 resources shared by all the HRTIM timers operating in waveform mode:
3808 (+) Configure the burst mode controller
3809 (+) Configure an external event conditioning
3810 (+) Configure the external events sampling clock
3811 (+) Configure a fault conditioning
3812 (+) Enable or disable fault inputs
3813 (+) Configure the faults sampling clock
3814 (+) Configure an ADC trigger
3815
3816 @endverbatim
3817 * @{
3818 */
3819
3820 /**
3821 * @brief Configure the burst mode feature of the HRTIM
3822 * @param hhrtim pointer to HAL HRTIM handle
3823 * @param pBurstModeCfg pointer to the burst mode configuration structure
3824 * @retval HAL status
3825 * @note This function must be called before starting the burst mode
3826 * controller
3827 */
HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,HRTIM_BurstModeCfgTypeDef * pBurstModeCfg)3828 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
3829 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
3830 {
3831 uint32_t hrtim_bmcr;
3832
3833 /* Check parameters */
3834 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3835 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3836 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3837 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3838 assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
3839
3840 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3841 {
3842 return HAL_BUSY;
3843 }
3844
3845 /* Process Locked */
3846 __HAL_LOCK(hhrtim);
3847
3848 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3849
3850 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3851
3852 /* Set the burst mode operating mode */
3853 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3854 hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
3855
3856 /* Set the burst mode clock source */
3857 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3858 hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
3859
3860 /* Set the burst mode prescaler */
3861 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3862 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3863
3864 /* Enable/disable burst mode registers preload */
3865 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3866 hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
3867
3868 /* Set the burst mode trigger */
3869 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3870
3871 /* Set the burst mode compare value */
3872 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3873
3874 /* Set the burst mode period */
3875 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3876
3877 /* Update the HRTIM registers */
3878 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3879
3880 hhrtim->State = HAL_HRTIM_STATE_READY;
3881
3882 /* Process Unlocked */
3883 __HAL_UNLOCK(hhrtim);
3884
3885 return HAL_OK;
3886 }
3887
3888 /**
3889 * @brief Configure the conditioning of an external event
3890 * @param hhrtim pointer to HAL HRTIM handle
3891 * @param Event external event to configure
3892 * This parameter can be one of the following values:
3893 * @arg HRTIM_EVENT_NONE: no external Event
3894 * @arg HRTIM_EVENT_1: External event 1
3895 * @arg HRTIM_EVENT_2: External event 2
3896 * @arg HRTIM_EVENT_3: External event 3
3897 * @arg HRTIM_EVENT_4: External event 4
3898 * @arg HRTIM_EVENT_5: External event 5
3899 * @arg HRTIM_EVENT_6: External event 6
3900 * @arg HRTIM_EVENT_7: External event 7
3901 * @arg HRTIM_EVENT_8: External event 8
3902 * @arg HRTIM_EVENT_9: External event 9
3903 * @arg HRTIM_EVENT_10: External event 10
3904 * @param pEventCfg pointer to the event conditioning configuration structure
3905 * @note This function must be called before starting the timer
3906 * @retval HAL status
3907 */
HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,HRTIM_EventCfgTypeDef * pEventCfg)3908 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
3909 uint32_t Event,
3910 HRTIM_EventCfgTypeDef* pEventCfg)
3911 {
3912 /* Check parameters */
3913 assert_param(IS_HRTIM_EVENT(Event));
3914 assert_param(IS_HRTIM_EVENTSRC(Event, pEventCfg->Source));
3915 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3916 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3917 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3918 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3919
3920 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3921 {
3922 return HAL_BUSY;
3923 }
3924
3925 /* Process Locked */
3926 __HAL_LOCK(hhrtim);
3927
3928 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3929
3930 /* Configure the event channel */
3931 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3932
3933 hhrtim->State = HAL_HRTIM_STATE_READY;
3934
3935 /* Process Unlocked */
3936 __HAL_UNLOCK(hhrtim);
3937
3938 return HAL_OK;
3939 }
3940
3941 /**
3942 * @brief Configure the external event conditioning block prescaler
3943 * @param hhrtim pointer to HAL HRTIM handle
3944 * @param Prescaler Prescaler value
3945 * This parameter can be one of the following values:
3946 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
3947 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
3948 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
3949 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
3950 * @note This function must be called before starting the timer
3951 * @retval HAL status
3952 */
HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)3953 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3954 uint32_t Prescaler)
3955 {
3956 /* Check parameters */
3957 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3958
3959 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3960 {
3961 return HAL_BUSY;
3962 }
3963
3964 /* Process Locked */
3965 __HAL_LOCK(hhrtim);
3966
3967 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3968
3969 /* Set the external event prescaler */
3970 MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
3971
3972 hhrtim->State = HAL_HRTIM_STATE_READY;
3973
3974 /* Process Unlocked */
3975 __HAL_UNLOCK(hhrtim);
3976
3977 return HAL_OK;
3978 }
3979
3980 /**
3981 * @brief Configure the conditioning of fault input
3982 * @param hhrtim pointer to HAL HRTIM handle
3983 * @param Fault fault input to configure
3984 * This parameter can be one of the following values:
3985 * @arg HRTIM_FAULT_1: Fault input 1
3986 * @arg HRTIM_FAULT_2: Fault input 2
3987 * @arg HRTIM_FAULT_3: Fault input 3
3988 * @arg HRTIM_FAULT_4: Fault input 4
3989 * @arg HRTIM_FAULT_5: Fault input 5
3990 * @arg HRTIM_FAULT_6: Fault input 6
3991 * @param pFaultCfg pointer to the fault conditioning configuration structure
3992 * @note This function must be called before starting the timer and before
3993 * enabling faults inputs
3994 * @retval HAL status
3995 */
HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault,HRTIM_FaultCfgTypeDef * pFaultCfg)3996 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
3997 uint32_t Fault,
3998 HRTIM_FaultCfgTypeDef* pFaultCfg)
3999 {
4000 uint32_t hrtim_fltinr1;
4001 uint32_t hrtim_fltinr2;
4002 uint32_t source0,source1;
4003
4004 /* Check parameters */
4005 assert_param(IS_HRTIM_FAULT(Fault));
4006 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
4007 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
4008 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
4009 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
4010
4011 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4012 {
4013 return HAL_BUSY;
4014 }
4015
4016 /* Process Locked */
4017 __HAL_LOCK(hhrtim);
4018
4019 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4020
4021 /* Configure fault channel */
4022 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
4023 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
4024
4025 source0 = (pFaultCfg->Source & 1U);
4026 source1 = ((pFaultCfg->Source & 2U) >> 1);
4027
4028 switch (Fault)
4029 {
4030 case HRTIM_FAULT_1:
4031 {
4032 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
4033 hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
4034 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT1SRC_0_Pos);
4035 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT1SRC_1);
4036 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT1SRC_1_Pos);
4037 hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
4038 hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
4039 break;
4040 }
4041
4042 case HRTIM_FAULT_2:
4043 {
4044 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
4045 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
4046 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT2SRC_0_Pos);
4047 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT2SRC_1);
4048 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT2SRC_1_Pos);
4049 hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
4050 hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
4051 break;
4052 }
4053
4054 case HRTIM_FAULT_3:
4055 {
4056 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
4057 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
4058 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT3SRC_0_Pos);
4059 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT3SRC_1);
4060 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT3SRC_1_Pos);
4061 hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
4062 hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
4063 break;
4064 }
4065
4066 case HRTIM_FAULT_4:
4067 {
4068 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC_0 | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
4069 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
4070 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT4SRC_0_Pos);
4071 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT4SRC_1);
4072 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT4SRC_1_Pos);
4073 hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
4074 hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
4075 break;
4076 }
4077
4078 case HRTIM_FAULT_5:
4079 {
4080 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
4081 hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
4082 hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT5SRC_0_Pos);
4083 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5SRC_1);
4084 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT5SRC_1_Pos);
4085 hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
4086 hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
4087 break;
4088 }
4089
4090 case HRTIM_FAULT_6:
4091 {
4092 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6P | HRTIM_FLTINR2_FLT6SRC_0 | HRTIM_FLTINR2_FLT6F | HRTIM_FLTINR2_FLT6LCK);
4093 hrtim_fltinr2 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR2_FLT6P);
4094 hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT6SRC_0_Pos);
4095 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6SRC_1);
4096 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT6SRC_1_Pos);
4097 hrtim_fltinr2 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR2_FLT6F);
4098 hrtim_fltinr2 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR2_FLT6LCK);
4099 break;
4100 }
4101
4102 default:
4103 {
4104 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4105
4106 /* Process Unlocked */
4107 __HAL_UNLOCK(hhrtim);
4108
4109 break;
4110 }
4111 }
4112
4113 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4114 {
4115 return HAL_ERROR;
4116 }
4117
4118 /* Update the HRTIM registers except LOCK bit */
4119 hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
4120 hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
4121
4122 /* Update the HRTIM registers LOCK bit */
4123 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
4124 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
4125
4126 hhrtim->State = HAL_HRTIM_STATE_READY;
4127
4128 /* Process Unlocked */
4129 __HAL_UNLOCK(hhrtim);
4130
4131 return HAL_OK;
4132 }
4133
4134 /**
4135 * @brief Configure the fault conditioning block prescaler
4136 * @param hhrtim pointer to HAL HRTIM handle
4137 * @param Prescaler Prescaler value
4138 * This parameter can be one of the following values:
4139 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
4140 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
4141 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
4142 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
4143 * @retval HAL status
4144 * @note This function must be called before starting the timer and before
4145 * enabling faults inputs
4146 */
HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Prescaler)4147 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
4148 uint32_t Prescaler)
4149 {
4150 /* Check parameters */
4151 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
4152
4153 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4154 {
4155 return HAL_BUSY;
4156 }
4157
4158 /* Process Locked */
4159 __HAL_LOCK(hhrtim);
4160
4161 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4162
4163 /* Set the external event prescaler */
4164 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
4165
4166 hhrtim->State = HAL_HRTIM_STATE_READY;
4167
4168 /* Process Unlocked */
4169 __HAL_UNLOCK(hhrtim);
4170
4171 return HAL_OK;
4172 }
4173
4174 /**
4175 * @brief Configure and Enable the blanking source of a Fault input
4176 * @param hhrtim pointer to HAL HRTIM handle
4177 * @param Fault fault input to configure
4178 * This parameter can be one of the following values:
4179 * @arg HRTIM_FAULT_1: Fault input 1
4180 * @arg HRTIM_FAULT_2: Fault input 2
4181 * @arg HRTIM_FAULT_3: Fault input 3
4182 * @arg HRTIM_FAULT_4: Fault input 4
4183 * @arg HRTIM_FAULT_5: Fault input 5
4184 * @arg HRTIM_FAULT_6: Fault input 6
4185 * @param pFaultBlkCfg: pointer to the fault conditioning configuration structure
4186 * @note This function automatically enables the Blanking on Fault
4187 * @note This function must be called when fault is not enabled
4188 * @retval HAL status
4189 */
HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault,HRTIM_FaultBlankingCfgTypeDef * pFaultBlkCfg)4190 HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim,
4191 uint32_t Fault,
4192 HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg)
4193 {
4194 /* Check parameters */
4195 assert_param(IS_HRTIM_FAULT(Fault));
4196 assert_param(IS_HRTIM_FAULTBLANKNGMODE(pFaultBlkCfg->BlankingSource));
4197
4198 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4199 {
4200 return HAL_BUSY;
4201 }
4202
4203 /* Process Locked */
4204 __HAL_LOCK(hhrtim);
4205
4206 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4207
4208 switch (Fault)
4209 {
4210 case HRTIM_FAULT_1:
4211 {
4212 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4213 (HRTIM_FLTINR3_FLT1BLKS | HRTIM_FLTINR3_FLT1BLKE),
4214 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT1BLKS_Pos) |
4215 HRTIM_FLTINR3_FLT1BLKE));
4216 break;
4217 }
4218 case HRTIM_FAULT_2:
4219 {
4220 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4221 (HRTIM_FLTINR3_FLT2BLKS | HRTIM_FLTINR3_FLT2BLKE),
4222 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT2BLKS_Pos) |
4223 HRTIM_FLTINR3_FLT2BLKE));
4224 break;
4225 }
4226 case HRTIM_FAULT_3:
4227 {
4228 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4229 (HRTIM_FLTINR3_FLT3BLKS | HRTIM_FLTINR3_FLT3BLKE),
4230 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT3BLKS_Pos) |
4231 HRTIM_FLTINR3_FLT3BLKE));
4232 break;
4233 }
4234 case HRTIM_FAULT_4:
4235 {
4236 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4237 (HRTIM_FLTINR3_FLT4BLKS | HRTIM_FLTINR3_FLT4BLKE),
4238 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT4BLKS_Pos) |
4239 HRTIM_FLTINR3_FLT4BLKE));
4240 break;
4241 }
4242 case HRTIM_FAULT_5:
4243 {
4244 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4245 (HRTIM_FLTINR4_FLT5BLKS | HRTIM_FLTINR4_FLT5BLKE),
4246 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT5BLKS_Pos) |
4247 HRTIM_FLTINR4_FLT5BLKE));
4248 break;
4249 }
4250 case HRTIM_FAULT_6:
4251 {
4252 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4253 (HRTIM_FLTINR4_FLT6BLKS | HRTIM_FLTINR4_FLT6BLKE),
4254 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT6BLKS_Pos) |
4255 HRTIM_FLTINR4_FLT6BLKE));
4256 break;
4257 }
4258
4259 default:
4260 {
4261 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4262
4263 /* Process Unlocked */
4264 __HAL_UNLOCK(hhrtim);
4265
4266 break;
4267 }
4268 }
4269
4270 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4271 {
4272 return HAL_ERROR;
4273 }
4274
4275 hhrtim->State = HAL_HRTIM_STATE_READY;
4276
4277 /* Process Unlocked */
4278 __HAL_UNLOCK(hhrtim);
4279
4280 return HAL_OK;
4281 }
4282
4283 /**
4284 * @brief Configure the Fault Counter (Threshold and Reset Mode)
4285 * @param hhrtim pointer to HAL HRTIM handle
4286 * @param Fault fault input to configure
4287 * This parameter can be one of the following values:
4288 * @arg HRTIM_FAULT_1: Fault input 1
4289 * @arg HRTIM_FAULT_2: Fault input 2
4290 * @arg HRTIM_FAULT_3: Fault input 3
4291 * @arg HRTIM_FAULT_4: Fault input 4
4292 * @arg HRTIM_FAULT_5: Fault input 5
4293 * @arg HRTIM_FAULT_6: Fault input 6
4294 * @param pFaultBlkCfg: pointer to the fault conditioning configuration structure
4295 * @retval HAL status
4296 * @note A fault is considered valid when the number of
4297 * events is equal to the (FLTxCNT[3:0]+1) value
4298 *
4299 * @retval HAL status
4300 */
HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault,HRTIM_FaultBlankingCfgTypeDef * pFaultBlkCfg)4301 HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim,
4302 uint32_t Fault,
4303 HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg)
4304 {
4305 /* Check parameters */
4306 assert_param(IS_HRTIM_FAULT(Fault));
4307 assert_param(IS_HRTIM_FAULTCOUNTER(pFaultBlkCfg->Threshold));
4308 assert_param(IS_HRTIM_FAULTCOUNTERRST(pFaultBlkCfg->ResetMode));
4309
4310 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4311 {
4312 return HAL_BUSY;
4313 }
4314
4315 /* Process Locked */
4316 __HAL_LOCK(hhrtim);
4317
4318 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4319
4320 switch (Fault)
4321 {
4322 case HRTIM_FAULT_1:
4323 {
4324 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4325 (HRTIM_FLTINR3_FLT1RSTM | HRTIM_FLTINR3_FLT1CNT),
4326 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT1CNT_Pos) |
4327 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT1RSTM_Pos));
4328 break;
4329 }
4330 case HRTIM_FAULT_2:
4331 {
4332 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4333 (HRTIM_FLTINR3_FLT2RSTM | HRTIM_FLTINR3_FLT2CNT),
4334 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT2CNT_Pos) |
4335 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT2RSTM_Pos));
4336 break;
4337 }
4338 case HRTIM_FAULT_3:
4339 {
4340 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4341 (HRTIM_FLTINR3_FLT3RSTM | HRTIM_FLTINR3_FLT3CNT),
4342 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT3CNT_Pos) |
4343 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT3RSTM_Pos));
4344 break;
4345 }
4346 case HRTIM_FAULT_4:
4347 {
4348 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4349 (HRTIM_FLTINR3_FLT4RSTM | HRTIM_FLTINR3_FLT4CNT),
4350 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT4CNT_Pos) |
4351 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT4RSTM_Pos));
4352 break;
4353 }
4354 case HRTIM_FAULT_5:
4355 {
4356 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4357 (HRTIM_FLTINR4_FLT5RSTM | HRTIM_FLTINR4_FLT5CNT),
4358 (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT5CNT_Pos) |
4359 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT5RSTM_Pos));
4360 break;
4361 }
4362 case HRTIM_FAULT_6:
4363 {
4364 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4365 (HRTIM_FLTINR4_FLT6RSTM | HRTIM_FLTINR4_FLT6CNT),
4366 (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT6CNT_Pos) |
4367 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT6RSTM_Pos));
4368 break;
4369 }
4370
4371 default:
4372 {
4373 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4374
4375 /* Process Unlocked */
4376 __HAL_UNLOCK(hhrtim);
4377
4378 break;
4379 }
4380 }
4381
4382 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4383 {
4384 return HAL_ERROR;
4385 }
4386
4387 hhrtim->State = HAL_HRTIM_STATE_READY;
4388
4389 /* Process Unlocked */
4390 __HAL_UNLOCK(hhrtim);
4391
4392 return HAL_OK;
4393 }
4394
4395 /**
4396 * @brief Reset the fault Counter Reset
4397 * @param hhrtim pointer to HAL HRTIM handle
4398 * @param Fault fault input to reset
4399 * This parameter can be one of the following values:
4400 * @arg HRTIM_FAULT_1: Fault input 1
4401 * @arg HRTIM_FAULT_2: Fault input 2
4402 * @arg HRTIM_FAULT_3: Fault input 3
4403 * @arg HRTIM_FAULT_4: Fault input 4
4404 * @arg HRTIM_FAULT_5: Fault input 5
4405 * @arg HRTIM_FAULT_6: Fault input 6
4406 * @retval HAL status
4407 */
HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim,uint32_t Fault)4408 HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim,
4409 uint32_t Fault)
4410 {
4411 /* Check parameters */
4412 assert_param(IS_HRTIM_FAULT(Fault));
4413
4414 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4415 {
4416 return HAL_BUSY;
4417 }
4418
4419 /* Process Locked */
4420 __HAL_LOCK(hhrtim);
4421
4422 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4423
4424 switch (Fault)
4425 {
4426 case HRTIM_FAULT_1:
4427 {
4428 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT1CRES, HRTIM_FLTINR3_FLT1CRES) ;
4429 break;
4430 }
4431 case HRTIM_FAULT_2:
4432 {
4433 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT2CRES, HRTIM_FLTINR3_FLT2CRES) ;
4434 break;
4435 }
4436 case HRTIM_FAULT_3:
4437 {
4438 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT3CRES, HRTIM_FLTINR3_FLT3CRES) ;
4439 break;
4440 }
4441 case HRTIM_FAULT_4:
4442 {
4443 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT4CRES, HRTIM_FLTINR3_FLT4CRES) ;
4444 break;
4445 }
4446 case HRTIM_FAULT_5:
4447 {
4448 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT5CRES, HRTIM_FLTINR4_FLT5CRES) ;
4449 break;
4450 }
4451 case HRTIM_FAULT_6:
4452 {
4453 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT6CRES, HRTIM_FLTINR4_FLT6CRES) ;
4454 break;
4455 }
4456
4457 default:
4458 {
4459 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4460
4461 /* Process Unlocked */
4462 __HAL_UNLOCK(hhrtim);
4463
4464 break;
4465 }
4466 }
4467
4468 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4469 {
4470 return HAL_ERROR;
4471 }
4472
4473 hhrtim->State = HAL_HRTIM_STATE_READY;
4474
4475 /* Process Unlocked */
4476 __HAL_UNLOCK(hhrtim);
4477
4478 return HAL_OK;
4479 }
4480
4481 /**
4482 * @brief Enable or disables the HRTIMx Fault mode.
4483 * @param hhrtim pointer to HAL HRTIM handle
4484 * @param Faults fault input(s) to enable or disable
4485 * This parameter can be any combination of the following values:
4486 * @arg HRTIM_FAULT_1: Fault input 1
4487 * @arg HRTIM_FAULT_2: Fault input 2
4488 * @arg HRTIM_FAULT_3: Fault input 3
4489 * @arg HRTIM_FAULT_4: Fault input 4
4490 * @arg HRTIM_FAULT_5: Fault input 5
4491 * @arg HRTIM_FAULT_6: Fault input 6
4492 * @param Enable Fault(s) enabling
4493 * This parameter can be one of the following values:
4494 * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
4495 * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
4496 * @retval None
4497 */
HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Faults,uint32_t Enable)4498 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
4499 uint32_t Faults,
4500 uint32_t Enable)
4501 {
4502 /* Check parameters */
4503 assert_param(IS_HRTIM_FAULT(Faults));
4504 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
4505
4506 if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
4507 {
4508 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
4509 }
4510 if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
4511 {
4512 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
4513 }
4514 if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
4515 {
4516 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
4517 }
4518 if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
4519 {
4520 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
4521 }
4522 if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
4523 {
4524 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
4525 }
4526 if ((Faults & HRTIM_FAULT_6) != (uint32_t)RESET)
4527 {
4528 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT6E, ((Enable << 8U) & HRTIM_FLTINR2_FLT6E));
4529 }
4530 }
4531
4532 /**
4533 * @brief Configure both the ADC trigger register update source and the ADC
4534 * trigger source.
4535 * @param hhrtim pointer to HAL HRTIM handle
4536 * @param ADCTrigger ADC trigger to configure
4537 * This parameter can be one of the following values:
4538 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
4539 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
4540 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
4541 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
4542 * @arg HRTIM_ADCTRIGGER_5: ADC trigger 5
4543 * @arg HRTIM_ADCTRIGGER_6: ADC trigger 6
4544 * @arg HRTIM_ADCTRIGGER_7: ADC trigger 7
4545 * @arg HRTIM_ADCTRIGGER_8: ADC trigger 8
4546 * @arg HRTIM_ADCTRIGGER_9: ADC trigger 9
4547 * @arg HRTIM_ADCTRIGGER_10: ADC trigger 10
4548 * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
4549 * for Trigger nb (1..4): pADCTriggerCfg->Trigger parameter
4550 * can be a combination of the following values
4551 * @arg HRTIM_ADCTRIGGEREVENT13_...
4552 * @arg HRTIM_ADCTRIGGEREVENT24_...
4553 * for Trigger nb (5..10): pADCTriggerCfg->Trigger parameter
4554 * can be one of the following values
4555 * @arg HRTIM_ADCTRIGGEREVENT579_...
4556 * @arg HRTIM_ADCTRIGGEREVENT6810_...
4557 * @retval HAL status
4558 * @note This function must be called before starting the timer
4559 */
HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t ADCTrigger,HRTIM_ADCTriggerCfgTypeDef * pADCTriggerCfg)4560 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
4561 uint32_t ADCTrigger,
4562 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
4563 {
4564 uint32_t hrtim_cr1;
4565 uint32_t hrtim_adcur;
4566
4567 /* Check parameters */
4568 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
4569 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
4570
4571 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4572 {
4573 return HAL_BUSY;
4574 }
4575
4576 /* Process Locked */
4577 __HAL_LOCK(hhrtim);
4578
4579 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4580
4581 /* Set the ADC trigger update source */
4582 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
4583 hrtim_adcur = hhrtim->Instance->sCommonRegs.ADCUR;
4584
4585 switch (ADCTrigger)
4586 {
4587 case HRTIM_ADCTRIGGER_1:
4588 {
4589 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
4590 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
4591
4592 /* Set the ADC trigger 1 source */
4593 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
4594 break;
4595 }
4596
4597 case HRTIM_ADCTRIGGER_2:
4598 {
4599 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
4600 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
4601
4602 /* Set the ADC trigger 2 source */
4603 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
4604 break;
4605 }
4606
4607 case HRTIM_ADCTRIGGER_3:
4608 {
4609 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
4610 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
4611
4612 /* Set the ADC trigger 3 source */
4613 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
4614 break;
4615 }
4616
4617 case HRTIM_ADCTRIGGER_4:
4618 {
4619 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
4620 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
4621
4622 /* Set the ADC trigger 4 source */
4623 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
4624 break;
4625 }
4626
4627 case HRTIM_ADCTRIGGER_5:
4628 {
4629 hrtim_adcur &= ~(HRTIM_ADCUR_AD5USRC);
4630 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 16U) & HRTIM_ADCUR_AD5USRC);
4631
4632 /* Set the ADC trigger 5 source */
4633 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD5TRG);
4634 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD5TRG_Pos) & HRTIM_ADCER_AD5TRG);
4635 break;
4636 }
4637
4638 case HRTIM_ADCTRIGGER_6:
4639 {
4640 hrtim_adcur &= ~(HRTIM_ADCUR_AD6USRC);
4641 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 12U) & HRTIM_ADCUR_AD6USRC);
4642
4643 /* Set the ADC trigger 6 source */
4644 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD6TRG);
4645 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD6TRG_Pos) & HRTIM_ADCER_AD6TRG);
4646 break;
4647 }
4648
4649 case HRTIM_ADCTRIGGER_7:
4650 {
4651 hrtim_adcur &= ~(HRTIM_ADCUR_AD7USRC);
4652 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 8U) & HRTIM_ADCUR_AD7USRC);
4653
4654 /* Set the ADC trigger 7 source */
4655 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD7TRG);
4656 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD7TRG_Pos) & HRTIM_ADCER_AD7TRG);
4657 break;
4658 }
4659
4660 case HRTIM_ADCTRIGGER_8:
4661 {
4662 hrtim_adcur &= ~(HRTIM_ADCUR_AD8USRC);
4663 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 4U) & HRTIM_ADCUR_AD8USRC);
4664
4665 /* Set the ADC trigger 8 source */
4666 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD8TRG);
4667 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD8TRG_Pos) & HRTIM_ADCER_AD8TRG);
4668 break;
4669 }
4670
4671 case HRTIM_ADCTRIGGER_9:
4672 {
4673 hrtim_adcur &= ~(HRTIM_ADCUR_AD9USRC);
4674 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource) & HRTIM_ADCUR_AD9USRC);
4675
4676 /* Set the ADC trigger 9 source */
4677 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD9TRG);
4678 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD9TRG_Pos) & HRTIM_ADCER_AD9TRG);
4679 break;
4680 }
4681
4682 case HRTIM_ADCTRIGGER_10:
4683 {
4684 hrtim_adcur &= ~(HRTIM_ADCUR_AD10USRC);
4685 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource << 4U) & HRTIM_ADCUR_AD10USRC);
4686
4687 /* Set the ADC trigger 10 source */
4688 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD10TRG);
4689 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD10TRG_Pos) & HRTIM_ADCER_AD10TRG);
4690 break;
4691 }
4692
4693 default:
4694 {
4695 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4696
4697 /* Process Unlocked */
4698 __HAL_UNLOCK(hhrtim);
4699
4700 break;
4701 }
4702 }
4703
4704 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4705 {
4706 return HAL_ERROR;
4707 }
4708
4709 /* Update the HRTIM registers */
4710 if (ADCTrigger < HRTIM_ADCTRIGGER_5)
4711 {
4712 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
4713 }
4714 else
4715 {
4716 hhrtim->Instance->sCommonRegs.ADCUR = hrtim_adcur;
4717 }
4718
4719 hhrtim->State = HAL_HRTIM_STATE_READY;
4720
4721 /* Process Unlocked */
4722 __HAL_UNLOCK(hhrtim);
4723
4724 return HAL_OK;
4725 }
4726
4727 /**
4728 * @brief Configure the ADC trigger postscaler register of the ADC
4729 * trigger source.
4730 * @param hhrtim pointer to HAL HRTIM handle
4731 * @param ADCTrigger ADC trigger to configure
4732 * This parameter can be one of the following values:
4733 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
4734 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
4735 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
4736 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
4737 * @arg HRTIM_ADCTRIGGER_5: ADC trigger 5
4738 * @arg HRTIM_ADCTRIGGER_6: ADC trigger 6
4739 * @arg HRTIM_ADCTRIGGER_7: ADC trigger 7
4740 * @arg HRTIM_ADCTRIGGER_8: ADC trigger 8
4741 * @arg HRTIM_ADCTRIGGER_9: ADC trigger 9
4742 * @arg HRTIM_ADCTRIGGER_10: ADC trigger 10
4743 * @param Postscaler value 0..1F
4744 * @retval HAL status
4745 * @note This function must be called before starting the timer
4746 */
HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t ADCTrigger,uint32_t Postscaler)4747 HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim,
4748 uint32_t ADCTrigger,
4749 uint32_t Postscaler)
4750 {
4751 /* Check parameters */
4752 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
4753
4754 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4755 {
4756 return HAL_BUSY;
4757 }
4758
4759 /* Process Locked */
4760 __HAL_LOCK(hhrtim);
4761
4762 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4763
4764 switch (ADCTrigger)
4765 {
4766 case HRTIM_ADCTRIGGER_1:
4767 {
4768 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD1PSC, (Postscaler & HRTIM_ADCPS1_AD1PSC));
4769 break;
4770 }
4771
4772 case HRTIM_ADCTRIGGER_2:
4773 {
4774 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD2PSC, ((Postscaler << HRTIM_ADCPS1_AD2PSC_Pos) & HRTIM_ADCPS1_AD2PSC));
4775 break;
4776 }
4777
4778 case HRTIM_ADCTRIGGER_3:
4779 {
4780 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD3PSC, ((Postscaler << HRTIM_ADCPS1_AD3PSC_Pos) & HRTIM_ADCPS1_AD3PSC));
4781 break;
4782 }
4783
4784 case HRTIM_ADCTRIGGER_4:
4785 {
4786 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD4PSC, ((Postscaler << HRTIM_ADCPS1_AD4PSC_Pos) & HRTIM_ADCPS1_AD4PSC));
4787 break;
4788 }
4789
4790 case HRTIM_ADCTRIGGER_5:
4791 {
4792 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD5PSC, ((Postscaler << HRTIM_ADCPS1_AD5PSC_Pos) & HRTIM_ADCPS1_AD5PSC));
4793 break;
4794 }
4795
4796 case HRTIM_ADCTRIGGER_6:
4797 {
4798 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD6PSC, ((Postscaler << HRTIM_ADCPS2_AD6PSC_Pos) & HRTIM_ADCPS2_AD6PSC));
4799 break;
4800 }
4801
4802 case HRTIM_ADCTRIGGER_7:
4803 {
4804 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD7PSC, ((Postscaler << HRTIM_ADCPS2_AD7PSC_Pos) & HRTIM_ADCPS2_AD7PSC));
4805 break;
4806 }
4807
4808 case HRTIM_ADCTRIGGER_8:
4809 {
4810 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD8PSC, ((Postscaler << HRTIM_ADCPS2_AD8PSC_Pos) & HRTIM_ADCPS2_AD8PSC));
4811 break;
4812 }
4813
4814 case HRTIM_ADCTRIGGER_9:
4815 {
4816 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD9PSC, ((Postscaler << HRTIM_ADCPS2_AD9PSC_Pos) & HRTIM_ADCPS2_AD9PSC));
4817 break;
4818 }
4819
4820 case HRTIM_ADCTRIGGER_10:
4821 {
4822 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD10PSC, ((Postscaler << HRTIM_ADCPS2_AD10PSC_Pos) & HRTIM_ADCPS2_AD10PSC));
4823 break;
4824 }
4825
4826 default:
4827 {
4828 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4829
4830 /* Process Unlocked */
4831 __HAL_UNLOCK(hhrtim);
4832
4833 break;
4834 }
4835 }
4836
4837 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4838 {
4839 return HAL_ERROR;
4840 }
4841
4842 hhrtim->State = HAL_HRTIM_STATE_READY;
4843
4844 /* Process Unlocked */
4845 __HAL_UNLOCK(hhrtim);
4846
4847 return HAL_OK;
4848 }
4849
4850 /**
4851 * @brief Configure the ADC Roll-Over mode of the ADC
4852 * trigger source.
4853 * @param hhrtim pointer to HAL HRTIM handle
4854 * @param TimerIdx Timer index
4855 * This parameter can be one of the following values:
4856 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4857 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4858 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4859 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4860 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4861 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
4862 * @param RollOverCfg This parameter can be a combination of all the following values:
4863 * @arg HRTIM_TIM_FEROM_BOTH or HRTIM_TIM_FEROM_CREST or HRTIM_TIM_FEROM_VALLEY
4864 * @arg HRTIM_TIM_BMROM_BOTH or HRTIM_TIM_BMROM_CREST or HRTIM_TIM_BMROM_VALLEY
4865 * @arg HRTIM_TIM_ADROM_BOTH or HRTIM_TIM_ADROM_CREST or HRTIM_TIM_ADROM_VALLEY
4866 * @arg HRTIM_TIM_OUTROM_BOTH or HRTIM_TIM_OUTROM_CREST or HRTIM_TIM_OUTROM_VALLEY
4867 * @arg HRTIM_TIM_ROM_BOTH or HRTIM_TIM_ROM_CREST or HRTIM_TIM_ROM_VALLEY
4868 * @note This function must be called before starting the timer
4869 */
HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t RollOverCfg)4870 HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim,
4871 uint32_t TimerIdx,
4872 uint32_t RollOverCfg)
4873 {
4874 /* Check parameters */
4875 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4876 assert_param(IS_HRTIM_ROLLOVERMODE(RollOverCfg));
4877
4878 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4879 {
4880 return HAL_BUSY;
4881 }
4882
4883 /* Process Locked */
4884 __HAL_LOCK(hhrtim);
4885
4886 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4887
4888 HRTIM_TimingUnitRollOver_Config(hhrtim,TimerIdx,RollOverCfg);
4889
4890 hhrtim->State = HAL_HRTIM_STATE_READY;
4891
4892 /* Process Unlocked */
4893 __HAL_UNLOCK(hhrtim);
4894
4895 return HAL_OK;
4896 }
4897
4898
4899 /**
4900 * @}
4901 */
4902
4903 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
4904 * @brief HRTIM timer configuration and control functions
4905 @verbatim
4906 ===============================================================================
4907 ##### HRTIM timer configuration and control functions #####
4908 ===============================================================================
4909 [..] This section provides functions used to configure and control a
4910 HRTIM timer operating in waveform mode:
4911 (+) Configure HRTIM timer general behavior
4912 (+) Configure HRTIM timer event filtering
4913 (+) Configure HRTIM timer deadtime insertion
4914 (+) Configure HRTIM timer chopper mode
4915 (+) Configure HRTIM timer burst DMA
4916 (+) Configure HRTIM timer compare unit
4917 (+) Configure HRTIM timer capture unit
4918 (+) Configure HRTIM timer output
4919 (+) Set HRTIM timer output level
4920 (+) Enable HRTIM timer output
4921 (+) Disable HRTIM timer output
4922 (+) Start HRTIM timer
4923 (+) Stop HRTIM timer
4924 (+) Start HRTIM timer and enable interrupt
4925 (+) Stop HRTIM timer and disable interrupt
4926 (+) Start HRTIM timer and enable DMA transfer
4927 (+) Stop HRTIM timer and disable DMA transfer
4928 (+) Enable or disable the burst mode controller
4929 (+) Start the burst mode controller (by software)
4930 (+) Trigger a Capture (by software)
4931 (+) Update the HRTIM timer preloadable registers (by software)
4932 (+) Reset the HRTIM timer counter (by software)
4933 (+) Start a burst DMA transfer
4934 (+) Enable timer register update
4935 (+) Disable timer register update
4936
4937 @endverbatim
4938 * @{
4939 */
4940
4941 /**
4942 * @brief Configure the general behavior of a timer operating in waveform mode
4943 * @param hhrtim pointer to HAL HRTIM handle
4944 * @param TimerIdx Timer index
4945 * This parameter can be one of the following values:
4946 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4947 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4948 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4949 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4950 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4951 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4952 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
4953 * @param pTimerCfg pointer to the timer configuration structure
4954 * @note When the timer operates in waveform mode, all the features supported by
4955 * the HRTIM are available without any limitation.
4956 * @retval HAL status
4957 * @note This function must be called before starting the timer
4958 */
HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,HRTIM_TimerCfgTypeDef * pTimerCfg)4959 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
4960 uint32_t TimerIdx,
4961 HRTIM_TimerCfgTypeDef * pTimerCfg)
4962 {
4963 /* Check parameters */
4964 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4965
4966 /* Relevant for all HRTIM timers, including the master */
4967 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
4968 assert_param(IS_HRTIM_INTERLEAVEDMODE(pTimerCfg->InterleavedMode));
4969 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
4970 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
4971 assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
4972 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
4973 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
4974 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
4975
4976 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4977 {
4978 return HAL_BUSY;
4979 }
4980
4981 /* Process Locked */
4982 __HAL_LOCK(hhrtim);
4983
4984 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4985
4986 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4987 {
4988 /* Check parameters */
4989 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
4990 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
4991 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
4992
4993 /* Configure master timer */
4994 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
4995 }
4996 else
4997 {
4998 /* Check parameters */
4999 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
5000 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
5001 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
5002 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
5003 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
5004 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
5005 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
5006 pTimerCfg->DeadTimeInsertion));
5007 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
5008 pTimerCfg->DelayedProtectionMode));
5009 assert_param(IS_HRTIM_OUTPUTBALANCEDIDLE(pTimerCfg->BalancedIdleAutomaticResume));
5010 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
5011 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
5012 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
5013 assert_param(IS_HRTIM_TIMSYNCUPDATE(pTimerCfg->ReSyncUpdate));
5014
5015 /* Configure timing unit */
5016 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
5017 }
5018
5019 /* Update timer parameters */
5020 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
5021 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
5022 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
5023 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
5024 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
5025
5026 /* Force a software update */
5027 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
5028
5029 /* Configure slave timer update re-synchronization */
5030 if ((TimerIdx != HRTIM_TIMERINDEX_MASTER)
5031 && (pTimerCfg->UpdateGating == HRTIM_UPDATEGATING_INDEPENDENT))
5032 {
5033 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR,
5034 HRTIM_TIMCR_RSYNCU_Msk,
5035 pTimerCfg->ReSyncUpdate << HRTIM_TIMCR_RSYNCU_Pos);
5036 }
5037
5038 hhrtim->State = HAL_HRTIM_STATE_READY;
5039
5040 /* Process Unlocked */
5041 __HAL_UNLOCK(hhrtim);
5042
5043 return HAL_OK;
5044 }
5045
5046 /**
5047 * @brief Configure the general behavior of a timer operating in waveform mode
5048 * @param hhrtim pointer to HAL HRTIM handle
5049 * @param TimerIdx Timer index
5050 * This parameter can be one of the following values:
5051 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5052 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5053 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5054 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5055 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5056 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5057 * @param pTimerCtl pointer to the timer configuration structure
5058 * @note When the timer operates in waveform mode, all the features supported by
5059 * the HRTIM are available without any limitation.
5060 * @retval HAL status
5061 * @note This function must be called before starting the timer
5062 */
HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,HRTIM_TimerCtlTypeDef * pTimerCtl)5063 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim,
5064 uint32_t TimerIdx,
5065 HRTIM_TimerCtlTypeDef * pTimerCtl)
5066 {
5067 /* Check parameters */
5068 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5069 /* Relevant for all A..F HRTIM timers */
5070 assert_param(IS_HRTIM_TIMERUPDOWNMODE(pTimerCtl->UpDownMode));
5071 assert_param(IS_HRTIM_TIMERTRGHLFMODE(pTimerCtl->TrigHalf));
5072 assert_param(IS_HRTIM_TIMERGTCMP3(pTimerCtl->GreaterCMP3));
5073 assert_param(IS_HRTIM_TIMERGTCMP1(pTimerCtl->GreaterCMP1));
5074 assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
5075 assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
5076 assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
5077
5078 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5079 {
5080 return HAL_BUSY;
5081 }
5082
5083 /* Process Locked */
5084 __HAL_LOCK(hhrtim);
5085
5086 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5087
5088 /* Configure timing unit */
5089 HRTIM_TimingUnitWaveform_Control(hhrtim, TimerIdx, pTimerCtl);
5090
5091 /* Force a software update */
5092 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
5093
5094 hhrtim->State = HAL_HRTIM_STATE_READY;
5095
5096 /* Process Unlocked */
5097 __HAL_UNLOCK(hhrtim);
5098
5099 return HAL_OK;
5100 }
5101
5102 /**
5103 * @brief Configure the Dual Channel Dac behavior of a timer operating in waveform mode
5104 * @param hhrtim: pointer to HAL HRTIM handle
5105 * @param TimerIdx Timer index
5106 * This parameter can be one of the following values:
5107 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5108 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5109 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5110 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5111 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5112 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5113 * @param pTimerCtl pointer to the timer DualChannel Dac configuration structure
5114 * @note When the timer operates in waveform mode, all the features supported by
5115 * the HRTIM are available without any limitation.
5116 * @retval HAL status
5117 * @note This function must be called before starting the timer
5118 */
HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,HRTIM_TimerCtlTypeDef * pTimerCtl)5119 HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim,
5120 uint32_t TimerIdx,
5121 HRTIM_TimerCtlTypeDef * pTimerCtl)
5122 {
5123 assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
5124 assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
5125 assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
5126
5127 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5128 {
5129 return HAL_BUSY;
5130 }
5131
5132 /* Process Locked */
5133 __HAL_LOCK(hhrtim);
5134
5135 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5136 /* clear DCDS,DCDR,DCDE bits */
5137 CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2,
5138 (HRTIM_TIMER_DCDE_ENABLED |
5139 HRTIM_TIMER_DCDS_OUT1RST |
5140 HRTIM_TIMER_DCDR_OUT1SET) );
5141
5142 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 ,
5143 (HRTIM_TIMER_DCDE_ENABLED |
5144 HRTIM_TIMER_DCDS_OUT1RST |
5145 HRTIM_TIMER_DCDR_OUT1SET),
5146 (pTimerCtl->DualChannelDacReset |
5147 pTimerCtl->DualChannelDacStep |
5148 pTimerCtl->DualChannelDacEnable));
5149
5150 hhrtim->State = HAL_HRTIM_STATE_READY;
5151
5152 /* Process Unlocked */
5153 __HAL_UNLOCK(hhrtim);
5154
5155 return HAL_OK;
5156 }
5157
5158 /**
5159 * @brief Configure the event filtering capabilities of a timer (blanking, windowing)
5160 * @param hhrtim pointer to HAL HRTIM handle
5161 * @param TimerIdx Timer index
5162 * This parameter can be one of the following values:
5163 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5164 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5165 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5166 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5167 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5168 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5169 * @param Event external event for which timer event filtering must be configured
5170 * This parameter can be one of the following values:
5171 * @arg HRTIM_EVENT_1: External event 1
5172 * @arg HRTIM_EVENT_2: External event 2
5173 * @arg HRTIM_EVENT_3: External event 3
5174 * @arg HRTIM_EVENT_4: External event 4
5175 * @arg HRTIM_EVENT_5: External event 5
5176 * @arg HRTIM_EVENT_6: External event 6
5177 * @arg HRTIM_EVENT_7: External event 7
5178 * @arg HRTIM_EVENT_8: External event 8
5179 * @arg HRTIM_EVENT_9: External event 9
5180 * @arg HRTIM_EVENT_10: External event 10
5181 * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
5182 * @note This function must be called before starting the timer
5183 * @retval HAL status
5184 */
HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event,HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg)5185 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
5186 uint32_t TimerIdx,
5187 uint32_t Event,
5188 HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
5189 {
5190 /* Check parameters */
5191 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5192 assert_param(IS_HRTIM_EVENT(Event));
5193 assert_param(IS_HRTIM_TIMEVENTFILTER(TimerIdx,pTimerEventFilteringCfg->Filter));
5194
5195 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
5196
5197 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5198 {
5199 return HAL_BUSY;
5200 }
5201
5202 /* Process Locked */
5203 __HAL_LOCK(hhrtim);
5204
5205 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5206
5207 /* Configure timer event filtering capabilities */
5208 switch (Event)
5209 {
5210 case HRTIM_EVENT_NONE:
5211 {
5212 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
5213 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
5214 break;
5215 }
5216
5217 case HRTIM_EVENT_1:
5218 {
5219 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
5220 break;
5221 }
5222
5223 case HRTIM_EVENT_2:
5224 {
5225 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
5226 break;
5227 }
5228
5229 case HRTIM_EVENT_3:
5230 {
5231 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
5232 break;
5233 }
5234
5235 case HRTIM_EVENT_4:
5236 {
5237 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
5238 break;
5239 }
5240
5241 case HRTIM_EVENT_5:
5242 {
5243 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
5244 break;
5245 }
5246
5247 case HRTIM_EVENT_6:
5248 {
5249 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) );
5250 break;
5251 }
5252
5253 case HRTIM_EVENT_7:
5254 {
5255 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
5256 break;
5257 }
5258
5259 case HRTIM_EVENT_8:
5260 {
5261 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
5262 break;
5263 }
5264
5265 case HRTIM_EVENT_9:
5266 {
5267 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
5268 break;
5269 }
5270
5271 case HRTIM_EVENT_10:
5272 {
5273 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
5274 break;
5275 }
5276
5277 default:
5278 {
5279 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5280
5281 /* Process Unlocked */
5282 __HAL_UNLOCK(hhrtim);
5283
5284 break;
5285 }
5286 }
5287
5288 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5289 {
5290 return HAL_ERROR;
5291 }
5292
5293 hhrtim->State = HAL_HRTIM_STATE_READY;
5294
5295 /* Process Unlocked */
5296 __HAL_UNLOCK(hhrtim);
5297
5298 return HAL_OK;
5299 }
5300
5301 /**
5302 * @brief Configure the external Event Counter A or B of a timer (source, threshold, reset mode)
5303 * but does not enable : call HAL_HRTIM_ExternalEventCounterEnable afterwards
5304 * @param hhrtim pointer to HAL HRTIM handle
5305 * @param TimerIdx Timer index
5306 * This parameter can be one of the following values:
5307 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5308 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5309 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5310 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5311 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5312 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5313 * @param EventCounter external event Counter A or B for which timer event must be configured
5314 * This parameter can be one of the following values:
5315 * @arg HRTIM_EVENTCOUNTER_A
5316 * @arg HRTIM_EVENTCOUNTER_B
5317 * @param pTimerExternalEventCfg: pointer to the timer external event configuration structure
5318 * @note This function must be called before starting the timer
5319 * @retval HAL status
5320 */
HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t EventCounter,HRTIM_ExternalEventCfgTypeDef * pTimerExternalEventCfg)5321 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim,
5322 uint32_t TimerIdx,
5323 uint32_t EventCounter,
5324 HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg)
5325 {
5326 uint32_t hrtim_eefr3;
5327
5328 /* Check parameters */
5329 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5330 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5331 assert_param(IS_HRTIM_TIMEEVENT_RESETMODE(pTimerExternalEventCfg->ResetMode));
5332 assert_param(IS_HRTIM_TIMEEVENT_COUNTER(pTimerExternalEventCfg->Counter));
5333 assert_param(IS_HRTIM_EVENT(pTimerExternalEventCfg->Source));
5334
5335 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5336 {
5337 return HAL_BUSY;
5338 }
5339
5340 /* Process Locked */
5341 __HAL_LOCK(hhrtim);
5342
5343 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5344
5345 if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
5346 {
5347 if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE)
5348 { /* reset External EventCounter A */
5349 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0xFFFF0000U);
5350 }
5351 else
5352 {
5353 /* Set timer External EventCounter A configuration */
5354 hrtim_eefr3 = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVARSTM_Pos;
5355 hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVASEL_Pos;
5356 hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVACNT_Pos;
5357 /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */
5358
5359 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, (HRTIM_EEFR3_EEVARSTM | HRTIM_EEFR3_EEVASEL | HRTIM_EEFR3_EEVACNT) , hrtim_eefr3 );
5360 }
5361 }
5362
5363 if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
5364 {
5365 if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE)
5366 { /* reset External EventCounter B */
5367 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0x0000FFFFU);
5368 }
5369 else
5370 {
5371 /* Set timer External EventCounter B configuration */
5372 hrtim_eefr3 = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVBRSTM_Pos;
5373 hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVBSEL_Pos;
5374 hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVBCNT_Pos;
5375 /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */
5376
5377 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, (HRTIM_EEFR3_EEVBRSTM | HRTIM_EEFR3_EEVBSEL | HRTIM_EEFR3_EEVBCNT) , hrtim_eefr3 );
5378 }
5379 }
5380 hhrtim->State = HAL_HRTIM_STATE_READY;
5381
5382 /* Process Unlocked */
5383 __HAL_UNLOCK(hhrtim);
5384
5385 return HAL_OK;
5386 }
5387
5388 /**
5389 * @brief Enable the external event Counter A or B of a timer
5390 * @param hhrtim: pointer to HAL HRTIM handle
5391 * @param TimerIdx: Timer index
5392 * This parameter can be one of the following values:
5393 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5394 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5395 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5396 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5397 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5398 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5399 * @param EventCounter external Event Counter A or B for which timer event must be configured
5400 * This parameter can be a one of the following values:
5401 * @arg HRTIM_EVENTCOUNTER_A
5402 * @arg HRTIM_EVENTCOUNTER_B
5403 * @note This function must be called before starting the timer
5404 * @retval HAL status
5405 */
HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t EventCounter)5406 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim,
5407 uint32_t TimerIdx,
5408 uint32_t EventCounter)
5409 {
5410 /* Check parameters */
5411 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5412 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5413
5414 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5415 {
5416 return HAL_BUSY;
5417 }
5418
5419 /* Process Locked */
5420 __HAL_LOCK(hhrtim);
5421
5422 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5423
5424 if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
5425 {
5426 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE);
5427 }
5428 if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
5429 {
5430 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE);
5431 }
5432
5433 hhrtim->State = HAL_HRTIM_STATE_READY;
5434
5435 /* Process Unlocked */
5436 __HAL_UNLOCK(hhrtim);
5437
5438 return HAL_OK;
5439 }
5440
5441 /**
5442 * @brief Disable the external event Counter A or B of a timer
5443 * @param hhrtim: pointer to HAL HRTIM handle
5444 * @param TimerIdx: Timer index
5445 * This parameter can be one of the following values:
5446 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5447 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5448 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5449 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5450 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5451 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5452 * @param EventCounter external event Counter A or B for which timer event must be configured
5453 * This parameter can be a one of the following values:
5454 * @arg HRTIM_EVENTCOUNTER_A
5455 * @arg HRTIM_EVENTCOUNTER_B
5456 * @retval HAL status
5457 */
HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t EventCounter)5458 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim,
5459 uint32_t TimerIdx,
5460 uint32_t EventCounter)
5461 {
5462 /* Check parameters */
5463 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5464 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5465
5466 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5467 {
5468 return HAL_BUSY;
5469 }
5470
5471 /* Process Locked */
5472 __HAL_LOCK(hhrtim);
5473
5474 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5475
5476 if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
5477 {
5478 CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE);
5479 }
5480
5481 if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
5482 {
5483 CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE);
5484 }
5485
5486 hhrtim->State = HAL_HRTIM_STATE_READY;
5487
5488 /* Process Unlocked */
5489 __HAL_UNLOCK(hhrtim);
5490
5491 return HAL_OK;
5492 }
5493
5494 /**
5495 * @brief Reset the external event Counter A or B of a timer
5496 * @param hhrtim pointer to HAL HRTIM handle
5497 * @param TimerIdx Timer index
5498 * This parameter can be one of the following values:
5499 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5500 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5501 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5502 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5503 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5504 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5505 * @param EventCounter external event Counter A or B for which timer event must be configured
5506 * This parameter can be one of the following values:
5507 * @arg HRTIM_EVENTCOUNTER_A
5508 * @arg HRTIM_EVENTCOUNTER_B
5509 * @note This function must be called before starting the timer
5510 * @retval HAL status
5511 */
HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t EventCounter)5512 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim,
5513 uint32_t TimerIdx,
5514 uint32_t EventCounter)
5515 {
5516 /* Check parameters */
5517 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5518 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5519
5520 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5521 {
5522 return HAL_BUSY;
5523 }
5524
5525 /* Process Locked */
5526 __HAL_LOCK(hhrtim);
5527
5528 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5529
5530 if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
5531 {
5532 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACRES);
5533 }
5534 if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
5535 {
5536 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3,HRTIM_EEFR3_EEVBCRES);
5537 }
5538
5539 hhrtim->State = HAL_HRTIM_STATE_READY;
5540
5541 /* Process Unlocked */
5542 __HAL_UNLOCK(hhrtim);
5543
5544 return HAL_OK;
5545 }
5546
5547 /**
5548 * @brief Configure the dead-time insertion feature for a timer
5549 * @param hhrtim pointer to HAL HRTIM handle
5550 * @param TimerIdx Timer index
5551 * This parameter can be one of the following values:
5552 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5553 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5554 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5555 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5556 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5557 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5558 * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
5559 * @retval HAL status
5560 * @note This function must be called before starting the timer
5561 */
HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,HRTIM_DeadTimeCfgTypeDef * pDeadTimeCfg)5562 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
5563 uint32_t TimerIdx,
5564 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
5565 {
5566 uint32_t hrtim_dtr;
5567
5568 /* Check parameters */
5569 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5570 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
5571 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
5572 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
5573 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
5574 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
5575 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
5576 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
5577
5578 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5579 {
5580 return HAL_BUSY;
5581 }
5582
5583 /* Process Locked */
5584 __HAL_LOCK(hhrtim);
5585
5586 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5587
5588 /* Set timer deadtime configuration */
5589 hrtim_dtr = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
5590 hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
5591 hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
5592 hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
5593 hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
5594 hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
5595 hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
5596 hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
5597 hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
5598
5599 /* Update the HRTIM registers */
5600 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
5601 HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
5602 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
5603 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
5604
5605 hhrtim->State = HAL_HRTIM_STATE_READY;
5606
5607 /* Process Unlocked */
5608 __HAL_UNLOCK(hhrtim);
5609
5610 return HAL_OK;
5611 }
5612
5613 /**
5614 * @brief Configure the chopper mode feature for a timer
5615 * @param hhrtim pointer to HAL HRTIM handle
5616 * @param TimerIdx Timer index
5617 * This parameter can be one of the following values:
5618 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5619 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5620 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5621 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5622 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5623 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5624 * @param pChopperModeCfg pointer to the chopper mode configuration structure
5625 * @retval HAL status
5626 * @note This function must be called before configuring the timer output(s)
5627 */
HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,HRTIM_ChopperModeCfgTypeDef * pChopperModeCfg)5628 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
5629 uint32_t TimerIdx,
5630 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
5631 {
5632 uint32_t hrtim_chpr;
5633
5634 /* Check parameters */
5635 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5636 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
5637 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
5638 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
5639
5640 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5641 {
5642 return HAL_BUSY;
5643 }
5644
5645 /* Process Locked */
5646 __HAL_LOCK(hhrtim);
5647
5648 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5649
5650 /* Set timer choppe mode configuration */
5651 hrtim_chpr = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
5652 hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
5653 hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
5654
5655 /* Update the HRTIM registers */
5656 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR, (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY |
5657 HRTIM_CHPR_STRPW) ,
5658 hrtim_chpr);
5659
5660 hhrtim->State = HAL_HRTIM_STATE_READY;
5661
5662 /* Process Unlocked */
5663 __HAL_UNLOCK(hhrtim);
5664
5665 return HAL_OK;
5666 }
5667
5668 /**
5669 * @brief Configure the burst DMA controller for a timer
5670 * @param hhrtim pointer to HAL HRTIM handle
5671 * @param TimerIdx Timer index
5672 * This parameter can be one of the following values:
5673 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5674 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5675 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5676 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5677 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5678 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5679 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5680 * @param RegistersToUpdate registers to be written by DMA
5681 * This parameter can be any combination of the following values:
5682 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
5683 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
5684 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
5685 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
5686 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
5687 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
5688 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
5689 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
5690 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
5691 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
5692 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
5693 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
5694 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
5695 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
5696 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
5697 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
5698 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
5699 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
5700 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
5701 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
5702 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
5703 * @retval HAL status
5704 * @note This function must be called before starting the timer
5705 */
HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t RegistersToUpdate)5706 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
5707 uint32_t TimerIdx,
5708 uint32_t RegistersToUpdate)
5709 {
5710 /* Check parameters */
5711 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
5712
5713 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5714 {
5715 return HAL_BUSY;
5716 }
5717
5718 /* Process Locked */
5719 __HAL_LOCK(hhrtim);
5720
5721 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5722
5723 /* Set the burst DMA timer update register */
5724 switch (TimerIdx)
5725 {
5726 case HRTIM_TIMERINDEX_TIMER_A:
5727 {
5728 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
5729 break;
5730 }
5731
5732 case HRTIM_TIMERINDEX_TIMER_B:
5733 {
5734 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
5735 break;
5736 }
5737
5738 case HRTIM_TIMERINDEX_TIMER_C:
5739 {
5740 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
5741 break;
5742 }
5743
5744 case HRTIM_TIMERINDEX_TIMER_D:
5745 {
5746 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
5747 break;
5748 }
5749
5750 case HRTIM_TIMERINDEX_TIMER_E:
5751 {
5752 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
5753 break;
5754 }
5755
5756 case HRTIM_TIMERINDEX_TIMER_F:
5757 {
5758 hhrtim->Instance->sCommonRegs.BDTFUPR = RegistersToUpdate;
5759 break;
5760 }
5761
5762 case HRTIM_TIMERINDEX_MASTER:
5763 {
5764 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
5765 break;
5766 }
5767
5768 default:
5769 {
5770 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5771
5772 /* Process Unlocked */
5773 __HAL_UNLOCK(hhrtim);
5774
5775 break;
5776 }
5777 }
5778
5779 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5780 {
5781 return HAL_ERROR;
5782 }
5783
5784 hhrtim->State = HAL_HRTIM_STATE_READY;
5785
5786 /* Process Unlocked */
5787 __HAL_UNLOCK(hhrtim);
5788
5789 return HAL_OK;
5790 }
5791
5792 /**
5793 * @brief Configure the compare unit of a timer operating in waveform mode
5794 * @param hhrtim pointer to HAL HRTIM handle
5795 * @param TimerIdx Timer index
5796 * This parameter can be one of the following values:
5797 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5798 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5799 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5800 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5801 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5802 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5803 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5804 * @param CompareUnit Compare unit to configure
5805 * This parameter can be one of the following values:
5806 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
5807 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
5808 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
5809 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
5810 * @param pCompareCfg pointer to the compare unit configuration structure
5811 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
5812 * application has to configure separately the capture unit. Capture unit
5813 * to configure in that case depends on the compare unit auto delayed mode
5814 * is applied to (see below):
5815 * Auto delayed on output compare 2: capture unit 1 must be configured
5816 * Auto delayed on output compare 4: capture unit 2 must be configured
5817 * @retval HAL status
5818 * @note This function must be called before starting the timer
5819 */
HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CompareUnit,HRTIM_CompareCfgTypeDef * pCompareCfg)5820 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
5821 uint32_t TimerIdx,
5822 uint32_t CompareUnit,
5823 HRTIM_CompareCfgTypeDef* pCompareCfg)
5824 {
5825 /* Check parameters */
5826 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5827
5828 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5829 {
5830 return HAL_BUSY;
5831 }
5832
5833 /* Process Locked */
5834 __HAL_LOCK(hhrtim);
5835
5836 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5837
5838 /* Configure the compare unit */
5839 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
5840 {
5841 switch (CompareUnit)
5842 {
5843 case HRTIM_COMPAREUNIT_1:
5844 {
5845 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
5846 break;
5847 }
5848
5849 case HRTIM_COMPAREUNIT_2:
5850 {
5851 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
5852 break;
5853 }
5854
5855 case HRTIM_COMPAREUNIT_3:
5856 {
5857 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
5858 break;
5859 }
5860
5861 case HRTIM_COMPAREUNIT_4:
5862 {
5863 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
5864 break;
5865 }
5866
5867 default:
5868 {
5869 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5870
5871 /* Process Unlocked */
5872 __HAL_UNLOCK(hhrtim);
5873
5874 break;
5875 }
5876 }
5877
5878 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5879 {
5880 return HAL_ERROR;
5881 }
5882
5883 }
5884 else
5885 {
5886 switch (CompareUnit)
5887 {
5888 case HRTIM_COMPAREUNIT_1:
5889 {
5890 /* Set the compare value */
5891 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
5892 break;
5893 }
5894
5895 case HRTIM_COMPAREUNIT_2:
5896 {
5897 /* Check parameters */
5898 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
5899
5900 /* Set the compare value */
5901 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
5902
5903 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
5904 {
5905 /* Configure auto-delayed mode */
5906 /* DELCMP2 bitfield must be reset when reprogrammed from one value */
5907 /* to the other to reinitialize properly the auto-delayed mechanism */
5908 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
5909 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
5910
5911 /* Set the compare value for timeout compare unit (if any) */
5912 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
5913 {
5914 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
5915 }
5916 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
5917 {
5918 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
5919 }
5920 else
5921 {
5922 /* nothing to do */
5923 }
5924 }
5925 else
5926 {
5927 /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
5928 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
5929 }
5930 break;
5931 }
5932
5933 case HRTIM_COMPAREUNIT_3:
5934 {
5935 /* Set the compare value */
5936 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
5937 break;
5938 }
5939
5940 case HRTIM_COMPAREUNIT_4:
5941 {
5942 /* Check parameters */
5943 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
5944
5945 /* Set the compare value */
5946 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
5947
5948 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
5949 {
5950 /* Configure auto-delayed mode */
5951 /* DELCMP4 bitfield must be reset when reprogrammed from one value */
5952 /* to the other to reinitialize properly the auto-delayed mechanism */
5953 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
5954 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
5955
5956 /* Set the compare value for timeout compare unit (if any) */
5957 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
5958 {
5959 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
5960 }
5961 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
5962 {
5963 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
5964 }
5965 else
5966 {
5967 /* nothing to do */
5968 }
5969 }
5970 else
5971 {
5972 /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
5973 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
5974 }
5975 break;
5976 }
5977
5978 default:
5979 {
5980 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5981
5982 /* Process Unlocked */
5983 __HAL_UNLOCK(hhrtim);
5984
5985 break;
5986 }
5987 }
5988
5989 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5990 {
5991 return HAL_ERROR;
5992 }
5993
5994 }
5995 hhrtim->State = HAL_HRTIM_STATE_READY;
5996
5997 /* Process Unlocked */
5998 __HAL_UNLOCK(hhrtim);
5999
6000 return HAL_OK;
6001 }
6002
6003 /**
6004 * @brief Configure the capture unit of a timer operating in waveform mode
6005 * @param hhrtim pointer to HAL HRTIM handle
6006 * @param TimerIdx Timer index
6007 * This parameter can be one of the following values:
6008 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6009 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6010 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6011 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6012 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6013 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6014 * @param CaptureUnit Capture unit to configure
6015 * This parameter can be one of the following values:
6016 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
6017 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
6018 * @param pCaptureCfg pointer to the compare unit configuration structure
6019 * @retval HAL status
6020 * @note This function must be called before starting the timer
6021 */
HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,HRTIM_CaptureCfgTypeDef * pCaptureCfg)6022 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
6023 uint32_t TimerIdx,
6024 uint32_t CaptureUnit,
6025 HRTIM_CaptureCfgTypeDef* pCaptureCfg)
6026 {
6027 uint32_t Trigger;
6028 uint32_t TimerF_Trigger = (uint32_t)(pCaptureCfg->Trigger >> 32);
6029
6030 /* Check parameters */
6031 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, (uint32_t)(pCaptureCfg->Trigger)));
6032 assert_param(IS_HRTIM_TIMER_CAPTUREFTRIGGER(TimerIdx, TimerF_Trigger));
6033 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6034
6035 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6036 {
6037 return HAL_BUSY;
6038 }
6039
6040 /* Process Locked */
6041 __HAL_LOCK(hhrtim);
6042
6043 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6044
6045 /* TimerF_Trigger is valid for setting other Timers than Timer F */
6046 if (TimerIdx == HRTIM_TIMERINDEX_TIMER_A)
6047 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFF0FFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TA1SET_Pos ); }
6048 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_B)
6049 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFF0FFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TB1SET_Pos ); }
6050 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_C)
6051 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFF0FFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TC1SET_Pos ); }
6052 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_D)
6053 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xF0FFFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TD1SET_Pos ); }
6054 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_E)
6055 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0x0FFFFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TE1SET_Pos ); }
6056 else
6057 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFFFFFFU); }
6058 /* for setting source capture on Timer F, use Trigger only (all bits are valid then) */
6059
6060 /* Configure the capture unit */
6061
6062 switch (CaptureUnit)
6063 {
6064 case HRTIM_CAPTUREUNIT_1:
6065 {
6066 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, Trigger);
6067 break;
6068 }
6069
6070 case HRTIM_CAPTUREUNIT_2:
6071 {
6072 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, Trigger);
6073 break;
6074 }
6075
6076 default:
6077 {
6078 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6079
6080 /* Process Unlocked */
6081 __HAL_UNLOCK(hhrtim);
6082
6083 break;
6084 }
6085 }
6086
6087 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
6088 {
6089 return HAL_ERROR;
6090 }
6091
6092
6093 hhrtim->State = HAL_HRTIM_STATE_READY;
6094
6095 /* Process Unlocked */
6096 __HAL_UNLOCK(hhrtim);
6097
6098 return HAL_OK;
6099 }
6100
6101 /**
6102 * @brief Configure the output of a timer operating in waveform mode
6103 * @param hhrtim pointer to HAL HRTIM handle
6104 * @param TimerIdx Timer index
6105 * This parameter can be one of the following values:
6106 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6107 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6108 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6109 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6110 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6111 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6112 * @param Output Timer output
6113 * This parameter can be one of the following values:
6114 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6115 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6116 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6117 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6118 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6119 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6120 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6121 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6122 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6123 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6124 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6125 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6126 * @param pOutputCfg pointer to the timer output configuration structure
6127 * @retval HAL status
6128 * @note This function must be called before configuring the timer and after
6129 * configuring the deadtime insertion feature (if required).
6130 */
HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,HRTIM_OutputCfgTypeDef * pOutputCfg)6131 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
6132 uint32_t TimerIdx,
6133 uint32_t Output,
6134 HRTIM_OutputCfgTypeDef * pOutputCfg)
6135 {
6136 /* Check parameters */
6137 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6138 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
6139 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
6140 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
6141 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
6142 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
6143 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
6144
6145 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6146 {
6147 return HAL_BUSY;
6148 }
6149
6150 /* Process Locked */
6151 __HAL_LOCK(hhrtim);
6152
6153 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6154
6155 /* Configure the timer output */
6156 HRTIM_OutputConfig(hhrtim,
6157 TimerIdx,
6158 Output,
6159 pOutputCfg);
6160
6161 hhrtim->State = HAL_HRTIM_STATE_READY;
6162
6163 /* Process Unlocked */
6164 __HAL_UNLOCK(hhrtim);
6165
6166 return HAL_OK;
6167 }
6168
6169 /**
6170 * @brief Force the timer output to its active or inactive state
6171 * @param hhrtim pointer to HAL HRTIM handle
6172 * @param TimerIdx Timer index
6173 * This parameter can be one of the following values:
6174 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6175 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6176 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6177 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6178 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6179 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6180 * @param Output Timer output
6181 * This parameter can be one of the following values:
6182 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6183 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6184 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6185 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6186 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6187 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6188 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6189 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6190 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6191 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6192 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6193 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6194 * @param OutputLevel indicates whether the output is forced to its active or inactive level
6195 * This parameter can be one of the following values:
6196 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
6197 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
6198 * @retval HAL status
6199 * @note The 'software set/reset trigger' bit in the output set/reset registers
6200 * is automatically reset by hardware
6201 */
HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,uint32_t OutputLevel)6202 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
6203 uint32_t TimerIdx,
6204 uint32_t Output,
6205 uint32_t OutputLevel)
6206 {
6207 /* Check parameters */
6208 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6209 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
6210
6211 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6212 {
6213 return HAL_BUSY;
6214 }
6215
6216 /* Process Locked */
6217 __HAL_LOCK(hhrtim);
6218
6219 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6220
6221 /* Force timer output level */
6222 switch (Output)
6223 {
6224 case HRTIM_OUTPUT_TA1:
6225 case HRTIM_OUTPUT_TB1:
6226 case HRTIM_OUTPUT_TC1:
6227 case HRTIM_OUTPUT_TD1:
6228 case HRTIM_OUTPUT_TE1:
6229 case HRTIM_OUTPUT_TF1:
6230 {
6231 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
6232 {
6233 /* Force output to its active state */
6234 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST);
6235 }
6236 else
6237 {
6238 /* Force output to its inactive state */
6239 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
6240 }
6241 break;
6242 }
6243
6244 case HRTIM_OUTPUT_TA2:
6245 case HRTIM_OUTPUT_TB2:
6246 case HRTIM_OUTPUT_TC2:
6247 case HRTIM_OUTPUT_TD2:
6248 case HRTIM_OUTPUT_TE2:
6249 case HRTIM_OUTPUT_TF2:
6250 {
6251 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
6252 {
6253 /* Force output to its active state */
6254 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
6255 }
6256 else
6257 {
6258 /* Force output to its inactive state */
6259 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
6260 }
6261 break;
6262 }
6263
6264 default:
6265 {
6266 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6267
6268 /* Process Unlocked */
6269 __HAL_UNLOCK(hhrtim);
6270
6271 break;
6272 }
6273 }
6274
6275 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
6276 {
6277 return HAL_ERROR;
6278 }
6279
6280 hhrtim->State = HAL_HRTIM_STATE_READY;
6281
6282 /* Process Unlocked */
6283 __HAL_UNLOCK(hhrtim);
6284
6285 return HAL_OK;
6286 }
6287
6288 /**
6289 * @brief Enable the generation of the waveform signal on the designated output(s)
6290 * Outputs can be combined (ORed) to allow for simultaneous output enabling.
6291 * @param hhrtim pointer to HAL HRTIM handle
6292 * @param OutputsToStart Timer output(s) to enable
6293 * This parameter can be any combination of the following values:
6294 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6295 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6296 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6297 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6298 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6299 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6300 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6301 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6302 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6303 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6304 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6305 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6306 * @retval HAL status
6307 */
HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStart)6308 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
6309 uint32_t OutputsToStart)
6310 {
6311 /* Check the parameters */
6312 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
6313
6314 /* Process Locked */
6315 __HAL_LOCK(hhrtim);
6316
6317 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6318
6319 /* Enable the HRTIM outputs */
6320 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
6321
6322 hhrtim->State = HAL_HRTIM_STATE_READY;
6323
6324 /* Process Unlocked */
6325 __HAL_UNLOCK(hhrtim);
6326
6327 return HAL_OK;
6328 }
6329
6330 /**
6331 * @brief Disable the generation of the waveform signal on the designated output(s)
6332 * Outputs can be combined (ORed) to allow for simultaneous output disabling.
6333 * @param hhrtim pointer to HAL HRTIM handle
6334 * @param OutputsToStop Timer output(s) to disable
6335 * This parameter can be any combination of the following values:
6336 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6337 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6338 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6339 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6340 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6341 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6342 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6343 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6344 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6345 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6346 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6347 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6348 * @retval HAL status
6349 */
HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,uint32_t OutputsToStop)6350 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
6351 uint32_t OutputsToStop)
6352 {
6353 /* Check the parameters */
6354 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
6355
6356 /* Process Locked */
6357 __HAL_LOCK(hhrtim);
6358
6359 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6360
6361 /* Enable the HRTIM outputs */
6362 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
6363
6364 hhrtim->State = HAL_HRTIM_STATE_READY;
6365
6366 /* Process Unlocked */
6367 __HAL_UNLOCK(hhrtim);
6368
6369 return HAL_OK;
6370 }
6371
6372 /**
6373 * @brief Start the counter of the designated timer(s) operating in waveform mode
6374 * Timers can be combined (ORed) to allow for simultaneous counter start.
6375 * @param hhrtim pointer to HAL HRTIM handle
6376 * @param Timers Timer counter(s) to start
6377 * This parameter can be any combination of the following values:
6378 * @arg HRTIM_TIMERID_MASTER
6379 * @arg HRTIM_TIMERID_TIMER_A
6380 * @arg HRTIM_TIMERID_TIMER_B
6381 * @arg HRTIM_TIMERID_TIMER_C
6382 * @arg HRTIM_TIMERID_TIMER_D
6383 * @arg HRTIM_TIMERID_TIMER_E
6384 * @arg HRTIM_TIMERID_TIMER_F
6385 * @retval HAL status
6386 */
HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6387 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,
6388 uint32_t Timers)
6389 {
6390 /* Check the parameters */
6391 assert_param(IS_HRTIM_TIMERID(Timers));
6392
6393 /* Process Locked */
6394 __HAL_LOCK(hhrtim);
6395
6396 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6397
6398 /* Enable timer(s) counter */
6399 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
6400
6401 hhrtim->State = HAL_HRTIM_STATE_READY;
6402
6403 /* Process Unlocked */
6404 __HAL_UNLOCK(hhrtim);
6405
6406 return HAL_OK;
6407 }
6408
6409 /**
6410 * @brief Stop the counter of the designated timer(s) operating in waveform mode
6411 * Timers can be combined (ORed) to allow for simultaneous counter stop.
6412 * @param hhrtim pointer to HAL HRTIM handle
6413 * @param Timers Timer counter(s) to stop
6414 * This parameter can be any combination of the following values:
6415 * @arg HRTIM_TIMERID_MASTER
6416 * @arg HRTIM_TIMERID_TIMER_A
6417 * @arg HRTIM_TIMERID_TIMER_B
6418 * @arg HRTIM_TIMERID_TIMER_C
6419 * @arg HRTIM_TIMERID_TIMER_D
6420 * @arg HRTIM_TIMERID_TIMER_E
6421 * @arg HRTIM_TIMERID_TIMER_F
6422 * @retval HAL status
6423 * @note The counter of a timer is stopped only if all timer outputs are disabled
6424 */
HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6425 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,
6426 uint32_t Timers)
6427 {
6428 /* Check the parameters */
6429 assert_param(IS_HRTIM_TIMERID(Timers));
6430
6431 /* Process Locked */
6432 __HAL_LOCK(hhrtim);
6433
6434 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6435
6436 /* Disable timer(s) counter */
6437 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
6438
6439 hhrtim->State = HAL_HRTIM_STATE_READY;
6440
6441 /* Process Unlocked */
6442 __HAL_UNLOCK(hhrtim);
6443
6444 return HAL_OK;
6445 }
6446
6447 /**
6448 * @brief Start the counter of the designated timer(s) operating in waveform mode
6449 * Timers can be combined (ORed) to allow for simultaneous counter start.
6450 * @param hhrtim pointer to HAL HRTIM handle
6451 * @param Timers Timer counter(s) to start
6452 * This parameter can be any combination of the following values:
6453 * @arg HRTIM_TIMERID_MASTER
6454 * @arg HRTIM_TIMERID_TIMER_A
6455 * @arg HRTIM_TIMERID_TIMER_B
6456 * @arg HRTIM_TIMERID_TIMER_C
6457 * @arg HRTIM_TIMERID_TIMER_D
6458 * @arg HRTIM_TIMERID_TIMER_E
6459 * @arg HRTIM_TIMERID_TIMER_F
6460 * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
6461 * to the timers to start are enabled within this function.
6462 * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
6463 * function.
6464 * @retval HAL status
6465 */
HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6466 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,
6467 uint32_t Timers)
6468 {
6469 uint8_t timer_idx;
6470
6471 /* Check the parameters */
6472 assert_param(IS_HRTIM_TIMERID(Timers));
6473
6474 /* Process Locked */
6475 __HAL_LOCK(hhrtim);
6476
6477 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6478
6479 /* Enable HRTIM interrupts (if required) */
6480 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
6481
6482 /* Enable master timer related interrupts (if required) */
6483 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
6484 {
6485 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
6486 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
6487 }
6488
6489 /* Enable timing unit related interrupts (if required) */
6490 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6491 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6492 timer_idx++)
6493 {
6494 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
6495 {
6496 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
6497 timer_idx,
6498 hhrtim->TimerParam[timer_idx].InterruptRequests);
6499 }
6500 }
6501
6502 /* Enable timer(s) counter */
6503 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
6504
6505 hhrtim->State = HAL_HRTIM_STATE_READY;
6506
6507 /* Process Unlocked */
6508 __HAL_UNLOCK(hhrtim);
6509
6510 return HAL_OK;}
6511
6512 /**
6513 * @brief Stop the counter of the designated timer(s) operating in waveform mode
6514 * Timers can be combined (ORed) to allow for simultaneous counter stop.
6515 * @param hhrtim pointer to HAL HRTIM handle
6516 * @param Timers Timer counter(s) to stop
6517 * This parameter can be any combination of the following values:
6518 * @arg HRTIM_TIMERID_MASTER
6519 * @arg HRTIM_TIMERID_TIMER_A
6520 * @arg HRTIM_TIMERID_TIMER_B
6521 * @arg HRTIM_TIMERID_TIMER_C
6522 * @arg HRTIM_TIMERID_TIMER_D
6523 * @arg HRTIM_TIMERID_TIMER_E
6524 * @arg HRTIM_TIMERID_TIMER_F
6525 * @retval HAL status
6526 * @note The counter of a timer is stopped only if all timer outputs are disabled
6527 * @note All enabled timer related interrupts are disabled.
6528 */
HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6529 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,
6530 uint32_t Timers)
6531 {
6532 /* ++ WA */
6533 __IO uint32_t delai = (uint32_t)(0x17FU);
6534 /* -- WA */
6535
6536 uint8_t timer_idx;
6537
6538 /* Check the parameters */
6539 assert_param(IS_HRTIM_TIMERID(Timers));
6540
6541 /* Process Locked */
6542 __HAL_LOCK(hhrtim);
6543
6544 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6545
6546 /* Disable HRTIM interrupts (if required) */
6547 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
6548
6549 /* Disable master timer related interrupts (if required) */
6550 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
6551 {
6552 /* Interrupts enable flag must be cleared one by one */
6553 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
6554 }
6555
6556 /* Disable timing unit related interrupts (if required) */
6557 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6558 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6559 timer_idx++)
6560 {
6561 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
6562 {
6563 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
6564 }
6565 }
6566
6567 /* ++ WA */
6568 do { delai--; } while (delai != 0U);
6569 /* -- WA */
6570
6571 /* Disable timer(s) counter */
6572 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
6573
6574 hhrtim->State = HAL_HRTIM_STATE_READY;
6575
6576 /* Process Unlocked */
6577 __HAL_UNLOCK(hhrtim);
6578
6579 return HAL_OK;
6580 }
6581
6582 /**
6583 * @brief Start the counter of the designated timer(s) operating in waveform mode
6584 * Timers can be combined (ORed) to allow for simultaneous counter start.
6585 * @param hhrtim pointer to HAL HRTIM handle
6586 * @param Timers Timer counter(s) to start
6587 * This parameter can be any combination of the following values:
6588 * @arg HRTIM_TIMERID_MASTER
6589 * @arg HRTIM_TIMERID_TIMER_A
6590 * @arg HRTIM_TIMERID_TIMER_B
6591 * @arg HRTIM_TIMERID_TIMER_C
6592 * @arg HRTIM_TIMERID_TIMER_D
6593 * @arg HRTIM_TIMERID_TIMER_E
6594 * @arg HRTIM_TIMERID_TIMER_F
6595 * @retval HAL status
6596 * @note This function enables the dma request(s) mentioned in the timer
6597 * configuration data structure for every timers to start.
6598 * @note The source memory address, the destination memory address and the
6599 * size of each DMA transfer are specified at timer configuration time
6600 * (see HAL_HRTIM_WaveformTimerConfig)
6601 */
HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6602 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
6603 uint32_t Timers)
6604 {
6605 uint8_t timer_idx;
6606 DMA_HandleTypeDef * hdma;
6607
6608 /* Check the parameters */
6609 assert_param(IS_HRTIM_TIMERID(Timers));
6610
6611 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6612 {
6613 return HAL_BUSY;
6614 }
6615
6616 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6617
6618 /* Process Locked */
6619 __HAL_LOCK(hhrtim);
6620
6621 if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
6622 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
6623 {
6624 /* Set the DMA error callback */
6625 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
6626
6627 /* Set the DMA transfer completed callback */
6628 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
6629
6630 /* Enable the DMA channel */
6631 if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
6632 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
6633 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
6634 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
6635 {
6636 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6637
6638 /* Process Unlocked */
6639 __HAL_UNLOCK(hhrtim);
6640
6641 return HAL_ERROR;
6642 }
6643
6644 /* Enable the timer DMA request */
6645 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
6646 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
6647 }
6648
6649 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6650 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6651 timer_idx++)
6652 {
6653 if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
6654 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
6655 {
6656 /* Get the timer DMA handler */
6657 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
6658
6659 if (hdma == NULL)
6660 {
6661 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6662
6663 /* Process Unlocked */
6664 __HAL_UNLOCK(hhrtim);
6665
6666 return HAL_ERROR;
6667 }
6668
6669 /* Set the DMA error callback */
6670 hdma->XferErrorCallback = HRTIM_DMAError ;
6671
6672 /* Set the DMA transfer completed callback */
6673 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
6674
6675 /* Enable the DMA channel */
6676 if (HAL_DMA_Start_IT(hdma,
6677 hhrtim->TimerParam[timer_idx].DMASrcAddress,
6678 hhrtim->TimerParam[timer_idx].DMADstAddress,
6679 hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
6680 {
6681 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6682
6683 /* Process Unlocked */
6684 __HAL_UNLOCK(hhrtim);
6685
6686 return HAL_ERROR;
6687 }
6688
6689 /* Enable the timer DMA request */
6690 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
6691 timer_idx,
6692 hhrtim->TimerParam[timer_idx].DMARequests);
6693 }
6694 }
6695
6696 /* Enable the timer counter */
6697 __HAL_HRTIM_ENABLE(hhrtim, Timers);
6698
6699 hhrtim->State = HAL_HRTIM_STATE_READY;
6700
6701 /* Process Unlocked */
6702 __HAL_UNLOCK(hhrtim);
6703
6704 return HAL_OK;
6705 }
6706
6707 /**
6708 * @brief Stop the counter of the designated timer(s) operating in waveform mode
6709 * Timers can be combined (ORed) to allow for simultaneous counter stop.
6710 * @param hhrtim pointer to HAL HRTIM handle
6711 * @param Timers Timer counter(s) to stop
6712 * This parameter can be any combination of the following values:
6713 * @arg HRTIM_TIMERID_MASTER
6714 * @arg HRTIM_TIMERID_TIMER_A
6715 * @arg HRTIM_TIMERID_TIMER_B
6716 * @arg HRTIM_TIMERID_TIMER_C
6717 * @arg HRTIM_TIMERID_TIMER_D
6718 * @arg HRTIM_TIMERID_TIMER_E
6719 * @arg HRTIM_TIMERID_TIMER_F
6720 * @retval HAL status
6721 * @note The counter of a timer is stopped only if all timer outputs are disabled
6722 * @note All enabled timer related DMA requests are disabled.
6723 */
HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6724 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,
6725 uint32_t Timers)
6726 {
6727 uint8_t timer_idx;
6728
6729 /* Check the parameters */
6730 assert_param(IS_HRTIM_TIMERID(Timers));
6731
6732 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6733
6734 if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
6735 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
6736 {
6737 /* Disable the DMA */
6738 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
6739 {
6740 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6741 }
6742 else
6743 {
6744 hhrtim->State = HAL_HRTIM_STATE_READY;
6745 /* Disable the DMA request(s) */
6746 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
6747 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
6748 }
6749 }
6750
6751 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6752 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6753 timer_idx++)
6754 {
6755 if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
6756 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
6757 {
6758 /* Get the timer DMA handler */
6759 /* Disable the DMA */
6760 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
6761 {
6762 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6763 }
6764 else
6765 {
6766 hhrtim->State = HAL_HRTIM_STATE_READY;
6767
6768 /* Disable the DMA request(s) */
6769 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
6770 timer_idx,
6771 hhrtim->TimerParam[timer_idx].DMARequests);
6772 }
6773 }
6774 }
6775
6776 /* Disable the timer counter */
6777 __HAL_HRTIM_DISABLE(hhrtim, Timers);
6778
6779 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
6780 {
6781 return HAL_ERROR;
6782 }
6783 else
6784 {
6785 return HAL_OK;
6786 }
6787 }
6788
6789 /**
6790 * @brief Enable or disables the HRTIM burst mode controller.
6791 * @param hhrtim pointer to HAL HRTIM handle
6792 * @param Enable Burst mode controller enabling
6793 * This parameter can be one of the following values:
6794 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
6795 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
6796 * @retval HAL status
6797 * @note This function must be called after starting the timer(s)
6798 */
HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,uint32_t Enable)6799 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
6800 uint32_t Enable)
6801 {
6802 /* Check parameters */
6803 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
6804
6805 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6806 {
6807 return HAL_BUSY;
6808 }
6809
6810 /* Process Locked */
6811 __HAL_LOCK(hhrtim);
6812
6813 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6814
6815 /* Enable/Disable the burst mode controller */
6816 MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
6817
6818 hhrtim->State = HAL_HRTIM_STATE_READY;
6819
6820 /* Process Unlocked */
6821 __HAL_UNLOCK(hhrtim);
6822
6823 return HAL_OK;
6824 }
6825
6826 /**
6827 * @brief Trig the burst mode operation.
6828 * @param hhrtim pointer to HAL HRTIM handle
6829 * @retval HAL status
6830 */
HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef * hhrtim)6831 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
6832 {
6833 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6834 {
6835 return HAL_BUSY;
6836 }
6837
6838 /* Process Locked */
6839 __HAL_LOCK(hhrtim);
6840
6841 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6842
6843 /* Software trigger of the burst mode controller */
6844 SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
6845
6846 hhrtim->State = HAL_HRTIM_STATE_READY;
6847
6848 /* Process Unlocked */
6849 __HAL_UNLOCK(hhrtim);
6850
6851 return HAL_OK;
6852 }
6853
6854 /**
6855 * @brief Trig a software capture on the designed capture unit
6856 * @param hhrtim pointer to HAL HRTIM handle
6857 * @param TimerIdx Timer index
6858 * This parameter can be one of the following values:
6859 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6860 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6861 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6862 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6863 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6864 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6865 * @param CaptureUnit Capture unit to trig
6866 * This parameter can be one of the following values:
6867 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
6868 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
6869 * @retval HAL status
6870 * @note The 'software capture' bit in the capure configuration register is
6871 * automatically reset by hardware
6872 */
HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)6873 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
6874 uint32_t TimerIdx,
6875 uint32_t CaptureUnit)
6876 {
6877 /* Check parameters */
6878 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6879 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
6880
6881 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6882 {
6883 return HAL_BUSY;
6884 }
6885
6886 /* Process Locked */
6887 __HAL_LOCK(hhrtim);
6888
6889 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6890
6891 /* Force a software capture on concerned capture unit */
6892 switch (CaptureUnit)
6893 {
6894 case HRTIM_CAPTUREUNIT_1:
6895 {
6896 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
6897 break;
6898 }
6899
6900 case HRTIM_CAPTUREUNIT_2:
6901 {
6902 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
6903 break;
6904 }
6905
6906 default:
6907 {
6908 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6909
6910 /* Process Unlocked */
6911 __HAL_UNLOCK(hhrtim);
6912
6913 break;
6914 }
6915 }
6916
6917 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
6918 {
6919 return HAL_ERROR;
6920 }
6921
6922 hhrtim->State = HAL_HRTIM_STATE_READY;
6923
6924 /* Process Unlocked */
6925 __HAL_UNLOCK(hhrtim);
6926
6927 return HAL_OK;
6928 }
6929
6930 /**
6931 * @brief Trig the update of the registers of one or several timers
6932 * @param hhrtim pointer to HAL HRTIM handle
6933 * @param Timers timers concerned with the software register update
6934 * This parameter can be any combination of the following values:
6935 * @arg HRTIM_TIMERUPDATE_MASTER
6936 * @arg HRTIM_TIMERUPDATE_A
6937 * @arg HRTIM_TIMERUPDATE_B
6938 * @arg HRTIM_TIMERUPDATE_C
6939 * @arg HRTIM_TIMERUPDATE_D
6940 * @arg HRTIM_TIMERUPDATE_E
6941 * @arg HRTIM_TIMERUPDATE_F
6942 * @retval HAL status
6943 * @note The 'software update' bits in the HRTIM control register 2 register are
6944 * automatically reset by hardware
6945 */
HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6946 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
6947 uint32_t Timers)
6948 {
6949 /* Check parameters */
6950 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
6951
6952 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6953 {
6954 return HAL_BUSY;
6955 }
6956
6957 /* Process Locked */
6958 __HAL_LOCK(hhrtim);
6959
6960 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6961
6962 /* Force timer(s) registers update */
6963 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
6964
6965 hhrtim->State = HAL_HRTIM_STATE_READY;
6966
6967 /* Process Unlocked */
6968 __HAL_UNLOCK(hhrtim);
6969
6970 return HAL_OK;
6971 }
6972
6973 /**
6974 * @brief Swap the Timer outputs
6975 * @param hhrtim pointer to HAL HRTIM handle
6976 * @param Timers timers concerned with the software register update
6977 * This parameter can be any combination of the following values:
6978 * @arg HRTIM_TIMERSWAP_A
6979 * @arg HRTIM_TIMERSWAP_B
6980 * @arg HRTIM_TIMERSWAP_C
6981 * @arg HRTIM_TIMERSWAP_D
6982 * @arg HRTIM_TIMERSWAP_E
6983 * @arg HRTIM_TIMERSWAP_F
6984 * @retval HAL status
6985 * @note The function is not significant when the Push-pull mode is enabled (PSHPLL = 1)
6986 */
HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)6987 HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim,
6988 uint32_t Timers)
6989 {
6990 /* Check parameters */
6991 assert_param(IS_HRTIM_TIMERSWAP(Timers));
6992
6993 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6994 {
6995 return HAL_BUSY;
6996 }
6997
6998 /* Process Locked */
6999 __HAL_LOCK(hhrtim);
7000
7001 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7002
7003 /* Force timer(s) registers update */
7004 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
7005
7006 hhrtim->State = HAL_HRTIM_STATE_READY;
7007
7008 /* Process Unlocked */
7009 __HAL_UNLOCK(hhrtim);
7010
7011 return HAL_OK;
7012 }
7013
7014 /**
7015 * @brief Trig the reset of one or several timers
7016 * @param hhrtim pointer to HAL HRTIM handle
7017 * @param Timers timers concerned with the software counter reset
7018 * This parameter can be any combination of the following values:
7019 * @arg HRTIM_TIMERRESET_MASTER
7020 * @arg HRTIM_TIMERRESET_TIMER_A
7021 * @arg HRTIM_TIMERRESET_TIMER_B
7022 * @arg HRTIM_TIMERRESET_TIMER_C
7023 * @arg HRTIM_TIMERRESET_TIMER_D
7024 * @arg HRTIM_TIMERRESET_TIMER_E
7025 * @arg HRTIM_TIMERRESET_TIMER_F
7026 * @retval HAL status
7027 * @note The 'software reset' bits in the HRTIM control register 2 are
7028 * automatically reset by hardware
7029 */
HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7030 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
7031 uint32_t Timers)
7032 {
7033 /* Check parameters */
7034 assert_param(IS_HRTIM_TIMERRESET(Timers));
7035
7036 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
7037 {
7038 return HAL_BUSY;
7039 }
7040
7041 /* Process Locked */
7042 __HAL_LOCK(hhrtim);
7043
7044 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7045
7046 /* Force timer(s) registers reset */
7047 hhrtim->Instance->sCommonRegs.CR2 = Timers;
7048
7049 hhrtim->State = HAL_HRTIM_STATE_READY;
7050
7051 /* Process Unlocked */
7052 __HAL_UNLOCK(hhrtim);
7053
7054 return HAL_OK;
7055 }
7056
7057 /**
7058 * @brief Swap the output of one or several timers
7059 * @param hhrtim: pointer to HAL HRTIM handle
7060 * @param Timers: timers concerned with the software register update
7061 * This parameter can be any combination of the following values:
7062 * @arg HRTIM_TIMERSWAP_A
7063 * @arg HRTIM_TIMERSWAP_B
7064 * @arg HRTIM_TIMERSWAP_C
7065 * @arg HRTIM_TIMERSWAP_D
7066 * @arg HRTIM_TIMERSWAP_E
7067 * @arg HRTIM_TIMERSWAP_F
7068 * @retval HAL status
7069 */
HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7070 HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim,
7071 uint32_t Timers)
7072 {
7073 /* Check parameters */
7074 assert_param(IS_HRTIM_TIMERSWAP(Timers));
7075
7076 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
7077 {
7078 return HAL_BUSY;
7079 }
7080
7081 /* Process Locked */
7082 __HAL_LOCK(hhrtim);
7083
7084 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7085
7086 /* Force timer(s) registers update */
7087 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
7088
7089 hhrtim->State = HAL_HRTIM_STATE_READY;
7090
7091 /* Process Unlocked */
7092 __HAL_UNLOCK(hhrtim);
7093
7094 return HAL_OK;
7095 }
7096
7097 /**
7098 * @brief Un-swap the output of one or several timers
7099 * @param hhrtim: pointer to HAL HRTIM handle
7100 * @param Timers: timers concerned with the software register update
7101 * This parameter can be any combination of the following values:
7102 * @arg HRTIM_TIMERSWAP_A
7103 * @arg HRTIM_TIMERSWAP_B
7104 * @arg HRTIM_TIMERSWAP_C
7105 * @arg HRTIM_TIMERSWAP_D
7106 * @arg HRTIM_TIMERSWAP_E
7107 * @arg HRTIM_TIMERSWAP_F
7108 * @retval HAL status
7109 */
HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7110 HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim,
7111 uint32_t Timers)
7112 {
7113 /* Check parameters */
7114 assert_param(IS_HRTIM_TIMERSWAP(Timers));
7115
7116 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
7117 {
7118 return HAL_BUSY;
7119 }
7120
7121 /* Process Locked */
7122 __HAL_LOCK(hhrtim);
7123
7124 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7125
7126 /* Force timer(s) registers update */
7127 hhrtim->Instance->sCommonRegs.CR2 &= ~(Timers);
7128
7129 hhrtim->State = HAL_HRTIM_STATE_READY;
7130
7131 /* Process Unlocked */
7132 __HAL_UNLOCK(hhrtim);
7133
7134 return HAL_OK;
7135 }
7136
7137 /**
7138 * @brief Start a burst DMA operation to update HRTIM control registers content
7139 * @param hhrtim pointer to HAL HRTIM handle
7140 * @param TimerIdx Timer index
7141 * This parameter can be one of the following values:
7142 * @arg HRTIM_TIMERINDEX_MASTER for master timer
7143 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7144 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7145 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7146 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7147 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7148 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7149 * @param BurstBufferAddress address of the buffer the HRTIM control registers
7150 * content will be updated from.
7151 * @param BurstBufferLength size (in WORDS) of the burst buffer.
7152 * @retval HAL status
7153 * @note The TimerIdx parameter determines the dma channel to be used by the
7154 * DMA burst controller (see below)
7155 * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
7156 * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
7157 * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
7158 * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
7159 * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
7160 * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
7161 * HRTIM_TIMERINDEX_TIMER_F: DMA channel 8 is used by the DMA burst controller
7162 */
HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t BurstBufferAddress,uint32_t BurstBufferLength)7163 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
7164 uint32_t TimerIdx,
7165 uint32_t BurstBufferAddress,
7166 uint32_t BurstBufferLength)
7167 {
7168 DMA_HandleTypeDef * hdma;
7169
7170 /* Check the parameters */
7171 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
7172
7173 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
7174 {
7175 return HAL_BUSY;
7176 }
7177 if(hhrtim->State == HAL_HRTIM_STATE_READY)
7178 {
7179 if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
7180 {
7181 return HAL_ERROR;
7182 }
7183 else
7184 {
7185 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7186 }
7187 }
7188
7189 /* Process Locked */
7190 __HAL_LOCK(hhrtim);
7191
7192 /* Get the timer DMA handler */
7193 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
7194
7195 if (hdma == NULL)
7196 {
7197 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7198
7199 /* Process Unlocked */
7200 __HAL_UNLOCK(hhrtim);
7201
7202 return HAL_ERROR;
7203 }
7204
7205 /* Set the DMA transfer completed callback */
7206 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
7207
7208 /* Set the DMA error callback */
7209 hdma->XferErrorCallback = HRTIM_DMAError ;
7210
7211 /* Enable the DMA channel */
7212 if (HAL_DMA_Start_IT(hdma,
7213 BurstBufferAddress,
7214 (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
7215 BurstBufferLength) != HAL_OK)
7216 {
7217 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7218
7219 /* Process Unlocked */
7220 __HAL_UNLOCK(hhrtim);
7221
7222 return HAL_ERROR;
7223 }
7224
7225 hhrtim->State = HAL_HRTIM_STATE_READY;
7226
7227 /* Process Unlocked */
7228 __HAL_UNLOCK(hhrtim);
7229
7230 return HAL_OK;
7231 }
7232
7233 /**
7234 * @brief Enable the transfer from preload to active registers for one
7235 * or several timing units (including master timer).
7236 * @param hhrtim pointer to HAL HRTIM handle
7237 * @param Timers Timer(s) concerned by the register preload enabling command
7238 * This parameter can be any combination of the following values:
7239 * @arg HRTIM_TIMERUPDATE_MASTER
7240 * @arg HRTIM_TIMERUPDATE_A
7241 * @arg HRTIM_TIMERUPDATE_B
7242 * @arg HRTIM_TIMERUPDATE_C
7243 * @arg HRTIM_TIMERUPDATE_D
7244 * @arg HRTIM_TIMERUPDATE_E
7245 * @arg HRTIM_TIMERUPDATE_E
7246 * @retval HAL status
7247 */
HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7248 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
7249 uint32_t Timers)
7250 {
7251 /* Check the parameters */
7252 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
7253
7254 /* Process Locked */
7255 __HAL_LOCK(hhrtim);
7256
7257 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7258
7259 /* Enable timer(s) registers update */
7260 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
7261
7262 hhrtim->State = HAL_HRTIM_STATE_READY;
7263
7264 /* Process Unlocked */
7265 __HAL_UNLOCK(hhrtim);
7266
7267 return HAL_OK;
7268 }
7269
7270 /**
7271 * @brief Disable the transfer from preload to active registers for one
7272 * or several timing units (including master timer).
7273 * @param hhrtim pointer to HAL HRTIM handle
7274 * @param Timers Timer(s) concerned by the register preload disabling command
7275 * This parameter can be any combination of the following values:
7276 * @arg HRTIM_TIMERUPDATE_MASTER
7277 * @arg HRTIM_TIMERUPDATE_A
7278 * @arg HRTIM_TIMERUPDATE_B
7279 * @arg HRTIM_TIMERUPDATE_C
7280 * @arg HRTIM_TIMERUPDATE_D
7281 * @arg HRTIM_TIMERUPDATE_E
7282 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7283 * @retval HAL status
7284 */
HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef * hhrtim,uint32_t Timers)7285 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
7286 uint32_t Timers)
7287 {
7288 /* Check the parameters */
7289 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
7290
7291 /* Process Locked */
7292 __HAL_LOCK(hhrtim);
7293
7294 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7295
7296 /* Enable timer(s) registers update */
7297 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
7298
7299 hhrtim->State = HAL_HRTIM_STATE_READY;
7300
7301 /* Process Unlocked */
7302 __HAL_UNLOCK(hhrtim);
7303
7304 return HAL_OK;
7305 }
7306
7307 /**
7308 * @}
7309 */
7310
7311 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
7312 * @brief Peripheral State functions
7313 @verbatim
7314 ===============================================================================
7315 ##### Peripheral State functions #####
7316 ===============================================================================
7317 [..] This section provides functions used to get HRTIM or HRTIM timer
7318 specific information:
7319 (+) Get HRTIM HAL state
7320 (+) Get captured value
7321 (+) Get HRTIM timer output level
7322 (+) Get HRTIM timer output state
7323 (+) Get delayed protection status
7324 (+) Get burst status
7325 (+) Get current push-pull status
7326 (+) Get idle push-pull status
7327
7328 @endverbatim
7329 * @{
7330 */
7331
7332 /**
7333 * @brief Return the HRTIM HAL state
7334 * @param hhrtim pointer to HAL HRTIM handle
7335 * @retval HAL state
7336 */
HAL_HRTIM_GetState(HRTIM_HandleTypeDef * hhrtim)7337 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
7338 {
7339 /* Return HRTIM state */
7340 return hhrtim->State;
7341 }
7342
7343 /**
7344 * @brief Return actual value of the capture register of the designated capture unit
7345 * @param hhrtim pointer to HAL HRTIM handle
7346 * @param TimerIdx Timer index
7347 * This parameter can be one of the following values:
7348 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7349 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7350 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7351 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7352 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7353 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7354 * @param CaptureUnit Capture unit to trig
7355 * This parameter can be one of the following values:
7356 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
7357 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
7358 * @retval Captured value
7359 */
HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)7360 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
7361 uint32_t TimerIdx,
7362 uint32_t CaptureUnit)
7363 {
7364 uint32_t captured_value;
7365
7366 /* Check parameters */
7367 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7368 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
7369
7370 /* Read captured value */
7371 switch (CaptureUnit)
7372 {
7373 case HRTIM_CAPTUREUNIT_1:
7374 {
7375 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & 0x0000FFFFU;
7376 break;
7377 }
7378
7379 case HRTIM_CAPTUREUNIT_2:
7380 {
7381 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & 0x0000FFFFU;
7382 break;
7383 }
7384
7385 default:
7386 {
7387 captured_value = 0xFFFFFFFFUL;
7388
7389 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7390
7391 /* Process Unlocked */
7392 __HAL_UNLOCK(hhrtim);
7393 break;
7394 }
7395
7396 }
7397
7398 return captured_value;
7399 }
7400
7401 /**
7402 * @brief Return actual value and direction of the capture register of the designated capture unit
7403 * @param hhrtim pointer to HAL HRTIM handle
7404 * @param TimerIdx Timer index
7405 * This parameter can be one of the following values:
7406 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7407 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7408 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7409 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7410 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7411 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7412 * @param CaptureUnit Capture unit to trig
7413 * This parameter can be one of the following values:
7414 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
7415 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
7416 * @retval captured value and direction structure
7417 */
HAL_HRTIM_GetCaptured(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)7418 HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(HRTIM_HandleTypeDef * hhrtim,
7419 uint32_t TimerIdx,
7420 uint32_t CaptureUnit)
7421 {
7422 uint32_t tmp;
7423 HRTIM_CaptureValueTypeDef captured;
7424
7425 /* Check parameters */
7426 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7427 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
7428
7429 /* Read captured value */
7430 switch (CaptureUnit)
7431 {
7432 case HRTIM_CAPTUREUNIT_1:
7433 tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
7434 captured.Value = tmp & HRTIM_CPT1R_CPT1R & 0x0000FFFFU;
7435 captured.Dir = (((tmp & HRTIM_CPT1R_DIR) == HRTIM_CPT1R_DIR)?1U:0U);
7436 break;
7437 case HRTIM_CAPTUREUNIT_2:
7438 tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
7439 captured.Value = tmp & HRTIM_CPT2R_CPT2R & 0x0000FFFFU;
7440 captured.Dir = (((tmp & HRTIM_CPT2R_DIR ) == HRTIM_CPT2R_DIR)?1U:0U);
7441 break;
7442 default:
7443 captured.Value = 0xFFFFFFFFUL;
7444 captured.Dir = 0xFFFFFFFFUL;
7445 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7446
7447 /* Process Unlocked */
7448 __HAL_UNLOCK(hhrtim);
7449 break;
7450 }
7451
7452 return captured;
7453 }
7454
7455 /**
7456 * @brief Return actual direction of the capture register of the designated capture unit
7457 * @param hhrtim pointer to HAL HRTIM handle
7458 * @param TimerIdx Timer index
7459 * This parameter can be one of the following values:
7460 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7461 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7462 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7463 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7464 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7465 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7466 * @param CaptureUnit Capture unit to trig
7467 * This parameter can be one of the following values:
7468 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
7469 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
7470 * @retval captured direction
7471 * @arg This parameter is one HRTIM_Timer_UpDown_Mode :
7472 * @arg HRTIM_TIMERUPDOWNMODE_UP
7473 * @arg HRTIM_TIMERUPDOWNMODE_UPDOWN
7474 */
HAL_HRTIM_GetCapturedDir(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit)7475 uint32_t HAL_HRTIM_GetCapturedDir(HRTIM_HandleTypeDef * hhrtim,
7476 uint32_t TimerIdx,
7477 uint32_t CaptureUnit)
7478 {
7479 uint32_t tmp;
7480
7481 /* Check parameters */
7482 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7483 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
7484
7485 /* Read captured value */
7486 switch (CaptureUnit)
7487 {
7488 case HRTIM_CAPTUREUNIT_1:
7489 tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & HRTIM_CPT1R_DIR ) >> HRTIM_CPT1R_DIR_Pos);
7490 break;
7491 case HRTIM_CAPTUREUNIT_2:
7492 tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & HRTIM_CPT2R_DIR ) >> HRTIM_CPT2R_DIR_Pos);
7493 break;
7494 default:
7495 tmp = 0xFFFFFFFFU;
7496 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7497
7498 /* Process Unlocked */
7499 __HAL_UNLOCK(hhrtim);
7500 break;
7501 }
7502
7503 return tmp;
7504 }
7505
7506
7507 /**
7508 * @brief Return actual level (active or inactive) of the designated output
7509 * @param hhrtim pointer to HAL HRTIM handle
7510 * @param TimerIdx Timer index
7511 * This parameter can be one of the following values:
7512 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7513 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7514 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7515 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7516 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7517 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7518 * @param Output Timer output
7519 * This parameter can be one of the following values:
7520 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7521 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7522 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7523 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7524 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7525 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7526 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7527 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7528 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7529 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7530 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
7531 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
7532 * @retval Output level
7533 * @note Returned output level is taken before the output stage (chopper,
7534 * polarity).
7535 */
HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)7536 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
7537 uint32_t TimerIdx,
7538 uint32_t Output)
7539 {
7540 uint32_t output_level = (uint32_t)RESET;
7541
7542 /* Check parameters */
7543 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
7544
7545 /* Read the output level */
7546 switch (Output)
7547 {
7548 case HRTIM_OUTPUT_TA1:
7549 case HRTIM_OUTPUT_TB1:
7550 case HRTIM_OUTPUT_TC1:
7551 case HRTIM_OUTPUT_TD1:
7552 case HRTIM_OUTPUT_TE1:
7553 case HRTIM_OUTPUT_TF1:
7554 {
7555 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
7556 {
7557 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
7558 }
7559 else
7560 {
7561 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
7562 }
7563 break;
7564 }
7565
7566 case HRTIM_OUTPUT_TA2:
7567 case HRTIM_OUTPUT_TB2:
7568 case HRTIM_OUTPUT_TC2:
7569 case HRTIM_OUTPUT_TD2:
7570 case HRTIM_OUTPUT_TE2:
7571 case HRTIM_OUTPUT_TF2:
7572 {
7573 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
7574 {
7575 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
7576 }
7577 else
7578 {
7579 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
7580 }
7581 break;
7582 }
7583
7584 default:
7585 {
7586 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7587
7588 /* Process Unlocked */
7589 __HAL_UNLOCK(hhrtim);
7590
7591 break;
7592 }
7593 }
7594
7595 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
7596 {
7597 return (uint32_t)HAL_ERROR;
7598 }
7599
7600 return output_level;
7601 }
7602
7603 /**
7604 * @brief Return actual state (RUN, IDLE, FAULT) of the designated output
7605 * @param hhrtim pointer to HAL HRTIM handle
7606 * @param TimerIdx Timer index
7607 * This parameter can be one of the following values:
7608 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7609 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7610 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7611 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7612 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7613 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7614 * @param Output Timer output
7615 * This parameter can be one of the following values:
7616 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7617 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7618 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7619 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7620 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7621 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7622 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7623 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7624 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7625 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7626 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
7627 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
7628 * @retval Output state
7629 */
HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)7630 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
7631 uint32_t TimerIdx,
7632 uint32_t Output)
7633 {
7634 uint32_t output_bit = (uint32_t)RESET;
7635 uint32_t output_state;
7636
7637 /* Check parameters */
7638 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
7639
7640 /* Prevent unused argument(s) compilation warning */
7641 UNUSED(TimerIdx);
7642
7643 /* Set output state according to output control status and output disable status */
7644 switch (Output)
7645 {
7646 case HRTIM_OUTPUT_TA1:
7647 {
7648 output_bit = HRTIM_OENR_TA1OEN;
7649 break;
7650 }
7651
7652 case HRTIM_OUTPUT_TA2:
7653 {
7654 output_bit = HRTIM_OENR_TA2OEN;
7655 break;
7656 }
7657
7658 case HRTIM_OUTPUT_TB1:
7659 {
7660 output_bit = HRTIM_OENR_TB1OEN;
7661 break;
7662 }
7663
7664 case HRTIM_OUTPUT_TB2:
7665 {
7666 output_bit = HRTIM_OENR_TB2OEN;
7667 break;
7668 }
7669
7670 case HRTIM_OUTPUT_TC1:
7671 {
7672 output_bit = HRTIM_OENR_TC1OEN;
7673 break;
7674 }
7675
7676 case HRTIM_OUTPUT_TC2:
7677 {
7678 output_bit = HRTIM_OENR_TC2OEN;
7679 break;
7680 }
7681
7682 case HRTIM_OUTPUT_TD1:
7683 {
7684 output_bit = HRTIM_OENR_TD1OEN;
7685 break;
7686 }
7687
7688 case HRTIM_OUTPUT_TD2:
7689 {
7690 output_bit = HRTIM_OENR_TD2OEN;
7691 break;
7692 }
7693
7694 case HRTIM_OUTPUT_TE1:
7695 {
7696 output_bit = HRTIM_OENR_TE1OEN;
7697 break;
7698 }
7699
7700 case HRTIM_OUTPUT_TE2:
7701 {
7702 output_bit = HRTIM_OENR_TE2OEN;
7703 break;
7704 }
7705
7706 case HRTIM_OUTPUT_TF1:
7707 {
7708 output_bit = HRTIM_OENR_TF1OEN;
7709 break;
7710 }
7711
7712 case HRTIM_OUTPUT_TF2:
7713 {
7714 output_bit = HRTIM_OENR_TF2OEN;
7715 break;
7716 }
7717
7718 default:
7719 {
7720 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7721
7722 /* Process Unlocked */
7723 __HAL_UNLOCK(hhrtim);
7724
7725 break;
7726 }
7727 }
7728
7729 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
7730 {
7731 return (uint32_t)HAL_ERROR;
7732 }
7733
7734 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
7735 {
7736 /* Output is enabled: output in RUN state (whatever output disable status is)*/
7737 output_state = HRTIM_OUTPUTSTATE_RUN;
7738 }
7739 else
7740 {
7741 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
7742 {
7743 /* Output is disabled: output in FAULT state */
7744 output_state = HRTIM_OUTPUTSTATE_FAULT;
7745 }
7746 else
7747 {
7748 /* Output is disabled: output in IDLE state */
7749 output_state = HRTIM_OUTPUTSTATE_IDLE;
7750 }
7751 }
7752
7753 return(output_state);
7754 }
7755
7756 /**
7757 * @brief Return the level (active or inactive) of the designated output
7758 * when the delayed protection was triggered.
7759 * @param hhrtim pointer to HAL HRTIM handle
7760 * @param TimerIdx Timer index
7761 * This parameter can be one of the following values:
7762 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7763 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7764 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7765 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7766 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7767 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7768 * @param Output Timer output
7769 * This parameter can be one of the following values:
7770 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7771 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7772 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7773 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7774 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7775 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7776 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7777 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7778 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7779 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7780 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
7781 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
7782 * @retval Delayed protection status
7783 */
HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output)7784 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
7785 uint32_t TimerIdx,
7786 uint32_t Output)
7787 {
7788 uint32_t delayed_protection_status = (uint32_t)RESET;
7789
7790 /* Check parameters */
7791 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
7792
7793 /* Read the delayed protection status */
7794 switch (Output)
7795 {
7796 case HRTIM_OUTPUT_TA1:
7797 case HRTIM_OUTPUT_TB1:
7798 case HRTIM_OUTPUT_TC1:
7799 case HRTIM_OUTPUT_TD1:
7800 case HRTIM_OUTPUT_TE1:
7801 case HRTIM_OUTPUT_TF1:
7802 {
7803 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
7804 {
7805 /* Output 1 was active when the delayed idle protection was triggered */
7806 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
7807 }
7808 else
7809 {
7810 /* Output 1 was inactive when the delayed idle protection was triggered */
7811 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
7812 }
7813 break;
7814 }
7815
7816 case HRTIM_OUTPUT_TA2:
7817 case HRTIM_OUTPUT_TB2:
7818 case HRTIM_OUTPUT_TC2:
7819 case HRTIM_OUTPUT_TD2:
7820 case HRTIM_OUTPUT_TE2:
7821 case HRTIM_OUTPUT_TF2:
7822 {
7823 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
7824 {
7825 /* Output 2 was active when the delayed idle protection was triggered */
7826 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
7827 }
7828 else
7829 {
7830 /* Output 2 was inactive when the delayed idle protection was triggered */
7831 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
7832 }
7833 break;
7834 }
7835
7836 default:
7837 {
7838 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7839
7840 /* Process Unlocked */
7841 __HAL_UNLOCK(hhrtim);
7842
7843 break;
7844 }
7845 }
7846
7847 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
7848 {
7849 return (uint32_t)HAL_ERROR;
7850 }
7851
7852 return delayed_protection_status;
7853 }
7854
7855 /**
7856 * @brief Return the actual status (active or inactive) of the burst mode controller
7857 * @param hhrtim pointer to HAL HRTIM handle
7858 * @retval Burst mode controller status
7859 */
HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)7860 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
7861 {
7862 uint32_t burst_mode_status;
7863
7864 /* Read burst mode status */
7865 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
7866
7867 return burst_mode_status;
7868 }
7869
7870 /**
7871 * @brief Indicate on which output the signal is currently active (when the
7872 * push pull mode is enabled).
7873 * @param hhrtim pointer to HAL HRTIM handle
7874 * @param TimerIdx Timer index
7875 * This parameter can be one of the following values:
7876 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7877 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7878 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7879 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7880 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7881 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7882 * @retval Burst mode controller status
7883 */
HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7884 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
7885 uint32_t TimerIdx)
7886 {
7887 uint32_t current_pushpull_status;
7888
7889 /* Check the parameters */
7890 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7891
7892 /* Read current push pull status */
7893 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
7894
7895 return current_pushpull_status;
7896 }
7897
7898
7899 /**
7900 * @brief Indicate on which output the signal was applied, in push-pull mode,
7901 balanced fault mode or delayed idle mode, when the protection was triggered.
7902 * @param hhrtim pointer to HAL HRTIM handle
7903 * @param TimerIdx Timer index
7904 * This parameter can be one of the following values:
7905 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7906 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7907 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7908 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7909 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7910 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7911 * @retval Idle Push Pull Status
7912 */
HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)7913 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
7914 uint32_t TimerIdx)
7915 {
7916 uint32_t idle_pushpull_status;
7917
7918 /* Check the parameters */
7919 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7920
7921 /* Read current push pull status */
7922 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
7923
7924 return idle_pushpull_status;
7925 }
7926
7927 /**
7928 * @}
7929 */
7930
7931 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
7932 * @brief Functions called when HRTIM generates an interrupt
7933 * 7 interrupts can be generated by the master timer:
7934 * - Master timer registers update
7935 * - Synchronization event received
7936 * - Master timer repetition event
7937 * - Master Compare 1 to 4 event
7938 * 14 interrupts can be generated by each timing unit:
7939 * - Delayed protection triggered
7940 * - Counter reset or roll-over event
7941 * - Output 1 and output 2 reset (transition active to inactive)
7942 * - Output 1 and output 2 set (transition inactive to active)
7943 * - Capture 1 and 2 events
7944 * - Timing unit registers update
7945 * - Repetition event
7946 * - Compare 1 to 4 event
7947 * 8 global interrupts are generated for the whole HRTIM:
7948 * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
7949 * - DLL calibration done
7950 * - Burst mode period completed
7951 @verbatim
7952 ===============================================================================
7953 ##### HRTIM interrupts handling #####
7954 ===============================================================================
7955 [..]
7956 This subsection provides a set of functions allowing to manage the HRTIM
7957 interrupts:
7958 (+) HRTIM interrupt handler
7959 (+) Callback function called when Fault1 interrupt occurs
7960 (+) Callback function called when Fault2 interrupt occurs
7961 (+) Callback function called when Fault3 interrupt occurs
7962 (+) Callback function called when Fault4 interrupt occurs
7963 (+) Callback function called when Fault5 interrupt occurs
7964 (+) Callback function called when Fault6 interrupt occurs
7965 (+) Callback function called when system Fault interrupt occurs
7966 (+) Callback function called when DLL ready interrupt occurs
7967 (+) Callback function called when burst mode period interrupt occurs
7968 (+) Callback function called when synchronization input interrupt occurs
7969 (+) Callback function called when a timer register update interrupt occurs
7970 (+) Callback function called when a timer repetition interrupt occurs
7971 (+) Callback function called when a compare 1 match interrupt occurs
7972 (+) Callback function called when a compare 2 match interrupt occurs
7973 (+) Callback function called when a compare 3 match interrupt occurs
7974 (+) Callback function called when a compare 4 match interrupt occurs
7975 (+) Callback function called when a capture 1 interrupt occurs
7976 (+) Callback function called when a capture 2 interrupt occurs
7977 (+) Callback function called when a delayed protection interrupt occurs
7978 (+) Callback function called when a timer counter reset interrupt occurs
7979 (+) Callback function called when a timer output 1 set interrupt occurs
7980 (+) Callback function called when a timer output 1 reset interrupt occurs
7981 (+) Callback function called when a timer output 2 set interrupt occurs
7982 (+) Callback function called when a timer output 2 reset interrupt occurs
7983 (+) Callback function called when a timer output 2 reset interrupt occurs
7984 (+) Callback function called upon completion of a burst DMA transfer
7985 (+) HRTIM callback function registration
7986 (+) HRTIM callback function unregistration
7987 (+) HRTIM Timer x callback function registration
7988 (+) HRTIM Timer x callback function unregistration
7989
7990 @endverbatim
7991 * @{
7992 */
7993
7994 /**
7995 * @brief This function handles HRTIM interrupt request.
7996 * @param hhrtim pointer to HAL HRTIM handle
7997 * @param TimerIdx Timer index
7998 * This parameter can be any value of HRTIM_Timer_Index
7999 * @retval None
8000 */
HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8001 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
8002 uint32_t TimerIdx)
8003 {
8004 /* HRTIM interrupts handling */
8005 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
8006 {
8007 HRTIM_HRTIM_ISR(hhrtim);
8008 }
8009 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
8010 {
8011 /* Master related interrupts handling */
8012 HRTIM_Master_ISR(hhrtim);
8013 }
8014 else
8015 {
8016 /* Timing unit related interrupts handling */
8017 HRTIM_Timer_ISR(hhrtim, TimerIdx);
8018 }
8019
8020 }
8021
8022 /**
8023 * @brief Callback function invoked when a fault 1 interrupt occurred
8024 * @param hhrtim pointer to HAL HRTIM handle * @retval None
8025 * @retval None
8026 */
HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)8027 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
8028 {
8029 /* Prevent unused argument(s) compilation warning */
8030 UNUSED(hhrtim);
8031
8032 /* NOTE : This function should not be modified, when the callback is needed,
8033 the HAL_HRTIM_Fault1Callback could be implemented in the user file
8034 */
8035 }
8036
8037 /**
8038 * @brief Callback function invoked when a fault 2 interrupt occurred
8039 * @param hhrtim pointer to HAL HRTIM handle
8040 * @retval None
8041 */
HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)8042 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
8043 {
8044 /* Prevent unused argument(s) compilation warning */
8045 UNUSED(hhrtim);
8046
8047 /* NOTE : This function should not be modified, when the callback is needed,
8048 the HAL_HRTIM_Fault2Callback could be implemented in the user file
8049 */
8050 }
8051
8052 /**
8053 * @brief Callback function invoked when a fault 3 interrupt occurred
8054 * @param hhrtim pointer to HAL HRTIM handle
8055 * @retval None
8056 */
HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)8057 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
8058 {
8059 /* Prevent unused argument(s) compilation warning */
8060 UNUSED(hhrtim);
8061
8062 /* NOTE : This function should not be modified, when the callback is needed,
8063 the HAL_HRTIM_Fault3Callback could be implemented in the user file
8064 */
8065 }
8066
8067 /**
8068 * @brief Callback function invoked when a fault 4 interrupt occurred
8069 * @param hhrtim pointer to HAL HRTIM handle
8070 * @retval None
8071 */
HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)8072 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
8073 {
8074 /* Prevent unused argument(s) compilation warning */
8075 UNUSED(hhrtim);
8076
8077 /* NOTE : This function should not be modified, when the callback is needed,
8078 the HAL_HRTIM_Fault4Callback could be implemented in the user file
8079 */
8080 }
8081
8082 /**
8083 * @brief Callback function invoked when a fault 5 interrupt occurred
8084 * @param hhrtim pointer to HAL HRTIM handle
8085 * @retval None
8086 */
HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)8087 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
8088 {
8089 /* Prevent unused argument(s) compilation warning */
8090 UNUSED(hhrtim);
8091
8092 /* NOTE : This function should not be modified, when the callback is needed,
8093 the HAL_HRTIM_Fault5Callback could be implemented in the user file
8094 */
8095 }
8096
8097 /**
8098 * @brief Callback function invoked when a fault 6 interrupt occurred
8099 * @param hhrtim pointer to HAL HRTIM handle
8100 * @retval None
8101 */
HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef * hhrtim)8102 __weak void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef * hhrtim)
8103 {
8104 /* Prevent unused argument(s) compilation warning */
8105 UNUSED(hhrtim);
8106
8107 /* NOTE : This function should not be modified, when the callback is needed,
8108 the HAL_HRTIM_Fault6Callback could be implemented in the user file
8109 */
8110 }
8111
8112 /**
8113 * @brief Callback function invoked when a system fault interrupt occurred
8114 * @param hhrtim pointer to HAL HRTIM handle
8115 * @retval None
8116 */
HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)8117 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
8118 {
8119 /* Prevent unused argument(s) compilation warning */
8120 UNUSED(hhrtim);
8121
8122 /* NOTE : This function should not be modified, when the callback is needed,
8123 the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
8124 */
8125 }
8126
8127 /**
8128 * @brief Callback function invoked when the DLL calibration is completed
8129 * @param hhrtim pointer to HAL HRTIM handle
8130 * @retval None
8131 */
HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)8132 __weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
8133 {
8134 /* Prevent unused argument(s) compilation warning */
8135 UNUSED(hhrtim);
8136
8137 /* NOTE : This function should not be modified, when the callback is needed,
8138 the HAL_HRTIM_DLLCalibrationCallback could be implemented in the user file
8139 */
8140 }
8141
8142 /**
8143 * @brief Callback function invoked when the end of the burst mode period is reached
8144 * @param hhrtim pointer to HAL HRTIM handle
8145 * @retval None
8146 */
HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)8147 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
8148 {
8149 /* Prevent unused argument(s) compilation warning */
8150 UNUSED(hhrtim);
8151
8152 /* NOTE : This function should not be modified, when the callback is needed,
8153 the HAL_HRTIM_BurstModeCallback could be implemented in the user file
8154 */
8155 }
8156
8157 /**
8158 * @brief Callback function invoked when a synchronization input event is received
8159 * @param hhrtim pointer to HAL HRTIM handle
8160 * @retval None
8161 */
HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)8162 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
8163 {
8164 /* Prevent unused argument(s) compilation warning */
8165 UNUSED(hhrtim);
8166
8167 /* NOTE : This function should not be modified, when the callback is needed,
8168 the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
8169 */
8170 }
8171
8172 /**
8173 * @brief Callback function invoked when timer registers are updated
8174 * @param hhrtim pointer to HAL HRTIM handle
8175 * @param TimerIdx Timer index
8176 * This parameter can be one of the following values:
8177 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8178 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8179 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8180 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8181 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8182 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8183 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8184 * @retval None
8185 */
HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8186 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
8187 uint32_t TimerIdx)
8188 {
8189 /* Prevent unused argument(s) compilation warning */
8190 UNUSED(hhrtim);
8191 UNUSED(TimerIdx);
8192
8193 /* NOTE : This function should not be modified, when the callback is needed,
8194 the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
8195 */
8196 }
8197
8198 /**
8199 * @brief Callback function invoked when timer repetition period has elapsed
8200 * @param hhrtim pointer to HAL HRTIM handle
8201 * @param TimerIdx Timer index
8202 * This parameter can be one of the following values:
8203 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8204 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8205 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8206 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8207 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8208 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8209 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8210 * @retval None
8211 */
HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8212 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
8213 uint32_t TimerIdx)
8214 {
8215 /* Prevent unused argument(s) compilation warning */
8216 UNUSED(hhrtim);
8217 UNUSED(TimerIdx);
8218
8219 /* NOTE : This function should not be modified, when the callback is needed,
8220 the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
8221 */
8222 }
8223
8224 /**
8225 * @brief Callback function invoked when the timer counter matches the value
8226 * programmed in the compare 1 register
8227 * @param hhrtim pointer to HAL HRTIM handle
8228 * @param TimerIdx Timer index
8229 * This parameter can be one of the following values:
8230 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8231 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8232 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8233 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8234 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8235 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8236 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8237 * @retval None
8238 */
HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8239 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
8240 uint32_t TimerIdx)
8241 {
8242 /* Prevent unused argument(s) compilation warning */
8243 UNUSED(hhrtim);
8244 UNUSED(TimerIdx);
8245
8246 /* NOTE : This function should not be modified, when the callback is needed,
8247 the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
8248 */
8249 }
8250
8251 /**
8252 * @brief Callback function invoked when the timer counter matches the value
8253 * programmed in the compare 2 register
8254 * @param hhrtim pointer to HAL HRTIM handle
8255 * @retval None
8256 * @param TimerIdx Timer index
8257 * This parameter can be one of the following values:
8258 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8259 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8260 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8261 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8262 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8263 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8264 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8265 */
HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8266 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
8267 uint32_t TimerIdx)
8268 {
8269 /* Prevent unused argument(s) compilation warning */
8270 UNUSED(hhrtim);
8271 UNUSED(TimerIdx);
8272
8273 /* NOTE : This function should not be modified, when the callback is needed,
8274 the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
8275 */
8276 }
8277
8278 /**
8279 * @brief Callback function invoked when the timer counter matches the value
8280 * programmed in the compare 3 register
8281 * @param hhrtim pointer to HAL HRTIM handle
8282 * @param TimerIdx Timer index
8283 * This parameter can be one of the following values:
8284 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8285 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8286 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8287 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8288 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8289 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8290 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8291 * @retval None
8292 */
HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8293 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
8294 uint32_t TimerIdx)
8295 {
8296 /* Prevent unused argument(s) compilation warning */
8297 UNUSED(hhrtim);
8298 UNUSED(TimerIdx);
8299
8300 /* NOTE : This function should not be modified, when the callback is needed,
8301 the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
8302 */
8303 }
8304
8305 /**
8306 * @brief Callback function invoked when the timer counter matches the value
8307 * programmed in the compare 4 register.
8308 * @param hhrtim pointer to HAL HRTIM handle
8309 * @param TimerIdx Timer index
8310 * This parameter can be one of the following values:
8311 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8312 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8313 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8314 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8315 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8316 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8317 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8318 * @retval None
8319 */
HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8320 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
8321 uint32_t TimerIdx)
8322 {
8323 /* Prevent unused argument(s) compilation warning */
8324 UNUSED(hhrtim);
8325 UNUSED(TimerIdx);
8326
8327 /* NOTE : This function should not be modified, when the callback is needed,
8328 the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
8329 */
8330 }
8331
8332 /**
8333 * @brief Callback function invoked when the timer x capture 1 event occurs
8334 * @param hhrtim pointer to HAL HRTIM handle
8335 * @param TimerIdx Timer index
8336 * This parameter can be one of the following values:
8337 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8338 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8339 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8340 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8341 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8342 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8343 * @retval None
8344 */
HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8345 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
8346 uint32_t TimerIdx)
8347 {
8348 /* Prevent unused argument(s) compilation warning */
8349 UNUSED(hhrtim);
8350 UNUSED(TimerIdx);
8351
8352 /* NOTE : This function should not be modified, when the callback is needed,
8353 the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
8354 */
8355 }
8356
8357 /**
8358 * @brief Callback function invoked when the timer x capture 2 event occurs
8359 * @param hhrtim pointer to HAL HRTIM handle
8360 * @param TimerIdx Timer index
8361 * This parameter can be one of the following values:
8362 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8363 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8364 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8365 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8366 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8367 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8368 * @retval None
8369 */
HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8370 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
8371 uint32_t TimerIdx)
8372 {
8373 /* Prevent unused argument(s) compilation warning */
8374 UNUSED(hhrtim);
8375 UNUSED(TimerIdx);
8376
8377 /* NOTE : This function should not be modified, when the callback is needed,
8378 the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
8379 */
8380 }
8381
8382 /**
8383 * @brief Callback function invoked when the delayed idle or balanced idle mode is
8384 * entered.
8385 * @param hhrtim pointer to HAL HRTIM handle
8386 * @param TimerIdx Timer index
8387 * This parameter can be one of the following values:
8388 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8389 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8390 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8391 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8392 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8393 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8394 * @retval None
8395 */
HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8396 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
8397 uint32_t TimerIdx)
8398 {
8399 /* Prevent unused argument(s) compilation warning */
8400 UNUSED(hhrtim);
8401 UNUSED(TimerIdx);
8402
8403 /* NOTE : This function should not be modified, when the callback is needed,
8404 the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
8405 */
8406 }
8407
8408 /**
8409 * @brief Callback function invoked when the timer x counter reset/roll-over
8410 * event occurs.
8411 * @param hhrtim pointer to HAL HRTIM handle
8412 * @param TimerIdx Timer index
8413 * This parameter can be one of the following values:
8414 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8415 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8416 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8417 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8418 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8419 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8420 * @retval None
8421 */
HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8422 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
8423 uint32_t TimerIdx)
8424 {
8425 /* Prevent unused argument(s) compilation warning */
8426 UNUSED(hhrtim);
8427 UNUSED(TimerIdx);
8428
8429 /* NOTE : This function should not be modified, when the callback is needed,
8430 the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
8431 */
8432 }
8433
8434 /**
8435 * @brief Callback function invoked when the timer x output 1 is set
8436 * @param hhrtim pointer to HAL HRTIM handle
8437 * @param TimerIdx Timer index
8438 * This parameter can be one of the following values:
8439 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8440 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8441 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8442 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8443 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8444 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8445 * @retval None
8446 */
HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8447 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
8448 uint32_t TimerIdx)
8449 {
8450 /* Prevent unused argument(s) compilation warning */
8451 UNUSED(hhrtim);
8452 UNUSED(TimerIdx);
8453
8454 /* NOTE : This function should not be modified, when the callback is needed,
8455 the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
8456 */
8457 }
8458
8459 /**
8460 * @brief Callback function invoked when the timer x output 1 is reset
8461 * @param hhrtim pointer to HAL HRTIM handle
8462 * @param TimerIdx Timer index
8463 * This parameter can be one of the following values:
8464 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8465 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8466 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8467 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8468 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8469 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8470 * @retval None
8471 */
HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8472 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
8473 uint32_t TimerIdx)
8474 {
8475 /* Prevent unused argument(s) compilation warning */
8476 UNUSED(hhrtim);
8477 UNUSED(TimerIdx);
8478
8479 /* NOTE : This function should not be modified, when the callback is needed,
8480 the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
8481 */
8482 }
8483
8484 /**
8485 * @brief Callback function invoked when the timer x output 2 is set
8486 * @param hhrtim pointer to HAL HRTIM handle
8487 * @param TimerIdx Timer index
8488 * This parameter can be one of the following values:
8489 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8490 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8491 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8492 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8493 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8494 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8495 * @retval None
8496 */
HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8497 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
8498 uint32_t TimerIdx)
8499 {
8500 /* Prevent unused argument(s) compilation warning */
8501 UNUSED(hhrtim);
8502 UNUSED(TimerIdx);
8503
8504 /* NOTE : This function should not be modified, when the callback is needed,
8505 the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
8506 */
8507 }
8508
8509 /**
8510 * @brief Callback function invoked when the timer x output 2 is reset
8511 * @param hhrtim pointer to HAL HRTIM handle
8512 * @param TimerIdx Timer index
8513 * This parameter can be one of the following values:
8514 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8515 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8516 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8517 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8518 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8519 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8520 * @retval None
8521 */
HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8522 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
8523 uint32_t TimerIdx)
8524 {
8525 /* Prevent unused argument(s) compilation warning */
8526 UNUSED(hhrtim);
8527 UNUSED(TimerIdx);
8528
8529 /* NOTE : This function should not be modified, when the callback is needed,
8530 the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
8531 */
8532 }
8533
8534 /**
8535 * @brief Callback function invoked when a DMA burst transfer is completed
8536 * @param hhrtim pointer to HAL HRTIM handle
8537 * @param TimerIdx Timer index
8538 * This parameter can be one of the following values:
8539 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8540 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8541 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8542 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8543 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8544 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8545 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8546 * @retval None
8547 */
HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)8548 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
8549 uint32_t TimerIdx)
8550 {
8551 /* Prevent unused argument(s) compilation warning */
8552 UNUSED(hhrtim);
8553 UNUSED(TimerIdx);
8554
8555 /* NOTE : This function should not be modified, when the callback is needed,
8556 the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
8557 */
8558 }
8559
8560 /**
8561 * @brief Callback function invoked when a DMA error occurs
8562 * @param hhrtim pointer to HAL HRTIM handle
8563 * @retval None
8564 */
HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef * hhrtim)8565 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
8566 {
8567 /* Prevent unused argument(s) compilation warning */
8568 UNUSED(hhrtim);
8569
8570 /* NOTE : This function should not be modified, when the callback is needed,
8571 the HAL_HRTIM_ErrorCallback could be implemented in the user file
8572 */
8573 }
8574
8575 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8576 /**
8577 * @brief HRTIM callback function registration
8578 * @param hhrtim pointer to HAL HRTIM handle
8579 * @param CallbackID ID of the HRTIM callback function to register
8580 * This parameter can be one of the following values:
8581 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
8582 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
8583 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
8584 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
8585 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
8586 * @arg HAL_HRTIM_FAULT6CALLBACK_CB_ID
8587 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
8588 * @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
8589 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
8590 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
8591 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
8592 * @arg HAL_HRTIM_MSPINIT_CB_ID
8593 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
8594 * @param pCallback Callback function pointer
8595 * @retval HAL status
8596 */
HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_CallbackTypeDef pCallback)8597 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,
8598 HAL_HRTIM_CallbackIDTypeDef CallbackID,
8599 pHRTIM_CallbackTypeDef pCallback)
8600 {
8601 HAL_StatusTypeDef status = HAL_OK;
8602
8603 if (pCallback == NULL)
8604 {
8605 /* Update the state */
8606 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8607
8608 return HAL_ERROR;
8609 }
8610
8611 /* Process locked */
8612 __HAL_LOCK(hhrtim);
8613
8614 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8615 {
8616 switch (CallbackID)
8617 {
8618 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
8619 hhrtim->Fault1Callback = pCallback;
8620 break;
8621
8622 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
8623 hhrtim->Fault2Callback = pCallback;
8624 break;
8625
8626 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
8627 hhrtim->Fault3Callback = pCallback;
8628 break;
8629
8630 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
8631 hhrtim->Fault4Callback = pCallback;
8632 break;
8633
8634 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
8635 hhrtim->Fault5Callback = pCallback;
8636 break;
8637
8638 case HAL_HRTIM_FAULT6CALLBACK_CB_ID :
8639 hhrtim->Fault6Callback = pCallback;
8640 break;
8641
8642 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
8643 hhrtim->SystemFaultCallback = pCallback;
8644 break;
8645
8646 case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
8647 hhrtim->DLLCalibrationReadyCallback = pCallback;
8648 break;
8649
8650 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
8651 hhrtim->BurstModePeriodCallback = pCallback;
8652 break;
8653
8654 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
8655 hhrtim->SynchronizationEventCallback = pCallback;
8656 break;
8657
8658 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
8659 hhrtim->ErrorCallback = pCallback;
8660 break;
8661
8662 case HAL_HRTIM_MSPINIT_CB_ID :
8663 hhrtim->MspInitCallback = pCallback;
8664 break;
8665
8666 case HAL_HRTIM_MSPDEINIT_CB_ID :
8667 hhrtim->MspDeInitCallback = pCallback;
8668 break;
8669
8670 default :
8671 /* Update the state */
8672 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8673
8674 /* Return error status */
8675 status = HAL_ERROR;
8676 break;
8677 }
8678 }
8679 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
8680 {
8681 switch (CallbackID)
8682 {
8683 case HAL_HRTIM_MSPINIT_CB_ID :
8684 hhrtim->MspInitCallback = pCallback;
8685 break;
8686
8687 case HAL_HRTIM_MSPDEINIT_CB_ID :
8688 hhrtim->MspDeInitCallback = pCallback;
8689 break;
8690
8691 default :
8692 /* Update the state */
8693 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8694
8695 /* Return error status */
8696 status = HAL_ERROR;
8697 break;
8698 }
8699 }
8700 else
8701 {
8702 /* Update the state */
8703 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8704
8705 /* Return error status */
8706 status = HAL_ERROR;
8707 }
8708
8709 /* Release Lock */
8710 __HAL_UNLOCK(hhrtim);
8711
8712 return status;
8713 }
8714
8715 /**
8716 * @brief HRTIM callback function un-registration
8717 * @param hhrtim pointer to HAL HRTIM handle
8718 * @param CallbackID ID of the HRTIM callback function to unregister
8719 * This parameter can be one of the following values:
8720 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
8721 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
8722 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
8723 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
8724 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
8725 * @arg HAL_HRTIM_FAULT6CALLBACK_CB_ID
8726 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
8727 * @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
8728 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
8729 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
8730 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
8731 * @arg HAL_HRTIM_MSPINIT_CB_ID
8732 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
8733 * @retval HAL status
8734 */
HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)8735 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
8736 HAL_HRTIM_CallbackIDTypeDef CallbackID)
8737 {
8738 HAL_StatusTypeDef status = HAL_OK;
8739
8740 /* Process locked */
8741 __HAL_LOCK(hhrtim);
8742
8743 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8744 {
8745 switch (CallbackID)
8746 {
8747 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
8748 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
8749 break;
8750
8751 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
8752 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
8753 break;
8754
8755 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
8756 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
8757 break;
8758
8759 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
8760 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
8761 break;
8762
8763 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
8764 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
8765 break;
8766
8767 case HAL_HRTIM_FAULT6CALLBACK_CB_ID :
8768 hhrtim->Fault6Callback = HAL_HRTIM_Fault6Callback;
8769 break;
8770
8771 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
8772 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
8773 break;
8774
8775 case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
8776 hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
8777 break;
8778
8779 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
8780 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
8781 break;
8782
8783 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
8784 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
8785 break;
8786
8787 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
8788 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
8789 break;
8790
8791 case HAL_HRTIM_MSPINIT_CB_ID :
8792 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
8793 break;
8794
8795 case HAL_HRTIM_MSPDEINIT_CB_ID :
8796 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
8797 break;
8798
8799 default :
8800 /* Update the state */
8801 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8802
8803 /* Return error status */
8804 status = HAL_ERROR;
8805 break;
8806 }
8807 }
8808 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
8809 {
8810 switch (CallbackID)
8811 {
8812 case HAL_HRTIM_MSPINIT_CB_ID :
8813 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
8814 break;
8815
8816 case HAL_HRTIM_MSPDEINIT_CB_ID :
8817 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
8818 break;
8819
8820 default :
8821 /* Update the state */
8822 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8823
8824 /* Return error status */
8825 status = HAL_ERROR;
8826 break;
8827 }
8828 }
8829 else
8830 {
8831 /* Update the state */
8832 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8833
8834 /* Return error status */
8835 status = HAL_ERROR;
8836 }
8837
8838 /* Release Lock */
8839 __HAL_UNLOCK(hhrtim);
8840
8841 return status;
8842 }
8843
8844 /**
8845 * @brief HRTIM Timer x callback function registration
8846 * @param hhrtim pointer to HAL HRTIM handle
8847 * @param CallbackID ID of the HRTIM Timer x callback function to register
8848 * This parameter can be one of the following values:
8849 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
8850 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
8851 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
8852 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
8853 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
8854 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
8855 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
8856 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
8857 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
8858 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
8859 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
8860 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
8861 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
8862 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
8863 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
8864 * @param pCallback Callback function pointer
8865 * @retval HAL status
8866 */
HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID,pHRTIM_TIMxCallbackTypeDef pCallback)8867 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
8868 HAL_HRTIM_CallbackIDTypeDef CallbackID,
8869 pHRTIM_TIMxCallbackTypeDef pCallback)
8870 {
8871 HAL_StatusTypeDef status = HAL_OK;
8872
8873 if (pCallback == NULL)
8874 {
8875 /* Update the state */
8876 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8877
8878 return HAL_ERROR;
8879 }
8880
8881 /* Process locked */
8882 __HAL_LOCK(hhrtim);
8883
8884 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8885 {
8886 switch (CallbackID)
8887 {
8888 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
8889 hhrtim->RegistersUpdateCallback = pCallback;
8890 break;
8891
8892 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
8893 hhrtim->RepetitionEventCallback = pCallback;
8894 break;
8895
8896 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
8897 hhrtim->Compare1EventCallback = pCallback;
8898 break;
8899
8900 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
8901 hhrtim->Compare2EventCallback = pCallback;
8902 break;
8903
8904 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
8905 hhrtim->Compare3EventCallback = pCallback;
8906 break;
8907
8908 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
8909 hhrtim->Compare4EventCallback = pCallback;
8910 break;
8911
8912 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
8913 hhrtim->Capture1EventCallback = pCallback;
8914 break;
8915
8916 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
8917 hhrtim->Capture2EventCallback = pCallback;
8918 break;
8919
8920 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
8921 hhrtim->DelayedProtectionCallback = pCallback;
8922 break;
8923
8924 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
8925 hhrtim->CounterResetCallback = pCallback;
8926 break;
8927
8928 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
8929 hhrtim->Output1SetCallback = pCallback;
8930 break;
8931
8932 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
8933 hhrtim->Output1ResetCallback = pCallback;
8934 break;
8935
8936 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
8937 hhrtim->Output2SetCallback = pCallback;
8938 break;
8939
8940 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
8941 hhrtim->Output2ResetCallback = pCallback;
8942 break;
8943
8944 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
8945 hhrtim->BurstDMATransferCallback = pCallback;
8946 break;
8947
8948 default :
8949 /* Update the state */
8950 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8951
8952 /* Return error status */
8953 status = HAL_ERROR;
8954 break;
8955 }
8956 }
8957 else
8958 {
8959 /* Update the state */
8960 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8961
8962 /* Return error status */
8963 status = HAL_ERROR;
8964 }
8965
8966 /* Release Lock */
8967 __HAL_UNLOCK(hhrtim);
8968
8969 return status;
8970 }
8971
8972 /**
8973 * @brief HRTIM Timer x callback function un-registration
8974 * @param hhrtim pointer to HAL HRTIM handle
8975 * @param CallbackID ID of the HRTIM callback Timer x function to unregister
8976 * This parameter can be one of the following values:
8977 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
8978 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
8979 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
8980 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
8981 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
8982 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
8983 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
8984 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
8985 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
8986 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
8987 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
8988 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
8989 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
8990 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
8991 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
8992 * @retval HAL status
8993 */
HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,HAL_HRTIM_CallbackIDTypeDef CallbackID)8994 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
8995 HAL_HRTIM_CallbackIDTypeDef CallbackID)
8996 {
8997 HAL_StatusTypeDef status = HAL_OK;
8998
8999 /* Process locked */
9000 __HAL_LOCK(hhrtim);
9001
9002 if (HAL_HRTIM_STATE_READY == hhrtim->State)
9003 {
9004 switch (CallbackID)
9005 {
9006 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
9007 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
9008 break;
9009
9010 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
9011 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
9012 break;
9013
9014 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
9015 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
9016 break;
9017
9018 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
9019 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
9020 break;
9021
9022 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
9023 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
9024 break;
9025
9026 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
9027 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
9028 break;
9029
9030 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
9031 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
9032 break;
9033
9034 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
9035 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
9036 break;
9037
9038 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
9039 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
9040 break;
9041
9042 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
9043 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
9044 break;
9045
9046 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
9047 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
9048 break;
9049
9050 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
9051 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
9052 break;
9053
9054 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
9055 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
9056 break;
9057
9058 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
9059 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
9060 break;
9061
9062 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
9063 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
9064 break;
9065
9066 default :
9067 /* Update the state */
9068 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
9069
9070 /* Return error status */
9071 status = HAL_ERROR;
9072 break;
9073 }
9074 }
9075 else
9076 {
9077 /* Update the state */
9078 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
9079
9080 /* Return error status */
9081 status = HAL_ERROR;
9082 }
9083
9084 /* Release Lock */
9085 __HAL_UNLOCK(hhrtim);
9086
9087 return status;
9088 }
9089 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9090 /**
9091 * @}
9092 */
9093
9094 /**
9095 * @}
9096 */
9097
9098 /** @addtogroup HRTIM_Private_Functions
9099 * @{
9100 */
9101
9102 /**
9103 * @brief Configure the master timer time base
9104 * @param hhrtim pointer to HAL HRTIM handle
9105 * @param pTimeBaseCfg pointer to the time base configuration structure
9106 * @retval None
9107 */
HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)9108 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
9109 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
9110 {
9111 uint32_t hrtim_mcr;
9112
9113 /* Configure master timer */
9114 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
9115
9116 /* Set the prescaler ratio */
9117 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
9118 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
9119
9120 /* Set the operating mode */
9121 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
9122 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
9123
9124 /* Update the HRTIM registers */
9125 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
9126 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
9127 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
9128 }
9129
9130 /**
9131 * @brief Configure timing unit (Timer A to Timer F) time base
9132 * @param hhrtim pointer to HAL HRTIM handle
9133 * @param TimerIdx Timer index
9134 * @param pTimeBaseCfg pointer to the time base configuration structure
9135 * @retval None
9136 */
HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)9137 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
9138 uint32_t TimerIdx ,
9139 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
9140 {
9141 uint32_t hrtim_timcr;
9142
9143 /* Configure master timing unit */
9144 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
9145
9146 /* Set the prescaler ratio */
9147 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
9148 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
9149
9150 /* Set the operating mode */
9151 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
9152 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
9153
9154 /* Update the HRTIM registers */
9155 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
9156 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
9157 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
9158 }
9159
9160 /**
9161 * @brief Configure the master timer in waveform mode
9162 * @param hhrtim pointer to HAL HRTIM handle
9163 * @param pTimerCfg pointer to the timer configuration data structure
9164 * @retval None
9165 */
HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,HRTIM_TimerCfgTypeDef * pTimerCfg)9166 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
9167 HRTIM_TimerCfgTypeDef * pTimerCfg)
9168 {
9169 uint32_t hrtim_mcr;
9170 uint32_t hrtim_bmcr;
9171
9172 /* Configure master timer */
9173 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
9174 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
9175
9176 /* Enable/Disable the half mode */
9177 hrtim_mcr &= ~(HRTIM_MCR_HALF);
9178 hrtim_mcr |= pTimerCfg->HalfModeEnable;
9179
9180 /* INTLVD bits are set to 00 */
9181 hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
9182 if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
9183 {
9184 /* INTLVD bits set to 00 */
9185 hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
9186 hrtim_mcr |= (HRTIM_MCR_HALF);
9187 }
9188 else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
9189 {
9190 hrtim_mcr |= (HRTIM_MCR_INTLVD_0);
9191 hrtim_mcr &= ~(HRTIM_MCR_INTLVD_1);
9192 }
9193 else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
9194 {
9195 hrtim_mcr |= (HRTIM_MCR_INTLVD_1);
9196 hrtim_mcr &= ~(HRTIM_MCR_INTLVD_0);
9197 }
9198 else
9199 {
9200 hrtim_mcr &= ~(HRTIM_MCR_HALF);
9201 hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
9202 }
9203
9204 /* Enable/Disable the timer start upon synchronization event reception */
9205 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
9206 hrtim_mcr |= pTimerCfg->StartOnSync;
9207
9208 /* Enable/Disable the timer reset upon synchronization event reception */
9209 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
9210 hrtim_mcr |= pTimerCfg->ResetOnSync;
9211
9212 /* Enable/Disable the DAC synchronization event generation */
9213 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
9214 hrtim_mcr |= pTimerCfg->DACSynchro;
9215
9216 /* Enable/Disable preload mechanism for timer registers */
9217 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
9218 hrtim_mcr |= pTimerCfg->PreloadEnable;
9219
9220 /* Master timer registers update handling */
9221 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
9222 hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
9223
9224 /* Enable/Disable registers update on repetition */
9225 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
9226 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
9227
9228 /* Set the timer burst mode */
9229 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
9230 hrtim_bmcr |= pTimerCfg->BurstMode;
9231
9232 /* Update the HRTIM registers */
9233 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
9234 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
9235 }
9236
9237 /**
9238 * @brief Configure timing unit (Timer A to Timer F) in waveform mode
9239 * @param hhrtim pointer to HAL HRTIM handle
9240 * @param TimerIdx Timer index
9241 * @param pTimerCfg pointer to the timer configuration data structure
9242 * @retval None
9243 */
HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,HRTIM_TimerCfgTypeDef * pTimerCfg)9244 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
9245 uint32_t TimerIdx,
9246 HRTIM_TimerCfgTypeDef * pTimerCfg)
9247 {
9248 uint32_t hrtim_timcr;
9249 uint32_t hrtim_timfltr;
9250 uint32_t hrtim_timoutr;
9251 uint32_t hrtim_timrstr;
9252 uint32_t hrtim_bmcr;
9253
9254 /* UPDGAT bitfield must be reset before programming a new value */
9255 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
9256
9257 /* Configure timing unit (Timer A to Timer F) */
9258 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
9259 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
9260 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
9261 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
9262
9263 /* Enable/Disable the half mode */
9264 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
9265 hrtim_timcr |= pTimerCfg->HalfModeEnable;
9266
9267 if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
9268 {
9269 /* INTLVD bits set to 00 */
9270 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
9271 hrtim_timcr |= (HRTIM_TIMCR_HALF);
9272 }
9273 else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
9274 {
9275 hrtim_timcr |= (HRTIM_TIMCR_INTLVD_0);
9276 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_1);
9277 }
9278 else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
9279 {
9280 hrtim_timcr |= (HRTIM_TIMCR_INTLVD_1);
9281 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_0);
9282 }
9283 else
9284 {
9285 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
9286 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
9287 }
9288
9289 /* Enable/Disable the timer start upon synchronization event reception */
9290 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
9291 hrtim_timcr |= pTimerCfg->StartOnSync;
9292
9293 /* Enable/Disable the timer reset upon synchronization event reception */
9294 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
9295 hrtim_timcr |= pTimerCfg->ResetOnSync;
9296
9297 /* Enable/Disable the DAC synchronization event generation */
9298 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
9299 hrtim_timcr |= pTimerCfg->DACSynchro;
9300
9301 /* Enable/Disable preload mechanism for timer registers */
9302 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
9303 hrtim_timcr |= pTimerCfg->PreloadEnable;
9304
9305 /* Timing unit registers update handling */
9306 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
9307 hrtim_timcr |= pTimerCfg->UpdateGating;
9308
9309 /* Enable/Disable registers update on repetition */
9310 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
9311 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
9312 {
9313 hrtim_timcr |= HRTIM_TIMCR_TREPU;
9314 }
9315
9316 /* Set the push-pull mode */
9317 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
9318 hrtim_timcr |= pTimerCfg->PushPull;
9319
9320 /* Enable/Disable registers update on timer counter reset */
9321 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
9322 hrtim_timcr |= pTimerCfg->ResetUpdate;
9323
9324 /* Set the timer update trigger */
9325 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
9326 hrtim_timcr |= pTimerCfg->UpdateTrigger;
9327
9328 /* Enable/Disable the fault channel at timer level */
9329 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
9330 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
9331
9332 /* Lock/Unlock fault sources at timer level */
9333 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
9334 hrtim_timfltr |= pTimerCfg->FaultLock;
9335
9336 /* Enable/Disable dead time insertion at timer level */
9337 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
9338 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
9339
9340 /* Enable/Disable delayed protection at timer level
9341 Delayed Idle is available whatever the timer operating mode (regular, push-pull)
9342 Balanced Idle is only available in push-pull mode
9343 */
9344 if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
9345 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
9346 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
9347 {
9348 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
9349 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
9350 }
9351
9352 /* Set the BIAR mode : one bit for both outputs */
9353 hrtim_timoutr &= ~(HRTIM_OUTR_BIAR);
9354 hrtim_timoutr |= (pTimerCfg->BalancedIdleAutomaticResume);
9355
9356 /* Set the timer counter reset trigger */
9357 hrtim_timrstr = pTimerCfg->ResetTrigger;
9358
9359 /* Set the timer burst mode */
9360 switch (TimerIdx)
9361 {
9362 case HRTIM_TIMERINDEX_TIMER_A:
9363 {
9364 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
9365 hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
9366 break;
9367 }
9368
9369 case HRTIM_TIMERINDEX_TIMER_B:
9370 {
9371 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
9372 hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
9373 break;
9374 }
9375
9376 case HRTIM_TIMERINDEX_TIMER_C:
9377 {
9378 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
9379 hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
9380 break;
9381 }
9382
9383 case HRTIM_TIMERINDEX_TIMER_D:
9384 {
9385 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
9386 hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
9387 break;
9388 }
9389
9390 case HRTIM_TIMERINDEX_TIMER_E:
9391 {
9392 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
9393 hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
9394 break;
9395 }
9396
9397 case HRTIM_TIMERINDEX_TIMER_F:
9398 {
9399 hrtim_bmcr &= ~(HRTIM_BMCR_TFBM);
9400 hrtim_bmcr |= ( pTimerCfg->BurstMode << 6U);
9401 break;
9402 }
9403
9404 default:
9405 break;
9406 }
9407
9408 /* Update the HRTIM registers */
9409 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
9410 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
9411 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
9412 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
9413 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
9414 }
9415
9416 /**
9417 * @brief Control timing unit (timer A to timer F) in waveform mode
9418 * @param hhrtim pointer to HAL HRTIM handle
9419 * @param TimerIdx Timer index
9420 * @param pTimerCtl pointer to the timer configuration data structure
9421 * @retval None
9422 */
HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,HRTIM_TimerCtlTypeDef * pTimerCtl)9423 static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim,
9424 uint32_t TimerIdx,
9425 HRTIM_TimerCtlTypeDef * pTimerCtl)
9426 {
9427 uint32_t hrtim_timcr2;
9428
9429 /* Configure timing unit (Timer A to Timer F) */
9430 hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
9431
9432 /* Set the UpDown counting Mode */
9433 hrtim_timcr2 &= ~(HRTIM_TIMCR2_UDM);
9434 hrtim_timcr2 |= (pTimerCtl->UpDownMode << HRTIM_TIMCR2_UDM_Pos) ;
9435
9436 /* Set the TrigHalf Mode : requires the counter to be disabled */
9437 hrtim_timcr2 &= ~(HRTIM_TIMCR2_TRGHLF);
9438 hrtim_timcr2 |= pTimerCtl->TrigHalf;
9439
9440 /* define the compare event operating mode */
9441 hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP1);
9442 hrtim_timcr2 |= pTimerCtl->GreaterCMP1;
9443
9444 /* define the compare event operating mode */
9445 hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP3);
9446 hrtim_timcr2 |= pTimerCtl->GreaterCMP3;
9447
9448 if (pTimerCtl->DualChannelDacEnable == HRTIM_TIMER_DCDE_ENABLED)
9449 {
9450 /* Set the DualChannel DAC Reset trigger : requires DCDE enabled */
9451 hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDR);
9452 hrtim_timcr2 |= pTimerCtl->DualChannelDacReset;
9453
9454 /* Set the DualChannel DAC Step trigger : requires DCDE enabled */
9455 hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDS);
9456 hrtim_timcr2 |= pTimerCtl->DualChannelDacStep;
9457
9458 /* Enable the DualChannel DAC trigger */
9459 hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDE);
9460 hrtim_timcr2 |= pTimerCtl->DualChannelDacEnable;
9461 }
9462 /* Update the HRTIM registers */
9463 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2;
9464
9465 }
9466
9467 /**
9468 * @brief Configure timing RollOver Mode (Timer A to Timer F)
9469 * @param hhrtim pointer to HAL HRTIM handle
9470 * @param TimerIdx Timer index
9471 * @param pRollOverMode: a combination of the timer RollOver Mode configuration
9472 * @retval None
9473 */
HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t pRollOverMode)9474 static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim,
9475 uint32_t TimerIdx,
9476 uint32_t pRollOverMode)
9477 {
9478 uint32_t hrtim_timcr2;
9479
9480 /* Configure timing unit (Timer A to Timer F) */
9481 hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
9482
9483 if ((hrtim_timcr2 & HRTIM_TIMCR2_UDM) != 0U)
9484 {
9485 /* xxROM bitfield must be reset before programming a new value */
9486 hrtim_timcr2 &= ~(HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM |
9487 HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM);
9488
9489 /* Update the HRTIM TIMxCR2 register */
9490 hrtim_timcr2 |= pRollOverMode & (HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM |
9491 HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM);
9492
9493 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2;
9494 }
9495 }
9496
9497 /**
9498 * @brief Configure a capture unit
9499 * @param hhrtim pointer to HAL HRTIM handle
9500 * @param TimerIdx Timer index
9501 * @param CaptureUnit Capture unit identifier
9502 * @param Event Event reference
9503 * @retval None
9504 */
HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t CaptureUnit,uint32_t Event)9505 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
9506 uint32_t TimerIdx,
9507 uint32_t CaptureUnit,
9508 uint32_t Event)
9509 {
9510 uint32_t CaptureTrigger = 0xFFFFFFFFU;
9511
9512 switch (Event)
9513 {
9514 case HRTIM_EVENT_1:
9515 {
9516 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
9517 break;
9518 }
9519
9520 case HRTIM_EVENT_2:
9521 {
9522 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
9523 break;
9524 }
9525
9526 case HRTIM_EVENT_3:
9527 {
9528 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
9529 break;
9530 }
9531
9532 case HRTIM_EVENT_4:
9533 {
9534 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
9535 break;
9536 }
9537
9538 case HRTIM_EVENT_5:
9539 {
9540 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
9541 break;
9542 }
9543
9544 case HRTIM_EVENT_6:
9545 {
9546 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
9547 break;
9548 }
9549
9550 case HRTIM_EVENT_7:
9551 {
9552 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
9553 break;
9554 }
9555
9556 case HRTIM_EVENT_8:
9557 {
9558 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
9559 break;
9560 }
9561
9562 case HRTIM_EVENT_9:
9563 {
9564 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
9565 break;
9566 }
9567
9568 case HRTIM_EVENT_10:
9569 {
9570 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
9571 break;
9572 }
9573
9574 default:
9575 break;
9576 }
9577
9578 switch (CaptureUnit)
9579 {
9580 case HRTIM_CAPTUREUNIT_1:
9581 {
9582 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
9583 break;
9584 }
9585
9586 case HRTIM_CAPTUREUNIT_2:
9587 {
9588 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
9589 break;
9590 }
9591
9592 default:
9593 break;
9594 }
9595 }
9596
9597 /**
9598 * @brief Configure the output of a timing unit
9599 * @param hhrtim pointer to HAL HRTIM handle
9600 * @param TimerIdx Timer index
9601 * @param Output timing unit output identifier
9602 * @param pOutputCfg pointer to the output configuration data structure
9603 * @retval None
9604 */
HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Output,HRTIM_OutputCfgTypeDef * pOutputCfg)9605 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
9606 uint32_t TimerIdx,
9607 uint32_t Output,
9608 HRTIM_OutputCfgTypeDef * pOutputCfg)
9609 {
9610 uint32_t hrtim_outr;
9611 uint32_t hrtim_dtr;
9612
9613 uint32_t shift = 0U;
9614
9615 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
9616 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
9617
9618 switch (Output)
9619 {
9620 case HRTIM_OUTPUT_TA1:
9621 case HRTIM_OUTPUT_TB1:
9622 case HRTIM_OUTPUT_TC1:
9623 case HRTIM_OUTPUT_TD1:
9624 case HRTIM_OUTPUT_TE1:
9625 case HRTIM_OUTPUT_TF1:
9626 {
9627 /* Set the output set/reset crossbar */
9628 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
9629 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
9630 break;
9631 }
9632
9633 case HRTIM_OUTPUT_TA2:
9634 case HRTIM_OUTPUT_TB2:
9635 case HRTIM_OUTPUT_TC2:
9636 case HRTIM_OUTPUT_TD2:
9637 case HRTIM_OUTPUT_TE2:
9638 case HRTIM_OUTPUT_TF2:
9639 {
9640 /* Set the output set/reset crossbar */
9641 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
9642 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
9643 shift = 16U;
9644 break;
9645 }
9646
9647 default:
9648 break;
9649 }
9650
9651 /* Clear output config */
9652 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
9653 HRTIM_OUTR_IDLM1 |
9654 HRTIM_OUTR_IDLES1|
9655 HRTIM_OUTR_FAULT1|
9656 HRTIM_OUTR_CHP1 |
9657 HRTIM_OUTR_DIDL1) << shift);
9658
9659 /* Set the polarity */
9660 hrtim_outr |= (pOutputCfg->Polarity << shift);
9661
9662 /* Set the IDLE mode */
9663 hrtim_outr |= (pOutputCfg->IdleMode << shift);
9664
9665 /* Set the IDLE state */
9666 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
9667
9668 /* Set the FAULT state */
9669 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
9670
9671 /* Set the chopper mode */
9672 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
9673
9674 /* Set the burst mode entry mode : deadtime insertion when entering the idle
9675 state during a burst mode operation is allowed only under the following
9676 conditions:
9677 - the outputs is active during the burst mode (IDLES=1U)
9678 - positive deadtimes (SDTR/SDTF set to 0U)
9679 */
9680 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
9681 ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
9682 ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
9683 {
9684 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
9685 }
9686
9687 /* Update HRTIM register */
9688 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
9689 }
9690
9691 /**
9692 * @brief Configure an external event channel
9693 * @param hhrtim pointer to HAL HRTIM handle
9694 * @param Event Event channel identifier
9695 * @param pEventCfg pointer to the event channel configuration data structure
9696 * @retval None
9697 */
HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t Event,HRTIM_EventCfgTypeDef * pEventCfg)9698 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
9699 uint32_t Event,
9700 HRTIM_EventCfgTypeDef *pEventCfg)
9701 {
9702 uint32_t hrtim_eecr1;
9703 uint32_t hrtim_eecr2;
9704 uint32_t hrtim_eecr3;
9705
9706 /* Configure external event channel */
9707 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
9708 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
9709 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
9710
9711 switch (Event)
9712 {
9713 case HRTIM_EVENT_NONE:
9714 {
9715 /* Update the HRTIM registers */
9716 hhrtim->Instance->sCommonRegs.EECR1 = 0U;
9717 hhrtim->Instance->sCommonRegs.EECR2 = 0U;
9718 hhrtim->Instance->sCommonRegs.EECR3 = 0U;
9719 break;
9720 }
9721
9722 case HRTIM_EVENT_1:
9723 {
9724 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
9725 hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
9726 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
9727 hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
9728 /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
9729 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9730 /* Update the HRTIM registers (EE1FAST bit) */
9731 hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST);
9732 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9733 break;
9734 }
9735
9736 case HRTIM_EVENT_2:
9737 {
9738 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
9739 hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
9740 hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
9741 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
9742 /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
9743 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9744 /* Update the HRTIM registers (EE2FAST bit) */
9745 hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
9746 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9747 break;
9748 }
9749
9750 case HRTIM_EVENT_3:
9751 {
9752 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
9753 hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
9754 hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
9755 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
9756 /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
9757 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9758 /* Update the HRTIM registers (EE3FAST bit) */
9759 hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
9760 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9761 break;
9762 }
9763
9764 case HRTIM_EVENT_4:
9765 {
9766 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
9767 hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
9768 hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
9769 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
9770 /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
9771 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9772 /* Update the HRTIM registers (EE4FAST bit) */
9773 hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
9774 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9775 break;
9776 }
9777
9778 case HRTIM_EVENT_5:
9779 {
9780 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
9781 hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
9782 hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
9783 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
9784 /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
9785 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9786 /* Update the HRTIM registers (EE5FAST bit) */
9787 hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
9788 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9789 break;
9790 }
9791
9792 case HRTIM_EVENT_6:
9793 {
9794 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
9795 hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
9796 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
9797 hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
9798 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
9799 hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
9800 /* Update the HRTIM registers */
9801 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9802 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9803 break;
9804 }
9805
9806 case HRTIM_EVENT_7:
9807 {
9808 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
9809 hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
9810 hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
9811 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
9812 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
9813 hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
9814 /* Update the HRTIM registers */
9815 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9816 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9817 break;
9818 }
9819
9820 case HRTIM_EVENT_8:
9821 {
9822 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
9823 hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
9824 hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
9825 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
9826 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
9827 hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F );
9828 /* Update the HRTIM registers */
9829 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9830 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9831 break;
9832 }
9833
9834 case HRTIM_EVENT_9:
9835 {
9836 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
9837 hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
9838 hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
9839 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
9840 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
9841 hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
9842 /* Update the HRTIM registers */
9843 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9844 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9845 break;
9846 }
9847
9848 case HRTIM_EVENT_10:
9849 {
9850 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
9851 hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
9852 hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
9853 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
9854 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
9855 hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
9856 /* Update the HRTIM registers */
9857 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9858 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9859 break;
9860 }
9861
9862 default:
9863 break;
9864 }
9865 }
9866
9867 /**
9868 * @brief Configure the timer counter reset
9869 * @param hhrtim pointer to HAL HRTIM handle
9870 * @param TimerIdx Timer index
9871 * @param Event Event channel identifier
9872 * @retval None
9873 */
HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t Event)9874 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
9875 uint32_t TimerIdx,
9876 uint32_t Event)
9877 {
9878 switch (Event)
9879 {
9880 case HRTIM_EVENT_1:
9881 {
9882 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
9883 break;
9884 }
9885
9886 case HRTIM_EVENT_2:
9887 {
9888 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
9889 break;
9890 }
9891
9892 case HRTIM_EVENT_3:
9893 {
9894 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
9895 break;
9896 }
9897
9898 case HRTIM_EVENT_4:
9899 {
9900 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
9901 break;
9902 }
9903
9904 case HRTIM_EVENT_5:
9905 {
9906 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
9907 break;
9908 }
9909
9910 case HRTIM_EVENT_6:
9911 {
9912 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
9913 break;
9914 }
9915
9916 case HRTIM_EVENT_7:
9917 {
9918 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
9919 break;
9920 }
9921
9922 case HRTIM_EVENT_8:
9923 {
9924 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
9925 break;
9926 }
9927
9928 case HRTIM_EVENT_9:
9929 {
9930 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
9931 break;
9932 }
9933
9934 case HRTIM_EVENT_10:
9935 {
9936 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
9937 break;
9938 }
9939
9940 default:
9941 break;
9942 }
9943 }
9944
9945 /**
9946 * @brief Return the interrupt to enable or disable according to the
9947 * OC mode.
9948 * @param hhrtim pointer to HAL HRTIM handle
9949 * @param TimerIdx Timer index
9950 * @param OCChannel Timer output
9951 * This parameter can be one of the following values:
9952 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
9953 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
9954 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
9955 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
9956 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
9957 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
9958 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
9959 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
9960 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
9961 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
9962 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
9963 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
9964 * @retval Interrupt to enable or disable
9965 */
HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)9966 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
9967 uint32_t TimerIdx,
9968 uint32_t OCChannel)
9969 {
9970 uint32_t hrtim_set;
9971 uint32_t hrtim_reset;
9972 uint32_t interrupt = 0U;
9973
9974 switch (OCChannel)
9975 {
9976 case HRTIM_OUTPUT_TA1:
9977 case HRTIM_OUTPUT_TB1:
9978 case HRTIM_OUTPUT_TC1:
9979 case HRTIM_OUTPUT_TD1:
9980 case HRTIM_OUTPUT_TE1:
9981 case HRTIM_OUTPUT_TF1:
9982 {
9983 /* Retreives actual OC mode and set interrupt accordingly */
9984 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
9985 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
9986
9987 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
9988 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
9989 {
9990 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
9991 interrupt = HRTIM_TIM_IT_CMP1;
9992 }
9993 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
9994 (hrtim_reset == 0U))
9995 {
9996 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
9997 interrupt = HRTIM_TIM_IT_SET1;
9998 }
9999 else if ((hrtim_set == 0U) &&
10000 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
10001 {
10002 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10003 interrupt = HRTIM_TIM_IT_RST1;
10004 }
10005 else
10006 {
10007 /* nothing to do */
10008 }
10009 break;
10010 }
10011
10012 case HRTIM_OUTPUT_TA2:
10013 case HRTIM_OUTPUT_TB2:
10014 case HRTIM_OUTPUT_TC2:
10015 case HRTIM_OUTPUT_TD2:
10016 case HRTIM_OUTPUT_TE2:
10017 case HRTIM_OUTPUT_TF2:
10018 {
10019 /* Retreives actual OC mode and set interrupt accordingly */
10020 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
10021 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
10022
10023 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10024 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10025 {
10026 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
10027 interrupt = HRTIM_TIM_IT_CMP2;
10028 }
10029 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10030 (hrtim_reset == 0U))
10031 {
10032 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
10033 interrupt = HRTIM_TIM_IT_SET2;
10034 }
10035 else if ((hrtim_set == 0U) &&
10036 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10037 {
10038 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10039 interrupt = HRTIM_TIM_IT_RST2;
10040 }
10041 else
10042 {
10043 /* nothing to do */
10044 }
10045 break;
10046 }
10047
10048 default:
10049 break;
10050 }
10051
10052 return interrupt;
10053 }
10054
10055 /**
10056 * @brief Return the DMA request to enable or disable according to the
10057 * OC mode.
10058 * @param hhrtim pointer to HAL HRTIM handle
10059 * @param TimerIdx Timer index
10060 * @param OCChannel Timer output
10061 * This parameter can be one of the following values:
10062 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
10063 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
10064 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
10065 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
10066 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
10067 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
10068 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
10069 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
10070 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
10071 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
10072 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
10073 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
10074 * @retval DMA request to enable or disable
10075 */
HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx,uint32_t OCChannel)10076 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
10077 uint32_t TimerIdx,
10078 uint32_t OCChannel)
10079 {
10080 uint32_t hrtim_set;
10081 uint32_t hrtim_reset;
10082 uint32_t dma_request = 0U;
10083
10084 switch (OCChannel)
10085 {
10086 case HRTIM_OUTPUT_TA1:
10087 case HRTIM_OUTPUT_TB1:
10088 case HRTIM_OUTPUT_TC1:
10089 case HRTIM_OUTPUT_TD1:
10090 case HRTIM_OUTPUT_TE1:
10091 case HRTIM_OUTPUT_TF1:
10092 {
10093 /* Retreives actual OC mode and set dma_request accordingly */
10094 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
10095 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
10096
10097 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
10098 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
10099 {
10100 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
10101 dma_request = HRTIM_TIM_DMA_CMP1;
10102 }
10103 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
10104 (hrtim_reset == 0U))
10105 {
10106 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
10107 dma_request = HRTIM_TIM_DMA_SET1;
10108 }
10109 else if ((hrtim_set == 0U) &&
10110 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
10111 {
10112 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10113 dma_request = HRTIM_TIM_DMA_RST1;
10114 }
10115 else
10116 {
10117 /* nothing to do */
10118 }
10119 break;
10120 }
10121
10122 case HRTIM_OUTPUT_TA2:
10123 case HRTIM_OUTPUT_TB2:
10124 case HRTIM_OUTPUT_TC2:
10125 case HRTIM_OUTPUT_TD2:
10126 case HRTIM_OUTPUT_TE2:
10127 case HRTIM_OUTPUT_TF2:
10128 {
10129 /* Retreives actual OC mode and set dma_request accordingly */
10130 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
10131 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
10132
10133 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10134 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10135 {
10136 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
10137 dma_request = HRTIM_TIM_DMA_CMP2;
10138 }
10139 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10140 (hrtim_reset == 0U))
10141 {
10142 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
10143 dma_request = HRTIM_TIM_DMA_SET2;
10144 }
10145 else if ((hrtim_set == 0U) &&
10146 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10147 {
10148 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10149 dma_request = HRTIM_TIM_DMA_RST2;
10150 }
10151 else
10152 {
10153 /* nothing to do */
10154 }
10155 break;
10156 }
10157
10158 default:
10159 break;
10160 }
10161
10162 return dma_request;
10163 }
10164
HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)10165 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
10166 uint32_t TimerIdx)
10167 {
10168 DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
10169
10170 switch (TimerIdx)
10171 {
10172 case HRTIM_TIMERINDEX_MASTER:
10173 {
10174 hdma = hhrtim->hdmaMaster;
10175 break;
10176 }
10177
10178 case HRTIM_TIMERINDEX_TIMER_A:
10179 {
10180 hdma = hhrtim->hdmaTimerA;
10181 break;
10182 }
10183
10184 case HRTIM_TIMERINDEX_TIMER_B:
10185 {
10186 hdma = hhrtim->hdmaTimerB;
10187 break;
10188 }
10189
10190 case HRTIM_TIMERINDEX_TIMER_C:
10191 {
10192 hdma = hhrtim->hdmaTimerC;
10193 break;
10194 }
10195
10196 case HRTIM_TIMERINDEX_TIMER_D:
10197 {
10198 hdma = hhrtim->hdmaTimerD;
10199 break;
10200 }
10201
10202 case HRTIM_TIMERINDEX_TIMER_E:
10203 {
10204 hdma = hhrtim->hdmaTimerE;
10205 break;
10206 }
10207
10208 case HRTIM_TIMERINDEX_TIMER_F:
10209 {
10210 hdma = hhrtim->hdmaTimerF;
10211 break;
10212 }
10213
10214 default:
10215 break;
10216 }
10217
10218 return hdma;
10219 }
10220
GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,DMA_HandleTypeDef * hdma)10221 static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
10222 DMA_HandleTypeDef * hdma)
10223 {
10224 uint32_t timed_idx = 0xFFFFFFFFU;
10225
10226 if (hdma == hhrtim->hdmaMaster)
10227 {
10228 timed_idx = HRTIM_TIMERINDEX_MASTER;
10229 }
10230 else if (hdma == hhrtim->hdmaTimerA)
10231 {
10232 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
10233 }
10234 else if (hdma == hhrtim->hdmaTimerB)
10235 {
10236 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
10237 }
10238 else if (hdma == hhrtim->hdmaTimerC)
10239 {
10240 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
10241 }
10242 else if (hdma == hhrtim->hdmaTimerD)
10243 {
10244 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
10245 }
10246 else if (hdma == hhrtim->hdmaTimerE)
10247 {
10248 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
10249 }
10250 else if (hdma == hhrtim->hdmaTimerF)
10251 {
10252 timed_idx = HRTIM_TIMERINDEX_TIMER_F;
10253 }
10254 else
10255 {
10256 /* nothing to do */
10257 }
10258 return timed_idx;
10259 }
10260
10261 /**
10262 * @brief Force an immediate transfer from the preload to the active
10263 * registers.
10264 * @param hhrtim pointer to HAL HRTIM handle
10265 * @param TimerIdx Timer index
10266 * @retval None
10267 */
HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)10268 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
10269 uint32_t TimerIdx)
10270 {
10271 switch (TimerIdx)
10272 {
10273 case HRTIM_TIMERINDEX_MASTER:
10274 {
10275 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
10276 break;
10277 }
10278
10279 case HRTIM_TIMERINDEX_TIMER_A:
10280 {
10281 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
10282 break;
10283 }
10284
10285 case HRTIM_TIMERINDEX_TIMER_B:
10286 {
10287 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
10288 break;
10289 }
10290
10291 case HRTIM_TIMERINDEX_TIMER_C:
10292 {
10293 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
10294 break;
10295 }
10296
10297 case HRTIM_TIMERINDEX_TIMER_D:
10298 {
10299 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
10300 break;
10301 }
10302
10303 case HRTIM_TIMERINDEX_TIMER_E:
10304 {
10305 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
10306 break;
10307 }
10308
10309 case HRTIM_TIMERINDEX_TIMER_F:
10310 {
10311 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TFSWU;
10312 break;
10313 }
10314
10315 default:
10316 break;
10317 }
10318 }
10319
10320
10321 /**
10322 * @brief HRTIM interrupts service routine
10323 * @param hhrtim pointer to HAL HRTIM handle
10324 * @retval None
10325 */
HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)10326 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
10327 {
10328 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
10329 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
10330
10331 /* Fault 1 event */
10332 if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
10333 {
10334 if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
10335 {
10336 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
10337
10338 /* Invoke Fault 1 event callback */
10339 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10340 hhrtim->Fault1Callback(hhrtim);
10341 #else
10342 HAL_HRTIM_Fault1Callback(hhrtim);
10343 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10344 }
10345 }
10346
10347 /* Fault 2 event */
10348 if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
10349 {
10350 if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
10351 {
10352 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
10353
10354 /* Invoke Fault 2 event callback */
10355 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10356 hhrtim->Fault2Callback(hhrtim);
10357 #else
10358 HAL_HRTIM_Fault2Callback(hhrtim);
10359 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10360 }
10361 }
10362
10363 /* Fault 3 event */
10364 if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
10365 {
10366 if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
10367 {
10368 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
10369
10370 /* Invoke Fault 3 event callback */
10371 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10372 hhrtim->Fault3Callback(hhrtim);
10373 #else
10374 HAL_HRTIM_Fault3Callback(hhrtim);
10375 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10376 }
10377 }
10378
10379 /* Fault 4 event */
10380 if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
10381 {
10382 if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
10383 {
10384 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
10385
10386 /* Invoke Fault 4 event callback */
10387 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10388 hhrtim->Fault4Callback(hhrtim);
10389 #else
10390 HAL_HRTIM_Fault4Callback(hhrtim);
10391 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10392 }
10393 }
10394
10395 /* Fault 5 event */
10396 if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
10397 {
10398 if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
10399 {
10400 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
10401
10402 /* Invoke Fault 5 event callback */
10403 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10404 hhrtim->Fault5Callback(hhrtim);
10405 #else
10406 HAL_HRTIM_Fault5Callback(hhrtim);
10407 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10408 }
10409 }
10410
10411 /* Fault 6 event */
10412 if((uint32_t)(isrflags & HRTIM_FLAG_FLT6) != (uint32_t)RESET)
10413 {
10414 if((uint32_t)(ierits & HRTIM_IT_FLT6) != (uint32_t)RESET)
10415 {
10416 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT6);
10417
10418 /* Invoke Fault 6 event callback */
10419 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10420 hhrtim->Fault6Callback(hhrtim);
10421 #else
10422 HAL_HRTIM_Fault6Callback(hhrtim);
10423 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10424 }
10425 }
10426
10427 /* System fault event */
10428 if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
10429 {
10430 if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
10431 {
10432 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
10433
10434 /* Invoke System fault event callback */
10435 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10436 hhrtim->SystemFaultCallback(hhrtim);
10437 #else
10438 HAL_HRTIM_SystemFaultCallback(hhrtim);
10439 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10440 }
10441 }
10442 }
10443
10444 /**
10445 * @brief Master timer interrupts service routine
10446 * @param hhrtim pointer to HAL HRTIM handle
10447 * @retval None
10448 */
HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)10449 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
10450 {
10451 uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
10452 uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER);
10453 uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
10454 uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
10455
10456 /* DLL calibration ready event */
10457 if((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET)
10458 {
10459 if((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET)
10460 {
10461 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
10462
10463 /* Set HRTIM State */
10464 hhrtim->State = HAL_HRTIM_STATE_READY;
10465
10466 /* Process unlocked */
10467 __HAL_UNLOCK(hhrtim);
10468
10469 /* Invoke System fault event callback */
10470 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10471 hhrtim->DLLCalibrationReadyCallback(hhrtim);
10472 #else
10473 HAL_HRTIM_DLLCalibrationReadyCallback(hhrtim);
10474 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10475 }
10476 }
10477
10478 /* Burst mode period event */
10479 if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
10480 {
10481 if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
10482 {
10483 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
10484
10485 /* Invoke Burst mode period event callback */
10486 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10487 hhrtim->BurstModePeriodCallback(hhrtim);
10488 #else
10489 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
10490 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10491 }
10492 }
10493
10494 /* Master timer compare 1 event */
10495 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
10496 {
10497 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
10498 {
10499 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
10500
10501 /* Invoke compare 1 event callback */
10502 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10503 hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10504 #else
10505 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10506 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10507 }
10508 }
10509
10510 /* Master timer compare 2 event */
10511 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
10512 {
10513 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
10514 {
10515 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
10516
10517 /* Invoke compare 2 event callback */
10518 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10519 hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10520 #else
10521 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10522 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10523 }
10524 }
10525
10526 /* Master timer compare 3 event */
10527 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
10528 {
10529 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
10530 {
10531 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
10532
10533 /* Invoke compare 3 event callback */
10534 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10535 hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10536 #else
10537 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10538 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10539 }
10540 }
10541
10542 /* Master timer compare 4 event */
10543 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
10544 {
10545 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
10546 {
10547 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
10548
10549 /* Invoke compare 4 event callback */
10550 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10551 hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10552 #else
10553 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10554 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10555 }
10556 }
10557
10558 /* Master timer repetition event */
10559 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
10560 {
10561 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
10562 {
10563 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
10564
10565 /* Invoke repetition event callback */
10566 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10567 hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10568 #else
10569 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10570 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10571 }
10572 }
10573
10574 /* Synchronization input event */
10575 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
10576 {
10577 if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
10578 {
10579 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
10580
10581 /* Invoke synchronization event callback */
10582 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10583 hhrtim->SynchronizationEventCallback(hhrtim);
10584 #else
10585 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
10586 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10587 }
10588 }
10589
10590 /* Master timer registers update event */
10591 if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
10592 {
10593 if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
10594 {
10595 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
10596
10597 /* Invoke registers update event callback */
10598 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10599 hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10600 #else
10601 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10602 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10603 }
10604 }
10605 }
10606
10607 /**
10608 * @brief Timer interrupts service routine
10609 * @param hhrtim pointer to HAL HRTIM handle
10610 * @param TimerIdx Timer index
10611 * This parameter can be one of the following values:
10612 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
10613 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
10614 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
10615 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
10616 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
10617 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
10618 * @retval None
10619 */
HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,uint32_t TimerIdx)10620 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
10621 uint32_t TimerIdx)
10622 {
10623 uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
10624 uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
10625
10626 /* Timer compare 1 event */
10627 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
10628 {
10629 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
10630 {
10631 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
10632
10633 /* Invoke compare 1 event callback */
10634 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10635 hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
10636 #else
10637 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
10638 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10639 }
10640 }
10641
10642 /* Timer compare 2 event */
10643 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
10644 {
10645 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
10646 {
10647 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
10648
10649 /* Invoke compare 2 event callback */
10650 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10651 hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
10652 #else
10653 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
10654 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10655 }
10656 }
10657
10658 /* Timer compare 3 event */
10659 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
10660 {
10661 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
10662 {
10663 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
10664
10665 /* Invoke compare 3 event callback */
10666 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10667 hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
10668 #else
10669 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
10670 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10671 }
10672 }
10673
10674 /* Timer compare 4 event */
10675 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
10676 {
10677 if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
10678 {
10679 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
10680
10681 /* Invoke compare 4 event callback */
10682 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10683 hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
10684 #else
10685 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
10686 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10687 }
10688 }
10689
10690 /* Timer repetition event */
10691 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
10692 {
10693 if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
10694 {
10695 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
10696
10697 /* Invoke repetition event callback */
10698 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10699 hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
10700 #else
10701 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
10702 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10703 }
10704 }
10705
10706 /* Timer registers update event */
10707 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
10708 {
10709 if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
10710 {
10711 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
10712
10713 /* Invoke registers update event callback */
10714 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10715 hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
10716 #else
10717 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
10718 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10719 }
10720 }
10721
10722 /* Timer capture 1 event */
10723 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
10724 {
10725 if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
10726 {
10727 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
10728
10729 /* Invoke capture 1 event callback */
10730 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10731 hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
10732 #else
10733 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
10734 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10735 }
10736 }
10737
10738 /* Timer capture 2 event */
10739 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
10740 {
10741 if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
10742 {
10743 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
10744
10745 /* Invoke capture 2 event callback */
10746 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10747 hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
10748 #else
10749 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
10750 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10751 }
10752 }
10753
10754 /* Timer output 1 set event */
10755 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
10756 {
10757 if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
10758 {
10759 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
10760
10761 /* Invoke output 1 set event callback */
10762 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10763 hhrtim->Output1SetCallback(hhrtim, TimerIdx);
10764 #else
10765 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
10766 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10767 }
10768 }
10769
10770 /* Timer output 1 reset event */
10771 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
10772 {
10773 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
10774 {
10775 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
10776
10777 /* Invoke output 1 reset event callback */
10778 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10779 hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
10780 #else
10781 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
10782 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10783 }
10784 }
10785
10786 /* Timer output 2 set event */
10787 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
10788 {
10789 if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
10790 {
10791 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
10792
10793 /* Invoke output 2 set event callback */
10794 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10795 hhrtim->Output2SetCallback(hhrtim, TimerIdx);
10796 #else
10797 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
10798 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10799 }
10800 }
10801
10802 /* Timer output 2 reset event */
10803 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
10804 {
10805 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
10806 {
10807 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
10808
10809 /* Invoke output 2 reset event callback */
10810 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10811 hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
10812 #else
10813 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
10814 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10815 }
10816 }
10817
10818 /* Timer reset event */
10819 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
10820 {
10821 if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
10822 {
10823 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
10824
10825 /* Invoke timer reset callback */
10826 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10827 hhrtim->CounterResetCallback(hhrtim, TimerIdx);
10828 #else
10829 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
10830 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10831 }
10832 }
10833
10834 /* Delayed protection event */
10835 if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
10836 {
10837 if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
10838 {
10839 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
10840
10841 /* Invoke delayed protection callback */
10842 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10843 hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
10844 #else
10845 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
10846 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10847 }
10848 }
10849 }
10850
10851 /**
10852 * @brief DMA callback invoked upon master timer related DMA request completion
10853 * @param hdma pointer to DMA handle.
10854 * @retval None
10855 */
HRTIM_DMAMasterCplt(DMA_HandleTypeDef * hdma)10856 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
10857 {
10858 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
10859
10860 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
10861 {
10862 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10863 hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10864 #else
10865 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10866 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10867 }
10868 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
10869 {
10870 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10871 hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10872 #else
10873 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10874 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10875 }
10876 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
10877 {
10878 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10879 hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10880 #else
10881 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10882 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10883 }
10884 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
10885 {
10886 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10887 hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10888 #else
10889 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10890 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10891 }
10892 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
10893 {
10894 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10895 hrtim->SynchronizationEventCallback(hrtim);
10896 #else
10897 HAL_HRTIM_SynchronizationEventCallback(hrtim);
10898 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10899 }
10900 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
10901 {
10902 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10903 hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10904 #else
10905 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10906 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10907 }
10908 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
10909 {
10910 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10911 hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10912 #else
10913 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10914 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10915 }
10916 else
10917 {
10918 /* nothing to do */
10919 }
10920 }
10921
10922 /**
10923 * @brief DMA callback invoked upon timer A..F related DMA request completion
10924 * @param hdma pointer to DMA handle.
10925 * @retval None
10926 */
HRTIM_DMATimerxCplt(DMA_HandleTypeDef * hdma)10927 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
10928 {
10929 uint8_t timer_idx;
10930
10931 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
10932
10933 timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
10934
10935 if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;}
10936
10937 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
10938 {
10939 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10940 hrtim->Compare1EventCallback(hrtim, timer_idx);
10941 #else
10942 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
10943 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10944 }
10945 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
10946 {
10947 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10948 hrtim->Compare2EventCallback(hrtim, timer_idx);
10949 #else
10950 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
10951 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10952 }
10953 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
10954 {
10955 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10956 hrtim->Compare3EventCallback(hrtim, timer_idx);
10957 #else
10958 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
10959 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10960 }
10961 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
10962 {
10963 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10964 hrtim->Compare4EventCallback(hrtim, timer_idx);
10965 #else
10966 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
10967 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10968 }
10969 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
10970 {
10971 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10972 hrtim->RegistersUpdateCallback(hrtim, timer_idx);
10973 #else
10974 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
10975 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10976 }
10977 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
10978 {
10979 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10980 hrtim->Capture1EventCallback(hrtim, timer_idx);
10981 #else
10982 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
10983 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10984 }
10985 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
10986 {
10987 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10988 hrtim->Capture2EventCallback(hrtim, timer_idx);
10989 #else
10990 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
10991 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10992 }
10993 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
10994 {
10995 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10996 hrtim->Output1SetCallback(hrtim, timer_idx);
10997 #else
10998 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
10999 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11000 }
11001 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
11002 {
11003 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11004 hrtim->Output1ResetCallback(hrtim, timer_idx);
11005 #else
11006 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
11007 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11008 }
11009 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
11010 {
11011 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11012 hrtim->Output2SetCallback(hrtim, timer_idx);
11013 #else
11014 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
11015 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11016 }
11017 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
11018 {
11019 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11020 hrtim->Output2ResetCallback(hrtim, timer_idx);
11021 #else
11022 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
11023 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11024 }
11025 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
11026 {
11027 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11028 hrtim->CounterResetCallback(hrtim, timer_idx);
11029 #else
11030 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
11031 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11032 }
11033 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
11034 {
11035 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11036 hrtim->DelayedProtectionCallback(hrtim, timer_idx);
11037 #else
11038 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
11039 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11040 }
11041 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
11042 {
11043 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11044 hrtim->RepetitionEventCallback(hrtim, timer_idx);
11045 #else
11046 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
11047 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11048 }
11049 else
11050 {
11051 /* nothing to do */
11052 }
11053 }
11054
11055 /**
11056 * @brief DMA error callback
11057 * @param hdma pointer to DMA handle.
11058 * @retval None
11059 */
HRTIM_DMAError(DMA_HandleTypeDef * hdma)11060 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
11061 {
11062 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
11063
11064 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11065 hrtim->ErrorCallback(hrtim);
11066 #else
11067 HAL_HRTIM_ErrorCallback(hrtim);
11068 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11069 }
11070
11071 /**
11072 * @brief DMA callback invoked upon burst DMA transfer completion
11073 * @param hdma pointer to DMA handle.
11074 * @retval None
11075 */
HRTIM_BurstDMACplt(DMA_HandleTypeDef * hdma)11076 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
11077 {
11078 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
11079
11080 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11081 hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
11082 #else
11083 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
11084 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11085 }
11086
11087 /**
11088 * @}
11089 */
11090
11091 /**
11092 * @}
11093 */
11094
11095 #endif /* HRTIM1 */
11096
11097 #endif /* HAL_HRTIM_MODULE_ENABLED */
11098
11099 /**
11100 * @}
11101 */
11102
