1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal_gtzc.h 4 * @author MCD Application Team 5 * @brief Header file of GTZC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32U5xx_HAL_GTZC_H 21 #define STM32U5xx_HAL_GTZC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32u5xx_hal_def.h" 29 30 /** @addtogroup STM32U5xx_HAL_Driver 31 * @{ 32 */ 33 34 /** @addtogroup GTZC 35 * @{ 36 */ 37 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup GTZC_Exported_Types GTZC Exported Types 41 * @{ 42 */ 43 44 /*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ 45 #define GTZC_MCPBB_NB_VCTR_REG_MAX (32U) 46 #define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX (1U) 47 typedef struct 48 { 49 uint32_t MPCBB_SecConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for 50 a super-block. Each bit corresponds to a block 51 inside the super-block. 0 means non-secure, 52 1 means secure */ 53 uint32_t MPCBB_PrivConfig_array[GTZC_MCPBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for 54 a super-block. Each bit corresponds to a block 55 inside the super-block. 0 means non-privilege, 56 1 means privilege */ 57 uint32_t MPCBB_LockConfig_array[GTZC_MCPBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of 58 a super-block (32 blocks). 0 means unlocked, 59 1 means locked */ 60 } MPCBB_Attribute_ConfigTypeDef; 61 62 typedef struct 63 { 64 uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access 65 field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ 66 uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). 67 It can be a value of @ref GTZC_MPCBB_InvertSecureState */ 68 MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ 69 } MPCBB_ConfigTypeDef; 70 71 typedef struct 72 { 73 uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref 74 GTZC_MPCWM_AreaId */ 75 uint32_t Offset; /*!< Offset of the watermark area, starting from the selected 76 memory base address. It must aligned on 128KB for FMC 77 and OCTOSPI memories, and on 32-byte for BKPSRAM */ 78 uint32_t Length; /*!< Length of the watermark area, starting from the selected 79 Offset. It must aligned on 128KB for FMC and OCTOSPI 80 memories, and on 32-byte for BKPSRAM */ 81 uint32_t Attribute; /*!< Attributes of the watermark area. It can be a value 82 of @ref GTZC_MPCWM_Attribute */ 83 uint32_t Lock; /*!< Lock of the watermark area. It can be a value 84 of @ref GTZC_MPCWM_Lock */ 85 uint32_t AreaStatus; /*!< Status of the watermark area. It can be set to 86 ENABLE or DISABLE */ 87 } MPCWM_ConfigTypeDef; 88 89 /** 90 * @} 91 */ 92 93 /* Private constants ---------------------------------------------------------*/ 94 95 /** @defgroup GTZC_Private_Constants GTZC Private Constants 96 * @{ 97 */ 98 99 /** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition 100 * @{ 101 */ 102 103 /* composition definition for Peripheral identifier parameter (PeriphId) used in 104 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 105 * functions and also in all HAL_GTZC_TZIC relative functions. 106 * Bitmap Definition 107 * bits[31:28] Field "register". Define the register index a peripheral belongs to. 108 * Each bit is dedicated to a single register. 109 * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets 110 * all peripherals within all registers. 111 * bits[4:0] Field "bit position". Define the bit position within the 112 * register dedicated to the peripheral, value from 0 to 31. 113 */ 114 #define GTZC_PERIPH_REG_SHIFT (28U) 115 #define GTZC_PERIPH_REG (0xF0000000U) 116 #define GTZC1_PERIPH_REG1 (0x00000000U) 117 #define GTZC1_PERIPH_REG2 (0x10000000U) 118 #define GTZC1_PERIPH_REG3 (0x20000000U) 119 #define GTZC1_PERIPH_REG4 (0x30000000U) 120 #define GTZC2_PERIPH_REG1 (0x40000000U) 121 #define GTZC2_PERIPH_REG2 (0x50000000U) 122 #define GTZC_PERIPH_BIT_POSITION (0x0000001FU) 123 124 /** 125 * @} 126 */ 127 128 /** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks 129 * @{ 130 */ 131 #define GTZC_ATTR_SEC_MASK 0x100U 132 #define GTZC_ATTR_PRIV_MASK 0x200U 133 134 /** 135 * @} 136 */ 137 138 /** 139 * @} 140 */ 141 142 /* Exported constants --------------------------------------------------------*/ 143 144 /** @defgroup GTZC_Exported_Constants GTZC Exported Constants 145 * @{ 146 */ 147 148 /** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values 149 * @{ 150 */ 151 152 #define GTZC_MPCBB_SRWILADIS_ENABLE (0U) 153 #define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) 154 155 /** 156 * @} 157 */ 158 159 /** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values 160 * @{ 161 */ 162 163 #define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) 164 #define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) 165 166 /** 167 * @} 168 */ 169 170 /** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values 171 * @{ 172 */ 173 174 #define GTZC_TZSC_MPCWM_ID1 (0U) 175 #define GTZC_TZSC_MPCWM_ID2 (1U) 176 177 /** 178 * @} 179 */ 180 181 /** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values 182 * @{ 183 */ 184 /* GTZC1 */ 185 #define GTZC_PERIPH_TIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) 186 #define GTZC_PERIPH_TIM3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) 187 #define GTZC_PERIPH_TIM4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos) 188 #define GTZC_PERIPH_TIM5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos) 189 #define GTZC_PERIPH_TIM6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos) 190 #define GTZC_PERIPH_TIM7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos) 191 #define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) 192 #define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) 193 #define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) 194 #define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) 195 #define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) 196 #define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos) 197 #define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos) 198 #define GTZC_PERIPH_I2C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) 199 #define GTZC_PERIPH_I2C2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos) 200 #define GTZC_PERIPH_CRS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos) 201 #define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos) 202 #define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) 203 #define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos) 204 #define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos) 205 #define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) 206 #define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) 207 #define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos) 208 #define GTZC_PERIPH_USART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) 209 #define GTZC_PERIPH_TIM15 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos) 210 #define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) 211 #define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) 212 #define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) 213 #define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos) 214 #define GTZC_PERIPH_MDF1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_MDF1_Pos) 215 #define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos) 216 #define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos) 217 #define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) 218 #define GTZC_PERIPH_TSC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) 219 #define GTZC_PERIPH_DMA2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DMA2D_Pos) 220 #define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) 221 #define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos) 222 #define GTZC_PERIPH_ADC12 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos) 223 #define GTZC_PERIPH_DCMI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos) 224 #define GTZC_PERIPH_OTG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OTG_Pos) 225 #define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) 226 #define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) 227 #define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) 228 #define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) 229 #define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) 230 #define GTZC_PERIPH_OCTOSPIM (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPIM_Pos) 231 #define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos) 232 #define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos) 233 #define GTZC_PERIPH_FSMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FSMC_REG_Pos) 234 #define GTZC_PERIPH_OCTOSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos) 235 #define GTZC_PERIPH_OCTOSPI2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI2_REG_Pos) 236 #define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) 237 #define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) 238 #define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) 239 #define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) 240 #define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos) 241 #define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos) 242 #define GTZC_PERIPH_TZSC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC1_Pos) 243 #define GTZC_PERIPH_TZIC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC1_Pos) 244 #define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos) 245 #define GTZC_PERIPH_FSMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FSMC_MEM_Pos) 246 #define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos) 247 #define GTZC_PERIPH_OCTOSPI2_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI2_MEM_Pos) 248 #define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) 249 #define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) 250 #define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) 251 #define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) 252 #define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos) 253 #define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos) 254 255 /* GTZC2 */ 256 #define GTZC_PERIPH_SPI3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos) 257 #define GTZC_PERIPH_LPUART1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPUART1_Pos) 258 #define GTZC_PERIPH_I2C3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_I2C3_Pos) 259 #define GTZC_PERIPH_LPTIM1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM1_Pos) 260 #define GTZC_PERIPH_LPTIM3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM3_Pos) 261 #define GTZC_PERIPH_LPTIM4 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM4_Pos) 262 #define GTZC_PERIPH_OPAMP (GTZC2_PERIPH_REG1 | GTZC_CFGR1_OPAMP_Pos) 263 #define GTZC_PERIPH_COMP (GTZC2_PERIPH_REG1 | GTZC_CFGR1_COMP_Pos) 264 #define GTZC_PERIPH_ADC4 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_ADC4_Pos) 265 #define GTZC_PERIPH_VREFBUF (GTZC2_PERIPH_REG1 | GTZC_CFGR1_VREFBUF_Pos) 266 #define GTZC_PERIPH_DAC1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_DAC1_Pos) 267 #define GTZC_PERIPH_ADF1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_ADF1_Pos) 268 #define GTZC_PERIPH_SYSCFG (GTZC2_PERIPH_REG2 | GTZC_CFGR2_SYSCFG_Pos) 269 #define GTZC_PERIPH_RTC (GTZC2_PERIPH_REG2 | GTZC_CFGR2_RTC_Pos) 270 #define GTZC_PERIPH_TAMP (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TAMP_Pos) 271 #define GTZC_PERIPH_PWR (GTZC2_PERIPH_REG2 | GTZC_CFGR2_PWR_Pos) 272 #define GTZC_PERIPH_RCC (GTZC2_PERIPH_REG2 | GTZC_CFGR2_RCC_Pos) 273 #define GTZC_PERIPH_LPDMA1 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_LPDMA1_Pos) 274 #define GTZC_PERIPH_EXTI (GTZC2_PERIPH_REG2 | GTZC_CFGR2_EXTI_Pos) 275 #define GTZC_PERIPH_TZSC2 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TZSC2_Pos) 276 #define GTZC_PERIPH_TZIC2 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TZIC2_Pos) 277 #define GTZC_PERIPH_SRAM4 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_SRAM4_Pos) 278 #define GTZC_PERIPH_MPCBB4_REG (GTZC2_PERIPH_REG2 | GTZC_CFGR2_MPCBB4_REG_Pos) 279 280 #define GTZC_PERIPH_ALL (0x00000020U) 281 282 /* Note that two maximum values are also defined here: 283 * - max number of securable AHB/APB peripherals or masters 284 * (used in TZSC sub-block) 285 * - max number of securable and TrustZone-aware AHB/APB peripherals or masters 286 * (used in TZIC sub-block) 287 */ 288 #define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_TZSC_GET_ARRAY_INDEX(GTZC_PERIPH_ADF1 + 1U)) 289 #define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_TZIC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB4_REG + 1U)) 290 291 /** 292 * @} 293 */ 294 295 /** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values 296 * @{ 297 */ 298 299 /* user-oriented definitions for attribute parameter (PeriphAttributes) used in 300 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 301 * functions 302 */ 303 #define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ 304 #define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ 305 #define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ 306 #define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ 307 308 /** 309 * @} 310 */ 311 312 /** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values 313 * @{ 314 */ 315 316 /* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ 317 #define GTZC_TZSC_LOCK_OFF (0U) 318 #define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk 319 320 /** 321 * @} 322 */ 323 324 /** @defgroup GTZC_MPCWM_Group GTZC MPCWM values 325 * @{ 326 */ 327 328 /* user-oriented definitions for TZSC_MPCWM */ 329 #define GTZC_TZSC_MPCWM_GRANULARITY_1 0x00020000U /* OCTOSPI & FMC granularity: 128 kbytes */ 330 #define GTZC_TZSC_MPCWM_GRANULARITY_2 0x00000020U /* BKPSRAM granularity: 32 bytes */ 331 332 /** 333 * @} 334 */ 335 336 /** @defgroup GTZC_MPCWM_Lock GTZC MPCWM Lock values 337 * @{ 338 */ 339 340 /* user-oriented definitions for TZSC_MPCWM */ 341 #define GTZC_TZSC_MPCWM_LOCK_OFF (0U) 342 #define GTZC_TZSC_MPCWM_LOCK_ON GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk 343 344 /** 345 * @} 346 */ 347 348 /** @defgroup GTZC_MPCWM_Attribute GTZC MPCWM Attribute values 349 * @{ 350 */ 351 352 /* user-oriented definitions for TZSC_MPCWM */ 353 #define GTZC_TZSC_MPCWM_REGION_NSEC (0U) 354 #define GTZC_TZSC_MPCWM_REGION_SEC (1U) 355 #define GTZC_TZSC_MPCWM_REGION_NPRIV (0U) 356 #define GTZC_TZSC_MPCWM_REGION_PRIV (2U) 357 358 /** 359 * @} 360 */ 361 362 /** @defgroup GTZC_MPCBB_Group GTZC MPCBB values 363 * @{ 364 */ 365 366 /* user-oriented definitions for MPCBB */ 367 #define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ 368 #define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ 369 #define GTZC_MCPBB_SUPERBLOCK_UNLOCKED (0U) 370 #define GTZC_MCPBB_SUPERBLOCK_LOCKED (1U) 371 372 #define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) 373 #define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) 374 #define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) 375 #define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) 376 377 /* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ 378 #define GTZC_MCPBB_LOCK_OFF (0U) 379 #define GTZC_MCPBB_LOCK_ON (1U) 380 381 /** 382 * @} 383 */ 384 385 /** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values 386 * @{ 387 */ 388 389 /* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ 390 #define GTZC_TZIC_NO_ILA_EVENT (0U) 391 #define GTZC_TZIC_ILA_EVENT_PENDING (1U) 392 393 /** 394 * @} 395 */ 396 397 /** 398 * @} 399 */ 400 401 /* Private macros ------------------------------------------------------------*/ 402 403 /** @defgroup GTZC_Private_Macros GTZC Private Macros 404 * @{ 405 */ 406 407 /* retrieve information to access register for a specific PeriphId */ 408 #define GTZC_GET_REG_INDEX(periph_id)\ 409 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) 410 #define GTZC_GET_REG_INDEX_IN_INSTANCE(periph_id)\ 411 ((((periph_id) & GTZC_PERIPH_REG) <= GTZC1_PERIPH_REG4) ? \ 412 (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) : \ 413 ((((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) - 4U)) 414 #define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) 415 416 #define IS_GTZC_BASE_ADDRESS(mem, address)\ 417 ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ 418 ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) 419 420 #define GTZC_MEM_SIZE(mem)\ 421 ( mem ## _SIZE ) 422 423 #define GTZC_BASE_ADDRESS_S(mem)\ 424 ( mem ## _BASE_S ) 425 426 #define GTZC_BASE_ADDRESS_NS(mem)\ 427 ( mem ## _BASE_NS ) 428 429 /** 430 * @} 431 */ 432 433 /* Exported macros -----------------------------------------------------------*/ 434 435 /** @defgroup GTZC_Exported_Macros GTZC Exported Macros 436 * @{ 437 */ 438 439 /* user-oriented macro to get array index of a specific PeriphId 440 * in case of GTZC_PERIPH_ALL usage in the two following functions: 441 * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() 442 */ 443 #define HAL_GTZC_TZSC_GET_ARRAY_INDEX(periph_id) \ 444 (uint32_t)((HAL_GTZC_TZSC_GET_INSTANCE(periph_id) == GTZC_TZSC1)? \ 445 ((GTZC_GET_REG_INDEX(periph_id) * 32U) + GTZC_GET_PERIPH_POS(periph_id)) : \ 446 (((GTZC_GET_REG_INDEX(periph_id) - 1U) * 32U) + GTZC_GET_PERIPH_POS(periph_id) )) 447 448 #define HAL_GTZC_TZIC_GET_ARRAY_INDEX(periph_id) \ 449 ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) ) 450 451 /* user-oriented macro to get TZSC instance of a specific PeriphId */ 452 #define HAL_GTZC_TZSC_GET_INSTANCE(periph_id) \ 453 ((GTZC_GET_REG_INDEX(periph_id) <= (GTZC1_PERIPH_REG4 >> GTZC_PERIPH_REG_SHIFT))? \ 454 GTZC_TZSC1 : GTZC_TZSC2) 455 456 /* user-oriented macro to get TZIC instance of a specific PeriphId */ 457 #define HAL_GTZC_TZIC_GET_INSTANCE(periph_id) \ 458 ((GTZC_GET_REG_INDEX(periph_id) <= (GTZC1_PERIPH_REG4>> GTZC_PERIPH_REG_SHIFT))? \ 459 GTZC_TZIC1 : GTZC_TZIC2) 460 461 /** 462 * @} 463 */ 464 465 /* Exported functions --------------------------------------------------------*/ 466 467 /** @addtogroup GTZC_Exported_Functions 468 * @{ 469 */ 470 471 /** @addtogroup GTZC_Exported_Functions_Group1 472 * @brief TZSC Initialization and Configuration functions 473 * @{ 474 */ 475 476 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, 477 uint32_t PeriphAttributes); 478 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, 479 uint32_t *PeriphAttributes); 480 481 /** 482 * @} 483 */ 484 485 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 486 487 /** @addtogroup GTZC_Exported_Functions_Group2 488 * @brief MPCWM Initialization and Configuration functions 489 * @{ 490 */ 491 492 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, 493 MPCWM_ConfigTypeDef *pMPCWM_Desc); 494 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, 495 MPCWM_ConfigTypeDef *pMPCWM_Desc); 496 /** 497 * @} 498 */ 499 500 /** @addtogroup GTZC_Exported_Functions_Group3 501 * @brief TZSC and TZSC-MPCWM Lock functions 502 * @{ 503 */ 504 505 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); 506 uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSC_Instance); 507 508 /** 509 * @} 510 */ 511 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 512 /** @addtogroup GTZC_Exported_Functions_Group4 513 * @brief MPCBB Initialization and Configuration functions 514 * @{ 515 */ 516 517 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, 518 MPCBB_ConfigTypeDef *pMPCBB_desc); 519 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, 520 MPCBB_ConfigTypeDef *pMPCBB_desc); 521 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, 522 uint32_t NbBlocks, 523 uint32_t *pMemAttributes); 524 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, 525 uint32_t NbBlocks, 526 uint32_t *pMemAttributes); 527 528 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 529 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, 530 uint32_t NbSuperBlocks, 531 uint32_t *pLockAttributes); 532 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, 533 uint32_t NbSuperBlocks, 534 uint32_t *pLockAttributes); 535 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); 536 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, 537 uint32_t *pLockState); 538 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 539 540 /** 541 * @} 542 */ 543 544 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 545 546 /** @addtogroup GTZC_Exported_Functions_Group5 547 * @brief TZIC functions 548 * @{ 549 */ 550 551 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); 552 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); 553 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); 554 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); 555 556 /** 557 * @} 558 */ 559 560 /** @addtogroup GTZC_Exported_Functions_Group6 561 * @brief IRQ related Functions 562 * @{ 563 */ 564 565 void HAL_GTZC_IRQHandler(void); 566 void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); 567 568 /** 569 * @} 570 */ 571 572 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ 573 574 /** 575 * @} 576 */ 577 578 /** 579 * @} 580 */ 581 582 /** 583 * @} 584 */ 585 586 #ifdef __cplusplus 587 } 588 #endif 589 590 #endif /* STM32U5xx_HAL_GTZC_H */ 591 592
