1 /** 2 ****************************************************************************** 3 * @file stm32f4xx_hal_fmpsmbus.h 4 * @author MCD Application Team 5 * @brief Header file of FMPSMBUS HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2016 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32F4xx_HAL_FMPSMBUS_H 21 #define STM32F4xx_HAL_FMPSMBUS_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 #if defined(FMPI2C_CR1_PE) 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32f4xx_hal_def.h" 30 31 /** @addtogroup STM32F4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FMPSMBUS 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types 41 * @{ 42 */ 43 44 /** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition 45 * @brief FMPSMBUS Configuration Structure definition 46 * @{ 47 */ 48 typedef struct 49 { 50 uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value. 51 This parameter calculated by referring to FMPSMBUS initialization section 52 in Reference manual */ 53 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 54 This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ 55 56 uint32_t OwnAddress1; /*!< Specifies the first device own address. 57 This parameter can be a 7-bit or 10-bit address. */ 58 59 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 60 This parameter can be a value of @ref FMPSMBUS_addressing_mode */ 61 62 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 63 This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ 64 65 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 66 This parameter can be a 7-bit address. */ 67 68 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address 69 if dual addressing mode is selected 70 This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ 71 72 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 73 This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ 74 75 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 76 This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ 77 78 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 79 This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ 80 81 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 82 This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ 83 84 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value. 85 (Enable bits and different timeout values) 86 This parameter calculated by referring to FMPSMBUS initialization section 87 in Reference manual */ 88 } FMPSMBUS_InitTypeDef; 89 /** 90 * @} 91 */ 92 93 /** @defgroup HAL_state_definition HAL state definition 94 * @brief HAL State definition 95 * @{ 96 */ 97 #define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */ 98 #define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */ 99 #define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */ 100 #define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 101 #define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 102 #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 103 #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 104 #define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 105 /** 106 * @} 107 */ 108 109 /** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition 110 * @brief FMPSMBUS Error Code definition 111 * @{ 112 */ 113 #define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 114 #define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 115 #define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 116 #define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 117 #define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 118 #define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 119 #define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 120 #define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 121 #define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 122 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 123 #define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 124 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 125 #define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 126 /** 127 * @} 128 */ 129 130 /** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition 131 * @brief FMPSMBUS handle Structure definition 132 * @{ 133 */ 134 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 135 typedef struct __FMPSMBUS_HandleTypeDef 136 #else 137 typedef struct 138 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 139 { 140 FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */ 141 142 FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */ 143 144 uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */ 145 146 uint16_t XferSize; /*!< FMPSMBUS transfer size */ 147 148 __IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */ 149 150 __IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */ 151 152 __IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */ 153 154 HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */ 155 156 __IO uint32_t State; /*!< FMPSMBUS communication state */ 157 158 __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */ 159 160 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 161 void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 162 /*!< FMPSMBUS Master Tx Transfer completed callback */ 163 void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 164 /*!< FMPSMBUS Master Rx Transfer completed callback */ 165 void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 166 /*!< FMPSMBUS Slave Tx Transfer completed callback */ 167 void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 168 /*!< FMPSMBUS Slave Rx Transfer completed callback */ 169 void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 170 /*!< FMPSMBUS Listen Complete callback */ 171 void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 172 /*!< FMPSMBUS Error callback */ 173 174 void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 175 /*!< FMPSMBUS Slave Address Match callback */ 176 177 void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 178 /*!< FMPSMBUS Msp Init callback */ 179 void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 180 /*!< FMPSMBUS Msp DeInit callback */ 181 182 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 183 } FMPSMBUS_HandleTypeDef; 184 185 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 186 /** 187 * @brief HAL FMPSMBUS Callback ID enumeration definition 188 */ 189 typedef enum 190 { 191 HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */ 192 HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */ 193 HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */ 194 HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */ 195 HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */ 196 HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */ 197 198 HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */ 199 HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */ 200 201 } HAL_FMPSMBUS_CallbackIDTypeDef; 202 203 /** 204 * @brief HAL FMPSMBUS Callback pointer definition 205 */ 206 typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); 207 /*!< pointer to an FMPSMBUS callback function */ 208 typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, 209 uint16_t AddrMatchCode); 210 /*!< pointer to an FMPSMBUS Address Match callback function */ 211 212 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 213 /** 214 * @} 215 */ 216 217 /** 218 * @} 219 */ 220 /* Exported constants --------------------------------------------------------*/ 221 222 /** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants 223 * @{ 224 */ 225 226 /** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter 227 * @{ 228 */ 229 #define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U) 230 #define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF 231 /** 232 * @} 233 */ 234 235 /** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode 236 * @{ 237 */ 238 #define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 239 #define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U) 240 /** 241 * @} 242 */ 243 244 /** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode 245 * @{ 246 */ 247 248 #define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U) 249 #define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN 250 /** 251 * @} 252 */ 253 254 /** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks 255 * @{ 256 */ 257 258 #define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U) 259 #define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U) 260 #define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U) 261 #define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U) 262 #define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U) 263 #define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U) 264 #define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U) 265 #define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U) 266 /** 267 * @} 268 */ 269 270 271 /** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode 272 * @{ 273 */ 274 #define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U) 275 #define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN 276 /** 277 * @} 278 */ 279 280 /** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode 281 * @{ 282 */ 283 #define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U) 284 #define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH 285 /** 286 * @} 287 */ 288 289 /** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode 290 * @{ 291 */ 292 #define FMPSMBUS_PEC_DISABLE (0x00000000U) 293 #define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN 294 /** 295 * @} 296 */ 297 298 /** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode 299 * @{ 300 */ 301 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN 302 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U) 303 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN 304 /** 305 * @} 306 */ 307 308 /** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition 309 * @{ 310 */ 311 312 #define FMPSMBUS_SOFTEND_MODE (0x00000000U) 313 #define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD 314 #define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND 315 #define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE 316 /** 317 * @} 318 */ 319 320 /** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition 321 * @{ 322 */ 323 324 #define FMPSMBUS_NO_STARTSTOP (0x00000000U) 325 #define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) 326 #define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) 327 #define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) 328 /** 329 * @} 330 */ 331 332 /** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition 333 * @{ 334 */ 335 336 /* List of XferOptions in usage of : 337 * 1- Restart condition when direction change 338 * 2- No Restart condition in other use cases 339 */ 340 #define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE 341 #define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE)) 342 #define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE 343 #define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE 344 #define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE | FMPSMBUS_SENDPEC_MODE)) 345 #define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) 346 #define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) 347 348 /* List of XferOptions in usage of : 349 * 1- Restart condition in all use cases (direction change or not) 350 */ 351 #define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 352 #define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 353 #define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 354 #define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 355 /** 356 * @} 357 */ 358 359 /** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition 360 * @brief FMPSMBUS Interrupt definition 361 * Elements values convention: 0xXXXXXXXX 362 * - XXXXXXXX : Interrupt control mask 363 * @{ 364 */ 365 #define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE 366 #define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE 367 #define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE 368 #define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE 369 #define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE 370 #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE 371 #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE 372 #define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \ 373 FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) 374 #define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \ 375 FMPSMBUS_IT_RXI) 376 #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) 377 #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) 378 /** 379 * @} 380 */ 381 382 /** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition 383 * @brief Flag definition 384 * Elements values convention: 0xXXXXYYYY 385 * - XXXXXXXX : Flag mask 386 * @{ 387 */ 388 389 #define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE 390 #define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS 391 #define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE 392 #define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR 393 #define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF 394 #define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF 395 #define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC 396 #define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR 397 #define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR 398 #define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO 399 #define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR 400 #define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR 401 #define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT 402 #define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT 403 #define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY 404 #define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR 405 /** 406 * @} 407 */ 408 409 /** 410 * @} 411 */ 412 413 /* Exported macros ------------------------------------------------------------*/ 414 /** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros 415 * @{ 416 */ 417 418 /** @brief Reset FMPSMBUS handle state. 419 * @param __HANDLE__ specifies the FMPSMBUS Handle. 420 * @retval None 421 */ 422 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 423 #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 424 (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ 425 (__HANDLE__)->MspInitCallback = NULL; \ 426 (__HANDLE__)->MspDeInitCallback = NULL; \ 427 } while(0) 428 #else 429 #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) 430 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 431 432 /** @brief Enable the specified FMPSMBUS interrupts. 433 * @param __HANDLE__ specifies the FMPSMBUS Handle. 434 * @param __INTERRUPT__ specifies the interrupt source to enable. 435 * This parameter can be one of the following values: 436 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 437 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 438 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 439 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 440 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 441 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 442 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 443 * 444 * @retval None 445 */ 446 #define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 447 448 /** @brief Disable the specified FMPSMBUS interrupts. 449 * @param __HANDLE__ specifies the FMPSMBUS Handle. 450 * @param __INTERRUPT__ specifies the interrupt source to disable. 451 * This parameter can be one of the following values: 452 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 453 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 454 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 455 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 456 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 457 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 458 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 459 * 460 * @retval None 461 */ 462 #define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 463 464 /** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not. 465 * @param __HANDLE__ specifies the FMPSMBUS Handle. 466 * @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check. 467 * This parameter can be one of the following values: 468 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 469 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 470 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 471 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 472 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 473 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 474 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 475 * 476 * @retval The new state of __IT__ (SET or RESET). 477 */ 478 #define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 479 ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 480 481 /** @brief Check whether the specified FMPSMBUS flag is set or not. 482 * @param __HANDLE__ specifies the FMPSMBUS Handle. 483 * @param __FLAG__ specifies the flag to check. 484 * This parameter can be one of the following values: 485 * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty 486 * @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status 487 * @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty 488 * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) 489 * @arg @ref FMPSMBUS_FLAG_AF NACK received flag 490 * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag 491 * @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode) 492 * @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload 493 * @arg @ref FMPSMBUS_FLAG_BERR Bus error 494 * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost 495 * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun 496 * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception 497 * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 498 * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert 499 * @arg @ref FMPSMBUS_FLAG_BUSY Bus busy 500 * @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode) 501 * 502 * @retval The new state of __FLAG__ (SET or RESET). 503 */ 504 #define FMPSMBUS_FLAG_MASK (0x0001FFFFU) 505 #define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ 506 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ 507 ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) 508 509 /** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit. 510 * @param __HANDLE__ specifies the FMPSMBUS Handle. 511 * @param __FLAG__ specifies the flag to clear. 512 * This parameter can be any combination of the following values: 513 * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty 514 * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) 515 * @arg @ref FMPSMBUS_FLAG_AF NACK received flag 516 * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag 517 * @arg @ref FMPSMBUS_FLAG_BERR Bus error 518 * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost 519 * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun 520 * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception 521 * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 522 * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert 523 * 524 * @retval None 525 */ 526 #define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPSMBUS_FLAG_TXE) ? \ 527 ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ 528 ((__HANDLE__)->Instance->ICR = (__FLAG__))) 529 530 /** @brief Enable the specified FMPSMBUS peripheral. 531 * @param __HANDLE__ specifies the FMPSMBUS Handle. 532 * @retval None 533 */ 534 #define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 535 536 /** @brief Disable the specified FMPSMBUS peripheral. 537 * @param __HANDLE__ specifies the FMPSMBUS Handle. 538 * @retval None 539 */ 540 #define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 541 542 /** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode. 543 * @param __HANDLE__ specifies the FMPSMBUS Handle. 544 * @retval None 545 */ 546 #define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) 547 548 /** 549 * @} 550 */ 551 552 553 /* Private constants ---------------------------------------------------------*/ 554 555 /* Private macros ------------------------------------------------------------*/ 556 /** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros 557 * @{ 558 */ 559 560 #define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \ 561 ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) 562 563 #define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 564 565 #define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \ 566 ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) 567 568 #define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \ 569 ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) 570 571 #define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \ 572 ((MASK) == FMPSMBUS_OA2_MASK01) || \ 573 ((MASK) == FMPSMBUS_OA2_MASK02) || \ 574 ((MASK) == FMPSMBUS_OA2_MASK03) || \ 575 ((MASK) == FMPSMBUS_OA2_MASK04) || \ 576 ((MASK) == FMPSMBUS_OA2_MASK05) || \ 577 ((MASK) == FMPSMBUS_OA2_MASK06) || \ 578 ((MASK) == FMPSMBUS_OA2_MASK07)) 579 580 #define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \ 581 ((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) 582 583 #define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \ 584 ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) 585 586 #define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \ 587 ((PEC) == FMPSMBUS_PEC_ENABLE)) 588 589 #define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \ 590 ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ 591 ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) 592 593 #define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ 594 ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ 595 ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ 596 ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ 597 ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ 598 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ 599 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ 600 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ 601 FMPSMBUS_RELOAD_MODE ))) 602 603 604 #define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ 605 ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ 606 ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ 607 ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) 608 609 610 #define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ 611 ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ 612 ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ 613 ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 614 ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ 615 ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ 616 ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 617 ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) 618 619 #define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ 620 ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 621 ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ 622 ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 623 624 #define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ 625 (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ 626 FMPI2C_CR1_PECEN))) 627 #define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ 628 (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ 629 FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ 630 FMPI2C_CR2_RD_WRN))) 631 632 #define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \ 633 (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ 634 (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ 635 (~FMPI2C_CR2_RD_WRN)) : \ 636 (uint32_t)((((uint32_t)(__ADDRESS__) & \ 637 (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ 638 (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) 639 640 #define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) 641 #define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) 642 #define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) 643 #define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE) 644 #define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN) 645 646 #define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ 647 ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) 648 #define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 649 650 #define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 651 #define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 652 653 /** 654 * @} 655 */ 656 657 /* Include FMPSMBUS HAL Extended module */ 658 #include "stm32f4xx_hal_fmpsmbus_ex.h" 659 660 /* Exported functions --------------------------------------------------------*/ 661 /** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions 662 * @{ 663 */ 664 665 /** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 666 * @{ 667 */ 668 669 /* Initialization and de-initialization functions ****************************/ 670 HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus); 671 HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 672 void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 673 void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 674 HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter); 675 HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter); 676 677 /* Callbacks Register/UnRegister functions ***********************************/ 678 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 679 HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 680 HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, 681 pFMPSMBUS_CallbackTypeDef pCallback); 682 HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 683 HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); 684 685 HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 686 pFMPSMBUS_AddrCallbackTypeDef pCallback); 687 HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 688 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 689 /** 690 * @} 691 */ 692 693 /** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions 694 * @{ 695 */ 696 697 /* IO operation functions *****************************************************/ 698 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 699 * @{ 700 */ 701 /******* Blocking mode: Polling */ 702 HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, 703 uint32_t Timeout); 704 /** 705 * @} 706 */ 707 708 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 709 * @{ 710 */ 711 /******* Non-Blocking mode: Interrupt */ 712 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, 713 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 714 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, 715 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 716 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); 717 HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, 718 uint32_t XferOptions); 719 HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, 720 uint32_t XferOptions); 721 722 HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 723 HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 724 HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 725 HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 726 /** 727 * @} 728 */ 729 730 /** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 731 * @{ 732 */ 733 /******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 734 void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); 735 void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); 736 void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 737 void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 738 void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 739 void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 740 void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 741 void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 742 void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 743 744 /** 745 * @} 746 */ 747 748 /** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 749 * @{ 750 */ 751 752 /* Peripheral State and Errors functions **************************************************/ 753 uint32_t HAL_FMPSMBUS_GetState(const FMPSMBUS_HandleTypeDef *hfmpsmbus); 754 uint32_t HAL_FMPSMBUS_GetError(const FMPSMBUS_HandleTypeDef *hfmpsmbus); 755 756 /** 757 * @} 758 */ 759 760 /** 761 * @} 762 */ 763 764 /* Private Functions ---------------------------------------------------------*/ 765 /** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions 766 * @{ 767 */ 768 /* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */ 769 /** 770 * @} 771 */ 772 773 /** 774 * @} 775 */ 776 777 /** 778 * @} 779 */ 780 781 /** 782 * @} 783 */ 784 785 #endif /* FMPI2C_CR1_PE */ 786 #ifdef __cplusplus 787 } 788 #endif 789 790 791 #endif /* STM32F4xx_HAL_FMPSMBUS_H */ 792
