1 /**
2 ******************************************************************************
3 * @file stm32u5xx_hal_flash_ex.c
4 * @author MCD Application Team
5 * @brief Extended FLASH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the FLASH extended peripheral:
8 * + Extended programming operations functions
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2021 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software component is licensed by ST under BSD 3-Clause license,
17 * the "License"; You may not use this file except in compliance with the
18 * License. You may obtain a copy of the License at:
19 * opensource.org/licenses/BSD-3-Clause
20 *
21 ******************************************************************************
22 @verbatim
23 ==============================================================================
24 ##### Flash Extended features #####
25 ==============================================================================
26
27 [..] Comparing to other previous devices, the FLASH interface for STM32U5xx
28 devices contains the following additional features
29
30 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
31 capability (RWW)
32 (+) Dual bank memory organization
33 (+) Watermark-based secure area including the secure hide areas
34 (+) Block-based secure pages
35
36 ##### How to use this driver #####
37 ==============================================================================
38 [..] This driver provides functions to configure and program the FLASH memory
39 of all STM32U5xx devices. It includes:
40 (#) Flash Memory Erase functions:
41 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
42 HAL_FLASH_Lock() functions
43 (++) Erase function: page Erase and Bank/Mass Erase
44 (++) There are two modes of erase :
45 (+++) Polling Mode using HAL_FLASHEx_Erase()
46 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
47
48 (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to:
49 (++) Configure the write protection for each area
50 (++) Set the Read protection Level
51 (++) Program the user Option Bytes
52 (++) Configure the watermark security for each area including the secure hide areas
53 (++) Configure the boot lock (BOOT_LOCK)
54 (++) Configure the Boot addresses
55
56 (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to:
57 (++) Get the value of a write protection area
58 (++) Know if the read protection is activated
59 (++) Get the value of the user Option Bytes
60 (++) Get the configuration of a watermark security area including the secure hide areas
61 (++) Get the boot lock (BOOT_LOCK) configuration
62 (++) Get the value of a boot address
63
64 (#) Block-based secure / privilege area configuration function: Use HAL_FLASHEx_ConfigBBAttributes()
65 (++) Bit-field allowing to secure or un-secure each page
66 (++) Bit-field allowing to privilege or un-privilege each page
67
68 (#) Get the block-based secure / privilege area configuration function: Use HAL_FLASHEx_GetBBSec()
69 (++) Return the configuration of the block-based security and privilege for all the pages
70
71 (#) Activation of the secure hide area function: Use HAL_FLASHEx_EnableSecHideProtection()
72 (++) Deny the access to the secure hide area
73
74 (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode()
75 (++) FLASH register can be protected against non-privilege accesses
76
77 (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode()
78 (++) Return if the FLASH registers are protected against non-privilege accesses
79
80 (#) Security inversion configuration function: Use HAL_FLASHEx_ConfigSecInversion()
81 (++) FLASH secure state can be override
82
83 (#) Get the security inversion configuration function: Use HAL_FLASHEx_GetSecInversion()
84 (++) Return if FLASH secure state is override
85
86 (#) Enable bank low-power mode function: Use HAL_FLASHEx_EnablePowerDown()
87 (++) Enable low-power mode for Flash Bank 1 and/or Bank 2
88
89 (#) Enable low-power read mode function: Use HAL_FLASHEx_ConfigLowPowerRead()
90 (++) Enable low-power read mode for Flash memory
91
92 (#) Get the low-power read mode configuration function: Use HAL_FLASHEx_GetLowPowerRead()
93 (++) Return if FLASH is in low-power read mode or normal read mode
94
95 (#) Get Flash operation function: Use HAL_FLASHEx_GetOperation()
96 (++) Return information about the on-going Flash operation. After a
97 system reset, return information about the interrupted Flash operation, if any.
98
99 @endverbatim
100 ******************************************************************************
101 */
102
103 /* Includes ------------------------------------------------------------------*/
104 #include "stm32u5xx_hal.h"
105
106 /** @addtogroup STM32U5xx_HAL_Driver
107 * @{
108 */
109
110 /** @defgroup FLASHEx FLASHEx
111 * @brief FLASH Extended HAL module driver
112 * @{
113 */
114
115 #ifdef HAL_FLASH_MODULE_ENABLED
116
117 /* Private typedef -----------------------------------------------------------*/
118 /* Private define ------------------------------------------------------------*/
119 /* Private macro -------------------------------------------------------------*/
120 /* Private variables ---------------------------------------------------------*/
121 /* Private function prototypes -----------------------------------------------*/
122 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
123 * @{
124 */
125 static void FLASH_MassErase(uint32_t Banks);
126 static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset,
127 FunctionalState WRPLock);
128 static void FLASH_OB_RDPConfig(uint32_t RDPLevel);
129 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
130 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
131 static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage,
132 uint32_t WMHDPEndPage);
133 static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig);
134 #endif /* __ARM_FEATURE_CMSE */
135 static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr);
136 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset,
137 FunctionalState *WRPLock);
138 static uint32_t FLASH_OB_GetRDP(void);
139 static uint32_t FLASH_OB_GetUser(void);
140 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
141 static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage,
142 uint32_t *WMHDPEndPage);
143 static uint32_t FLASH_OB_GetBootLock(void);
144 #endif /* __ARM_FEATURE_CMSE */
145 static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr);
146 static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2);
147 /**
148 * @}
149 */
150
151 /* Exported functions -------------------------------------------------------*/
152 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
153 * @{
154 */
155
156 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
157 * @brief Extended IO operation functions
158 *
159 @verbatim
160 ===============================================================================
161 ##### Extended programming operation functions #####
162 ===============================================================================
163 [..]
164 This subsection provides a set of functions allowing to manage the Extended FLASH
165 programming operations Operations.
166
167 @endverbatim
168 * @{
169 */
170 /**
171 * @brief Perform a mass erase or erase the specified FLASH memory pages.
172 * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
173 * contains the configuration information for the erasing.
174 *
175 * @param[out] PageError pointer to variable that contains the configuration
176 * information on faulty page in case of error (0xFFFFFFFF means that all
177 * the pages have been correctly erased).
178 *
179 * @retval HAL Status
180 */
HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef * pEraseInit,uint32_t * PageError)181 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
182 {
183 HAL_StatusTypeDef status;
184 uint32_t page_index;
185 __IO uint32_t *reg_cr;
186
187 /* Check the parameters */
188 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
189
190 /* Process Locked */
191 __HAL_LOCK(&pFlash);
192
193 /* Reset error code */
194 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
195
196 /* Wait for last operation to be completed */
197 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
198
199 if (status == HAL_OK)
200 {
201 /* Current operation type */
202 pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
203
204 /* Access to SECCR or NSCR depends on operation type */
205 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR);
206
207 if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
208 {
209 /* Mass erase to be done */
210 FLASH_MassErase(pEraseInit->Banks);
211
212 /* Wait for last operation to be completed */
213 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
214 }
215 else
216 {
217 /*Initialization of PageError variable*/
218 *PageError = 0xFFFFFFFFU;
219
220 for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
221 {
222 FLASH_PageErase(page_index, pEraseInit->Banks);
223
224 /* Wait for last operation to be completed */
225 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
226
227 if (status != HAL_OK)
228 {
229 /* In case of error, stop erase procedure and return the faulty page */
230 *PageError = page_index;
231 break;
232 }
233 }
234 }
235
236 /* If the erase operation is completed, disable the associated bits */
237 CLEAR_BIT((*reg_cr), (pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK)));
238 }
239
240 /* Process Unlocked */
241 __HAL_UNLOCK(&pFlash);
242
243 return status;
244 }
245
246 /**
247 * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
248 * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
249 * contains the configuration information for the erasing.
250 *
251 * @retval HAL Status
252 */
HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef * pEraseInit)253 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
254 {
255 HAL_StatusTypeDef status;
256 __IO uint32_t *reg_cr;
257
258 /* Check the parameters */
259 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
260
261 /* Process Locked */
262 __HAL_LOCK(&pFlash);
263
264 /* Reset error code */
265 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
266
267 /* Wait for last operation to be completed */
268 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
269
270 if (status != HAL_OK)
271 {
272 /* Process Unlocked */
273 __HAL_UNLOCK(&pFlash);
274 }
275 else
276 {
277 /* Set internal variables used by the IRQ handler */
278 pFlash.ProcedureOnGoing = pEraseInit->TypeErase;
279 pFlash.Bank = pEraseInit->Banks;
280
281 /* Access to SECCR or NSCR depends on operation type */
282 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR);
283
284 /* Enable End of Operation and Error interrupts */
285 (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR);
286
287 if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE)
288 {
289 /* Mass erase to be done */
290 FLASH_MassErase(pEraseInit->Banks);
291 }
292 else
293 {
294 /* Erase by page to be done */
295 pFlash.NbPagesToErase = pEraseInit->NbPages;
296 pFlash.Page = pEraseInit->Page;
297
298 /* Erase first page and wait for IT */
299 FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
300 }
301 }
302
303 return status;
304 }
305
306 /**
307 * @brief Program Option bytes.
308 * @param pOBInit pointer to an FLASH_OBInitStruct structure that
309 * contains the configuration information for the programming.
310 *
311 * @note To configure any option bytes, the option lock bit OPTLOCK must be
312 * cleared with the call of HAL_FLASH_OB_Unlock() function.
313 * @note New option bytes configuration will be taken into account in two cases:
314 * - after an option bytes launch through the call of HAL_FLASH_OB_Launch()
315 * - after a power reset (BOR reset or exit from Standby/Shutdown modes)
316 *
317 * @retval HAL Status
318 */
HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef * pOBInit)319 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
320 {
321 HAL_StatusTypeDef status;
322
323 /* Check the parameters */
324 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
325
326 /* Process Locked */
327 __HAL_LOCK(&pFlash);
328
329 /* Reset error code */
330 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
331
332 /* Wait for last operation to be completed */
333 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
334
335 if (status == HAL_OK)
336 {
337 /* Write protection configuration */
338 if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
339 {
340 /* Configure of Write protection on the selected area */
341 FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset, pOBInit->WRPLock);
342 }
343
344 /* Read protection configuration */
345 if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
346 {
347 /* Configure the Read protection level */
348 FLASH_OB_RDPConfig(pOBInit->RDPLevel);
349 }
350
351 /* Read protection key configuration */
352 if ((pOBInit->OptionType & OPTIONBYTE_RDPKEY) != 0U)
353 {
354 /* Configure the Read protection key */
355 FLASH_OB_RDPKeyConfig(pOBInit->RDPKeyType, pOBInit->RDPKey1, pOBInit->RDPKey2);
356 }
357
358 /* User Configuration */
359 if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
360 {
361 /* Configure the user option bytes */
362 FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
363 }
364
365 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
366 /* Watermark secure configuration */
367 if ((pOBInit->OptionType & OPTIONBYTE_WMSEC) != 0U)
368 {
369 /* Configure the watermark-based secure area */
370 FLASH_OB_WMSECConfig(pOBInit->WMSecConfig, pOBInit->WMSecStartPage, pOBInit->WMSecEndPage,
371 pOBInit->WMHDPEndPage);
372 }
373
374 /* Unique boot entry point configuration */
375 if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U)
376 {
377 /* Configure the unique boot entry point */
378 FLASH_OB_BootLockConfig(pOBInit->BootLock);
379 }
380 #endif /* __ARM_FEATURE_CMSE */
381
382 /* Boot address configuration */
383 if ((pOBInit->OptionType & OPTIONBYTE_BOOTADDR) != 0U)
384 {
385 /* Configure the boot address */
386 FLASH_OB_BootAddrConfig(pOBInit->BootAddrConfig, pOBInit->BootAddr);
387 }
388
389 /* Set OPTSTRT Bit */
390 SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTSTRT);
391
392 /* Wait for last operation to be completed */
393 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
394 }
395
396 /* Process Unlocked */
397 __HAL_UNLOCK(&pFlash);
398
399 return status;
400 }
401
402 /**
403 * @brief Get the Option bytes configuration.
404 * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the
405 * configuration information.
406 * @note The fields pOBInit->WRPArea, pOBInit->WMSecConfig and pOBInit->BootAddrConfig
407 * should indicate which area/address is requested for the WRP, WM Security or
408 * Boot Address, else no information will be returned
409 *
410 * @retval None
411 */
HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef * pOBInit)412 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
413 {
414 pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
415
416 if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
417 (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
418 {
419 pOBInit->OptionType |= OPTIONBYTE_WRP;
420 /* Get write protection on the selected area */
421 FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset), &(pOBInit->WRPLock));
422 }
423
424 /* Get Read protection level */
425 pOBInit->RDPLevel = FLASH_OB_GetRDP();
426
427 /* Get the user option bytes */
428 pOBInit->USERConfig = FLASH_OB_GetUser();
429
430 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
431 /* Get the configuration of the watermark secure area for the selected area */
432 if ((pOBInit->WMSecConfig == OB_WMSEC_AREA1) || (pOBInit->WMSecConfig == OB_WMSEC_AREA2))
433 {
434 pOBInit->OptionType |= OPTIONBYTE_WMSEC;
435 FLASH_OB_GetWMSEC(&(pOBInit->WMSecConfig), &(pOBInit->WMSecStartPage), &(pOBInit->WMSecEndPage),
436 &(pOBInit->WMHDPEndPage));
437 }
438
439 pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK;
440
441 /* Get the configuration of the unique boot entry point */
442 pOBInit->BootLock = FLASH_OB_GetBootLock();
443 #endif /* __ARM_FEATURE_CMSE */
444
445 /* Get the value of the selected boot address */
446 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
447 if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1) ||
448 (pOBInit->BootAddrConfig == OB_BOOTADDR_SEC0))
449 #else
450 if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1))
451 #endif /* __ARM_FEATURE_CMSE */
452 {
453 pOBInit->OptionType |= OPTIONBYTE_BOOTADDR;
454 FLASH_OB_GetBootAddr(pOBInit->BootAddrConfig, &(pOBInit->BootAddr));
455 }
456 }
457
458 /**
459 * @brief Configure the block-based secure area.
460 *
461 * @param pBBAttributes pointer to an FLASH_BBAttributesTypeDef structure that
462 * contains the configuration information for the programming.
463 *
464 * @note The field pBBAttributes->Bank should indicate which area is requested
465 * for the block-based attributes.
466 * @note The field pBBAttributes->BBAttributesType should indicate which
467 * block-base attribute type is requested: Secure or Privilege.
468 *
469 * @retval HAL Status
470 */
HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef * pBBAttributes)471 HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
472 {
473 HAL_StatusTypeDef status;
474 uint8_t index;
475 __IO uint32_t *reg;
476
477 /* Check the parameters */
478 assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
479 assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType));
480
481 /* Wait for last operation to be completed */
482 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
483
484 if (status == HAL_OK)
485 {
486 /* Set the first Block-Based register to write */
487 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
488 if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
489 {
490 if (pBBAttributes->Bank == FLASH_BANK_1)
491 {
492 reg = &(FLASH->SECBB1R1);
493 }
494 else
495 {
496 reg = &(FLASH->SECBB2R1);
497 }
498 }
499 else
500 #endif /* __ARM_FEATURE_CMSE */
501 {
502 if (pBBAttributes->Bank == FLASH_BANK_1)
503 {
504 reg = &(FLASH->PRIVBB1R1);
505 }
506 else
507 {
508 reg = &(FLASH->PRIVBB2R1);
509 }
510 }
511
512 /* Modify the register values and check that new attributes are taken in account */
513 for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
514 {
515 *reg = pBBAttributes->BBAttributes_array[index];
516 if ((*reg) != pBBAttributes->BBAttributes_array[index])
517 {
518 status = HAL_ERROR;
519 }
520 reg++;
521 }
522
523 /* ISB instruction is called to be sure next instructions are performed with correct attributes */
524 __ISB();
525 }
526
527 /* Process Unlocked */
528 __HAL_UNLOCK(&pFlash);
529
530 return status;
531 }
532
533 /**
534 * @brief Return the block-based attributes.
535 *
536 * @param pBBAttributes [in/out] pointer to an FLASH_BBAttributesTypeDef structure
537 * that contains the configuration information.
538 * @note The field pBBAttributes->Bank should indicate which area is requested
539 * for the block-based attributes.
540 * @note The field pBBAttributes->BBAttributesType should indicate which
541 * block-base attribute type is requested: Secure or Privilege.
542 *
543 * @retval None
544 */
HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef * pBBAttributes)545 void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes)
546 {
547 uint8_t index;
548 __IO uint32_t *reg;
549
550 /* Check the parameters */
551 assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank));
552 assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType));
553
554 /* Set the first Block-Based register to read */
555 if (pBBAttributes->BBAttributesType == FLASH_BB_SEC)
556 {
557 if (pBBAttributes->Bank == FLASH_BANK_1)
558 {
559 reg = &(FLASH->SECBB1R1);
560 }
561 else
562 {
563 reg = &(FLASH->SECBB2R1);
564 }
565 }
566 else
567 {
568 if (pBBAttributes->Bank == FLASH_BANK_1)
569 {
570 reg = &(FLASH->PRIVBB1R1);
571 }
572 else
573 {
574 reg = &(FLASH->PRIVBB2R1);
575 }
576 }
577
578 /* Read the register values */
579 for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++)
580 {
581 pBBAttributes->BBAttributes_array[index] = (*reg);
582 reg++;
583 }
584 }
585
586 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
587 /**
588 * @brief Activation of the protection of the secure hide area.
589 *
590 * @param Banks indicate the bank concerned by the activation
591 * This parameter can be one of the following values:
592 * @arg FLASH_BANK_1: Bank1 to be protected
593 * @arg FLASH_BANK_2: Bank2 to be protected
594 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected
595 *
596 * @retval None
597 */
HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks)598 void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks)
599 {
600 /* Check the parameters */
601 assert_param(IS_FLASH_BANK(Banks));
602
603 if ((Banks & FLASH_BANK_1) != 0U)
604 {
605 SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP1_ACCDIS);
606 }
607
608 if ((Banks & FLASH_BANK_2) != 0U)
609 {
610 SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP2_ACCDIS);
611 }
612 }
613 #endif /* __ARM_FEATURE_CMSE */
614
615 /**
616 * @}
617 */
618
619 /** @addtogroup FLASHEx_Exported_Functions_Group2 FLASHEx Exported Functions Group2
620 * @{
621 */
622
623 /**
624 * @brief Configuration of the privilege attribute.
625 *
626 * @param PrivMode indicate privilege mode configuration
627 * This parameter can be one of the following values:
628 * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged
629 * or unprivileged access
630 * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied
631 * to unprivileged access
632 * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged
633 * or unprivileged access
634 * @arg FLASH_NSPRIV_DENIED: access to non-secure Flash registers is denied
635 * to unprivilege access
636 *
637 * @retval None
638 */
HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode)639 void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode)
640 {
641 /* Check the parameters */
642 assert_param(IS_FLASH_CFGPRIVMODE(PrivMode));
643
644 MODIFY_REG(FLASH->PRIVCFGR, (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV), PrivMode);
645 }
646
647 /**
648 * @brief Return the value of the privilege attribute.
649 *
650 * @retval It indicates the privilege mode configuration.
651 * This return value can be one of the following values:
652 * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged
653 * or unprivileged access
654 * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied
655 * to unprivileged access
656 * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged
657 * or unprivileged access
658 * @arg FLASH_NSPRIV_DENIED: access to Flash registers is denied
659 * to unprivilege accessP
660 */
HAL_FLASHEx_GetPrivMode(void)661 uint32_t HAL_FLASHEx_GetPrivMode(void)
662 {
663 return (FLASH->PRIVCFGR & (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV));
664 }
665
666 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
667 /**
668 * @brief Configuration of the security inversion.
669 *
670 * @param SecInvState indicate the flash security state configuration
671 * This parameter can be one of the following values:
672 * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
673 * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
674 *
675 * @retval HAL Status
676 */
HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState)677 HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState)
678 {
679 HAL_StatusTypeDef status;
680
681 /* Check the parameters */
682 assert_param(IS_FLASH_CFGSECINV(SecInvState));
683
684 /* Process Locked */
685 __HAL_LOCK(&pFlash);
686
687 /* Wait for last operation to be completed */
688 status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
689
690 if (status == HAL_OK)
691 {
692 MODIFY_REG(FLASH->SECCR, FLASH_SECCR_INV, SecInvState);
693 }
694
695 /* Process Unlocked */
696 __HAL_UNLOCK(&pFlash);
697
698 return status;
699 }
700
701 /**
702 * @brief Return the value of the security inversion.
703 *
704 * @retval It indicates the flash security state configuration
705 * This return value can be one of the following values:
706 * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted
707 * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted
708 */
HAL_FLASHEx_GetSecInversion(void)709 uint32_t HAL_FLASHEx_GetSecInversion(void)
710 {
711 return (FLASH->SECCR & FLASH_SECCR_INV);
712 }
713 #endif /* __ARM_FEATURE_CMSE */
714
715 /**
716 * @brief Enable the Power-down Mode for Flash Banks
717 * @param Banks indicate which bank to put in power-down mode
718 * This parameter can be one of the following values:
719 * @arg FLASH_BANK_1: Flash Bank 1
720 * @arg FLASH_BANK_2: Flash Bank 2
721 * @arg FLASH_BANK_BOTH: Flash Bank 1 and Bank 2
722 * @retval HAL Status
723 */
HAL_FLASHEx_EnablePowerDown(uint32_t Banks)724 HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks)
725 {
726 HAL_StatusTypeDef status = HAL_OK;
727 uint32_t tickstart;
728
729 /* Check the parameters */
730 assert_param(IS_FLASH_BANK(Banks));
731
732 /* Request power-down mode for Bank 1 */
733 if ((Banks & FLASH_BANK_1) != 0U)
734 {
735 /* Check PD1 and PDREQ1 bits (Bank 1 is not in power-down mode and not being
736 already under power-down request) */
737 if ((FLASH->NSSR & FLASH_NSSR_PD1) != 0U)
738 {
739 status = HAL_ERROR;
740 }
741 else if ((FLASH->ACR & FLASH_ACR_PDREQ1) != 0U)
742 {
743 status = HAL_ERROR;
744 }
745 else
746 {
747 /* Unlock PDREQ1 bit */
748 WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_1);
749 WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_2);
750
751 /* Set PDREQ1 in FLASH_ACR register */
752 SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1);
753
754 /* Check PD1 bit */
755 tickstart = HAL_GetTick();
756 while (((FLASH->NSSR & FLASH_NSSR_PD1) != FLASH_NSSR_PD1))
757 {
758 if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE)
759 {
760 return HAL_TIMEOUT;
761 }
762 }
763 }
764 }
765
766 /* Request power-down mode for Bank 2 */
767 if ((Banks & FLASH_BANK_2) != 0U)
768 {
769 /* Check PD2 and PDREQ2 bits (Bank 2 is not in power-down mode and not being
770 already under power-down request) */
771 if ((FLASH->NSSR & FLASH_NSSR_PD2) != 0U)
772 {
773 status = HAL_ERROR;
774 }
775 else if ((FLASH->ACR & FLASH_ACR_PDREQ2) != 0U)
776 {
777 status = HAL_ERROR;
778 }
779 else
780 {
781 /* Unlock PDREQ2 bit */
782 WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_1);
783 WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_2);
784
785 /* Set PDREQ2 in FLASH_ACR register */
786 SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2);
787
788 /* Check PD2 bit */
789 tickstart = HAL_GetTick();
790 while (((FLASH->NSSR & FLASH_NSSR_PD2) != FLASH_NSSR_PD2))
791 {
792 if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE)
793 {
794 return HAL_TIMEOUT;
795 }
796 }
797 }
798 }
799
800 return status;
801 }
802
803 /**
804 * @brief Configuration of the Low-Power read Mode.
805 *
806 * @param ConfigLPM indicate the Low-Power read Mode configuration.
807 * This parameter can be one of the following values:
808 * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode
809 * @arg FLASH_LPM_DISABLE: Flash is in normal read mode
810 *
811 * @retval HAL Status
812 */
HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM)813 HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM)
814 {
815 HAL_StatusTypeDef status = HAL_OK;
816
817 /* Check the parameters */
818 assert_param(IS_FLASH_CFGLPM(ConfigLPM));
819
820 /* Set LPM Bit in FLASH_ACR register */
821 MODIFY_REG(FLASH->ACR, FLASH_ACR_LPM, ConfigLPM);
822
823 /* Check that low power read mode has been activated */
824 if (READ_BIT(FLASH->ACR, FLASH_ACR_LPM) != ConfigLPM)
825 {
826 status = HAL_ERROR;
827 }
828
829 return status;
830 }
831
832 /**
833 * @brief Return the value of the Low-Power read Mode.
834 *
835 * @retval It indicates the flash low-power read mode configuration
836 * This return value can be one of the following values:
837 * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode
838 * @arg FLASH_LPM_DISABLE: Flash is in normal read mode
839 */
HAL_FLASHEx_GetLowPowerRead(void)840 uint32_t HAL_FLASHEx_GetLowPowerRead(void)
841 {
842 return (FLASH->ACR & FLASH_ACR_LPM);
843 }
844
845 /**
846 * @brief Return the on-going Flash Operation. After a system reset, return
847 * the interrupted Flash operation, if any.
848 * @param pFlashOperation [out] pointer to a FLASH_OperationTypeDef structure
849 * that contains the Flash operation information.
850 *
851 * @retval None
852 */
HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef * pFlashOperation)853 void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation)
854 {
855 uint32_t opsr_reg = FLASH->OPSR;
856
857 /* Get Flash operation Type */
858 pFlashOperation->OperationType = opsr_reg & FLASH_OPSR_CODE_OP;
859
860 /* Get Flash operation memory */
861 pFlashOperation->FlashArea = opsr_reg & (FLASH_OPSR_SYSF_OP | FLASH_OPSR_BK_OP);
862
863 /* Get Flash operation address */
864 pFlashOperation->Address = opsr_reg & FLASH_OPSR_ADDR_OP;
865 }
866
867 /**
868 * @}
869 */
870
871 /**
872 * @}
873 */
874
875 /* Private functions ---------------------------------------------------------*/
876
877 /** @addtogroup FLASHEx_Private_Functions
878 * @{
879 */
880 /**
881 * @brief Mass erase of FLASH memory.
882 * @param Banks Banks to be erased
883 * This parameter can be one of the following values:
884 * @arg FLASH_BANK_1: Bank1 to be erased
885 * @arg FLASH_BANK_2: Bank2 to be erased
886 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
887 * @retval None
888 */
FLASH_MassErase(uint32_t Banks)889 static void FLASH_MassErase(uint32_t Banks)
890 {
891 __IO uint32_t *reg_cr;
892
893 /* Check the parameters */
894 assert_param(IS_FLASH_BANK(Banks));
895
896 /* Access to SECCR or NSCR registers depends on operation type */
897 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
898
899 /* Set the Mass Erase Bit for the bank 1 and proceed to erase */
900 if ((Banks & FLASH_BANK_1) != 0U)
901 {
902 SET_BIT((*reg_cr), FLASH_NSCR_MER1 | FLASH_NSCR_STRT);
903 }
904
905 /* Set the Mass Erase Bit for the bank 2 and proceed to erase */
906 if ((Banks & FLASH_BANK_2) != 0U)
907 {
908 SET_BIT((*reg_cr), FLASH_NSCR_MER2 | FLASH_NSCR_STRT);
909 }
910 }
911
912 /**
913 * @brief Erase the specified FLASH memory page.
914 * @param Page FLASH page to erase
915 * This parameter must be a value between 0 and (max number of pages in the bank - 1)
916 * @param Banks Bank(s) where the page will be erased
917 * This parameter can be one of the following values:
918 * @arg FLASH_BANK_1: Page in bank 1 to be erased
919 * @arg FLASH_BANK_2: Page in bank 2 to be erased
920 * @retval None
921 */
FLASH_PageErase(uint32_t Page,uint32_t Banks)922 void FLASH_PageErase(uint32_t Page, uint32_t Banks)
923 {
924 __IO uint32_t *reg_cr;
925
926 /* Check the parameters */
927 assert_param(IS_FLASH_PAGE(Page));
928 assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
929
930 /* Access to SECCR or NSCR registers depends on operation type */
931 reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR);
932
933 if ((Banks & FLASH_BANK_1) != 0U)
934 {
935 CLEAR_BIT((*reg_cr), FLASH_NSCR_BKER);
936 }
937 else
938 {
939 SET_BIT((*reg_cr), FLASH_NSCR_BKER);
940 }
941
942 /* Proceed to erase the page */
943 MODIFY_REG((*reg_cr), (FLASH_NSCR_PNB | FLASH_NSCR_PER | FLASH_NSCR_STRT), \
944 ((Page << FLASH_NSCR_PNB_Pos) | FLASH_NSCR_PER | FLASH_NSCR_STRT));
945 }
946
947 /**
948 * @brief Configure the write protection of the desired pages.
949 *
950 * @note When the memory read protection level is selected (RDP level = 1),
951 * it is not possible to program or erase Flash memory if the CPU debug
952 * features are connected (JTAG or single wire) or boot code is being
953 * executed from RAM or System flash, even if WRP is not activated.
954 * @note To configure the WRP options, the option lock bit OPTLOCK must be
955 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
956 * @note To validate the WRP options, the option bytes must be reloaded
957 * through the call of the HAL_FLASH_OB_Launch() function.
958 *
959 * @param WRPArea specifies the area to be configured.
960 * This parameter can be one of the following values:
961 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
962 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
963 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A
964 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B
965 *
966 * @param WRPStartOffset specifies the start page of the write protected area
967 * This parameter can be page number between 0 and (max number of pages in the bank - 1)
968 *
969 * @param WRPEndOffset specifies the end page of the write protected area
970 * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
971 *
972 * @param WRPLock enables the lock of the write protected area
973 * This parameter can be set to ENABLE or DISABLE
974 *
975 * @retval None
976 */
FLASH_OB_WRPConfig(uint32_t WRPArea,uint32_t WRPStartOffset,uint32_t WRPEndOffset,FunctionalState WRPLock)977 static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset,
978 FunctionalState WRPLock)
979 {
980 /* Check the parameters */
981 assert_param(IS_OB_WRPAREA(WRPArea));
982 assert_param(IS_FLASH_PAGE(WRPStartOffset));
983 assert_param(IS_FLASH_PAGE(WRPEndOffset));
984 assert_param(IS_FUNCTIONAL_STATE(WRPLock));
985
986 /* Configure the write protected area */
987 if (WRPArea == OB_WRPAREA_BANK1_AREAA)
988 {
989 FLASH->WRP1AR = (((uint32_t)(~WRPLock) << FLASH_WRP1AR_UNLOCK_Pos) | \
990 (WRPEndOffset << FLASH_WRP1AR_WRP1A_PEND_Pos) | \
991 WRPStartOffset);
992 }
993 else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
994 {
995 FLASH->WRP1BR = (((uint32_t)(~WRPLock) << FLASH_WRP1BR_UNLOCK_Pos) | \
996 (WRPEndOffset << FLASH_WRP1BR_WRP1B_PEND_Pos) | \
997 WRPStartOffset);
998 }
999 else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
1000 {
1001 FLASH->WRP2AR = (((uint32_t)(~WRPLock) << FLASH_WRP2AR_UNLOCK_Pos) | \
1002 (WRPEndOffset << FLASH_WRP2AR_WRP2A_PEND_Pos) | \
1003 WRPStartOffset);
1004 }
1005 else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
1006 {
1007 FLASH->WRP2BR = (((uint32_t)(~WRPLock) << FLASH_WRP2BR_UNLOCK_Pos) | \
1008 (WRPEndOffset << FLASH_WRP2BR_WRP2B_PEND_Pos) | \
1009 WRPStartOffset);
1010 }
1011 else
1012 {
1013 /* Empty statement (to be compliant MISRA 15.7) */
1014 }
1015 }
1016
1017 /**
1018 * @brief Set the read protection level.
1019 *
1020 * @note To configure the RDP level, the option lock bit OPTLOCK must be
1021 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
1022 * @note To validate the RDP level, the option bytes must be reloaded
1023 * through the call of the HAL_FLASH_OB_Launch() function.
1024 * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
1025 * to go back to other levels !!!
1026 *
1027 * @param RDPLevel specifies the read protection level.
1028 * This parameter can be one of the following values:
1029 * @arg OB_RDP_LEVEL_0: No protection
1030 * @arg OB_RDP_LEVEL_0_5: No debug access to secure area
1031 * @arg OB_RDP_LEVEL_1: Read protection of the memory
1032 * @arg OB_RDP_LEVEL_2: Full chip protection
1033 *
1034 * @retval None
1035 */
FLASH_OB_RDPConfig(uint32_t RDPLevel)1036 static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
1037 {
1038 /* Check the parameters */
1039 assert_param(IS_OB_RDP_LEVEL(RDPLevel));
1040
1041 /* Configure the RDP level in the option bytes register */
1042 MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
1043 }
1044
1045 /**
1046 * @brief Set the read protection key.
1047 * @param RDPKeyType specifies the read protection key type.
1048 * This parameter can be one of the following values:
1049 * @arg OB_RDP_KEY_OEM1: OEM1 key
1050 * @arg OB_RDP_KEY_OEM2: OEM2 key
1051 * @param RDPKey1 specifies the RDP key 1.
1052 * @param RDPKey2 specifies the RDP key 2.
1053 * @retval None
1054 */
FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType,uint32_t RDPKey1,uint32_t RDPKey2)1055 static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2)
1056 {
1057 /* Check the parameters */
1058 assert_param(IS_OB_RDP_KEY_TYPE(RDPKeyType));
1059
1060 /* Configure the RDP OEM key */
1061 if (RDPKeyType == OB_RDP_KEY_OEM1)
1062 {
1063 WRITE_REG(FLASH->OEM1KEYR1, RDPKey1);
1064 WRITE_REG(FLASH->OEM1KEYR2, RDPKey2);
1065 }
1066 else
1067 {
1068 WRITE_REG(FLASH->OEM2KEYR1, RDPKey1);
1069 WRITE_REG(FLASH->OEM2KEYR2, RDPKey2);
1070 }
1071 }
1072
1073 /**
1074 * @brief Program the FLASH User Option Byte.
1075 *
1076 * @note To configure the user option bytes, the option lock bit OPTLOCK must
1077 * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
1078 * @note To validate the user option bytes, the option bytes must be reloaded
1079 * through the call of the HAL_FLASH_OB_Launch() function.
1080 * @param UserType: The FLASH User Option Bytes to be modified.
1081 * This parameter can be a combination of @ref FLASH_OB_USER_Type
1082 * @param UserConfig The selected User Option Bytes values.
1083 * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
1084 * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
1085 * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
1086 * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
1087 * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
1088 * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
1089 * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC,
1090 * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST,
1091 * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
1092 * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV,
1093 * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN
1094 * @retval None
1095 */
FLASH_OB_UserConfig(uint32_t UserType,uint32_t UserConfig)1096 static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
1097 {
1098 uint32_t optr_reg_val = 0;
1099 uint32_t optr_reg_mask = 0;
1100
1101 /* Check the parameters */
1102 assert_param(IS_OB_USER_TYPE(UserType));
1103
1104 if ((UserType & OB_USER_BOR_LEV) != 0U)
1105 {
1106 /* BOR level option byte should be modified */
1107 assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
1108
1109 /* Set value and mask for BOR level option byte */
1110 optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
1111 optr_reg_mask |= FLASH_OPTR_BOR_LEV;
1112 }
1113
1114 if ((UserType & OB_USER_NRST_STOP) != 0U)
1115 {
1116 /* nRST_STOP option byte should be modified */
1117 assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
1118
1119 /* Set value and mask for nRST_STOP option byte */
1120 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
1121 optr_reg_mask |= FLASH_OPTR_nRST_STOP;
1122 }
1123
1124 if ((UserType & OB_USER_NRST_STDBY) != 0U)
1125 {
1126 /* nRST_STDBY option byte should be modified */
1127 assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
1128
1129 /* Set value and mask for nRST_STDBY option byte */
1130 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
1131 optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
1132 }
1133
1134 if ((UserType & OB_USER_NRST_SHDW) != 0U)
1135 {
1136 /* nRST_SHDW option byte should be modified */
1137 assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
1138
1139 /* Set value and mask for nRST_SHDW option byte */
1140 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
1141 optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
1142 }
1143
1144 if ((UserType & OB_USER_SRAM134_RST) != 0U)
1145 {
1146 /* SRAM134_RST option byte should be modified */
1147 assert_param(IS_OB_USER_SRAM134_RST(UserConfig & FLASH_OPTR_SRAM134_RST));
1148
1149 /* Set value and mask for SRAM134_RST option byte */
1150 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM134_RST);
1151 optr_reg_mask |= FLASH_OPTR_SRAM134_RST;
1152 }
1153
1154 if ((UserType & OB_USER_IWDG_SW) != 0U)
1155 {
1156 /* IWDG_SW option byte should be modified */
1157 assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
1158
1159 /* Set value and mask for IWDG_SW option byte */
1160 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
1161 optr_reg_mask |= FLASH_OPTR_IWDG_SW;
1162 }
1163
1164 if ((UserType & OB_USER_IWDG_STOP) != 0U)
1165 {
1166 /* IWDG_STOP option byte should be modified */
1167 assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
1168
1169 /* Set value and mask for IWDG_STOP option byte */
1170 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
1171 optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
1172 }
1173
1174 if ((UserType & OB_USER_IWDG_STDBY) != 0U)
1175 {
1176 /* IWDG_STDBY option byte should be modified */
1177 assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
1178
1179 /* Set value and mask for IWDG_STDBY option byte */
1180 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
1181 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
1182 }
1183
1184 if ((UserType & OB_USER_WWDG_SW) != 0U)
1185 {
1186 /* WWDG_SW option byte should be modified */
1187 assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
1188
1189 /* Set value and mask for WWDG_SW option byte */
1190 optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
1191 optr_reg_mask |= FLASH_OPTR_WWDG_SW;
1192 }
1193
1194 if ((UserType & OB_USER_SWAP_BANK) != 0U)
1195 {
1196 /* SWAP_BANK option byte should be modified */
1197 assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTR_SWAP_BANK));
1198
1199 /* Set value and mask for SWAP_BANK option byte */
1200 optr_reg_val |= (UserConfig & FLASH_OPTR_SWAP_BANK);
1201 optr_reg_mask |= FLASH_OPTR_SWAP_BANK;
1202 }
1203
1204 if ((UserType & OB_USER_DUALBANK) != 0U)
1205 {
1206 /* DUALBANK option byte should be modified */
1207 assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
1208
1209 /* Set value and mask for DUALBANK option byte */
1210 optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
1211 optr_reg_mask |= FLASH_OPTR_DUALBANK;
1212 }
1213
1214 if ((UserType & OB_USER_BKPRAM_ECC) != 0U)
1215 {
1216 /* BKPRAM_ECC option byte should be modified */
1217 assert_param(IS_OB_USER_BKPRAM_ECC(UserConfig & FLASH_OPTR_BKPRAM_ECC));
1218
1219 /* Set value and mask for BKPRAM_ECC option byte */
1220 optr_reg_val |= (UserConfig & FLASH_OPTR_BKPRAM_ECC);
1221 optr_reg_mask |= FLASH_OPTR_BKPRAM_ECC;
1222 }
1223
1224 if ((UserType & OB_USER_SRAM3_ECC) != 0U)
1225 {
1226 /* SRAM3_ECC option byte should be modified */
1227 assert_param(IS_OB_USER_SRAM3_ECC(UserConfig & FLASH_OPTR_SRAM3_ECC));
1228
1229 /* Set value and mask for SRAM3_ECC option byte */
1230 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM3_ECC);
1231 optr_reg_mask |= FLASH_OPTR_SRAM3_ECC;
1232 }
1233
1234 if ((UserType & OB_USER_SRAM2_ECC) != 0U)
1235 {
1236 /* SRAM2_ECC option byte should be modified */
1237 assert_param(IS_OB_USER_SRAM2_ECC(UserConfig & FLASH_OPTR_SRAM2_ECC));
1238
1239 /* Set value and mask for SRAM2_ECC option byte */
1240 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_ECC);
1241 optr_reg_mask |= FLASH_OPTR_SRAM2_ECC;
1242 }
1243
1244 if ((UserType & OB_USER_SRAM2_RST) != 0U)
1245 {
1246 /* SRAM2_RST option byte should be modified */
1247 assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
1248
1249 /* Set value and mask for SRAM2_RST option byte */
1250 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
1251 optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
1252 }
1253
1254 if ((UserType & OB_USER_NSWBOOT0) != 0U)
1255 {
1256 /* nSWBOOT0 option byte should be modified */
1257 assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
1258
1259 /* Set value and mask for nSWBOOT0 option byte */
1260 optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
1261 optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
1262 }
1263
1264 if ((UserType & OB_USER_NBOOT0) != 0U)
1265 {
1266 /* nBOOT0 option byte should be modified */
1267 assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
1268
1269 /* Set value and mask for nBOOT0 option byte */
1270 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
1271 optr_reg_mask |= FLASH_OPTR_nBOOT0;
1272 }
1273
1274 if ((UserType & OB_USER_PA15_PUPEN) != 0U)
1275 {
1276 /* PA15_PUPEN option byte should be modified */
1277 assert_param(IS_OB_USER_PA15_PUPEN(UserConfig & FLASH_OPTR_PA15_PUPEN));
1278
1279 /* Set value and mask for nBOOT0 option byte */
1280 optr_reg_val |= (UserConfig & FLASH_OPTR_PA15_PUPEN);
1281 optr_reg_mask |= FLASH_OPTR_PA15_PUPEN;
1282 }
1283
1284 if ((UserType & OB_USER_IO_VDD_HSLV) != 0U)
1285 {
1286 /* IO_VDD_HSLV option byte should be modified */
1287 assert_param(IS_OB_USER_IO_VDD_HSLV(UserConfig & FLASH_OPTR_IO_VDD_HSLV));
1288
1289 /* Set value and mask for IO_VDD_HSLV option byte */
1290 optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDD_HSLV);
1291 optr_reg_mask |= FLASH_OPTR_IO_VDD_HSLV;
1292 }
1293
1294 if ((UserType & OB_USER_IO_VDDIO2_HSLV) != 0U)
1295 {
1296 /* IO_VDDIO2_HSLV option byte should be modified */
1297 assert_param(IS_OB_USER_IO_VDDIO2_HSLV(UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV));
1298
1299 /* Set value and mask for IO_VDDIO2_HSLV option byte */
1300 optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV);
1301 optr_reg_mask |= FLASH_OPTR_IO_VDDIO2_HSLV;
1302 }
1303
1304 if ((UserType & OB_USER_TZEN) != 0U)
1305 {
1306 /* TZEN option byte should be modified */
1307 assert_param(IS_OB_USER_TZEN(UserConfig & FLASH_OPTR_TZEN));
1308
1309 /* Set value and mask for TZEN option byte */
1310 optr_reg_val |= (UserConfig & FLASH_OPTR_TZEN);
1311 optr_reg_mask |= FLASH_OPTR_TZEN;
1312 }
1313
1314 /* Configure the option bytes register */
1315 MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
1316 }
1317
1318 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1319 /**
1320 * @brief Configure the watermarked-based secure area.
1321 *
1322 * @param WMSecConfig specifies the area to be configured.
1323 * This parameter can be a combination of the following values:
1324 * @arg OB_WMSEC_AREA1 or @arg OB_WMSEC_AREA2: Select Flash Secure Area 1 or Area 2
1325 * @arg OB_WMSEC_SECURE_AREA_CONFIG: configure Flash Secure Area
1326 * @arg OB_WMSEC_HDP_AREA_CONFIG: configure Flash secure hide Area
1327 * @arg OB_WMSEC_HDP_AREA_ENABLE: enable secure hide Area in Secure Area
1328 * @arg OB_WMSEC_HDP_AREA_DISABLE: disable secure hide Area in Secure Area
1329 *
1330 * @param WMSecStartPage specifies the start page of the secure area
1331 * This parameter can be page number between 0 and (max number of pages in the bank - 1)
1332 *
1333 * @param WMSecEndPage specifies the end page of the secure area
1334 * This parameter can be page number between WMSecStartPage and (max number of pages in the bank - 1)
1335 *
1336 * @param WMHDPEndPage specifies the end page of the secure hide area
1337 * This parameter can be a page number between WMSecStartPage and WMSecEndPage
1338 *
1339 * @retval None
1340 */
FLASH_OB_WMSECConfig(uint32_t WMSecConfig,uint32_t WMSecStartPage,uint32_t WMSecEndPage,uint32_t WMHDPEndPage)1341 static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage,
1342 uint32_t WMHDPEndPage)
1343 {
1344 uint32_t tmp_secwm1 = 0U;
1345 uint32_t tmp_secwm2 = 0U;
1346
1347 /* Check the parameters */
1348 assert_param(IS_OB_WMSEC_CONFIG(WMSecConfig));
1349 assert_param(IS_OB_WMSEC_AREA_EXCLUSIVE(WMSecConfig & 0x3U));
1350 assert_param(IS_FLASH_PAGE(WMSecStartPage));
1351 assert_param(IS_FLASH_PAGE(WMSecEndPage));
1352 assert_param(IS_FLASH_PAGE(WMHDPEndPage));
1353
1354 /* Read SECWM registers */
1355 if ((WMSecConfig & OB_WMSEC_AREA1) != 0U)
1356 {
1357 tmp_secwm1 = FLASH->SECWM1R1;
1358 tmp_secwm2 = FLASH->SECWM1R2;
1359 }
1360 else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U)
1361 {
1362 tmp_secwm1 = FLASH->SECWM2R1;
1363 tmp_secwm2 = FLASH->SECWM2R2;
1364 }
1365 else
1366 {
1367 /* Nothing to do */
1368 }
1369
1370 /* Configure Secure Area */
1371 if ((WMSecConfig & OB_WMSEC_SECURE_AREA_CONFIG) != 0U)
1372 {
1373 tmp_secwm1 = ((WMSecEndPage << FLASH_SECWM1R1_SECWM1_PEND_Pos) | WMSecStartPage);
1374 }
1375
1376 /* Configure Secure Hide Area */
1377 if ((WMSecConfig & OB_WMSEC_HDP_AREA_CONFIG) != 0U)
1378 {
1379 tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1_PEND);
1380 tmp_secwm2 |= (WMHDPEndPage << FLASH_SECWM1R2_HDP1_PEND_Pos);
1381 }
1382
1383 /* Enable Secure Hide Area */
1384 if ((WMSecConfig & OB_WMSEC_HDP_AREA_ENABLE) != 0U)
1385 {
1386 tmp_secwm2 |= FLASH_SECWM1R2_HDP1EN;
1387 }
1388
1389 /* Disable Secure Hide Area */
1390 if ((WMSecConfig & OB_WMSEC_HDP_AREA_DISABLE) != 0U)
1391 {
1392 tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1EN);
1393 }
1394
1395 /* Write SECWM registers */
1396 if ((WMSecConfig & OB_WMSEC_AREA1) != 0U)
1397 {
1398 FLASH->SECWM1R1 = tmp_secwm1;
1399 FLASH->SECWM1R2 = tmp_secwm2;
1400 }
1401 else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U)
1402 {
1403 FLASH->SECWM2R1 = tmp_secwm1;
1404 FLASH->SECWM2R2 = tmp_secwm2;
1405 }
1406 else
1407 {
1408 /* Nothing to do */
1409 }
1410 }
1411
1412 /**
1413 * @brief Configure the boot lock.
1414 *
1415 * @param BootLockConfig specifies the activation of the BOOT_LOCK.
1416 * This parameter can be one of the following values:
1417 * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
1418 * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
1419 *
1420 * @retval None
1421 */
FLASH_OB_BootLockConfig(uint32_t BootLockConfig)1422 static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig)
1423 {
1424 /* Check the parameters */
1425 assert_param(IS_OB_BOOT_LOCK(BootLockConfig));
1426
1427 /* Configure the option bytes register */
1428 MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_BOOT_LOCK, BootLockConfig);
1429 }
1430 #endif /* __ARM_FEATURE_CMSE */
1431
1432 /**
1433 * @brief Configure the boot address.
1434 *
1435 * @param BootAddrConfig specifies the area to be configured.
1436 * This parameter can be one of the following values:
1437 * @arg OB_BOOTADDR_NS0: Non-secure boot address 0
1438 * @arg OB_BOOTADDR_NS1: Non-secure boot address 1
1439 * @arg OB_BOOTADDR_SEC0: Secure boot address 0
1440 *
1441 * @param BootAddr: specifies the address used for the boot
1442 * This parameter can be page number between 0 and 0xFFFFFF00
1443 *
1444 * @retval None
1445 */
FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig,uint32_t BootAddr)1446 static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr)
1447 {
1448 /* Check the parameters */
1449 assert_param(IS_OB_BOOTADDR_CONFIG(BootAddrConfig));
1450
1451 if (BootAddrConfig == OB_BOOTADDR_NS0)
1452 {
1453 FLASH->NSBOOTADD0R = BootAddr;
1454 }
1455 else if (BootAddrConfig == OB_BOOTADDR_NS1)
1456 {
1457 FLASH->NSBOOTADD1R = BootAddr;
1458 }
1459 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1460 else if (BootAddrConfig == OB_BOOTADDR_SEC0)
1461 {
1462 MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_SECBOOTADD0, BootAddr);
1463 }
1464 #endif /* __ARM_FEATURE_CMSE */
1465 else
1466 {
1467 /* Empty statement (to be compliant MISRA 15.7) */
1468 }
1469 }
1470
1471 /**
1472 * @brief Return the FLASH Write Protection Option Bytes value.
1473 *
1474 * @param[in] WRPArea specifies the area to be returned.
1475 * This parameter can be one of the following values:
1476 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
1477 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
1478 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A
1479 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B
1480 *
1481 * @param[out] WRPStartOffset specifies the address where to copied the start page
1482 * of the write protected area
1483 *
1484 * @param[out] WRPEndOffset specifies the address where to copied the end page of
1485 * the write protected area
1486 *
1487 * @param[out] WRPLock specifies the lock status of the write protected area.
1488 * The returned value can be ENABLE or DISABLE
1489 *
1490 * @retval None
1491 */
FLASH_OB_GetWRP(uint32_t WRPArea,uint32_t * WRPStartOffset,uint32_t * WRPEndOffset,FunctionalState * WRPLock)1492 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset,
1493 FunctionalState *WRPLock)
1494 {
1495 /* Get the configuration of the write protected area */
1496 if (WRPArea == OB_WRPAREA_BANK1_AREAA)
1497 {
1498 *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PSTRT);
1499 *WRPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PEND) >> FLASH_WRP1AR_WRP1A_PEND_Pos);
1500 *WRPLock = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_UNLOCK) != 0U) ? DISABLE : ENABLE;
1501 }
1502 else if (WRPArea == OB_WRPAREA_BANK1_AREAB)
1503 {
1504 *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PSTRT);
1505 *WRPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PEND) >> FLASH_WRP1BR_WRP1B_PEND_Pos);
1506 *WRPLock = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_UNLOCK) != 0U) ? DISABLE : ENABLE;
1507 }
1508 else if (WRPArea == OB_WRPAREA_BANK2_AREAA)
1509 {
1510 *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PSTRT);
1511 *WRPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PEND) >> FLASH_WRP2AR_WRP2A_PEND_Pos);
1512 *WRPLock = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_UNLOCK) != 0U) ? DISABLE : ENABLE;
1513 }
1514 else if (WRPArea == OB_WRPAREA_BANK2_AREAB)
1515 {
1516 *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PSTRT);
1517 *WRPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PEND) >> FLASH_WRP2BR_WRP2B_PEND_Pos);
1518 *WRPLock = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_UNLOCK) != 0U) ? DISABLE : ENABLE;
1519 }
1520 else
1521 {
1522 /* Empty statement (to be compliant MISRA 15.7) */
1523 }
1524 }
1525
1526 /**
1527 * @brief Return the FLASH Read Protection level.
1528 * @retval FLASH ReadOut Protection Level.
1529 * This return value can be one of the following values:
1530 * @arg OB_RDP_LEVEL_0: No protection
1531 * @arg OB_RDP_LEVEL_0_5: No debug access to secure area
1532 * @arg OB_RDP_LEVEL_1: Read protection of the memory
1533 * @arg OB_RDP_LEVEL_2: Full chip protection
1534 */
FLASH_OB_GetRDP(void)1535 static uint32_t FLASH_OB_GetRDP(void)
1536 {
1537 uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
1538
1539 if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_0_5) && (rdp_level != OB_RDP_LEVEL_2))
1540 {
1541 return (OB_RDP_LEVEL_1);
1542 }
1543 else
1544 {
1545 return rdp_level;
1546 }
1547 }
1548
1549 /**
1550 * @brief Return the FLASH User Option Byte value.
1551 * @retval The FLASH User Option Bytes values.
1552 * The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
1553 * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
1554 * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM134_RST,
1555 * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP,
1556 * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW,
1557 * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK,
1558 * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC,
1559 * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST,
1560 * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
1561 * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV,
1562 * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN
1563 */
FLASH_OB_GetUser(void)1564 static uint32_t FLASH_OB_GetUser(void)
1565 {
1566 uint32_t user_config = READ_REG(FLASH->OPTR);
1567 CLEAR_BIT(user_config, FLASH_OPTR_RDP);
1568
1569 return user_config;
1570 }
1571
1572 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1573 /**
1574 * @brief Return the watermarked-based secure area configuration.
1575 *
1576 * @param WMSecConfig [in/out] specifies the area to be returned.
1577 * This parameter can be one of the following values:
1578 * @arg OB_WMSEC_AREA1: select Flash Secure Area 1
1579 * @arg OB_WMSEC_AREA2: select Flash Secure Area 2
1580 * When return from the function, this parameter will be a combinaison of the following values:
1581 * @arg OB_WMSEC_AREAA or @arg OB_WMSEC_AREAB: selected Flash Secure Area A or Area B
1582 * @arg OB_WMSEC_HDP_AREA_ENABLE: Secure Hide Area in Secure Area enabled
1583 * @arg OB_WMSEC_HDP_AREA_DISABLE: Secure Hide Area in Secure Area disabled
1584 *
1585 * @param WMSecStartPage [out] specifies the start page of the secure area
1586 *
1587 * @param WMSecEndPage [out] specifies the end page of the secure area
1588 *
1589 * @param WMHDPEndPage [out] specifies the end page of the secure hide area
1590 *
1591 *
1592 * @retval None
1593 */
FLASH_OB_GetWMSEC(uint32_t * WMSecConfig,uint32_t * WMSecStartPage,uint32_t * WMSecEndPage,uint32_t * WMHDPEndPage)1594 static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage,
1595 uint32_t *WMHDPEndPage)
1596 {
1597 uint32_t tmp_secwm1 = 0U;
1598 uint32_t tmp_secwm2 = 0U;
1599
1600 /* Check the parameters */
1601 assert_param(IS_OB_WMSEC_CONFIG(*WMSecConfig));
1602 assert_param(IS_FLASH_BANK_EXCLUSIVE((*WMSecConfig) & 0x3U));
1603
1604 /* Read SECWM registers */
1605 if (((*WMSecConfig) & OB_WMSEC_AREA1) != 0U)
1606 {
1607 tmp_secwm1 = FLASH->SECWM1R1;
1608 tmp_secwm2 = FLASH->SECWM1R2;
1609 }
1610 else if (((*WMSecConfig) & OB_WMSEC_AREA2) != 0U)
1611 {
1612 tmp_secwm1 = FLASH->SECWM2R1;
1613 tmp_secwm2 = FLASH->SECWM2R2;
1614 }
1615 else
1616 {
1617 /* Empty statement (to be compliant MISRA 15.7) */
1618 }
1619
1620 /* Configuration of secure area */
1621 *WMSecStartPage = (tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PSTRT);
1622 *WMSecEndPage = ((tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PEND) >> FLASH_SECWM1R1_SECWM1_PEND_Pos);
1623
1624 /* Configuration of secure hide area */
1625 *WMHDPEndPage = ((tmp_secwm2 & FLASH_SECWM1R2_HDP1_PEND) >> FLASH_SECWM1R2_HDP1_PEND_Pos);
1626
1627 if ((tmp_secwm2 & FLASH_SECWM1R2_HDP1EN) == 0U)
1628 {
1629 *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_DISABLE);
1630 }
1631 else
1632 {
1633 *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_ENABLE);
1634 }
1635
1636 }
1637
1638 /**
1639 * @brief Return the boot lock configuration.
1640 *
1641 * @retval Value of Boot Lock configuration.
1642 * It can be one of the following values:
1643 * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated
1644 * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated
1645 */
FLASH_OB_GetBootLock(void)1646 static uint32_t FLASH_OB_GetBootLock(void)
1647 {
1648 return (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_BOOT_LOCK);
1649 }
1650 #endif /* __ARM_FEATURE_CMSE */
1651
1652 /**
1653 * @brief Return the boot address.
1654 *
1655 * @param[in] BootAddrConfig specifies the area to be returned.
1656 * This parameter can be one of the following values:
1657 * @arg OB_BOOTADDR_NS0: Non-secure boot address 0
1658 * @arg OB_BOOTADDR_NS1: Non-secure boot address 1
1659 * @arg OB_BOOTADDR_SEC0: Secure boot address 0
1660 *
1661 * @param[out] BootAddr specifies the boot address value
1662 *
1663 * @retval None
1664 */
FLASH_OB_GetBootAddr(uint32_t BootAddrConfig,uint32_t * BootAddr)1665 static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr)
1666 {
1667 if (BootAddrConfig == OB_BOOTADDR_NS0)
1668 {
1669 *BootAddr = (FLASH->NSBOOTADD0R & FLASH_NSBOOTADD0R_NSBOOTADD0);
1670 }
1671 else if (BootAddrConfig == OB_BOOTADDR_NS1)
1672 {
1673 *BootAddr = (FLASH->NSBOOTADD1R & FLASH_NSBOOTADD1R_NSBOOTADD1);
1674 }
1675 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1676 else if (BootAddrConfig == OB_BOOTADDR_SEC0)
1677 {
1678 *BootAddr = (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_SECBOOTADD0);
1679 }
1680 #endif /* __ARM_FEATURE_CMSE */
1681 else
1682 {
1683 /* Empty statement (to be compliant MISRA 15.7) */
1684 }
1685 }
1686
1687 /**
1688 * @}
1689 */
1690
1691 #endif /* HAL_FLASH_MODULE_ENABLED */
1692
1693 /**
1694 * @}
1695 */
1696
1697 /**
1698 * @}
1699 */
1700
