1 /**
2 ******************************************************************************
3 * @file stm32l4xx_hal_flash_ex.c
4 * @author MCD Application Team
5 * @brief Extended FLASH HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the FLASH extended peripheral:
8 * + Extended programming operations functions
9 *
10 @verbatim
11 ==============================================================================
12 ##### Flash Extended features #####
13 ==============================================================================
14
15 [..] Comparing to other previous devices, the FLASH interface for STM32L4xx
16 devices contains the following additional features
17
18 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
19 capability (RWW)
20 (+) Dual bank memory organization
21 (+) PCROP protection for all banks
22
23 ##### How to use this driver #####
24 ==============================================================================
25 [..] This driver provides functions to configure and program the FLASH memory
26 of all STM32L4xx devices. It includes
27 (#) Flash Memory Erase functions:
28 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
29 HAL_FLASH_Lock() functions
30 (++) Erase function: Erase page, erase all sectors
31 (++) There are two modes of erase :
32 (+++) Polling Mode using HAL_FLASHEx_Erase()
33 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
34
35 (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
36 (++) Set/Reset the write protection
37 (++) Set the Read protection Level
38 (++) Program the user Option Bytes
39 (++) Configure the PCROP protection
40
41 (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
42 (++) Get the value of a write protection area
43 (++) Know if the read protection is activated
44 (++) Get the value of the user Option Bytes
45 (++) Get the value of a PCROP area
46
47 @endverbatim
48 ******************************************************************************
49 * @attention
50 *
51 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
52 *
53 * Redistribution and use in source and binary forms, with or without modification,
54 * are permitted provided that the following conditions are met:
55 * 1. Redistributions of source code must retain the above copyright notice,
56 * this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright notice,
58 * this list of conditions and the following disclaimer in the documentation
59 * and/or other materials provided with the distribution.
60 * 3. Neither the name of STMicroelectronics nor the names of its contributors
61 * may be used to endorse or promote products derived from this software
62 * without specific prior written permission.
63 *
64 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
65 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
67 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
70 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
71 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
72 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
73 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
74 *
75 ******************************************************************************
76 */
77
78 /* Includes ------------------------------------------------------------------*/
79 #include "stm32l4xx_hal.h"
80
81 /** @addtogroup STM32L4xx_HAL_Driver
82 * @{
83 */
84
85 /** @defgroup FLASHEx FLASHEx
86 * @brief FLASH Extended HAL module driver
87 * @{
88 */
89
90 #ifdef HAL_FLASH_MODULE_ENABLED
91
92 /* Private typedef -----------------------------------------------------------*/
93 /* Private define ------------------------------------------------------------*/
94 /* Private macro -------------------------------------------------------------*/
95 /* Private variables ---------------------------------------------------------*/
96 /** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables
97 * @{
98 */
99 extern FLASH_ProcessTypeDef pFlash;
100 /**
101 * @}
102 */
103
104 /* Private function prototypes -----------------------------------------------*/
105 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
106 * @{
107 */
108 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
109 void FLASH_PageErase(uint32_t Page, uint32_t Banks);
110 static void FLASH_MassErase(uint32_t Banks);
111 void FLASH_FlushCaches(void);
112 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
113 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
114 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
115 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
116 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);
117 static uint32_t FLASH_OB_GetRDP(void);
118 static uint32_t FLASH_OB_GetUser(void);
119 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);
120 /**
121 * @}
122 */
123
124 /* Exported functions -------------------------------------------------------*/
125 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
126 * @{
127 */
128
129 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
130 * @brief Extended IO operation functions
131 *
132 @verbatim
133 ===============================================================================
134 ##### Extended programming operation functions #####
135 ===============================================================================
136 [..]
137 This subsection provides a set of functions allowing to manage the Extended FLASH
138 programming operations Operations.
139
140 @endverbatim
141 * @{
142 */
143 /**
144 * @brief Perform a mass erase or erase the specified FLASH memory pages.
145 * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
146 * contains the configuration information for the erasing.
147 *
148 * @param[out] PageError : pointer to variable that contains the configuration
149 * information on faulty page in case of error (0xFFFFFFFF means that all
150 * the pages have been correctly erased)
151 *
152 * @retval HAL Status
153 */
HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef * pEraseInit,uint32_t * PageError)154 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
155 {
156 HAL_StatusTypeDef status;
157 uint32_t page_index;
158
159 /* Process Locked */
160 __HAL_LOCK(&pFlash);
161
162 /* Check the parameters */
163 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
164
165 /* Wait for last operation to be completed */
166 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
167
168 if (status == HAL_OK)
169 {
170 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
171
172 /* Deactivate the cache if they are activated to avoid data misbehavior */
173 if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
174 {
175 /* Disable instruction cache */
176 __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
177
178 if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
179 {
180 /* Disable data cache */
181 __HAL_FLASH_DATA_CACHE_DISABLE();
182 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
183 }
184 else
185 {
186 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
187 }
188 }
189 else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
190 {
191 /* Disable data cache */
192 __HAL_FLASH_DATA_CACHE_DISABLE();
193 pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
194 }
195 else
196 {
197 pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
198 }
199
200 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
201 {
202 /* Mass erase to be done */
203 FLASH_MassErase(pEraseInit->Banks);
204
205 /* Wait for last operation to be completed */
206 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
207
208 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
209 defined (STM32L496xx) || defined (STM32L4A6xx) || \
210 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
211 /* If the erase operation is completed, disable the MER1 and MER2 Bits */
212 CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
213 #else
214 /* If the erase operation is completed, disable the MER1 Bit */
215 CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1));
216 #endif
217 }
218 else
219 {
220 /*Initialization of PageError variable*/
221 *PageError = 0xFFFFFFFFU;
222
223 for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
224 {
225 FLASH_PageErase(page_index, pEraseInit->Banks);
226
227 /* Wait for last operation to be completed */
228 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
229
230 /* If the erase operation is completed, disable the PER Bit */
231 CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
232
233 if (status != HAL_OK)
234 {
235 /* In case of error, stop erase procedure and return the faulty address */
236 *PageError = page_index;
237 break;
238 }
239 }
240 }
241
242 /* Flush the caches to be sure of the data consistency */
243 FLASH_FlushCaches();
244 }
245
246 /* Process Unlocked */
247 __HAL_UNLOCK(&pFlash);
248
249 return status;
250 }
251
252 /**
253 * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
254 * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
255 * contains the configuration information for the erasing.
256 *
257 * @retval HAL Status
258 */
HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef * pEraseInit)259 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
260 {
261 HAL_StatusTypeDef status = HAL_OK;
262
263 /* Process Locked */
264 __HAL_LOCK(&pFlash);
265
266 /* Check the parameters */
267 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
268
269 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
270
271 /* Deactivate the cache if they are activated to avoid data misbehavior */
272 if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U)
273 {
274 /* Disable instruction cache */
275 __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
276
277 if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
278 {
279 /* Disable data cache */
280 __HAL_FLASH_DATA_CACHE_DISABLE();
281 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_DCACHE_ENABLED;
282 }
283 else
284 {
285 pFlash.CacheToReactivate = FLASH_CACHE_ICACHE_ENABLED;
286 }
287 }
288 else if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U)
289 {
290 /* Disable data cache */
291 __HAL_FLASH_DATA_CACHE_DISABLE();
292 pFlash.CacheToReactivate = FLASH_CACHE_DCACHE_ENABLED;
293 }
294 else
295 {
296 pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
297 }
298
299 /* Enable End of Operation and Error interrupts */
300 __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
301
302 pFlash.Bank = pEraseInit->Banks;
303
304 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
305 {
306 /* Mass erase to be done */
307 pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
308 FLASH_MassErase(pEraseInit->Banks);
309 }
310 else
311 {
312 /* Erase by page to be done */
313 pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
314 pFlash.NbPagesToErase = pEraseInit->NbPages;
315 pFlash.Page = pEraseInit->Page;
316
317 /*Erase 1st page and wait for IT */
318 FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
319 }
320
321 return status;
322 }
323
324 /**
325 * @brief Program Option bytes.
326 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
327 * contains the configuration information for the programming.
328 *
329 * @retval HAL Status
330 */
HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef * pOBInit)331 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
332 {
333 HAL_StatusTypeDef status = HAL_OK;
334
335 /* Process Locked */
336 __HAL_LOCK(&pFlash);
337
338 /* Check the parameters */
339 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
340
341 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
342
343 /* Write protection configuration */
344 if((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U)
345 {
346 /* Configure of Write protection on the selected area */
347 if(FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset) != HAL_OK)
348 {
349 status = HAL_ERROR;
350 }
351
352 }
353
354 /* Read protection configuration */
355 if((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
356 {
357 /* Configure the Read protection level */
358 if(FLASH_OB_RDPConfig(pOBInit->RDPLevel) != HAL_OK)
359 {
360 status = HAL_ERROR;
361 }
362 }
363
364 /* User Configuration */
365 if((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
366 {
367 /* Configure the user option bytes */
368 if(FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig) != HAL_OK)
369 {
370 status = HAL_ERROR;
371 }
372 }
373
374 /* PCROP Configuration */
375 if((pOBInit->OptionType & OPTIONBYTE_PCROP) != 0U)
376 {
377 if (pOBInit->PCROPStartAddr != pOBInit->PCROPEndAddr)
378 {
379 /* Configure the Proprietary code readout protection */
380 if(FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr) != HAL_OK)
381 {
382 status = HAL_ERROR;
383 }
384 }
385 }
386
387 /* Process Unlocked */
388 __HAL_UNLOCK(&pFlash);
389
390 return status;
391 }
392
393 /**
394 * @brief Get the Option bytes configuration.
395 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that contains the
396 * configuration information.
397 * @note The fields pOBInit->WRPArea and pOBInit->PCROPConfig should indicate
398 * which area is requested for the WRP and PCROP, else no information will be returned
399 *
400 * @retval None
401 */
HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef * pOBInit)402 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
403 {
404 pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER);
405
406 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
407 defined (STM32L496xx) || defined (STM32L4A6xx) || \
408 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
409 if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) ||
410 (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB))
411 #else
412 if((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
413 #endif
414 {
415 pOBInit->OptionType |= OPTIONBYTE_WRP;
416 /* Get write protection on the selected area */
417 FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
418 }
419
420 /* Get Read protection level */
421 pOBInit->RDPLevel = FLASH_OB_GetRDP();
422
423 /* Get the user option bytes */
424 pOBInit->USERConfig = FLASH_OB_GetUser();
425
426 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
427 defined (STM32L496xx) || defined (STM32L4A6xx) || \
428 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
429 if((pOBInit->PCROPConfig == FLASH_BANK_1) || (pOBInit->PCROPConfig == FLASH_BANK_2))
430 #else
431 if(pOBInit->PCROPConfig == FLASH_BANK_1)
432 #endif
433 {
434 pOBInit->OptionType |= OPTIONBYTE_PCROP;
435 /* Get the Proprietary code readout protection */
436 FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
437 }
438 }
439
440 /**
441 * @}
442 */
443
444 #if defined (FLASH_CFGR_LVEN)
445 /** @defgroup FLASHEx_Exported_Functions_Group2 Extended specific configuration functions
446 * @brief Extended specific configuration functions
447 *
448 @verbatim
449 ===============================================================================
450 ##### Extended specific configuration functions #####
451 ===============================================================================
452 [..]
453 This subsection provides a set of functions allowing to manage the Extended FLASH
454 specific configurations.
455
456 @endverbatim
457 * @{
458 */
459
460 /**
461 * @brief Configuration of the LVE pin of the Flash (managed by power controller
462 * or forced to low in order to use an external SMPS)
463 * @param ConfigLVE: Configuration of the LVE pin,
464 * This parameter can be one of the following values:
465 * @arg FLASH_LVE_PIN_CTRL: LVE FLASH pin controlled by power controller
466 * @arg FLASH_LVE_PIN_FORCED: LVE FLASH pin enforced to low (external SMPS used)
467 *
468 * @note Before enforcing the LVE pin to low, the SOC should be in low voltage
469 * range 2 and the voltage VDD12 should be higher than 1.08V and SMPS is ON.
470 *
471 * @retval HAL Status
472 */
HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE)473 HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE)
474 {
475 HAL_StatusTypeDef status;
476
477 /* Process Locked */
478 __HAL_LOCK(&pFlash);
479
480 /* Check the parameters */
481 assert_param(IS_FLASH_LVE_PIN(ConfigLVE));
482
483 /* Wait for last operation to be completed */
484 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
485
486 if (status == HAL_OK)
487 {
488 /* Check that the voltage scaling is range 2 */
489 if (HAL_PWREx_GetVoltageRange() == PWR_REGULATOR_VOLTAGE_SCALE2)
490 {
491 /* Configure the LVEN bit */
492 MODIFY_REG(FLASH->CFGR, FLASH_CFGR_LVEN, ConfigLVE);
493
494 /* Check that the bit has been correctly configured */
495 if (READ_BIT(FLASH->CFGR, FLASH_CFGR_LVEN) != ConfigLVE)
496 {
497 status = HAL_ERROR;
498 }
499 }
500 else
501 {
502 /* Not allow to force Flash LVE pin if not in voltage range 2 */
503 status = HAL_ERROR;
504 }
505 }
506
507 /* Process Unlocked */
508 __HAL_UNLOCK(&pFlash);
509
510 return status;
511 }
512
513 /**
514 * @}
515 */
516 #endif /* FLASH_CFGR_LVEN */
517
518 /**
519 * @}
520 */
521
522 /* Private functions ---------------------------------------------------------*/
523
524 /** @addtogroup FLASHEx_Private_Functions
525 * @{
526 */
527 /**
528 * @brief Mass erase of FLASH memory.
529 * @param Banks: Banks to be erased
530 * This parameter can be one of the following values:
531 * @arg FLASH_BANK_1: Bank1 to be erased
532 * @arg FLASH_BANK_2: Bank2 to be erased
533 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
534 * @retval None
535 */
FLASH_MassErase(uint32_t Banks)536 static void FLASH_MassErase(uint32_t Banks)
537 {
538 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
539 if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) != 0U)
540 #endif
541 {
542 /* Check the parameters */
543 assert_param(IS_FLASH_BANK(Banks));
544
545 /* Set the Mass Erase Bit for the bank 1 if requested */
546 if((Banks & FLASH_BANK_1) != 0U)
547 {
548 SET_BIT(FLASH->CR, FLASH_CR_MER1);
549 }
550
551 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
552 defined (STM32L496xx) || defined (STM32L4A6xx) || \
553 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
554 /* Set the Mass Erase Bit for the bank 2 if requested */
555 if((Banks & FLASH_BANK_2) != 0U)
556 {
557 SET_BIT(FLASH->CR, FLASH_CR_MER2);
558 }
559 #endif
560 }
561 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
562 else
563 {
564 SET_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
565 }
566 #endif
567
568 /* Proceed to erase all sectors */
569 SET_BIT(FLASH->CR, FLASH_CR_STRT);
570 }
571
572 /**
573 * @brief Erase the specified FLASH memory page.
574 * @param Page: FLASH page to erase
575 * This parameter must be a value between 0 and (max number of pages in the bank - 1)
576 * @param Banks: Bank(s) where the page will be erased
577 * This parameter can be one of the following values:
578 * @arg FLASH_BANK_1: Page in bank 1 to be erased
579 * @arg FLASH_BANK_2: Page in bank 2 to be erased
580 * @retval None
581 */
FLASH_PageErase(uint32_t Page,uint32_t Banks)582 void FLASH_PageErase(uint32_t Page, uint32_t Banks)
583 {
584 /* Check the parameters */
585 assert_param(IS_FLASH_PAGE(Page));
586
587 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
588 defined (STM32L496xx) || defined (STM32L4A6xx) || \
589 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
590 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
591 if(READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
592 {
593 CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
594 }
595 else
596 #endif
597 {
598 assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
599
600 if((Banks & FLASH_BANK_1) != 0U)
601 {
602 CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
603 }
604 else
605 {
606 SET_BIT(FLASH->CR, FLASH_CR_BKER);
607 }
608 }
609 #else
610 /* Prevent unused argument(s) compilation warning */
611 UNUSED(Banks);
612 #endif
613
614 /* Proceed to erase the page */
615 MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page & 0xFFU) << FLASH_CR_PNB_Pos));
616 SET_BIT(FLASH->CR, FLASH_CR_PER);
617 SET_BIT(FLASH->CR, FLASH_CR_STRT);
618 }
619
620 /**
621 * @brief Flush the instruction and data caches.
622 * @retval None
623 */
FLASH_FlushCaches(void)624 void FLASH_FlushCaches(void)
625 {
626 FLASH_CacheTypeDef cache = pFlash.CacheToReactivate;
627
628 /* Flush instruction cache */
629 if((cache == FLASH_CACHE_ICACHE_ENABLED) ||
630 (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
631 {
632 /* Reset instruction cache */
633 __HAL_FLASH_INSTRUCTION_CACHE_RESET();
634 /* Enable instruction cache */
635 __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
636 }
637
638 /* Flush data cache */
639 if((cache == FLASH_CACHE_DCACHE_ENABLED) ||
640 (cache == FLASH_CACHE_ICACHE_DCACHE_ENABLED))
641 {
642 /* Reset data cache */
643 __HAL_FLASH_DATA_CACHE_RESET();
644 /* Enable data cache */
645 __HAL_FLASH_DATA_CACHE_ENABLE();
646 }
647
648 /* Reset internal variable */
649 pFlash.CacheToReactivate = FLASH_CACHE_DISABLED;
650 }
651
652 /**
653 * @brief Configure the write protection of the desired pages.
654 *
655 * @note When the memory read protection level is selected (RDP level = 1),
656 * it is not possible to program or erase Flash memory if the CPU debug
657 * features are connected (JTAG or single wire) or boot code is being
658 * executed from RAM or System flash, even if WRP is not activated.
659 * @note To configure the WRP options, the option lock bit OPTLOCK must be
660 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
661 * @note To validate the WRP options, the option bytes must be reloaded
662 * through the call of the HAL_FLASH_OB_Launch() function.
663 *
664 * @param WRPArea: specifies the area to be configured.
665 * This parameter can be one of the following values:
666 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
667 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
668 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices)
669 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices)
670 *
671 * @param WRPStartOffset: specifies the start page of the write protected area
672 * This parameter can be page number between 0 and (max number of pages in the bank - 1)
673 *
674 * @param WRDPEndOffset: specifies the end page of the write protected area
675 * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1)
676 *
677 * @retval HAL Status
678 */
FLASH_OB_WRPConfig(uint32_t WRPArea,uint32_t WRPStartOffset,uint32_t WRDPEndOffset)679 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
680 {
681 HAL_StatusTypeDef status;
682
683 /* Check the parameters */
684 assert_param(IS_OB_WRPAREA(WRPArea));
685 assert_param(IS_FLASH_PAGE(WRPStartOffset));
686 assert_param(IS_FLASH_PAGE(WRDPEndOffset));
687
688 /* Wait for last operation to be completed */
689 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
690
691 if(status == HAL_OK)
692 {
693 /* Configure the write protected area */
694 if(WRPArea == OB_WRPAREA_BANK1_AREAA)
695 {
696 MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END),
697 (WRPStartOffset | (WRDPEndOffset << 16)));
698 }
699 else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
700 {
701 MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END),
702 (WRPStartOffset | (WRDPEndOffset << 16)));
703 }
704 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
705 defined (STM32L496xx) || defined (STM32L4A6xx) || \
706 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
707 else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
708 {
709 MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END),
710 (WRPStartOffset | (WRDPEndOffset << 16)));
711 }
712 else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
713 {
714 MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END),
715 (WRPStartOffset | (WRDPEndOffset << 16)));
716 }
717 #endif
718 else
719 {
720 /* Nothing to do */
721 }
722
723 /* Set OPTSTRT Bit */
724 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
725
726 /* Wait for last operation to be completed */
727 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
728
729 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
730 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
731 }
732
733 return status;
734 }
735
736 /**
737 * @brief Set the read protection level.
738 *
739 * @note To configure the RDP level, the option lock bit OPTLOCK must be
740 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
741 * @note To validate the RDP level, the option bytes must be reloaded
742 * through the call of the HAL_FLASH_OB_Launch() function.
743 * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
744 * to go back to level 1 or 0 !!!
745 *
746 * @param RDPLevel: specifies the read protection level.
747 * This parameter can be one of the following values:
748 * @arg OB_RDP_LEVEL_0: No protection
749 * @arg OB_RDP_LEVEL_1: Read protection of the memory
750 * @arg OB_RDP_LEVEL_2: Full chip protection
751 *
752 * @retval HAL status
753 */
FLASH_OB_RDPConfig(uint32_t RDPLevel)754 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
755 {
756 HAL_StatusTypeDef status;
757
758 /* Check the parameters */
759 assert_param(IS_OB_RDP_LEVEL(RDPLevel));
760
761 /* Wait for last operation to be completed */
762 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
763
764 if(status == HAL_OK)
765 {
766 /* Configure the RDP level in the option bytes register */
767 MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
768
769 /* Set OPTSTRT Bit */
770 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
771
772 /* Wait for last operation to be completed */
773 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
774
775 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
776 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
777 }
778
779 return status;
780 }
781
782 /**
783 * @brief Program the FLASH User Option Byte.
784 *
785 * @note To configure the user option bytes, the option lock bit OPTLOCK must
786 * be cleared with the call of the HAL_FLASH_OB_Unlock() function.
787 * @note To validate the user option bytes, the option bytes must be reloaded
788 * through the call of the HAL_FLASH_OB_Launch() function.
789 *
790 * @param UserType: The FLASH User Option Bytes to be modified
791 * @param UserConfig: The FLASH User Option Bytes values:
792 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),
793 * IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20),
794 * DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
795 *
796 * @retval HAL status
797 */
FLASH_OB_UserConfig(uint32_t UserType,uint32_t UserConfig)798 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
799 {
800 uint32_t optr_reg_val = 0;
801 uint32_t optr_reg_mask = 0;
802 HAL_StatusTypeDef status;
803
804 /* Check the parameters */
805 assert_param(IS_OB_USER_TYPE(UserType));
806
807 /* Wait for last operation to be completed */
808 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
809
810 if(status == HAL_OK)
811 {
812 if((UserType & OB_USER_BOR_LEV) != 0U)
813 {
814 /* BOR level option byte should be modified */
815 assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
816
817 /* Set value and mask for BOR level option byte */
818 optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
819 optr_reg_mask |= FLASH_OPTR_BOR_LEV;
820 }
821
822 if((UserType & OB_USER_nRST_STOP) != 0U)
823 {
824 /* nRST_STOP option byte should be modified */
825 assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
826
827 /* Set value and mask for nRST_STOP option byte */
828 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
829 optr_reg_mask |= FLASH_OPTR_nRST_STOP;
830 }
831
832 if((UserType & OB_USER_nRST_STDBY) != 0U)
833 {
834 /* nRST_STDBY option byte should be modified */
835 assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
836
837 /* Set value and mask for nRST_STDBY option byte */
838 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
839 optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
840 }
841
842 if((UserType & OB_USER_nRST_SHDW) != 0U)
843 {
844 /* nRST_SHDW option byte should be modified */
845 assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
846
847 /* Set value and mask for nRST_SHDW option byte */
848 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
849 optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
850 }
851
852 if((UserType & OB_USER_IWDG_SW) != 0U)
853 {
854 /* IWDG_SW option byte should be modified */
855 assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
856
857 /* Set value and mask for IWDG_SW option byte */
858 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
859 optr_reg_mask |= FLASH_OPTR_IWDG_SW;
860 }
861
862 if((UserType & OB_USER_IWDG_STOP) != 0U)
863 {
864 /* IWDG_STOP option byte should be modified */
865 assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
866
867 /* Set value and mask for IWDG_STOP option byte */
868 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
869 optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
870 }
871
872 if((UserType & OB_USER_IWDG_STDBY) != 0U)
873 {
874 /* IWDG_STDBY option byte should be modified */
875 assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
876
877 /* Set value and mask for IWDG_STDBY option byte */
878 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
879 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
880 }
881
882 if((UserType & OB_USER_WWDG_SW) != 0U)
883 {
884 /* WWDG_SW option byte should be modified */
885 assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
886
887 /* Set value and mask for WWDG_SW option byte */
888 optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
889 optr_reg_mask |= FLASH_OPTR_WWDG_SW;
890 }
891
892 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
893 defined (STM32L496xx) || defined (STM32L4A6xx) || \
894 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
895 if((UserType & OB_USER_BFB2) != 0U)
896 {
897 /* BFB2 option byte should be modified */
898 assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
899
900 /* Set value and mask for BFB2 option byte */
901 optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
902 optr_reg_mask |= FLASH_OPTR_BFB2;
903 }
904
905 if((UserType & OB_USER_DUALBANK) != 0U)
906 {
907 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
908 /* DUALBANK option byte should be modified */
909 assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DB1M));
910
911 /* Set value and mask for DUALBANK option byte */
912 optr_reg_val |= (UserConfig & FLASH_OPTR_DB1M);
913 optr_reg_mask |= FLASH_OPTR_DB1M;
914 #else
915 /* DUALBANK option byte should be modified */
916 assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
917
918 /* Set value and mask for DUALBANK option byte */
919 optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
920 optr_reg_mask |= FLASH_OPTR_DUALBANK;
921 #endif
922 }
923 #endif
924
925 if((UserType & OB_USER_nBOOT1) != 0U)
926 {
927 /* nBOOT1 option byte should be modified */
928 assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
929
930 /* Set value and mask for nBOOT1 option byte */
931 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
932 optr_reg_mask |= FLASH_OPTR_nBOOT1;
933 }
934
935 if((UserType & OB_USER_SRAM2_PE) != 0U)
936 {
937 /* SRAM2_PE option byte should be modified */
938 assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));
939
940 /* Set value and mask for SRAM2_PE option byte */
941 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);
942 optr_reg_mask |= FLASH_OPTR_SRAM2_PE;
943 }
944
945 if((UserType & OB_USER_SRAM2_RST) != 0U)
946 {
947 /* SRAM2_RST option byte should be modified */
948 assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
949
950 /* Set value and mask for SRAM2_RST option byte */
951 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
952 optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
953 }
954
955 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || \
956 defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || \
957 defined (STM32L496xx) || defined (STM32L4A6xx) || \
958 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
959 if((UserType & OB_USER_nSWBOOT0) != 0U)
960 {
961 /* nSWBOOT0 option byte should be modified */
962 assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0));
963
964 /* Set value and mask for nSWBOOT0 option byte */
965 optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0);
966 optr_reg_mask |= FLASH_OPTR_nSWBOOT0;
967 }
968
969 if((UserType & OB_USER_nBOOT0) != 0U)
970 {
971 /* nBOOT0 option byte should be modified */
972 assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0));
973
974 /* Set value and mask for nBOOT0 option byte */
975 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0);
976 optr_reg_mask |= FLASH_OPTR_nBOOT0;
977 }
978 #endif
979
980 /* Configure the option bytes register */
981 MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
982
983 /* Set OPTSTRT Bit */
984 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
985
986 /* Wait for last operation to be completed */
987 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
988
989 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
990 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
991 }
992
993 return status;
994 }
995
996 /**
997 * @brief Configure the Proprietary code readout protection of the desired addresses.
998 *
999 * @note To configure the PCROP options, the option lock bit OPTLOCK must be
1000 * cleared with the call of the HAL_FLASH_OB_Unlock() function.
1001 * @note To validate the PCROP options, the option bytes must be reloaded
1002 * through the call of the HAL_FLASH_OB_Launch() function.
1003 *
1004 * @param PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option).
1005 * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
1006 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
1007 *
1008 * @param PCROPStartAddr: specifies the start address of the Proprietary code readout protection
1009 * This parameter can be an address between begin and end of the bank
1010 *
1011 * @param PCROPEndAddr: specifies the end address of the Proprietary code readout protection
1012 * This parameter can be an address between PCROPStartAddr and end of the bank
1013 *
1014 * @retval HAL Status
1015 */
FLASH_OB_PCROPConfig(uint32_t PCROPConfig,uint32_t PCROPStartAddr,uint32_t PCROPEndAddr)1016 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
1017 {
1018 HAL_StatusTypeDef status;
1019 uint32_t reg_value;
1020 uint32_t bank1_addr;
1021 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
1022 defined (STM32L496xx) || defined (STM32L4A6xx) || \
1023 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
1024 uint32_t bank2_addr;
1025 #endif
1026
1027 /* Check the parameters */
1028 assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
1029 assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
1030 assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
1031 assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
1032
1033 /* Wait for last operation to be completed */
1034 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
1035
1036 if(status == HAL_OK)
1037 {
1038 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
1039 defined (STM32L496xx) || defined (STM32L4A6xx) || \
1040 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
1041 /* Get the information about the bank swapping */
1042 if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)
1043 {
1044 bank1_addr = FLASH_BASE;
1045 bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
1046 }
1047 else
1048 {
1049 bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
1050 bank2_addr = FLASH_BASE;
1051 }
1052 #else
1053 bank1_addr = FLASH_BASE;
1054 #endif
1055
1056 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
1057 if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
1058 {
1059 /* Configure the Proprietary code readout protection */
1060 if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
1061 {
1062 reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
1063 MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
1064
1065 reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
1066 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
1067 }
1068 else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
1069 {
1070 reg_value = ((PCROPStartAddr - FLASH_BASE) >> 4);
1071 MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
1072
1073 reg_value = ((PCROPEndAddr - FLASH_BASE) >> 4);
1074 MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
1075 }
1076 else
1077 {
1078 /* Nothing to do */
1079 }
1080 }
1081 else
1082 #endif
1083 {
1084 /* Configure the Proprietary code readout protection */
1085 if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
1086 {
1087 reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
1088 MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
1089
1090 reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
1091 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
1092 }
1093 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
1094 defined (STM32L496xx) || defined (STM32L4A6xx) || \
1095 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
1096 else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
1097 {
1098 reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
1099 MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
1100
1101 reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
1102 MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
1103 }
1104 #endif
1105 else
1106 {
1107 /* Nothing to do */
1108 }
1109 }
1110
1111 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
1112
1113 /* Set OPTSTRT Bit */
1114 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
1115
1116 /* Wait for last operation to be completed */
1117 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
1118
1119 /* If the option byte program operation is completed, disable the OPTSTRT Bit */
1120 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
1121 }
1122
1123 return status;
1124 }
1125
1126 /**
1127 * @brief Return the FLASH Write Protection Option Bytes value.
1128 *
1129 * @param[in] WRPArea: specifies the area to be returned.
1130 * This parameter can be one of the following values:
1131 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A
1132 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B
1133 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices)
1134 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices)
1135 *
1136 * @param[out] WRPStartOffset: specifies the address where to copied the start page
1137 * of the write protected area
1138 *
1139 * @param[out] WRDPEndOffset: specifies the address where to copied the end page of
1140 * the write protected area
1141 *
1142 * @retval None
1143 */
FLASH_OB_GetWRP(uint32_t WRPArea,uint32_t * WRPStartOffset,uint32_t * WRDPEndOffset)1144 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)
1145 {
1146 /* Get the configuration of the write protected area */
1147 if(WRPArea == OB_WRPAREA_BANK1_AREAA)
1148 {
1149 *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
1150 *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);
1151 }
1152 else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
1153 {
1154 *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
1155 *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);
1156 }
1157 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
1158 defined (STM32L496xx) || defined (STM32L4A6xx) || \
1159 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
1160 else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
1161 {
1162 *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
1163 *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);
1164 }
1165 else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
1166 {
1167 *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
1168 *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);
1169 }
1170 #endif
1171 else
1172 {
1173 /* Nothing to do */
1174 }
1175 }
1176
1177 /**
1178 * @brief Return the FLASH Read Protection level.
1179 * @retval FLASH ReadOut Protection Status:
1180 * This return value can be one of the following values:
1181 * @arg OB_RDP_LEVEL_0: No protection
1182 * @arg OB_RDP_LEVEL_1: Read protection of the memory
1183 * @arg OB_RDP_LEVEL_2: Full chip protection
1184 */
FLASH_OB_GetRDP(void)1185 static uint32_t FLASH_OB_GetRDP(void)
1186 {
1187 uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP);
1188
1189 if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
1190 {
1191 return (OB_RDP_LEVEL_1);
1192 }
1193 else
1194 {
1195 return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));
1196 }
1197 }
1198
1199 /**
1200 * @brief Return the FLASH User Option Byte value.
1201 * @retval The FLASH User Option Bytes values:
1202 * For STM32L47x/STM32L48x devices :
1203 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
1204 * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
1205 * BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25).
1206 * For STM32L43x/STM32L44x devices :
1207 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14),
1208 * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),
1209 * nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27).
1210 */
FLASH_OB_GetUser(void)1211 static uint32_t FLASH_OB_GetUser(void)
1212 {
1213 uint32_t user_config = READ_REG(FLASH->OPTR);
1214 CLEAR_BIT(user_config, FLASH_OPTR_RDP);
1215
1216 return user_config;
1217 }
1218
1219 /**
1220 * @brief Return the FLASH Write Protection Option Bytes value.
1221 *
1222 * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).
1223 * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2
1224 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
1225 *
1226 * @param PCROPStartAddr [out]: specifies the address where to copied the start address
1227 * of the Proprietary code readout protection
1228 *
1229 * @param PCROPEndAddr [out]: specifies the address where to copied the end address of
1230 * the Proprietary code readout protection
1231 *
1232 * @retval None
1233 */
FLASH_OB_GetPCROP(uint32_t * PCROPConfig,uint32_t * PCROPStartAddr,uint32_t * PCROPEndAddr)1234 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)
1235 {
1236 uint32_t reg_value;
1237 uint32_t bank1_addr;
1238 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
1239 defined (STM32L496xx) || defined (STM32L4A6xx) || \
1240 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
1241 uint32_t bank2_addr;
1242 #endif
1243
1244 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
1245 defined (STM32L496xx) || defined (STM32L4A6xx) || \
1246 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
1247 /* Get the information about the bank swapping */
1248 if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0U)
1249 {
1250 bank1_addr = FLASH_BASE;
1251 bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
1252 }
1253 else
1254 {
1255 bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
1256 bank2_addr = FLASH_BASE;
1257 }
1258 #else
1259 bank1_addr = FLASH_BASE;
1260 #endif
1261
1262 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
1263 if (READ_BIT(FLASH->OPTR, FLASH_OPTR_DBANK) == 0U)
1264 {
1265 if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
1266 {
1267 reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
1268 *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
1269
1270 reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
1271 *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
1272 }
1273 else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
1274 {
1275 reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
1276 *PCROPStartAddr = (reg_value << 4) + FLASH_BASE;
1277
1278 reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
1279 *PCROPEndAddr = (reg_value << 4) + FLASH_BASE;
1280 }
1281 else
1282 {
1283 /* Nothing to do */
1284 }
1285 }
1286 else
1287 #endif
1288 {
1289 if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
1290 {
1291 reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
1292 *PCROPStartAddr = (reg_value << 3) + bank1_addr;
1293
1294 reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
1295 *PCROPEndAddr = (reg_value << 3) + bank1_addr;
1296 }
1297 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \
1298 defined (STM32L496xx) || defined (STM32L4A6xx) || \
1299 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
1300 else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
1301 {
1302 reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
1303 *PCROPStartAddr = (reg_value << 3) + bank2_addr;
1304
1305 reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
1306 *PCROPEndAddr = (reg_value << 3) + bank2_addr;
1307 }
1308 #endif
1309 else
1310 {
1311 /* Nothing to do */
1312 }
1313 }
1314
1315 *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
1316 }
1317 /**
1318 * @}
1319 */
1320
1321 /**
1322 * @}
1323 */
1324
1325 #endif /* HAL_FLASH_MODULE_ENABLED */
1326
1327 /**
1328 * @}
1329 */
1330
1331 /**
1332 * @}
1333 */
1334
1335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1336
