1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal.c
4 * @author MCD Application Team
5 * @brief HAL module driver.
6 * This is the common part of the HAL initialization
7 *
8 ******************************************************************************
9 * @attention
10 *
11 * Copyright (c) 2017 STMicroelectronics.
12 * All rights reserved.
13 *
14 * This software is licensed under terms that can be found in the LICENSE file
15 * in the root directory of this software component.
16 * If no LICENSE file comes with this software, it is provided AS-IS.
17 *
18 ******************************************************************************
19 @verbatim
20 ==============================================================================
21 ##### How to use this driver #####
22 ==============================================================================
23 [..]
24 The common HAL driver contains a set of generic and common APIs that can be
25 used by the PPP peripheral drivers and the user to start using the HAL.
26 [..]
27 The HAL contains two APIs' categories:
28 (+) Common HAL APIs
29 (+) Services HAL APIs
30
31 @endverbatim
32 ******************************************************************************
33 */
34
35 /* Includes ------------------------------------------------------------------*/
36 #include "stm32h7xx_hal.h"
37
38 /** @addtogroup STM32H7xx_HAL_Driver
39 * @{
40 */
41
42 /** @defgroup HAL HAL
43 * @brief HAL module driver.
44 * @{
45 */
46
47 /* Private typedef -----------------------------------------------------------*/
48 /* Private define ------------------------------------------------------------*/
49 /**
50 * @brief STM32H7xx HAL Driver version number V1.11.1
51 */
52 #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
53 #define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */
54 #define __STM32H7xx_HAL_VERSION_SUB2 (0x01UL) /*!< [15:8] sub2 version */
55 #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
56 #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
57 |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
58 |(__STM32H7xx_HAL_VERSION_SUB2 << 8 )\
59 |(__STM32H7xx_HAL_VERSION_RC))
60
61 #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
62 #define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */
63
64 /* Private macro -------------------------------------------------------------*/
65 /* Private variables ---------------------------------------------------------*/
66 /* Exported variables --------------------------------------------------------*/
67
68 /** @defgroup HAL_Exported_Variables HAL Exported Variables
69 * @{
70 */
71 __IO uint32_t uwTick;
72 uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
73 HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
74 /**
75 * @}
76 */
77
78 /* Private function prototypes -----------------------------------------------*/
79 /* Private functions ---------------------------------------------------------*/
80
81 /** @addtogroup HAL_Exported_Functions
82 * @{
83 */
84
85 /** @addtogroup HAL_Group1
86 * @brief Initialization and de-initialization functions
87 *
88 @verbatim
89 ===============================================================================
90 ##### Initialization and de-initialization functions #####
91 ===============================================================================
92 [..] This section provides functions allowing to:
93 (+) Initializes the Flash interface the NVIC allocation and initial clock
94 configuration. It initializes the systick also when timeout is needed
95 and the backup domain when enabled.
96 (+) De-Initializes common part of the HAL.
97 (+) Configure The time base source to have 1ms time base with a dedicated
98 Tick interrupt priority.
99 (++) SysTick timer is used by default as source of time base, but user
100 can eventually implement his proper time base source (a general purpose
101 timer for example or other time source), keeping in mind that Time base
102 duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
103 handled in milliseconds basis.
104 (++) Time base configuration function (HAL_InitTick ()) is called automatically
105 at the beginning of the program after reset by HAL_Init() or at any time
106 when clock is configured, by HAL_RCC_ClockConfig().
107 (++) Source of time base is configured to generate interrupts at regular
108 time intervals. Care must be taken if HAL_Delay() is called from a
109 peripheral ISR process, the Tick interrupt line must have higher priority
110 (numerically lower) than the peripheral interrupt. Otherwise the caller
111 ISR process will be blocked.
112 (++) functions affecting time base configurations are declared as __weak
113 to make override possible in case of other implementations in user file.
114 @endverbatim
115 * @{
116 */
117
118 /**
119 * @brief This function is used to initialize the HAL Library; it must be the first
120 * instruction to be executed in the main program (before to call any other
121 * HAL function), it performs the following:
122 * Configures the SysTick to generate an interrupt each 1 millisecond,
123 * which is clocked by the HSI (at this stage, the clock is not yet
124 * configured and thus the system is running from the internal HSI at 16 MHz).
125 * Set NVIC Group Priority to 4.
126 * Calls the HAL_MspInit() callback function defined in user file
127 * "stm32h7xx_hal_msp.c" to do the global low level hardware initialization
128 *
129 * @note SysTick is used as time base for the HAL_Delay() function, the application
130 * need to ensure that the SysTick time base is always set to 1 millisecond
131 * to have correct HAL operation.
132 * @retval HAL status
133 */
HAL_Init(void)134 HAL_StatusTypeDef HAL_Init(void)
135 {
136
137 uint32_t common_system_clock;
138
139 #if defined(DUAL_CORE) && defined(CORE_CM4)
140 /* Configure Cortex-M4 Instruction cache through ART accelerator */
141 __HAL_RCC_ART_CLK_ENABLE(); /* Enable the Cortex-M4 ART Clock */
142 __HAL_ART_CONFIG_BASE_ADDRESS(0x08100000UL); /* Configure the Cortex-M4 ART Base address to the Flash Bank 2 : */
143 __HAL_ART_ENABLE(); /* Enable the Cortex-M4 ART */
144 #endif /* DUAL_CORE && CORE_CM4 */
145
146 /* Set Interrupt Group Priority */
147 HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
148
149 /* Update the SystemCoreClock global variable */
150 #if defined(RCC_D1CFGR_D1CPRE)
151 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
152 #else
153 common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
154 #endif
155
156 /* Update the SystemD2Clock global variable */
157 #if defined(RCC_D1CFGR_HPRE)
158 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
159 #else
160 SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
161 #endif
162
163 #if defined(DUAL_CORE) && defined(CORE_CM4)
164 SystemCoreClock = SystemD2Clock;
165 #else
166 SystemCoreClock = common_system_clock;
167 #endif /* DUAL_CORE && CORE_CM4 */
168
169 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
170 if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
171 {
172 return HAL_ERROR;
173 }
174
175 /* Init the low level hardware */
176 HAL_MspInit();
177
178 /* Return function status */
179 return HAL_OK;
180 }
181
182 /**
183 * @brief This function de-Initializes common part of the HAL and stops the systick.
184 * This function is optional.
185 * @retval HAL status
186 */
HAL_DeInit(void)187 HAL_StatusTypeDef HAL_DeInit(void)
188 {
189 /* Reset of all peripherals */
190 __HAL_RCC_AHB3_FORCE_RESET();
191 __HAL_RCC_AHB3_RELEASE_RESET();
192
193 __HAL_RCC_AHB1_FORCE_RESET();
194 __HAL_RCC_AHB1_RELEASE_RESET();
195
196 __HAL_RCC_AHB2_FORCE_RESET();
197 __HAL_RCC_AHB2_RELEASE_RESET();
198
199 __HAL_RCC_AHB4_FORCE_RESET();
200 __HAL_RCC_AHB4_RELEASE_RESET();
201
202 __HAL_RCC_APB3_FORCE_RESET();
203 __HAL_RCC_APB3_RELEASE_RESET();
204
205 __HAL_RCC_APB1L_FORCE_RESET();
206 __HAL_RCC_APB1L_RELEASE_RESET();
207
208 __HAL_RCC_APB1H_FORCE_RESET();
209 __HAL_RCC_APB1H_RELEASE_RESET();
210
211 __HAL_RCC_APB2_FORCE_RESET();
212 __HAL_RCC_APB2_RELEASE_RESET();
213
214 __HAL_RCC_APB4_FORCE_RESET();
215 __HAL_RCC_APB4_RELEASE_RESET();
216
217 /* De-Init the low level hardware */
218 HAL_MspDeInit();
219
220 /* Return function status */
221 return HAL_OK;
222 }
223
224 /**
225 * @brief Initializes the MSP.
226 * @retval None
227 */
HAL_MspInit(void)228 __weak void HAL_MspInit(void)
229 {
230 /* NOTE : This function Should not be modified, when the callback is needed,
231 the HAL_MspInit could be implemented in the user file
232 */
233 }
234
235 /**
236 * @brief DeInitializes the MSP.
237 * @retval None
238 */
HAL_MspDeInit(void)239 __weak void HAL_MspDeInit(void)
240 {
241 /* NOTE : This function Should not be modified, when the callback is needed,
242 the HAL_MspDeInit could be implemented in the user file
243 */
244 }
245
246 /**
247 * @brief This function configures the source of the time base.
248 * The time source is configured to have 1ms time base with a dedicated
249 * Tick interrupt priority.
250 * @note This function is called automatically at the beginning of program after
251 * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
252 * @note In the default implementation, SysTick timer is the source of time base.
253 * It is used to generate interrupts at regular time intervals.
254 * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
255 * the SysTick interrupt must have higher priority (numerically lower)
256 * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
257 * The function is declared as __weak to be overwritten in case of other
258 * implementation in user file.
259 * @param TickPriority: Tick interrupt priority.
260 * @retval HAL status
261 */
HAL_InitTick(uint32_t TickPriority)262 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
263 {
264 /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
265 if((uint32_t)uwTickFreq == 0UL)
266 {
267 return HAL_ERROR;
268 }
269
270 /* Configure the SysTick to have interrupt in 1ms time basis*/
271 if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
272 {
273 return HAL_ERROR;
274 }
275
276 /* Configure the SysTick IRQ priority */
277 if (TickPriority < (1UL << __NVIC_PRIO_BITS))
278 {
279 HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
280 uwTickPrio = TickPriority;
281 }
282 else
283 {
284 return HAL_ERROR;
285 }
286
287 /* Return function status */
288 return HAL_OK;
289 }
290
291 /**
292 * @}
293 */
294
295 /** @addtogroup HAL_Group2
296 * @brief HAL Control functions
297 *
298 @verbatim
299 ===============================================================================
300 ##### HAL Control functions #####
301 ===============================================================================
302 [..] This section provides functions allowing to:
303 (+) Provide a tick value in millisecond
304 (+) Provide a blocking delay in millisecond
305 (+) Suspend the time base source interrupt
306 (+) Resume the time base source interrupt
307 (+) Get the HAL API driver version
308 (+) Get the device identifier
309 (+) Get the device revision identifier
310 (+) Enable/Disable Debug module during SLEEP mode
311 (+) Enable/Disable Debug module during STOP mode
312 (+) Enable/Disable Debug module during STANDBY mode
313
314 @endverbatim
315 * @{
316 */
317
318 /**
319 * @brief This function is called to increment a global variable "uwTick"
320 * used as application time base.
321 * @note In the default implementation, this variable is incremented each 1ms
322 * in Systick ISR.
323 * @note This function is declared as __weak to be overwritten in case of other
324 * implementations in user file.
325 * @retval None
326 */
HAL_IncTick(void)327 __weak void HAL_IncTick(void)
328 {
329 uwTick += (uint32_t)uwTickFreq;
330 }
331
332 /**
333 * @brief Provides a tick value in millisecond.
334 * @note This function is declared as __weak to be overwritten in case of other
335 * implementations in user file.
336 * @retval tick value
337 */
HAL_GetTick(void)338 __weak uint32_t HAL_GetTick(void)
339 {
340 return uwTick;
341 }
342
343 /**
344 * @brief This function returns a tick priority.
345 * @retval tick priority
346 */
HAL_GetTickPrio(void)347 uint32_t HAL_GetTickPrio(void)
348 {
349 return uwTickPrio;
350 }
351
352 /**
353 * @brief Set new tick Freq.
354 * @retval Status
355 */
HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)356 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
357 {
358 HAL_StatusTypeDef status = HAL_OK;
359 HAL_TickFreqTypeDef prevTickFreq;
360
361 assert_param(IS_TICKFREQ(Freq));
362
363 if (uwTickFreq != Freq)
364 {
365
366 /* Back up uwTickFreq frequency */
367 prevTickFreq = uwTickFreq;
368
369 /* Update uwTickFreq global variable used by HAL_InitTick() */
370 uwTickFreq = Freq;
371
372 /* Apply the new tick Freq */
373 status = HAL_InitTick(uwTickPrio);
374 if (status != HAL_OK)
375 {
376 /* Restore previous tick frequency */
377 uwTickFreq = prevTickFreq;
378 }
379 }
380
381 return status;
382 }
383
384 /**
385 * @brief Return tick frequency.
386 * @retval tick period in Hz
387 */
HAL_GetTickFreq(void)388 HAL_TickFreqTypeDef HAL_GetTickFreq(void)
389 {
390 return uwTickFreq;
391 }
392
393 /**
394 * @brief This function provides minimum delay (in milliseconds) based
395 * on variable incremented.
396 * @note In the default implementation , SysTick timer is the source of time base.
397 * It is used to generate interrupts at regular time intervals where uwTick
398 * is incremented.
399 * @note This function is declared as __weak to be overwritten in case of other
400 * implementations in user file.
401 * @param Delay specifies the delay time length, in milliseconds.
402 * @retval None
403 */
HAL_Delay(uint32_t Delay)404 __weak void HAL_Delay(uint32_t Delay)
405 {
406 uint32_t tickstart = HAL_GetTick();
407 uint32_t wait = Delay;
408
409 /* Add a freq to guarantee minimum wait */
410 if (wait < HAL_MAX_DELAY)
411 {
412 wait += (uint32_t)(uwTickFreq);
413 }
414
415 while ((HAL_GetTick() - tickstart) < wait)
416 {
417 }
418 }
419
420 /**
421 * @brief Suspend Tick increment.
422 * @note In the default implementation , SysTick timer is the source of time base. It is
423 * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
424 * is called, the SysTick interrupt will be disabled and so Tick increment
425 * is suspended.
426 * @note This function is declared as __weak to be overwritten in case of other
427 * implementations in user file.
428 * @retval None
429 */
HAL_SuspendTick(void)430 __weak void HAL_SuspendTick(void)
431 {
432 /* Disable SysTick Interrupt */
433 SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
434 }
435
436 /**
437 * @brief Resume Tick increment.
438 * @note In the default implementation , SysTick timer is the source of time base. It is
439 * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
440 * is called, the SysTick interrupt will be enabled and so Tick increment
441 * is resumed.
442 * @note This function is declared as __weak to be overwritten in case of other
443 * implementations in user file.
444 * @retval None
445 */
HAL_ResumeTick(void)446 __weak void HAL_ResumeTick(void)
447 {
448 /* Enable SysTick Interrupt */
449 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
450 }
451
452 /**
453 * @brief Returns the HAL revision
454 * @retval version : 0xXYZR (8bits for each decimal, R for RC)
455 */
HAL_GetHalVersion(void)456 uint32_t HAL_GetHalVersion(void)
457 {
458 return __STM32H7xx_HAL_VERSION;
459 }
460
461 /**
462 * @brief Returns the device revision identifier.
463 * @retval Device revision identifier
464 */
HAL_GetREVID(void)465 uint32_t HAL_GetREVID(void)
466 {
467 return((DBGMCU->IDCODE) >> 16);
468 }
469
470 /**
471 * @brief Returns the device identifier.
472 * @retval Device identifier
473 */
HAL_GetDEVID(void)474 uint32_t HAL_GetDEVID(void)
475 {
476 return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
477 }
478
479 /**
480 * @brief Return the first word of the unique device identifier (UID based on 96 bits)
481 * @retval Device identifier
482 */
HAL_GetUIDw0(void)483 uint32_t HAL_GetUIDw0(void)
484 {
485 return(READ_REG(*((uint32_t *)UID_BASE)));
486 }
487
488 /**
489 * @brief Return the second word of the unique device identifier (UID based on 96 bits)
490 * @retval Device identifier
491 */
HAL_GetUIDw1(void)492 uint32_t HAL_GetUIDw1(void)
493 {
494 return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
495 }
496
497 /**
498 * @brief Return the third word of the unique device identifier (UID based on 96 bits)
499 * @retval Device identifier
500 */
HAL_GetUIDw2(void)501 uint32_t HAL_GetUIDw2(void)
502 {
503 return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
504 }
505
506 /**
507 * @brief Configure the internal voltage reference buffer voltage scale.
508 * @param VoltageScaling specifies the output voltage to achieve
509 * This parameter can be one of the following values:
510 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.5 V.
511 * This requires VDDA equal to or higher than 2.8 V.
512 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.048 V.
513 * This requires VDDA equal to or higher than 2.4 V.
514 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.8 V.
515 * This requires VDDA equal to or higher than 2.1 V.
516 * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.5 V.
517 * This requires VDDA equal to or higher than 1.8 V.
518 * @retval None
519 */
HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)520 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
521 {
522 /* Check the parameters */
523 assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
524
525 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
526 }
527
528 /**
529 * @brief Configure the internal voltage reference buffer high impedance mode.
530 * @param Mode specifies the high impedance mode
531 * This parameter can be one of the following values:
532 * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
533 * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
534 * @retval None
535 */
HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)536 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
537 {
538 /* Check the parameters */
539 assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
540
541 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
542 }
543
544 /**
545 * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
546 * @retval None
547 */
HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)548 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
549 {
550 /* Check the parameters */
551 assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
552
553 MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
554 }
555
556 /**
557 * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
558 * @retval HAL_OK/HAL_TIMEOUT
559 */
HAL_SYSCFG_EnableVREFBUF(void)560 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
561 {
562 uint32_t tickstart;
563
564 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
565
566 /* Get Start Tick*/
567 tickstart = HAL_GetTick();
568
569 /* Wait for VRR bit */
570 while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
571 {
572 if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
573 {
574 return HAL_TIMEOUT;
575 }
576 }
577
578 return HAL_OK;
579 }
580
581 /**
582 * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
583 *
584 * @retval None
585 */
HAL_SYSCFG_DisableVREFBUF(void)586 void HAL_SYSCFG_DisableVREFBUF(void)
587 {
588 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
589 }
590
591 #if defined(SYSCFG_PMCR_EPIS_SEL)
592 /**
593 * @brief Ethernet PHY Interface Selection either MII or RMII
594 * @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface
595 * This parameter can be one of the following values:
596 * @arg SYSCFG_ETH_MII : Select the Media Independent Interface
597 * @arg SYSCFG_ETH_RMII: Select the Reduced Media Independent Interface
598 * @retval None
599 */
HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)600 void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
601 {
602 /* Check the parameter */
603 assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
604
605 MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, (uint32_t)(SYSCFG_ETHInterface));
606 }
607 #endif /* SYSCFG_PMCR_EPIS_SEL */
608
609 /**
610 * @brief Analog Switch control for dual analog pads.
611 * @param SYSCFG_AnalogSwitch: Selects the analog pad
612 * This parameter can be one or a combination of the following values:
613 * @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
614 * @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch
615 * @arg SYSCFG_SWITCH_PC2 : Select PC2 analog switch
616 * @arg SYSCFG_SWITCH_PC3: Select PC3 analog switch
617 * @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (PXn and PXn_C)
618 * This parameter can be one or a combination of the following values:
619 * @arg SYSCFG_SWITCH_PA0_OPEN
620 * @arg SYSCFG_SWITCH_PA0_CLOSE
621 * @arg SYSCFG_SWITCH_PA1_OPEN
622 * @arg SYSCFG_SWITCH_PA1_CLOSE
623 * @arg SYSCFG_SWITCH_PC2_OPEN
624 * @arg SYSCFG_SWITCH_PC2_CLOSE
625 * @arg SYSCFG_SWITCH_PC3_OPEN
626 * @arg SYSCFG_SWITCH_PC3_CLOSE
627 * @retval None
628 */
629
HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch,uint32_t SYSCFG_SwitchState)630 void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
631 {
632 /* Check the parameter */
633 assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
634 assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
635
636 MODIFY_REG(SYSCFG->PMCR, (uint32_t) SYSCFG_AnalogSwitch, (uint32_t)(SYSCFG_SwitchState));
637 }
638
639 #if defined(SYSCFG_PMCR_BOOSTEN)
640 /**
641 * @brief Enables the booster to reduce the total harmonic distortion of the analog
642 * switch when the supply voltage is lower than 2.7 V.
643 * @note Activating the booster allows to guaranty the analog switch AC performance
644 * when the supply voltage is below 2.7 V: in this case, the analog switch
645 * performance is the same on the full voltage range
646 * @retval None
647 */
HAL_SYSCFG_EnableBOOST(void)648 void HAL_SYSCFG_EnableBOOST(void)
649 {
650 SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
651 }
652
653 /**
654 * @brief Disables the booster
655 * @note Activating the booster allows to guaranty the analog switch AC performance
656 * when the supply voltage is below 2.7 V: in this case, the analog switch
657 * performance is the same on the full voltage range
658 * @retval None
659 */
HAL_SYSCFG_DisableBOOST(void)660 void HAL_SYSCFG_DisableBOOST(void)
661 {
662 CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;
663 }
664 #endif /* SYSCFG_PMCR_BOOSTEN */
665
666 #if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0)
667 /**
668 * @brief BootCM7 address 0 configuration
669 * @param BootRegister :Specifies the Boot Address register (Address0 or Address1)
670 * This parameter can be one of the following values:
671 * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
672 * @arg SYSCFG_BOOT_ADDR1: Select the boot address1
673 * @param BootAddress :Specifies the CM7 Boot Address to be loaded in Address0 or Address1
674 * @retval None
675 */
HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister,uint32_t BootAddress)676 void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
677 {
678 /* Check the parameters */
679 assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
680 assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
681 if ( BootRegister == SYSCFG_BOOT_ADDR0 )
682 {
683 /* Configure CM7 BOOT ADD0 */
684 #if defined(DUAL_CORE)
685 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos));
686 #else
687 MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos));
688 #endif /*DUAL_CORE*/
689 }
690 else
691 {
692 /* Configure CM7 BOOT ADD1 */
693 #if defined(DUAL_CORE)
694 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16));
695 #else
696 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
697 #endif /*DUAL_CORE*/
698 }
699 }
700 #endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0 */
701
702 #if defined(DUAL_CORE)
703 /**
704 * @brief BootCM4 address 0 configuration
705 * @param BootRegister :Specifies the Boot Address register (Address0 or Address1)
706 * This parameter can be one of the following values:
707 * @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
708 * @arg SYSCFG_BOOT_ADDR1: Select the boot address1
709 * @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1
710 * @retval None
711 */
HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister,uint32_t BootAddress)712 void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
713 {
714 /* Check the parameters */
715 assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
716 assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
717
718 if ( BootRegister == SYSCFG_BOOT_ADDR0 )
719 {
720 /* Configure CM4 BOOT ADD0 */
721 MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos));
722 }
723
724 else
725 {
726 /* Configure CM4 BOOT ADD1 */
727 MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16));
728 }
729 }
730
731 /**
732 * @brief Enables the Cortex-M7 boot
733 * @retval None
734 */
HAL_SYSCFG_EnableCM7BOOT(void)735 void HAL_SYSCFG_EnableCM7BOOT(void)
736 {
737 SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7);
738 }
739
740 /**
741 * @brief Disables the Cortex-M7 boot
742 * @note Disabling the boot will gate the CPU clock
743 * @retval None
744 */
HAL_SYSCFG_DisableCM7BOOT(void)745 void HAL_SYSCFG_DisableCM7BOOT(void)
746 {
747 CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ;
748 }
749
750 /**
751 * @brief Enables the Cortex-M4 boot
752 * @retval None
753 */
HAL_SYSCFG_EnableCM4BOOT(void)754 void HAL_SYSCFG_EnableCM4BOOT(void)
755 {
756 SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
757 }
758
759 /**
760 * @brief Disables the Cortex-M4 boot
761 * @note Disabling the boot will gate the CPU clock
762 * @retval None
763 */
HAL_SYSCFG_DisableCM4BOOT(void)764 void HAL_SYSCFG_DisableCM4BOOT(void)
765 {
766 CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
767 }
768 #endif /*DUAL_CORE*/
769 /**
770 * @brief Enables the I/O Compensation Cell.
771 * @note The I/O compensation cell can be used only when the device supply
772 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
773 * @retval None
774 */
HAL_EnableCompensationCell(void)775 void HAL_EnableCompensationCell(void)
776 {
777 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) ;
778 }
779
780 /**
781 * @brief Power-down the I/O Compensation Cell.
782 * @note The I/O compensation cell can be used only when the device supply
783 * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V.
784 * @retval None
785 */
HAL_DisableCompensationCell(void)786 void HAL_DisableCompensationCell(void)
787 {
788 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);
789 }
790
791
792 /**
793 * @brief To Enable optimize the I/O speed when the product voltage is low.
794 * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
795 * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
796 * higher than 2.5 V might be destructive.
797 * @retval None
798 */
HAL_SYSCFG_EnableIOSpeedOptimize(void)799 void HAL_SYSCFG_EnableIOSpeedOptimize(void)
800 {
801 #if defined(SYSCFG_CCCSR_HSLV)
802 SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
803 #else
804 SET_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3));
805 #endif /* SYSCFG_CCCSR_HSLV */
806 }
807
808 /**
809 * @brief To Disable optimize the I/O speed when the product voltage is low.
810 * @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
811 * used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
812 * higher than 2.5 V might be destructive.
813 * @retval None
814 */
HAL_SYSCFG_DisableIOSpeedOptimize(void)815 void HAL_SYSCFG_DisableIOSpeedOptimize(void)
816 {
817 #if defined(SYSCFG_CCCSR_HSLV)
818 CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);
819 #else
820 CLEAR_BIT(SYSCFG->CCCSR, (SYSCFG_CCCSR_HSLV0| SYSCFG_CCCSR_HSLV1 | SYSCFG_CCCSR_HSLV2 | SYSCFG_CCCSR_HSLV3));
821 #endif /* SYSCFG_CCCSR_HSLV */
822 }
823
824 /**
825 * @brief Code selection for the I/O Compensation cell
826 * @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
827 * This parameter can be one of the following values:
828 * @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
829 * @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
830 * @retval None
831 */
HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)832 void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
833 {
834 /* Check the parameter */
835 assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
836 MODIFY_REG(SYSCFG->CCCSR, SYSCFG_CCCSR_CS, (uint32_t)(SYSCFG_CompCode));
837 }
838
839 /**
840 * @brief Code selection for the I/O Compensation cell
841 * @param SYSCFG_PMOSCode: PMOS compensation code
842 * This code is applied to the I/O compensation cell when the CS bit of the
843 * SYSCFG_CMPCR is set
844 * @param SYSCFG_NMOSCode: NMOS compensation code
845 * This code is applied to the I/O compensation cell when the CS bit of the
846 * SYSCFG_CMPCR is set
847 * @retval None
848 */
HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode,uint32_t SYSCFG_NMOSCode)849 void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
850 {
851 /* Check the parameter */
852 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
853 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
854 MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC|SYSCFG_CCCR_PCC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
855 }
856
857 #if defined(SYSCFG_CCCR_NCC_MMC)
858 /**
859 * @brief Code selection for the I/O Compensation cell
860 * @param SYSCFG_PMOSCode: VDDMMC PMOS compensation code
861 * This code is applied to the I/O compensation cell when the CS bit of the
862 * SYSCFG_CMPCR is set
863 * @param SYSCFG_NMOSCode: VDDMMC NMOS compensation code
864 * This code is applied to the I/O compensation cell when the CS bit of the
865 * SYSCFG_CMPCR is set
866 * @retval None
867 */
HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode,uint32_t SYSCFG_NMOSCode)868 void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
869 {
870 /* Check the parameter */
871 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
872 assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
873 MODIFY_REG(SYSCFG->CCCR, (SYSCFG_CCCR_NCC_MMC | SYSCFG_CCCR_PCC_MMC), (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
874 }
875 #endif /* SYSCFG_CCCR_NCC_MMC */
876
877 #if defined(SYSCFG_ADC2ALT_ADC2_ROUT0)
878 /** @brief SYSCFG ADC2 internal input alternate connection macros
879 * @param Adc2AltRout0 This parameter can be a value of :
880 * @arg @ref SYSCFG_ADC2_ROUT0_DAC1_1 DAC1_out1 connected to ADC2 VINP[16]
881 * @arg @ref SYSCFG_ADC2_ROUT0_VBAT4 VBAT/4 connected to ADC2 VINP[16]
882 */
HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0)883 void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0)
884 {
885 /* Check the parameters */
886 assert_param(IS_SYSCFG_ADC2ALT_ROUT0(Adc2AltRout0));
887
888 MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0);
889 }
890 #endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/
891
892 #if defined(SYSCFG_ADC2ALT_ADC2_ROUT1)
893 /** @brief SYSCFG ADC2 internal input alternate connection macros
894 * @param Adc2AltRout1 This parameter can be a value of :
895 * @arg @ref SYSCFG_ADC2_ROUT1_DAC1_2 DAC1_out2 connected to ADC2 VINP[17]
896 * @arg @ref SYSCFG_ADC2_ROUT1_VREFINT VREFINT connected to ADC2 VINP[17]
897 */
HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1)898 void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1)
899 {
900 /* Check the parameters */
901 assert_param(IS_SYSCFG_ADC2ALT_ROUT1(Adc2AltRout1));
902
903 MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1);
904 }
905 #endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/
906
907 /**
908 * @brief Enable the Debug Module during Domain1/CDomain SLEEP mode
909 * @retval None
910 */
HAL_DBGMCU_EnableDBGSleepMode(void)911 void HAL_DBGMCU_EnableDBGSleepMode(void)
912 {
913 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
914 }
915
916 /**
917 * @brief Disable the Debug Module during Domain1/CDomain SLEEP mode
918 * @retval None
919 */
HAL_DBGMCU_DisableDBGSleepMode(void)920 void HAL_DBGMCU_DisableDBGSleepMode(void)
921 {
922 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
923 }
924
925
926 /**
927 * @brief Enable the Debug Module during Domain1/CDomain STOP mode
928 * @retval None
929 */
HAL_DBGMCU_EnableDBGStopMode(void)930 void HAL_DBGMCU_EnableDBGStopMode(void)
931 {
932 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
933 }
934
935 /**
936 * @brief Disable the Debug Module during Domain1/CDomain STOP mode
937 * @retval None
938 */
HAL_DBGMCU_DisableDBGStopMode(void)939 void HAL_DBGMCU_DisableDBGStopMode(void)
940 {
941 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
942 }
943
944 /**
945 * @brief Enable the Debug Module during Domain1/CDomain STANDBY mode
946 * @retval None
947 */
HAL_DBGMCU_EnableDBGStandbyMode(void)948 void HAL_DBGMCU_EnableDBGStandbyMode(void)
949 {
950 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
951 }
952
953 /**
954 * @brief Disable the Debug Module during Domain1/CDomain STANDBY mode
955 * @retval None
956 */
HAL_DBGMCU_DisableDBGStandbyMode(void)957 void HAL_DBGMCU_DisableDBGStandbyMode(void)
958 {
959 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
960 }
961
962 #if defined(DUAL_CORE)
963 /**
964 * @brief Enable the Debug Module during Domain1 SLEEP mode
965 * @retval None
966 */
HAL_EnableDomain2DBGSleepMode(void)967 void HAL_EnableDomain2DBGSleepMode(void)
968 {
969 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
970 }
971
972 /**
973 * @brief Disable the Debug Module during Domain2 SLEEP mode
974 * @retval None
975 */
HAL_DisableDomain2DBGSleepMode(void)976 void HAL_DisableDomain2DBGSleepMode(void)
977 {
978 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
979 }
980
981 /**
982 * @brief Enable the Debug Module during Domain2 STOP mode
983 * @retval None
984 */
HAL_EnableDomain2DBGStopMode(void)985 void HAL_EnableDomain2DBGStopMode(void)
986 {
987 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
988 }
989
990 /**
991 * @brief Disable the Debug Module during Domain2 STOP mode
992 * @retval None
993 */
HAL_DisableDomain2DBGStopMode(void)994 void HAL_DisableDomain2DBGStopMode(void)
995 {
996 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
997 }
998
999 /**
1000 * @brief Enable the Debug Module during Domain2 STANDBY mode
1001 * @retval None
1002 */
HAL_EnableDomain2DBGStandbyMode(void)1003 void HAL_EnableDomain2DBGStandbyMode(void)
1004 {
1005 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1006 }
1007
1008 /**
1009 * @brief Disable the Debug Module during Domain2 STANDBY mode
1010 * @retval None
1011 */
HAL_DisableDomain2DBGStandbyMode(void)1012 void HAL_DisableDomain2DBGStandbyMode(void)
1013 {
1014 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
1015 }
1016 #endif /*DUAL_CORE*/
1017
1018 #if defined(DBGMCU_CR_DBG_STOPD3)
1019 /**
1020 * @brief Enable the Debug Module during Domain3/SRDomain STOP mode
1021 * @retval None
1022 */
HAL_EnableDomain3DBGStopMode(void)1023 void HAL_EnableDomain3DBGStopMode(void)
1024 {
1025 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1026 }
1027
1028 /**
1029 * @brief Disable the Debug Module during Domain3/SRDomain STOP mode
1030 * @retval None
1031 */
HAL_DisableDomain3DBGStopMode(void)1032 void HAL_DisableDomain3DBGStopMode(void)
1033 {
1034 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);
1035 }
1036 #endif /*DBGMCU_CR_DBG_STOPD3*/
1037
1038 #if defined(DBGMCU_CR_DBG_STANDBYD3)
1039 /**
1040 * @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode
1041 * @retval None
1042 */
HAL_EnableDomain3DBGStandbyMode(void)1043 void HAL_EnableDomain3DBGStandbyMode(void)
1044 {
1045 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1046 }
1047
1048 /**
1049 * @brief Disable the Debug Module during Domain3/SRDomain STANDBY mode
1050 * @retval None
1051 */
HAL_DisableDomain3DBGStandbyMode(void)1052 void HAL_DisableDomain3DBGStandbyMode(void)
1053 {
1054 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);
1055 }
1056 #endif /*DBGMCU_CR_DBG_STANDBYD3*/
1057
1058 /**
1059 * @brief Set the FMC Memory Mapping Swapping config.
1060 * @param BankMapConfig: Defines the FMC Bank mapping configuration. This parameter can be
1061 FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
1062 * @retval HAL state
1063 */
HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)1064 void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig)
1065 {
1066 /* Check the parameter */
1067 assert_param(IS_FMC_SWAPBMAP_MODE(BankMapConfig));
1068 MODIFY_REG(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP, BankMapConfig);
1069 }
1070
1071 /**
1072 * @brief Get FMC Bank mapping mode.
1073 * @retval The FMC Bank mapping mode. This parameter can be
1074 FMC_SWAPBMAP_DISABLE, FMC_SWAPBMAP_SDRAM_SRAM, FMC_SWAPBMAP_SDRAMB2
1075 */
HAL_GetFMCMemorySwappingConfig(void)1076 uint32_t HAL_GetFMCMemorySwappingConfig(void)
1077 {
1078 return READ_BIT(FMC_Bank1_R->BTCR[0], FMC_BCR1_BMAP);
1079 }
1080
1081 /**
1082 * @brief Configure the EXTI input event line edge
1083 * @note No edge configuration for direct lines but for configurable lines:(EXTI_LINE0..EXTI_LINE21),
1084 * EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
1085 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1086 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1087 * @param EXTI_Edge: Specifies EXTI line Edge used.
1088 * This parameter can be one of the following values :
1089 * @arg EXTI_RISING_EDGE : Configurable line, with Rising edge trigger detection
1090 * @arg EXTI_FALLING_EDGE: Configurable line, with Falling edge trigger detection
1091 * @retval None
1092 */
HAL_EXTI_EdgeConfig(uint32_t EXTI_Line,uint32_t EXTI_Edge)1093 void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge )
1094 {
1095 /* Check the parameter */
1096 assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
1097 assert_param(IS_EXTI_EDGE_LINE(EXTI_Edge));
1098
1099 /* Clear Rising Falling edge configuration */
1100 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1101 CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1102
1103 if( (EXTI_Edge & EXTI_RISING_EDGE) == EXTI_RISING_EDGE)
1104 {
1105 SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1106 }
1107 if( (EXTI_Edge & EXTI_FALLING_EDGE) == EXTI_FALLING_EDGE)
1108 {
1109 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1110 }
1111 }
1112
1113 /**
1114 * @brief Generates a Software interrupt on selected EXTI line.
1115 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1116 * (EXTI_LINE0..EXTI_LINE21),EXTI_LINE49,EXTI_LINE51,EXTI_LINE82,EXTI_LINE84,EXTI_LINE85 and EXTI_LINE86.
1117 * @retval None
1118 */
HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)1119 void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
1120 {
1121 /* Check the parameters */
1122 assert_param(IS_HAL_EXTI_CONFIG_LINE(EXTI_Line));
1123
1124 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER1)) + ((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1125 }
1126
1127
1128 /**
1129 * @brief Clears the EXTI's line pending flags for Domain D1
1130 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1131 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1132 * @retval None
1133 */
HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)1134 void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
1135 {
1136 /* Check the parameters */
1137 assert_param(IS_EXTI_D1_LINE(EXTI_Line));
1138 WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1139
1140 }
1141
1142 #if defined(DUAL_CORE)
1143 /**
1144 * @brief Clears the EXTI's line pending flags for Domain D2
1145 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1146 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1147 * @retval None
1148 */
HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)1149 void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
1150 {
1151 /* Check the parameters */
1152 assert_param(IS_EXTI_D2_LINE(EXTI_Line));
1153 WRITE_REG(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1154 }
1155
1156 #endif /*DUAL_CORE*/
1157 /**
1158 * @brief Configure the EXTI input event line for Domain D1
1159 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1160 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1161 * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
1162 * This parameter can be one or a combination of the following values :
1163 * @arg EXTI_MODE_IT : Interrupt Mode selected
1164 * @arg EXTI_MODE_EVT : Event Mode selected
1165 * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
1166
1167 * @retval None
1168 */
HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line,uint32_t EXTI_Mode,uint32_t EXTI_LineCmd)1169 void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd )
1170 {
1171 /* Check the parameter */
1172 assert_param(IS_EXTI_D1_LINE(EXTI_Line));
1173 assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
1174
1175 if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
1176 {
1177 if( EXTI_LineCmd == 0UL)
1178 {
1179 /* Clear EXTI line configuration */
1180 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
1181 }
1182 else
1183 {
1184 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D1->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1185 }
1186 }
1187
1188 if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
1189 {
1190 if( EXTI_LineCmd == 0UL)
1191 {
1192 /* Clear EXTI line configuration */
1193 CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1194 }
1195 else
1196 {
1197 SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D1->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1198 }
1199 }
1200 }
1201
1202 #if defined(DUAL_CORE)
1203 /**
1204 * @brief Configure the EXTI input event line for Domain D2
1205 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1206 * (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
1207 * @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
1208 * This parameter can be one or a combination of the following values :
1209 * @arg EXTI_MODE_IT : Interrupt Mode selected
1210 * @arg EXTI_MODE_EVT : Event Mode selected
1211 * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
1212
1213 * @retval None
1214 */
HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line,uint32_t EXTI_Mode,uint32_t EXTI_LineCmd)1215 void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd )
1216 {
1217 /* Check the parameter */
1218 assert_param(IS_EXTI_D2_LINE(EXTI_Line));
1219 assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
1220
1221 if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
1222 {
1223 if( EXTI_LineCmd == 0UL)
1224 {
1225 /* Clear EXTI line configuration */
1226 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
1227 }
1228 else
1229 {
1230 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1231 }
1232 }
1233
1234 if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
1235 {
1236 if( EXTI_LineCmd == 0UL)
1237 {
1238 /* Clear EXTI line configuration */
1239 CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1240 }
1241 else
1242 {
1243 SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1244 }
1245 }
1246 }
1247 #endif /*DUAL_CORE*/
1248
1249 /**
1250 * @brief Configure the EXTI input event line for Domain D3
1251 * @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
1252 * (EXTI_LINE0...EXTI_LINE15),(EXTI_LINE19...EXTI_LINE21),EXTI_LINE25, EXTI_LINE34,
1253 * EXTI_LINE35,EXTI_LINE41,(EXTI_LINE48...EXTI_LINE53)
1254 * @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
1255 * @param EXTI_ClearSrc: Specifies the clear source of D3 pending event.
1256 * This parameter can be one of the following values :
1257 * @arg BDMA_CH6_CLEAR : BDMA ch6 event selected as D3 domain pendclear source
1258 * @arg BDMA_CH7_CLEAR : BDMA ch7 event selected as D3 domain pendclear source
1259 * @arg LPTIM4_OUT_CLEAR : LPTIM4 out selected as D3 domain pendclear source
1260 * @arg LPTIM5_OUT_CLEAR : LPTIM5 out selected as D3 domain pendclear source
1261 * @retval None
1262 */
HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line,uint32_t EXTI_LineCmd,uint32_t EXTI_ClearSrc)1263 void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc )
1264 {
1265 __IO uint32_t *pRegv;
1266
1267 /* Check the parameter */
1268 assert_param(IS_EXTI_D3_LINE(EXTI_Line));
1269 assert_param(IS_EXTI_D3_CLEAR(EXTI_ClearSrc));
1270
1271 if( EXTI_LineCmd == 0UL)
1272 {
1273 /* Clear EXTI line configuration */
1274 CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) + ((EXTI_Line >> 5 ) * 0x20UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
1275 }
1276 else
1277 {
1278 SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI->D3PMR1)) +((EXTI_Line >> 5 ) * 0x20UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
1279 }
1280
1281 if(((EXTI_Line>>4)%2UL) == 0UL)
1282 {
1283 pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1L)) + ((EXTI_Line >> 5 ) * 0x20UL));
1284 }
1285 else
1286 {
1287 pRegv = (__IO uint32_t *) (((uint32_t) &(EXTI->D3PCR1H)) + ((EXTI_Line >> 5 ) * 0x20UL));
1288 }
1289 MODIFY_REG(*pRegv, (uint32_t)(3UL << ((EXTI_Line*2UL) & 0x1FUL)), (uint32_t)(EXTI_ClearSrc << ((EXTI_Line*2UL) & 0x1FUL)));
1290
1291 }
1292
1293
1294
1295 /**
1296 * @}
1297 */
1298
1299 /**
1300 * @}
1301 */
1302
1303 /**
1304 * @}
1305 */
1306
1307 /**
1308 * @}
1309 */
1310
1311
