1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_dac_ex.c
4 * @author MCD Application Team
5 * @brief Extended DAC HAL module driver.
6 * This file provides firmware functions to manage the extended
7 * functionalities of the DAC peripheral.
8 *
9 *
10 ******************************************************************************
11 * @attention
12 *
13 * Copyright (c) 2019 STMicroelectronics.
14 * All rights reserved.
15 *
16 * This software is licensed under terms that can be found in the LICENSE file
17 * in the root directory of this software component.
18 * If no LICENSE file comes with this software, it is provided AS-IS.
19 *
20 ******************************************************************************
21 @verbatim
22 ==============================================================================
23 ##### How to use this driver #####
24 ==============================================================================
25 [..]
26 *** Dual mode IO operation ***
27 ==============================
28 [..]
29 (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
30 for dual mode operation.
31 If software trigger is selected, using HAL_DACEx_DualStart() will start
32 the conversion of the value previously set by HAL_DACEx_DualSetValue().
33 (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
34 for dual mode operation.
35 (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
36 for dual mode operation using DMA to feed DAC converters.
37 First issued trigger will start the conversion of the value previously
38 set by HAL_DACEx_DualSetValue().
39 The same callbacks that are used in single mode are called in dual mode to notify
40 transfer completion (half complete or complete), errors or underrun.
41 (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
42 for dual mode operation using DMA to feed DAC converters.
43 (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
44 Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
45 HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
46 Channel 1 and Channel 2.
47 *** Signal generation operation ***
48 ===================================
49 [..]
50 (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
51 (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
52
53 (+) Use HAL_DACEx_SawtoothWaveGenerate() to generate sawtooth signal.
54 (+) Use HAL_DACEx_SawtoothWaveDataReset() to reset sawtooth wave.
55 (+) Use HAL_DACEx_SawtoothWaveDataStep() to step sawtooth wave.
56
57 (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
58 (+) HAL_DACEx_SetUserTrimming to set user trimming value.
59 (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
60 after reset, user setting if HAL_DACEx_SetUserTrimming have been used
61 at least one time after reset).
62
63 @endverbatim
64 ******************************************************************************
65 */
66
67
68 /* Includes ------------------------------------------------------------------*/
69 #include "stm32g4xx_hal.h"
70
71 /** @addtogroup STM32G4xx_HAL_Driver
72 * @{
73 */
74
75 #ifdef HAL_DAC_MODULE_ENABLED
76
77 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
78
79 /** @defgroup DACEx DACEx
80 * @brief DAC Extended HAL module driver
81 * @{
82 */
83
84 /* Private typedef -----------------------------------------------------------*/
85 /* Private define ------------------------------------------------------------*/
86
87 /* Delay for DAC minimum trimming time. */
88 /* Note: minimum time needed between two calibration steps */
89 /* The delay below is specified under conditions: */
90 /* - DAC channel output buffer enabled */
91 /* Literal set to maximum value (refer to device datasheet, */
92 /* electrical characteristics, parameter "tTRIM"). */
93 /* Unit: us */
94 #define DAC_DELAY_TRIM_US (50UL) /*!< Delay for DAC minimum trimming time */
95
96 /* Private macro -------------------------------------------------------------*/
97 /* Private variables ---------------------------------------------------------*/
98 /* Private function prototypes -----------------------------------------------*/
99 /* Exported functions --------------------------------------------------------*/
100
101 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
102 * @{
103 */
104
105 /** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
106 * @brief Extended IO operation functions
107 *
108 @verbatim
109 ==============================================================================
110 ##### Extended features functions #####
111 ==============================================================================
112 [..] This section provides functions allowing to:
113 (+) Start conversion.
114 (+) Stop conversion.
115 (+) Start conversion and enable DMA transfer.
116 (+) Stop conversion and disable DMA transfer.
117 (+) Get result of conversion.
118 (+) Get result of dual mode conversion.
119
120 @endverbatim
121 * @{
122 */
123
124
125 /**
126 * @brief Enables DAC and starts conversion of both channels.
127 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
128 * the configuration information for the specified DAC.
129 * @retval HAL status
130 */
HAL_DACEx_DualStart(DAC_HandleTypeDef * hdac)131 HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
132 {
133 uint32_t tmp_swtrig = 0UL;
134 __IO uint32_t wait_loop_index;
135
136 /* Check the DAC peripheral handle */
137 if (hdac == NULL)
138 {
139 return HAL_ERROR;
140 }
141
142 /* Check the parameters */
143 assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
144
145 /* Process locked */
146 __HAL_LOCK(hdac);
147
148 /* Change DAC state */
149 hdac->State = HAL_DAC_STATE_BUSY;
150
151 /* Enable the Peripheral */
152 __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
153 __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
154 /* Ensure minimum wait before using peripheral after enabling it */
155 /* Wait loop initialization and execution */
156 /* Note: Variable divided by 2 to compensate partially */
157 /* CPU processing cycles, scaling in us split to not */
158 /* exceed 32 bits register capacity and handle low frequency. */
159 wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
160 while (wait_loop_index != 0UL)
161 {
162 wait_loop_index--;
163 }
164
165 /* Check if software trigger enabled */
166 if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
167 {
168 tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
169 }
170 if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
171 {
172 tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
173 }
174 /* Enable the selected DAC software conversion*/
175 SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
176
177 /* Change DAC state */
178 hdac->State = HAL_DAC_STATE_READY;
179
180 /* Process unlocked */
181 __HAL_UNLOCK(hdac);
182
183 /* Return function status */
184 return HAL_OK;
185 }
186
187 /**
188 * @brief Disables DAC and stop conversion of both channels.
189 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
190 * the configuration information for the specified DAC.
191 * @retval HAL status
192 */
HAL_DACEx_DualStop(DAC_HandleTypeDef * hdac)193 HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
194 {
195 /* Check the DAC peripheral handle */
196 if (hdac == NULL)
197 {
198 return HAL_ERROR;
199 }
200
201 /* Check the parameters */
202 assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
203
204 /* Disable the Peripheral */
205 __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
206 __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
207
208 /* Change DAC state */
209 hdac->State = HAL_DAC_STATE_READY;
210
211 /* Return function status */
212 return HAL_OK;
213 }
214
215 /**
216 * @brief Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
217 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
218 * the configuration information for the specified DAC.
219 * @param Channel The DAC channel that will request data from DMA.
220 * This parameter can be one of the following values:
221 * @arg DAC_CHANNEL_1: DAC Channel1 selected
222 * @arg DAC_CHANNEL_2: DAC Channel2 selected
223 * @param pData The destination peripheral Buffer address.
224 * @param Length The length of data to be transferred from memory to DAC peripheral
225 * @param Alignment Specifies the data alignment for DAC channel.
226 * This parameter can be one of the following values:
227 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
228 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
229 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
230 * @retval HAL status
231 */
HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel,const uint32_t * pData,uint32_t Length,uint32_t Alignment)232 HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
233 const uint32_t *pData, uint32_t Length, uint32_t Alignment)
234 {
235 HAL_StatusTypeDef status;
236 uint32_t tmpreg = 0UL;
237 __IO uint32_t wait_loop_index;
238
239 /* Check the DAC peripheral handle */
240 if (hdac == NULL)
241 {
242 return HAL_ERROR;
243 }
244
245 /* Check the parameters */
246 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
247 /* Ensure Channel 2 exists for this particular DAC instance */
248 assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
249 assert_param(IS_DAC_ALIGN(Alignment));
250
251 /* Process locked */
252 __HAL_LOCK(hdac);
253
254 /* Change DAC state */
255 hdac->State = HAL_DAC_STATE_BUSY;
256
257 if (Channel == DAC_CHANNEL_1)
258 {
259 /* Set the DMA transfer complete callback for channel1 */
260 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
261
262 /* Set the DMA half transfer complete callback for channel1 */
263 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
264
265 /* Set the DMA error callback for channel1 */
266 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
267
268 /* Enable the selected DAC channel1 DMA request */
269 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
270 }
271 else
272 {
273 /* Set the DMA transfer complete callback for channel2 */
274 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
275
276 /* Set the DMA half transfer complete callback for channel2 */
277 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
278
279 /* Set the DMA error callback for channel2 */
280 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
281
282 /* Enable the selected DAC channel2 DMA request */
283 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
284 }
285
286 switch (Alignment)
287 {
288 case DAC_ALIGN_12B_R:
289 /* Get DHR12R1 address */
290 tmpreg = (uint32_t)&hdac->Instance->DHR12RD;
291 break;
292 case DAC_ALIGN_12B_L:
293 /* Get DHR12L1 address */
294 tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
295 break;
296 case DAC_ALIGN_8B_R:
297 /* Get DHR8R1 address */
298 tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
299 break;
300 default:
301 break;
302 }
303
304 /* Enable the DMA channel */
305 if (Channel == DAC_CHANNEL_1)
306 {
307 /* Enable the DAC DMA underrun interrupt */
308 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
309
310 /* Enable the DMA channel */
311 status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
312 }
313 else
314 {
315 /* Enable the DAC DMA underrun interrupt */
316 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
317
318 /* Enable the DMA channel */
319 status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
320 }
321
322 /* Process Unlocked */
323 __HAL_UNLOCK(hdac);
324
325 if (status == HAL_OK)
326 {
327 /* Enable the Peripheral */
328 __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
329 __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
330 /* Ensure minimum wait before using peripheral after enabling it */
331 /* Wait loop initialization and execution */
332 /* Note: Variable divided by 2 to compensate partially */
333 /* CPU processing cycles, scaling in us split to not */
334 /* exceed 32 bits register capacity and handle low frequency. */
335 wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
336 while (wait_loop_index != 0UL)
337 {
338 wait_loop_index--;
339 }
340 }
341 else
342 {
343 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
344 }
345
346 /* Return function status */
347 return status;
348 }
349
350 /**
351 * @brief Disables DAC and stop conversion both channel.
352 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
353 * the configuration information for the specified DAC.
354 * @param Channel The DAC channel that requests data from DMA.
355 * This parameter can be one of the following values:
356 * @arg DAC_CHANNEL_1: DAC Channel1 selected
357 * @arg DAC_CHANNEL_2: DAC Channel2 selected
358 * @retval HAL status
359 */
HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef * hdac,uint32_t Channel)360 HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
361 {
362 HAL_StatusTypeDef status;
363
364 /* Check the DAC peripheral handle */
365 if (hdac == NULL)
366 {
367 return HAL_ERROR;
368 }
369
370 /* Ensure Channel 2 exists for this particular DAC instance */
371 assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
372
373 /* Disable the selected DAC channel DMA request */
374 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
375
376 /* Disable the Peripheral */
377 __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
378 __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
379
380 /* Disable the DMA channel */
381
382 /* Channel1 is used */
383 if (Channel == DAC_CHANNEL_1)
384 {
385 /* Disable the DMA channel */
386 status = HAL_DMA_Abort(hdac->DMA_Handle1);
387
388 /* Disable the DAC DMA underrun interrupt */
389 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
390 }
391 else
392 {
393 /* Disable the DMA channel */
394 status = HAL_DMA_Abort(hdac->DMA_Handle2);
395
396 /* Disable the DAC DMA underrun interrupt */
397 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
398 }
399
400 /* Check if DMA Channel effectively disabled */
401 if (status != HAL_OK)
402 {
403 /* Update DAC state machine to error */
404 hdac->State = HAL_DAC_STATE_ERROR;
405 }
406 else
407 {
408 /* Change DAC state */
409 hdac->State = HAL_DAC_STATE_READY;
410 }
411
412 /* Return function status */
413 return status;
414 }
415
416
417 /**
418 * @brief Enable or disable the selected DAC channel wave generation.
419 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
420 * the configuration information for the specified DAC.
421 * @param Channel The selected DAC channel.
422 * This parameter can be one of the following values:
423 * @arg DAC_CHANNEL_1: DAC Channel1 selected
424 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
425 *
426 * (1) On this STM32 series, parameter not available on all instances.
427 * Refer to device datasheet for channels availability.
428 * @param Amplitude Select max triangle amplitude.
429 * This parameter can be one of the following values:
430 * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
431 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
432 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
433 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
434 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
435 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
436 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
437 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
438 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
439 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
440 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
441 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
442 * @retval HAL status
443 */
HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Amplitude)444 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
445 {
446 /* Check the DAC peripheral handle */
447 if (hdac == NULL)
448 {
449 return HAL_ERROR;
450 }
451
452 /* Check the parameters */
453 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
454 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
455
456 /* Process locked */
457 __HAL_LOCK(hdac);
458
459 /* Change DAC state */
460 hdac->State = HAL_DAC_STATE_BUSY;
461
462 /* Enable the triangle wave generation for the selected DAC channel */
463 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
464 (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
465
466 /* Change DAC state */
467 hdac->State = HAL_DAC_STATE_READY;
468
469 /* Process unlocked */
470 __HAL_UNLOCK(hdac);
471
472 /* Return function status */
473 return HAL_OK;
474 }
475
476 /**
477 * @brief Enable or disable the selected DAC channel wave generation.
478 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
479 * the configuration information for the specified DAC.
480 * @param Channel The selected DAC channel.
481 * This parameter can be one of the following values:
482 * @arg DAC_CHANNEL_1: DAC Channel1 selected
483 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
484 *
485 * (1) On this STM32 series, parameter not available on all instances.
486 * Refer to device datasheet for channels availability.
487 * @param Amplitude Unmask DAC channel LFSR for noise wave generation.
488 * This parameter can be one of the following values:
489 * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
490 * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
491 * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
492 * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
493 * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
494 * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
495 * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
496 * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
497 * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
498 * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
499 * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
500 * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
501 * @retval HAL status
502 */
HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Amplitude)503 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
504 {
505 /* Check the DAC peripheral handle */
506 if (hdac == NULL)
507 {
508 return HAL_ERROR;
509 }
510
511 /* Check the parameters */
512 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
513 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
514
515 /* Process locked */
516 __HAL_LOCK(hdac);
517
518 /* Change DAC state */
519 hdac->State = HAL_DAC_STATE_BUSY;
520
521 /* Enable the noise wave generation for the selected DAC channel */
522 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
523 (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
524
525 /* Change DAC state */
526 hdac->State = HAL_DAC_STATE_READY;
527
528 /* Process unlocked */
529 __HAL_UNLOCK(hdac);
530
531 /* Return function status */
532 return HAL_OK;
533 }
534
535 /**
536 * @brief Enable or disable the selected DAC channel sawtooth wave generation.
537 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
538 * the configuration information for the specified DAC.
539 * @param Channel The selected DAC channel.
540 * This parameter can be one of the following values:
541 * @arg DAC_CHANNEL_1: DAC Channel1 selected
542 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
543 *
544 * (1) On this STM32 series, parameter not available on all instances.
545 * Refer to device datasheet for channels availability.
546 * @param Polarity polarity to be used for wave generation.
547 * This parameter can be one of the following values:
548 * @arg DAC_SAWTOOTH_POLARITY_DECREMENT
549 * @arg DAC_SAWTOOTH_POLARITY_INCREMENT
550 * @param ResetData Sawtooth wave reset value.
551 * Range is from 0 to DAC full range 4095 (0xFFF)
552 * @param StepData Sawtooth wave step value.
553 * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
554 * Step value step is 1/16 = 0.0625
555 * Step value range is 0.0000 to 4095.9375 (0xFFF.F)
556 * @note Sawtooth reset and step triggers are configured by calling @ref HAL_DAC_ConfigChannel
557 * @retval HAL status
558 */
HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef * hdac,uint32_t Channel,uint32_t Polarity,uint32_t ResetData,uint32_t StepData)559 HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity,
560 uint32_t ResetData, uint32_t StepData)
561 {
562 /* Check the DAC peripheral handle */
563 if (hdac == NULL)
564 {
565 return HAL_ERROR;
566 }
567
568 /* Check the parameters */
569 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
570 assert_param(IS_DAC_SAWTOOTH_POLARITY(Polarity));
571 assert_param(IS_DAC_RESET_DATA(ResetData));
572 assert_param(IS_DAC_STEP_DATA(StepData));
573
574 /* Process locked */
575 __HAL_LOCK(hdac);
576
577 /* Change DAC state */
578 hdac->State = HAL_DAC_STATE_BUSY;
579
580 if (Channel == DAC_CHANNEL_1)
581 {
582 /* Configure the sawtooth wave generation data parameters */
583 MODIFY_REG(hdac->Instance->STR1,
584 DAC_STR1_STINCDATA1 | DAC_STR1_STDIR1 | DAC_STR1_STRSTDATA1,
585 (StepData << DAC_STR1_STINCDATA1_Pos)
586 | Polarity
587 | (ResetData << DAC_STR1_STRSTDATA1_Pos));
588 }
589 else
590 {
591 /* Configure the sawtooth wave generation data parameters */
592 MODIFY_REG(hdac->Instance->STR2,
593 DAC_STR2_STINCDATA2 | DAC_STR2_STDIR2 | DAC_STR2_STRSTDATA2,
594 (StepData << DAC_STR2_STINCDATA2_Pos)
595 | Polarity
596 | (ResetData << DAC_STR2_STRSTDATA2_Pos));
597 }
598
599 /* Enable the sawtooth wave generation for the selected DAC channel */
600 MODIFY_REG(hdac->Instance->CR,
601 (DAC_CR_WAVE1) << (Channel & 0x10UL),
602 (uint32_t)(DAC_CR_WAVE1_1 | DAC_CR_WAVE1_0) << (Channel & 0x10UL));
603
604 /* Change DAC state */
605 hdac->State = HAL_DAC_STATE_READY;
606
607 /* Process unlocked */
608 __HAL_UNLOCK(hdac);
609
610 /* Return function status */
611 return HAL_OK;
612 }
613
614 /**
615 * @brief Trig sawtooth wave reset
616 * @note This function allows to reset sawtooth wave in case of SW trigger
617 * has been configured for this usage.
618 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
619 * the configuration information for the specified DAC.
620 * @param Channel The selected DAC channel.
621 * This parameter can be one of the following values:
622 * @arg DAC_CHANNEL_1: DAC Channel1 selected
623 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
624 *
625 * (1) On this STM32 series, parameter not available on all instances.
626 * Refer to device datasheet for channels availability.
627 * @retval HAL status
628 */
HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef * hdac,uint32_t Channel)629 HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel)
630 {
631 HAL_StatusTypeDef status = HAL_OK;
632
633 /* Check the DAC peripheral handle */
634 if (hdac == NULL)
635 {
636 return HAL_ERROR;
637 }
638
639 /* Check the parameters */
640 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
641
642 /* Process locked */
643 __HAL_LOCK(hdac);
644
645 if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STRSTTRIGSEL1) == 0UL /* SW TRIGGER */)
646 {
647 /* Change DAC state */
648 hdac->State = HAL_DAC_STATE_BUSY;
649
650 if (Channel == DAC_CHANNEL_1)
651 {
652 /* Enable the selected DAC software conversion */
653 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
654 }
655 else
656 {
657 /* Enable the selected DAC software conversion */
658 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
659 }
660
661 /* Change DAC state */
662 hdac->State = HAL_DAC_STATE_READY;
663 }
664 else
665 {
666 status = HAL_ERROR;
667 }
668
669 /* Process unlocked */
670 __HAL_UNLOCK(hdac);
671
672 /* Return function status */
673 return status;
674 }
675
676 /**
677 * @brief Trig sawtooth wave step
678 * @note This function allows to generate step in sawtooth wave in case of
679 * SW trigger has been configured for this usage.
680 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
681 * the configuration information for the specified DAC.
682 * @param Channel The selected DAC channel.
683 * This parameter can be one of the following values:
684 * @arg DAC_CHANNEL_1: DAC Channel1 selected
685 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
686 *
687 * (1) On this STM32 series, parameter not available on all instances.
688 * Refer to device datasheet for channels availability.
689 * @retval HAL status
690 */
HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef * hdac,uint32_t Channel)691 HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel)
692 {
693 HAL_StatusTypeDef status = HAL_OK;
694
695 /* Check the DAC peripheral handle */
696 if (hdac == NULL)
697 {
698 return HAL_ERROR;
699 }
700
701 /* Check the parameters */
702 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
703
704 /* Process locked */
705 __HAL_LOCK(hdac);
706
707 if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STINCTRIGSEL1) == 0UL /* SW TRIGGER */)
708 {
709 /* Change DAC state */
710 hdac->State = HAL_DAC_STATE_BUSY;
711
712 if (Channel == DAC_CHANNEL_1)
713 {
714 /* Enable the selected DAC software conversion */
715 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB1);
716 }
717 else
718 {
719 /* Enable the selected DAC software conversion */
720 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB2);
721 }
722
723 /* Change DAC state */
724 hdac->State = HAL_DAC_STATE_READY;
725 }
726 else
727 {
728 status = HAL_ERROR;
729 }
730
731 /* Process unlocked */
732 __HAL_UNLOCK(hdac);
733
734 /* Return function status */
735 return status;
736 }
737
738
739 /**
740 * @brief Set the specified data holding register value for dual DAC channel.
741 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
742 * the configuration information for the specified DAC.
743 * @param Alignment Specifies the data alignment for dual channel DAC.
744 * This parameter can be one of the following values:
745 * DAC_ALIGN_8B_R: 8bit right data alignment selected
746 * DAC_ALIGN_12B_L: 12bit left data alignment selected
747 * DAC_ALIGN_12B_R: 12bit right data alignment selected
748 * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
749 * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register.
750 * @note In dual mode, a unique register access is required to write in both
751 * DAC channels at the same time.
752 * @retval HAL status
753 */
HAL_DACEx_DualSetValue(DAC_HandleTypeDef * hdac,uint32_t Alignment,uint32_t Data1,uint32_t Data2)754 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
755 {
756 uint32_t data;
757 uint32_t tmp;
758
759 /* Check the DAC peripheral handle */
760 if (hdac == NULL)
761 {
762 return HAL_ERROR;
763 }
764
765 /* Check the parameters */
766 assert_param(IS_DAC_ALIGN(Alignment));
767 assert_param(IS_DAC_DATA(Data1));
768 assert_param(IS_DAC_DATA(Data2));
769
770 /* Calculate and set dual DAC data holding register value */
771 if (Alignment == DAC_ALIGN_8B_R)
772 {
773 data = ((uint32_t)Data2 << 8U) | Data1;
774 }
775 else
776 {
777 data = ((uint32_t)Data2 << 16U) | Data1;
778 }
779
780 tmp = (uint32_t)hdac->Instance;
781 tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
782
783 /* Set the dual DAC selected data holding register */
784 *(__IO uint32_t *)tmp = data;
785
786 /* Return function status */
787 return HAL_OK;
788 }
789
790 /**
791 * @brief Conversion complete callback in non-blocking mode for Channel2.
792 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
793 * the configuration information for the specified DAC.
794 * @retval None
795 */
HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef * hdac)796 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
797 {
798 /* Prevent unused argument(s) compilation warning */
799 UNUSED(hdac);
800
801 /* NOTE : This function should not be modified, when the callback is needed,
802 the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
803 */
804 }
805
806 /**
807 * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2.
808 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
809 * the configuration information for the specified DAC.
810 * @retval None
811 */
HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef * hdac)812 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
813 {
814 /* Prevent unused argument(s) compilation warning */
815 UNUSED(hdac);
816
817 /* NOTE : This function should not be modified, when the callback is needed,
818 the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
819 */
820 }
821
822 /**
823 * @brief Error DAC callback for Channel2.
824 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
825 * the configuration information for the specified DAC.
826 * @retval None
827 */
HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef * hdac)828 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
829 {
830 /* Prevent unused argument(s) compilation warning */
831 UNUSED(hdac);
832
833 /* NOTE : This function should not be modified, when the callback is needed,
834 the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
835 */
836 }
837
838 /**
839 * @brief DMA underrun DAC callback for Channel2.
840 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
841 * the configuration information for the specified DAC.
842 * @retval None
843 */
HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef * hdac)844 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
845 {
846 /* Prevent unused argument(s) compilation warning */
847 UNUSED(hdac);
848
849 /* NOTE : This function should not be modified, when the callback is needed,
850 the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
851 */
852 }
853
854
855 /**
856 * @brief Run the self calibration of one DAC channel.
857 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
858 * the configuration information for the specified DAC.
859 * @param sConfig DAC channel configuration structure.
860 * @param Channel The selected DAC channel.
861 * This parameter can be one of the following values:
862 * @arg DAC_CHANNEL_1: DAC Channel1 selected
863 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
864 *
865 * (1) On this STM32 series, parameter not available on all instances.
866 * Refer to device datasheet for channels availability.
867 * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
868 * @retval HAL status
869 * @note Calibration runs about 7 ms.
870 */
HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef * hdac,DAC_ChannelConfTypeDef * sConfig,uint32_t Channel)871 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
872 {
873 HAL_StatusTypeDef status = HAL_OK;
874
875 uint32_t trimmingvalue;
876 uint32_t delta;
877 __IO uint32_t wait_loop_index;
878
879 /* store/restore channel configuration structure purpose */
880 uint32_t oldmodeconfiguration;
881
882 /* Check the parameters */
883 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
884
885 /* Check the DAC handle allocation */
886 /* Check if DAC running */
887 if ((hdac == NULL) || (sConfig == NULL))
888 {
889 status = HAL_ERROR;
890 }
891 else if (hdac->State == HAL_DAC_STATE_BUSY)
892 {
893 status = HAL_ERROR;
894 }
895 else
896 {
897 /* Process locked */
898 __HAL_LOCK(hdac);
899
900 /* Store configuration */
901 oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
902
903 /* Disable the selected DAC channel */
904 CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
905 /* Wait for ready bit to be de-asserted */
906 HAL_Delay(1);
907
908 /* Set mode in MCR for calibration */
909 MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
910
911 /* Enable the selected DAC channel calibration */
912 /* i.e. set DAC_CR_CENx bit */
913 SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
914
915 /* Init trimming counter */
916 /* Medium value */
917 trimmingvalue = 0x10UL;
918 delta = 0x08UL;
919 while (delta != 0UL)
920 {
921 /* Set candidate trimming */
922 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
923
924 /* Wait minimum time needed between two calibration steps (OTRIM) */
925 /* Wait loop initialization and execution */
926 /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
927 /* 32 bits register capacity and handle low frequency. */
928 wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
929 while (wait_loop_index != 0UL)
930 {
931 wait_loop_index--;
932 }
933
934 if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
935 {
936 /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
937 trimmingvalue -= delta;
938 }
939 else
940 {
941 /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
942 trimmingvalue += delta;
943 }
944 delta >>= 1UL;
945 }
946
947 /* Still need to check if right calibration is current value or one step below */
948 /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1 */
949 /* Set candidate trimming */
950 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
951
952 /* Wait minimum time needed between two calibration steps (OTRIM) */
953 /* Wait loop initialization and execution */
954 /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
955 /* 32 bits register capacity and handle low frequency. */
956 wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
957 while (wait_loop_index != 0UL)
958 {
959 wait_loop_index--;
960 }
961
962 if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
963 {
964 /* Check trimming value below maximum */
965 if (trimmingvalue < 0x1FU)
966 {
967 /* Trimming is actually one value more */
968 trimmingvalue++;
969 }
970 /* Set right trimming */
971 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
972 }
973
974 /* Disable the selected DAC channel calibration */
975 /* i.e. clear DAC_CR_CENx bit */
976 CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
977
978 sConfig->DAC_TrimmingValue = trimmingvalue;
979 sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
980
981 /* Restore configuration */
982 MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
983
984 /* Process unlocked */
985 __HAL_UNLOCK(hdac);
986 }
987
988 return status;
989 }
990
991 /**
992 * @brief Set the trimming mode and trimming value (user trimming mode applied).
993 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
994 * the configuration information for the specified DAC.
995 * @param sConfig DAC configuration structure updated with new DAC trimming value.
996 * @param Channel The selected DAC channel.
997 * This parameter can be one of the following values:
998 * @arg DAC_CHANNEL_1: DAC Channel1 selected
999 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
1000 *
1001 * (1) On this STM32 series, parameter not available on all instances.
1002 * Refer to device datasheet for channels availability.
1003 * @param NewTrimmingValue DAC new trimming value
1004 * @retval HAL status
1005 */
HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef * hdac,DAC_ChannelConfTypeDef * sConfig,uint32_t Channel,uint32_t NewTrimmingValue)1006 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
1007 uint32_t NewTrimmingValue)
1008 {
1009 HAL_StatusTypeDef status = HAL_OK;
1010
1011 /* Check the parameters */
1012 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
1013 assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
1014
1015 /* Check the DAC handle and channel configuration struct allocation */
1016 if ((hdac == NULL) || (sConfig == NULL))
1017 {
1018 status = HAL_ERROR;
1019 }
1020 else
1021 {
1022 /* Process locked */
1023 __HAL_LOCK(hdac);
1024
1025 /* Set new trimming */
1026 MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
1027
1028 /* Update trimming mode */
1029 sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
1030 sConfig->DAC_TrimmingValue = NewTrimmingValue;
1031
1032 /* Process unlocked */
1033 __HAL_UNLOCK(hdac);
1034 }
1035 return status;
1036 }
1037
1038 /**
1039 * @brief Return the DAC trimming value.
1040 * @param hdac DAC handle
1041 * @param Channel The selected DAC channel.
1042 * This parameter can be one of the following values:
1043 * @arg DAC_CHANNEL_1: DAC Channel1 selected
1044 * @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
1045 *
1046 * (1) On this STM32 series, parameter not available on all instances.
1047 * Refer to device datasheet for channels availability.
1048 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
1049 */
HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef * hdac,uint32_t Channel)1050 uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
1051 {
1052 /* Check the parameter */
1053 assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
1054
1055 /* Retrieve trimming */
1056 return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
1057 }
1058
1059 /**
1060 * @}
1061 */
1062
1063 /** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
1064 * @brief Extended Peripheral Control functions
1065 *
1066 @verbatim
1067 ==============================================================================
1068 ##### Peripheral Control functions #####
1069 ==============================================================================
1070 [..] This section provides functions allowing to:
1071 (+) Set the specified data holding register value for DAC channel.
1072
1073 @endverbatim
1074 * @{
1075 */
1076
1077
1078 /**
1079 * @brief Return the last data output value of the selected DAC channel.
1080 * @param hdac pointer to a DAC_HandleTypeDef structure that contains
1081 * the configuration information for the specified DAC.
1082 * @retval The selected DAC channel data output value.
1083 */
HAL_DACEx_DualGetValue(const DAC_HandleTypeDef * hdac)1084 uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
1085 {
1086 uint32_t tmp = 0UL;
1087
1088 tmp |= hdac->Instance->DOR1;
1089
1090 tmp |= hdac->Instance->DOR2 << 16UL;
1091
1092 /* Returns the DAC channel data output register value */
1093 return tmp;
1094 }
1095
1096
1097 /**
1098 * @}
1099 */
1100 /**
1101 * @}
1102 */
1103
1104 /* Private functions ---------------------------------------------------------*/
1105 /** @defgroup DACEx_Private_Functions DACEx private functions
1106 * @brief Extended private functions
1107 * @{
1108 */
1109
1110
1111 /**
1112 * @brief DMA conversion complete callback.
1113 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1114 * the configuration information for the specified DMA module.
1115 * @retval None
1116 */
DAC_DMAConvCpltCh2(DMA_HandleTypeDef * hdma)1117 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
1118 {
1119 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1120
1121 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1122 hdac->ConvCpltCallbackCh2(hdac);
1123 #else
1124 HAL_DACEx_ConvCpltCallbackCh2(hdac);
1125 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1126
1127 hdac->State = HAL_DAC_STATE_READY;
1128 }
1129
1130 /**
1131 * @brief DMA half transfer complete callback.
1132 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1133 * the configuration information for the specified DMA module.
1134 * @retval None
1135 */
DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef * hdma)1136 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
1137 {
1138 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1139 /* Conversion complete callback */
1140 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1141 hdac->ConvHalfCpltCallbackCh2(hdac);
1142 #else
1143 HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
1144 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1145 }
1146
1147 /**
1148 * @brief DMA error callback.
1149 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
1150 * the configuration information for the specified DMA module.
1151 * @retval None
1152 */
DAC_DMAErrorCh2(DMA_HandleTypeDef * hdma)1153 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
1154 {
1155 DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
1156
1157 /* Set DAC error code to DMA error */
1158 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
1159
1160 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
1161 hdac->ErrorCallbackCh2(hdac);
1162 #else
1163 HAL_DACEx_ErrorCallbackCh2(hdac);
1164 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
1165
1166 hdac->State = HAL_DAC_STATE_READY;
1167 }
1168
1169
1170 /**
1171 * @}
1172 */
1173
1174 /**
1175 * @}
1176 */
1177
1178 #endif /* DAC1 || DAC2 || DAC3 || DAC4 */
1179
1180 #endif /* HAL_DAC_MODULE_ENABLED */
1181
1182 /**
1183 * @}
1184 */
1185
