1 /** 2 ****************************************************************************** 3 * @file h3lis331dl_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * h3lis331dl_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef H3LIS331DL_REGS_H 23 #define H3LIS331DL_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup H3LIS331DL 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup H3LIS331DL_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> 0x31 if SA0=1 -> 0x33 **/ 172 #define H3LIS331DL_I2C_ADD_L 0x31 173 #define H3LIS331DL_I2C_ADD_H 0x33 174 175 /** Device Identification (Who am I) **/ 176 #define H3LIS331DL_ID 0x32 177 178 /** 179 * @} 180 * 181 */ 182 183 #define H3LIS331DL_WHO_AM_I 0x0FU 184 #define H3LIS331DL_CTRL_REG1 0x20U 185 typedef struct 186 { 187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 188 uint8_t xen : 1; 189 uint8_t yen : 1; 190 uint8_t zen : 1; 191 uint8_t dr : 2; 192 uint8_t pm : 3; 193 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 194 uint8_t pm : 3; 195 uint8_t dr : 2; 196 uint8_t zen : 1; 197 uint8_t yen : 1; 198 uint8_t xen : 1; 199 #endif /* DRV_BYTE_ORDER */ 200 } h3lis331dl_ctrl_reg1_t; 201 202 #define H3LIS331DL_CTRL_REG2 0x21U 203 typedef struct 204 { 205 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 206 uint8_t hpcf : 2; 207 uint8_t hpen : 2; 208 uint8_t fds : 1; 209 uint8_t hpm : 2; 210 uint8_t boot : 1; 211 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 212 uint8_t boot : 1; 213 uint8_t hpm : 2; 214 uint8_t fds : 1; 215 uint8_t hpen : 2; 216 uint8_t hpcf : 2; 217 #endif /* DRV_BYTE_ORDER */ 218 } h3lis331dl_ctrl_reg2_t; 219 220 #define H3LIS331DL_CTRL_REG3 0x22U 221 typedef struct 222 { 223 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 224 uint8_t i1_cfg : 2; 225 uint8_t lir1 : 1; 226 uint8_t i2_cfg : 2; 227 uint8_t lir2 : 1; 228 uint8_t pp_od : 1; 229 uint8_t ihl : 1; 230 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 231 uint8_t ihl : 1; 232 uint8_t pp_od : 1; 233 uint8_t lir2 : 1; 234 uint8_t i2_cfg : 2; 235 uint8_t lir1 : 1; 236 uint8_t i1_cfg : 2; 237 #endif /* DRV_BYTE_ORDER */ 238 } h3lis331dl_ctrl_reg3_t; 239 240 #define H3LIS331DL_CTRL_REG4 0x23U 241 typedef struct 242 { 243 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 244 uint8_t sim : 1; 245 uint8_t not_used_01 : 3; 246 uint8_t fs : 2; 247 uint8_t ble : 1; 248 uint8_t bdu : 1; 249 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 250 uint8_t bdu : 1; 251 uint8_t ble : 1; 252 uint8_t fs : 2; 253 uint8_t not_used_01 : 3; 254 uint8_t sim : 1; 255 #endif /* DRV_BYTE_ORDER */ 256 } h3lis331dl_ctrl_reg4_t; 257 258 #define H3LIS331DL_CTRL_REG5 0x24U 259 typedef struct 260 { 261 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 262 uint8_t turnon : 2; 263 uint8_t not_used_01 : 6; 264 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 265 uint8_t not_used_01 : 6; 266 uint8_t turnon : 2; 267 #endif /* DRV_BYTE_ORDER */ 268 } h3lis331dl_ctrl_reg5_t; 269 270 #define H3LIS331DL_HP_FILTER_RESET 0x25U 271 #define H3LIS331DL_REFERENCE 0x26U 272 #define H3LIS331DL_STATUS_REG 0x27U 273 typedef struct 274 { 275 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 276 uint8_t xda : 1; 277 uint8_t yda : 1; 278 uint8_t zda : 1; 279 uint8_t zyxda : 1; 280 uint8_t _xor : 1; 281 uint8_t yor : 1; 282 uint8_t zor : 1; 283 uint8_t zyxor : 1; 284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 285 uint8_t zyxor : 1; 286 uint8_t zor : 1; 287 uint8_t yor : 1; 288 uint8_t _xor : 1; 289 uint8_t zyxda : 1; 290 uint8_t zda : 1; 291 uint8_t yda : 1; 292 uint8_t xda : 1; 293 #endif /* DRV_BYTE_ORDER */ 294 } h3lis331dl_status_reg_t; 295 296 #define H3LIS331DL_OUT_X_L 0x28U 297 #define H3LIS331DL_OUT_X_H 0x29U 298 #define H3LIS331DL_OUT_Y_L 0x2AU 299 #define H3LIS331DL_OUT_Y_H 0x2BU 300 #define H3LIS331DL_OUT_Z_L 0x2CU 301 #define H3LIS331DL_OUT_Z_H 0x2DU 302 #define H3LIS331DL_INT1_CFG 0x30U 303 typedef struct 304 { 305 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 306 uint8_t xlie : 1; 307 uint8_t xhie : 1; 308 uint8_t ylie : 1; 309 uint8_t yhie : 1; 310 uint8_t zlie : 1; 311 uint8_t zhie : 1; 312 uint8_t not_used_01 : 1; 313 uint8_t aoi : 1; 314 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 315 uint8_t aoi : 1; 316 uint8_t not_used_01 : 1; 317 uint8_t zhie : 1; 318 uint8_t zlie : 1; 319 uint8_t yhie : 1; 320 uint8_t ylie : 1; 321 uint8_t xhie : 1; 322 uint8_t xlie : 1; 323 #endif /* DRV_BYTE_ORDER */ 324 } h3lis331dl_int1_cfg_t; 325 326 #define H3LIS331DL_INT1_SRC 0x31U 327 typedef struct 328 { 329 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 330 uint8_t xl : 1; 331 uint8_t xh : 1; 332 uint8_t yl : 1; 333 uint8_t yh : 1; 334 uint8_t zl : 1; 335 uint8_t zh : 1; 336 uint8_t ia : 1; 337 uint8_t not_used_01 : 1; 338 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 339 uint8_t not_used_01 : 1; 340 uint8_t ia : 1; 341 uint8_t zh : 1; 342 uint8_t zl : 1; 343 uint8_t yh : 1; 344 uint8_t yl : 1; 345 uint8_t xh : 1; 346 uint8_t xl : 1; 347 #endif /* DRV_BYTE_ORDER */ 348 } h3lis331dl_int1_src_t; 349 350 #define H3LIS331DL_INT1_THS 0x32U 351 typedef struct 352 { 353 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 354 uint8_t ths : 7; 355 uint8_t not_used_01 : 1; 356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 357 uint8_t not_used_01 : 1; 358 uint8_t ths : 7; 359 #endif /* DRV_BYTE_ORDER */ 360 } h3lis331dl_int1_ths_t; 361 362 #define H3LIS331DL_INT1_DURATION 0x33U 363 typedef struct 364 { 365 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 366 uint8_t d : 7; 367 uint8_t not_used_01 : 1; 368 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 369 uint8_t not_used_01 : 1; 370 uint8_t d : 7; 371 #endif /* DRV_BYTE_ORDER */ 372 } h3lis331dl_int1_duration_t; 373 374 #define H3LIS331DL_INT2_CFG 0x34U 375 typedef struct 376 { 377 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 378 uint8_t xlie : 1; 379 uint8_t xhie : 1; 380 uint8_t ylie : 1; 381 uint8_t yhie : 1; 382 uint8_t zlie : 1; 383 uint8_t zhie : 1; 384 uint8_t not_used_01 : 1; 385 uint8_t aoi : 1; 386 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 387 uint8_t aoi : 1; 388 uint8_t not_used_01 : 1; 389 uint8_t zhie : 1; 390 uint8_t zlie : 1; 391 uint8_t yhie : 1; 392 uint8_t ylie : 1; 393 uint8_t xhie : 1; 394 uint8_t xlie : 1; 395 #endif /* DRV_BYTE_ORDER */ 396 } h3lis331dl_int2_cfg_t; 397 398 #define H3LIS331DL_INT2_SRC 0x35U 399 typedef struct 400 { 401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 402 uint8_t xl : 1; 403 uint8_t xh : 1; 404 uint8_t yl : 1; 405 uint8_t yh : 1; 406 uint8_t zl : 1; 407 uint8_t zh : 1; 408 uint8_t ia : 1; 409 uint8_t not_used_01 : 1; 410 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 411 uint8_t not_used_01 : 1; 412 uint8_t ia : 1; 413 uint8_t zh : 1; 414 uint8_t zl : 1; 415 uint8_t yh : 1; 416 uint8_t yl : 1; 417 uint8_t xh : 1; 418 uint8_t xl : 1; 419 #endif /* DRV_BYTE_ORDER */ 420 } h3lis331dl_int2_src_t; 421 422 #define H3LIS331DL_INT2_THS 0x36U 423 typedef struct 424 { 425 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 426 uint8_t ths : 7; 427 uint8_t not_used_01 : 1; 428 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 429 uint8_t not_used_01 : 1; 430 uint8_t ths : 7; 431 #endif /* DRV_BYTE_ORDER */ 432 } h3lis331dl_int2_ths_t; 433 434 #define H3LIS331DL_INT2_DURATION 0x37U 435 typedef struct 436 { 437 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 438 uint8_t d : 7; 439 uint8_t not_used_01 : 1; 440 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 441 uint8_t not_used_01 : 1; 442 uint8_t d : 7; 443 #endif /* DRV_BYTE_ORDER */ 444 } h3lis331dl_int2_duration_t; 445 446 /** 447 * @defgroup H3LIS331DL_Register_Union 448 * @brief This union group all the registers having a bit-field 449 * description. 450 * This union is useful but it's not needed by the driver. 451 * 452 * REMOVING this union you are compliant with: 453 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 454 * 455 * @{ 456 * 457 */ 458 typedef union 459 { 460 h3lis331dl_ctrl_reg1_t ctrl_reg1; 461 h3lis331dl_ctrl_reg2_t ctrl_reg2; 462 h3lis331dl_ctrl_reg3_t ctrl_reg3; 463 h3lis331dl_ctrl_reg4_t ctrl_reg4; 464 h3lis331dl_ctrl_reg5_t ctrl_reg5; 465 h3lis331dl_status_reg_t status_reg; 466 h3lis331dl_int1_cfg_t int1_cfg; 467 h3lis331dl_int1_src_t int1_src; 468 h3lis331dl_int1_ths_t int1_ths; 469 h3lis331dl_int1_duration_t int1_duration; 470 h3lis331dl_int2_cfg_t int2_cfg; 471 h3lis331dl_int2_src_t int2_src; 472 h3lis331dl_int2_ths_t int2_ths; 473 h3lis331dl_int2_duration_t int2_duration; 474 bitwise_t bitwise; 475 uint8_t byte; 476 } h3lis331dl_reg_t; 477 478 /** 479 * @} 480 * 481 */ 482 483 #ifndef __weak 484 #define __weak __attribute__((weak)) 485 #endif /* __weak */ 486 487 /* 488 * These are the basic platform dependent I/O routines to read 489 * and write device registers connected on a standard bus. 490 * The driver keeps offering a default implementation based on function 491 * pointers to read/write routines for backward compatibility. 492 * The __weak directive allows the final application to overwrite 493 * them with a custom implementation. 494 */ 495 496 int32_t h3lis331dl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 497 uint8_t *data, 498 uint16_t len); 499 int32_t h3lis331dl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 500 uint8_t *data, 501 uint16_t len); 502 503 float_t h3lis331dl_from_fs100_to_mg(int16_t lsb); 504 float_t h3lis331dl_from_fs200_to_mg(int16_t lsb); 505 float_t h3lis331dl_from_fs400_to_mg(int16_t lsb); 506 507 int32_t h3lis331dl_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); 508 int32_t h3lis331dl_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 509 510 int32_t h3lis331dl_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); 511 int32_t h3lis331dl_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 512 513 int32_t h3lis331dl_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); 514 int32_t h3lis331dl_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 515 516 typedef enum 517 { 518 H3LIS331DL_ODR_OFF = 0x00, 519 H3LIS331DL_ODR_Hz5 = 0x02, 520 H3LIS331DL_ODR_1Hz = 0x03, 521 H3LIS331DL_ODR_2Hz = 0x04, 522 H3LIS331DL_ODR_5Hz = 0x05, 523 H3LIS331DL_ODR_10Hz = 0x06, 524 H3LIS331DL_ODR_50Hz = 0x01, 525 H3LIS331DL_ODR_100Hz = 0x11, 526 H3LIS331DL_ODR_400Hz = 0x21, 527 H3LIS331DL_ODR_1kHz = 0x31, 528 } h3lis331dl_dr_t; 529 int32_t h3lis331dl_data_rate_set(const stmdev_ctx_t *ctx, 530 h3lis331dl_dr_t val); 531 int32_t h3lis331dl_data_rate_get(const stmdev_ctx_t *ctx, 532 h3lis331dl_dr_t *val); 533 534 typedef enum 535 { 536 H3LIS331DL_NORMAL_MODE = 0, 537 H3LIS331DL_REF_MODE_ENABLE = 1, 538 } h3lis331dl_hpm_t; 539 int32_t h3lis331dl_reference_mode_set(const stmdev_ctx_t *ctx, 540 h3lis331dl_hpm_t val); 541 int32_t h3lis331dl_reference_mode_get(const stmdev_ctx_t *ctx, 542 h3lis331dl_hpm_t *val); 543 544 typedef enum 545 { 546 H3LIS331DL_100g = 0, 547 H3LIS331DL_200g = 1, 548 H3LIS331DL_400g = 3, 549 } h3lis331dl_fs_t; 550 int32_t h3lis331dl_full_scale_set(const stmdev_ctx_t *ctx, 551 h3lis331dl_fs_t val); 552 int32_t h3lis331dl_full_scale_get(const stmdev_ctx_t *ctx, 553 h3lis331dl_fs_t *val); 554 555 int32_t h3lis331dl_block_data_update_set(const stmdev_ctx_t *ctx, 556 uint8_t val); 557 int32_t h3lis331dl_block_data_update_get(const stmdev_ctx_t *ctx, 558 uint8_t *val); 559 560 int32_t h3lis331dl_status_reg_get(const stmdev_ctx_t *ctx, 561 h3lis331dl_status_reg_t *val); 562 563 int32_t h3lis331dl_flag_data_ready_get(const stmdev_ctx_t *ctx, 564 uint8_t *val); 565 566 int32_t h3lis331dl_acceleration_raw_get(const stmdev_ctx_t *ctx, 567 int16_t *val); 568 569 int32_t h3lis331dl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 570 571 int32_t h3lis331dl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 572 int32_t h3lis331dl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 573 574 typedef enum 575 { 576 H3LIS331DL_LSB_AT_LOW_ADD = 0, 577 H3LIS331DL_MSB_AT_LOW_ADD = 1, 578 } h3lis331dl_ble_t; 579 int32_t h3lis331dl_data_format_set(const stmdev_ctx_t *ctx, 580 h3lis331dl_ble_t val); 581 int32_t h3lis331dl_data_format_get(const stmdev_ctx_t *ctx, 582 h3lis331dl_ble_t *val); 583 584 typedef enum 585 { 586 H3LIS331DL_CUT_OFF_8Hz = 0, 587 H3LIS331DL_CUT_OFF_16Hz = 1, 588 H3LIS331DL_CUT_OFF_32Hz = 2, 589 H3LIS331DL_CUT_OFF_64Hz = 3, 590 } h3lis331dl_hpcf_t; 591 int32_t h3lis331dl_hp_bandwidth_set(const stmdev_ctx_t *ctx, 592 h3lis331dl_hpcf_t val); 593 int32_t h3lis331dl_hp_bandwidth_get(const stmdev_ctx_t *ctx, 594 h3lis331dl_hpcf_t *val); 595 596 typedef enum 597 { 598 H3LIS331DL_HP_DISABLE = 0, 599 H3LIS331DL_HP_ON_OUT = 4, 600 H3LIS331DL_HP_ON_INT1 = 1, 601 H3LIS331DL_HP_ON_INT2 = 2, 602 H3LIS331DL_HP_ON_INT1_INT2 = 3, 603 H3LIS331DL_HP_ON_INT1_INT2_OUT = 7, 604 H3LIS331DL_HP_ON_INT2_OUT = 6, 605 H3LIS331DL_HP_ON_INT1_OUT = 5, 606 } h3lis331dl_hpen_t; 607 int32_t h3lis331dl_hp_path_set(const stmdev_ctx_t *ctx, 608 h3lis331dl_hpen_t val); 609 int32_t h3lis331dl_hp_path_get(const stmdev_ctx_t *ctx, 610 h3lis331dl_hpen_t *val); 611 612 int32_t h3lis331dl_hp_reset_get(const stmdev_ctx_t *ctx); 613 614 int32_t h3lis331dl_hp_reference_value_set(const stmdev_ctx_t *ctx, 615 uint8_t val); 616 int32_t h3lis331dl_hp_reference_value_get(const stmdev_ctx_t *ctx, 617 uint8_t *val); 618 619 typedef enum 620 { 621 H3LIS331DL_SPI_4_WIRE = 0, 622 H3LIS331DL_SPI_3_WIRE = 1, 623 } h3lis331dl_sim_t; 624 int32_t h3lis331dl_spi_mode_set(const stmdev_ctx_t *ctx, 625 h3lis331dl_sim_t val); 626 int32_t h3lis331dl_spi_mode_get(const stmdev_ctx_t *ctx, 627 h3lis331dl_sim_t *val); 628 629 typedef enum 630 { 631 H3LIS331DL_PAD1_INT1_SRC = 0, 632 H3LIS331DL_PAD1_INT1_OR_INT2_SRC = 1, 633 H3LIS331DL_PAD1_DRDY = 2, 634 H3LIS331DL_PAD1_BOOT = 3, 635 } h3lis331dl_i1_cfg_t; 636 int32_t h3lis331dl_pin_int1_route_set(const stmdev_ctx_t *ctx, 637 h3lis331dl_i1_cfg_t val); 638 int32_t h3lis331dl_pin_int1_route_get(const stmdev_ctx_t *ctx, 639 h3lis331dl_i1_cfg_t *val); 640 641 typedef enum 642 { 643 H3LIS331DL_INT1_PULSED = 0, 644 H3LIS331DL_INT1_LATCHED = 1, 645 } h3lis331dl_lir1_t; 646 int32_t h3lis331dl_int1_notification_set(const stmdev_ctx_t *ctx, 647 h3lis331dl_lir1_t val); 648 int32_t h3lis331dl_int1_notification_get(const stmdev_ctx_t *ctx, 649 h3lis331dl_lir1_t *val); 650 651 typedef enum 652 { 653 H3LIS331DL_PAD2_INT2_SRC = 0, 654 H3LIS331DL_PAD2_INT1_OR_INT2_SRC = 1, 655 H3LIS331DL_PAD2_DRDY = 2, 656 H3LIS331DL_PAD2_BOOT = 3, 657 } h3lis331dl_i2_cfg_t; 658 int32_t h3lis331dl_pin_int2_route_set(const stmdev_ctx_t *ctx, 659 h3lis331dl_i2_cfg_t val); 660 int32_t h3lis331dl_pin_int2_route_get(const stmdev_ctx_t *ctx, 661 h3lis331dl_i2_cfg_t *val); 662 663 typedef enum 664 { 665 H3LIS331DL_INT2_PULSED = 0, 666 H3LIS331DL_INT2_LATCHED = 1, 667 } h3lis331dl_lir2_t; 668 int32_t h3lis331dl_int2_notification_set(const stmdev_ctx_t *ctx, 669 h3lis331dl_lir2_t val); 670 int32_t h3lis331dl_int2_notification_get(const stmdev_ctx_t *ctx, 671 h3lis331dl_lir2_t *val); 672 673 typedef enum 674 { 675 H3LIS331DL_PUSH_PULL = 0, 676 H3LIS331DL_OPEN_DRAIN = 1, 677 } h3lis331dl_pp_od_t; 678 int32_t h3lis331dl_pin_mode_set(const stmdev_ctx_t *ctx, 679 h3lis331dl_pp_od_t val); 680 int32_t h3lis331dl_pin_mode_get(const stmdev_ctx_t *ctx, 681 h3lis331dl_pp_od_t *val); 682 683 typedef enum 684 { 685 H3LIS331DL_ACTIVE_HIGH = 0, 686 H3LIS331DL_ACTIVE_LOW = 1, 687 } h3lis331dl_ihl_t; 688 int32_t h3lis331dl_pin_polarity_set(const stmdev_ctx_t *ctx, 689 h3lis331dl_ihl_t val); 690 int32_t h3lis331dl_pin_polarity_get(const stmdev_ctx_t *ctx, 691 h3lis331dl_ihl_t *val); 692 693 typedef struct 694 { 695 uint8_t int1_xlie : 1; 696 uint8_t int1_xhie : 1; 697 uint8_t int1_ylie : 1; 698 uint8_t int1_yhie : 1; 699 uint8_t int1_zlie : 1; 700 uint8_t int1_zhie : 1; 701 } h3lis331dl_int1_on_th_conf_t; 702 int32_t h3lis331dl_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, 703 h3lis331dl_int1_on_th_conf_t val); 704 int32_t h3lis331dl_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, 705 h3lis331dl_int1_on_th_conf_t *val); 706 707 typedef enum 708 { 709 H3LIS331DL_INT1_ON_THRESHOLD_OR = 0, 710 H3LIS331DL_INT1_ON_THRESHOLD_AND = 1, 711 } h3lis331dl_int1_aoi_t; 712 int32_t h3lis331dl_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, 713 h3lis331dl_int1_aoi_t val); 714 int32_t h3lis331dl_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, 715 h3lis331dl_int1_aoi_t *val); 716 717 int32_t h3lis331dl_int1_src_get(const stmdev_ctx_t *ctx, 718 h3lis331dl_int1_src_t *val); 719 720 int32_t h3lis331dl_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 721 int32_t h3lis331dl_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 722 723 int32_t h3lis331dl_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 724 int32_t h3lis331dl_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 725 726 typedef struct 727 { 728 uint8_t int2_xlie : 1; 729 uint8_t int2_xhie : 1; 730 uint8_t int2_ylie : 1; 731 uint8_t int2_yhie : 1; 732 uint8_t int2_zlie : 1; 733 uint8_t int2_zhie : 1; 734 } h3lis331dl_int2_on_th_conf_t; 735 int32_t h3lis331dl_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, 736 h3lis331dl_int2_on_th_conf_t val); 737 int32_t h3lis331dl_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, 738 h3lis331dl_int2_on_th_conf_t *val); 739 740 typedef enum 741 { 742 H3LIS331DL_INT2_ON_THRESHOLD_OR = 0, 743 H3LIS331DL_INT2_ON_THRESHOLD_AND = 1, 744 } h3lis331dl_int2_aoi_t; 745 int32_t h3lis331dl_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, 746 h3lis331dl_int2_aoi_t val); 747 int32_t h3lis331dl_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, 748 h3lis331dl_int2_aoi_t *val); 749 750 int32_t h3lis331dl_int2_src_get(const stmdev_ctx_t *ctx, 751 h3lis331dl_int2_src_t *val); 752 753 int32_t h3lis331dl_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 754 int32_t h3lis331dl_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 755 756 int32_t h3lis331dl_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 757 int32_t h3lis331dl_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 758 759 int32_t h3lis331dl_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val); 760 int32_t h3lis331dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); 761 762 /** 763 *@} 764 * 765 */ 766 767 #ifdef __cplusplus 768 } 769 #endif 770 771 #endif /* H3LIS331DL_REGS_H */ 772 773 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 774
