1 /*
2  * Copyright (c) 2024 Microchip Technology Inc.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _MEC5_MBOX_V1_H
7 #define _MEC5_MBOX_V1_H
8 
9 /** @addtogroup Device_Peripheral_peripherals
10   * @{
11   */
12 
13 /**
14   * @brief Host/EC Mailbox communication (MEC_MBOX0)
15   */
16 
17 typedef struct mec_mbox_regs {                  /*!< (@ 0x400F0000) MEC_MBOX0 Structure                                        */
18   __IOM uint8_t   HINDEX;                       /*!< (@ 0x00000000) Mailbox Host Index                                         */
19   __IOM uint8_t   HDATA;                        /*!< (@ 0x00000001) Mailbox Host Data                                          */
20   __IM  uint16_t  RESERVED;
21   __IM  uint32_t  RESERVED1[63];
22   __IOM uint8_t   H2EC;                         /*!< (@ 0x00000100) Mailbox Host to EC                                         */
23   __IM  uint8_t   RESERVED2;
24   __IM  uint16_t  RESERVED3;
25   __IOM uint8_t   EC2H;                         /*!< (@ 0x00000104) Mailbox EC to Host                                         */
26   __IM  uint8_t   RESERVED4;
27   __IM  uint16_t  RESERVED5;
28   __IOM uint8_t   ECSMIT;                       /*!< (@ 0x00000108) Mailbox EC SMI trigger                                     */
29   __IM  uint8_t   RESERVED6;
30   __IM  uint16_t  RESERVED7;
31   __IOM uint8_t   ECSMIM;                       /*!< (@ 0x0000010C) Mailbox EC SMI mask                                        */
32   __IM  uint8_t   RESERVED8;
33   __IM  uint16_t  RESERVED9;
34   __IOM uint32_t  MBOXD[8];                     /*!< (@ 0x00000110) Mailbox data registers 32-bit access                       */
35 } MEC_MBOX_Type;                                /*!< Size = 304 (0x130)                                                        */
36 
37 /** @} */ /* End of group Device_Peripheral_peripherals */
38 
39 /** @addtogroup PosMask_peripherals
40   * @{
41   */
42 /* ========================================================  ECSMIT  ========================================================= */
43 #define MEC_MBOX_ECSMIT_EC_WR_Pos         (0UL)                     /*!< EC_WR (Bit 0)                                         */
44 #define MEC_MBOX_ECSMIT_EC_WR_Msk         (0x1UL)                   /*!< EC_WR (Bitfield-Mask: 0x01)                           */
45 #define MEC_MBOX_ECSMIT_EC_SWI_Pos        (1UL)                     /*!< EC_SWI (Bit 1)                                        */
46 #define MEC_MBOX_ECSMIT_EC_SWI_Msk        (0xfeUL)                  /*!< EC_SWI (Bitfield-Mask: 0x7f)                          */
47 /* ========================================================  ECSMIM  ========================================================= */
48 #define MEC_MBOX_ECSMIM_EC_WR_EN_Pos      (0UL)                     /*!< EC_WR_EN (Bit 0)                                      */
49 #define MEC_MBOX_ECSMIM_EC_WR_EN_Msk      (0x1UL)                   /*!< EC_WR_EN (Bitfield-Mask: 0x01)                        */
50 #define MEC_MBOX_ECSMIM_EC_SWI_EN_Pos     (1UL)                     /*!< EC_SWI_EN (Bit 1)                                     */
51 #define MEC_MBOX_ECSMIM_EC_SWI_EN_Msk     (0xfeUL)                  /*!< EC_SWI_EN (Bitfield-Mask: 0x7f)                       */
52 
53 /** @} */ /* End of group PosMask_peripherals */
54 
55 #endif /* _MEC5_MBOX_V1_H */
56