1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup GMAC_DRIVER GMAC Driver
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Gmac_Ip.h"
25 #include "Gmac_Ip_Hw_Access.h"
26 #include "Gmac_Ip_TrustedFunctions.h"
27
28 #if (STD_ON == GMAC_IP_DEV_ERROR_DETECT)
29 #include "Devassert.h"
30 #endif /* (STD_ON == GMAC_IP_DEV_ERROR_DETECT) */
31
32 #if (STD_ON == GMAC_SET_USER_ACCESS_ALLOWED_AVAILABLE)
33 #define USER_MODE_REG_PROT_ENABLED (STD_ON)
34 #include "RegLockMacros.h"
35 #endif /* (STD_ON == GMAC_SET_USER_ACCESS_ALLOWED_AVAILABLE) */
36
37 #if(GMAC_HAS_CACHE_MANAGEMENT == STD_ON)
38 #include "Cache_Ip.h"
39 #endif
40
41 /*==================================================================================================
42 * SOURCE FILE VERSION INFORMATION
43 ==================================================================================================*/
44 #define GMAC_IP_VENDOR_ID_C 43
45 #define GMAC_IP_AR_RELEASE_MAJOR_VERSION_C 4
46 #define GMAC_IP_AR_RELEASE_MINOR_VERSION_C 7
47 #define GMAC_IP_AR_RELEASE_REVISION_VERSION_C 0
48 #define GMAC_IP_SW_MAJOR_VERSION_C 3
49 #define GMAC_IP_SW_MINOR_VERSION_C 0
50 #define GMAC_IP_SW_PATCH_VERSION_C 0
51
52 /*==================================================================================================
53 * FILE VERSION CHECKS
54 ==================================================================================================*/
55 /* Checks against Gmac_Ip.h */
56 #if (GMAC_IP_VENDOR_ID_C != GMAC_IP_VENDOR_ID)
57 #error "Gmac_Ip.c and Gmac_Ip.h have different vendor ids"
58 #endif
59 #if (( GMAC_IP_AR_RELEASE_MAJOR_VERSION_C != GMAC_IP_AR_RELEASE_MAJOR_VERSION) || \
60 ( GMAC_IP_AR_RELEASE_MINOR_VERSION_C != GMAC_IP_AR_RELEASE_MINOR_VERSION) || \
61 ( GMAC_IP_AR_RELEASE_REVISION_VERSION_C != GMAC_IP_AR_RELEASE_REVISION_VERSION))
62 #error "AUTOSAR Version Numbers of Gmac_Ip.c and Gmac_Ip.h are different"
63 #endif
64 #if (( GMAC_IP_SW_MAJOR_VERSION_C != GMAC_IP_SW_MAJOR_VERSION) || \
65 ( GMAC_IP_SW_MINOR_VERSION_C != GMAC_IP_SW_MINOR_VERSION) || \
66 ( GMAC_IP_SW_PATCH_VERSION_C != GMAC_IP_SW_PATCH_VERSION))
67 #error "Software Version Numbers of Gmac_Ip.c and Gmac_Ip.h are different"
68 #endif
69
70 /* Checks against Gmac_Ip_Hw_Access.h */
71 #if (GMAC_IP_VENDOR_ID_C != GMAC_IP_HW_ACCESS_VENDOR_ID)
72 #error "Gmac_Ip.c and Gmac_Ip_Hw_Access.h have different vendor ids"
73 #endif
74 #if (( GMAC_IP_AR_RELEASE_MAJOR_VERSION_C != GMAC_IP_HW_ACCESS_AR_RELEASE_MAJOR_VERSION) || \
75 ( GMAC_IP_AR_RELEASE_MINOR_VERSION_C != GMAC_IP_HW_ACCESS_AR_RELEASE_MINOR_VERSION) || \
76 ( GMAC_IP_AR_RELEASE_REVISION_VERSION_C != GMAC_IP_HW_ACCESS_AR_RELEASE_REVISION_VERSION))
77 #error "AUTOSAR Version Numbers of Gmac_Ip.c and Gmac_Ip_Hw_Access.h are different"
78 #endif
79 #if (( GMAC_IP_SW_MAJOR_VERSION_C != GMAC_IP_HW_ACCESS_SW_MAJOR_VERSION) || \
80 ( GMAC_IP_SW_MINOR_VERSION_C != GMAC_IP_HW_ACCESS_SW_MINOR_VERSION) || \
81 ( GMAC_IP_SW_PATCH_VERSION_C != GMAC_IP_HW_ACCESS_SW_PATCH_VERSION))
82 #error "Software Version Numbers of Gmac_Ip.c and Gmac_Ip_Hw_Access.h are different"
83 #endif
84
85 /* Checks against Gmac_Ip_TrustedFunctions.h */
86 #if (GMAC_IP_VENDOR_ID_C != GMAC_IP_TRUSTEDFUNCTIONS_VENDOR_ID)
87 #error "Gmac_Ip.c and Gmac_Ip_TrustedFunctions.h have different vendor ids"
88 #endif
89 #if (( GMAC_IP_AR_RELEASE_MAJOR_VERSION_C != GMAC_IP_TRUSTEDFUNCTIONS_AR_RELEASE_MAJOR_VERSION) || \
90 ( GMAC_IP_AR_RELEASE_MINOR_VERSION_C != GMAC_IP_TRUSTEDFUNCTIONS_AR_RELEASE_MINOR_VERSION) || \
91 ( GMAC_IP_AR_RELEASE_REVISION_VERSION_C != GMAC_IP_TRUSTEDFUNCTIONS_AR_RELEASE_REVISION_VERSION))
92 #error "AUTOSAR Version Numbers of Gmac_Ip.c and Gmac_Ip_TrustedFunctions.h are different"
93 #endif
94 #if (( GMAC_IP_SW_MAJOR_VERSION_C != GMAC_IP_TRUSTEDFUNCTIONS_SW_MAJOR_VERSION) || \
95 ( GMAC_IP_SW_MINOR_VERSION_C != GMAC_IP_TRUSTEDFUNCTIONS_SW_MINOR_VERSION) || \
96 ( GMAC_IP_SW_PATCH_VERSION_C != GMAC_IP_TRUSTEDFUNCTIONS_SW_PATCH_VERSION))
97 #error "Software Version Numbers of Gmac_Ip.c and Gmac_Ip_TrustedFunctions.h are different"
98 #endif
99
100 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
101 #if (STD_ON == GMAC_SET_USER_ACCESS_ALLOWED_AVAILABLE)
102 /* Checks against RegLockMacros.h */
103 #if ((GMAC_IP_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
104 (GMAC_IP_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
105 #error "AUTOSAR Version Numbers of Gmac_Ip.h and RegLockMacros.h are different"
106 #endif
107 #endif /* (STD_ON == GMAC_SET_USER_ACCESS_ALLOWED_AVAILABLE) */
108
109 /* Checks against Devassert.h*/
110 #if (STD_ON == GMAC_IP_DEV_ERROR_DETECT)
111 #if (( GMAC_IP_AR_RELEASE_MAJOR_VERSION_C != DEVASSERT_AR_RELEASE_MAJOR_VERSION) || \
112 ( GMAC_IP_AR_RELEASE_MINOR_VERSION_C != DEVASSERT_AR_RELEASE_MINOR_VERSION))
113 #error "AUTOSAR Version Numbers of Gmac_Ip.c and Devassert.h are different"
114 #endif
115 #endif
116 #endif
117
118 /*******************************************************************************
119 * Definitions
120 ******************************************************************************/
121
122 #define GMAC_TX_STAT_ERR_MASK (0x00007F0DU)
123 #define GMAC_TX_STAT_TTSS_MASK (0x00020000U)
124 #define GMAC_RX_STAT_ERR_MASK (0x01F80000U)
125
126 #define GMAC_TDES3_CPC(x) (((uint32)(((uint32)(x)) << 26U)) & 0x0C000000U)
127 #define GMAC_TDES3_CIC(x) (((uint32)(((uint32)(x)) << 16U)) & 0x00030000U)
128 #define GMAC_TDES3_OWN_MASK (0x80000000U)
129 #define GMAC_TDES3_FD_MASK (0x20000000U)
130 #define GMAC_TDES3_LD_MASK (0x10000000U)
131
132 #define GMAC_TDES2_IOC_MASK (0x80000000U)
133 #define GMAC_TDES2_TTSE_MASK (0x40000000U)
134
135 #define GMAC_RDES0_IVT_MASK (0xFFFF0000U)
136 #define GMAC_RDES0_IVT_SHIFT (16U)
137 #define GMAC_RDES0_OVT_MASK (0x0000FFFFU)
138
139 #define GMAC_RDES1_TSA_MASK (0x00004000U)
140 #define GMAC_RDES1_IPCE_MASK (0x00000080U)
141 #define GMAC_RDES1_IPV6_MASK (0x00000020U)
142 #define GMAC_RDES1_IPV4_MASK (0x00000010U)
143 #define GMAC_RDES1_IPHE_MASK (0x00000008U)
144 #define GMAC_RDES1_PT_MASK (0x00000007U)
145
146 #define GMAC_RDES3_PL_MASK (0x00007FFFU)
147 #define GMAC_RDES3_OWN_MASK (0x80000000U)
148 #define GMAC_RDES3_INTE_MASK (0x40000000U)
149 #define GMAC_RDES3_BUF1V_MASK (0x01000000U)
150 #define GMAC_RDES3_RS1V_MASK (0x04000000U)
151 #define GMAC_RDES3_RS0V_MASK (0x02000000U)
152
153 #define GMAC_RDES3_CTXT_MASK (0x40000000U)
154
155 #define GMAC_INFO1_CONSUMED_MASK (0x01000000U)
156 #define GMAC_INFO1_LOCKED_MASK (0x10000000U)
157 #define GMAC_INFO1_LENGTH_MASK (0x00003FFFU)
158
159 #define GMAC_BYTE_5_IN_ADDR_SHIFT (8U)
160 #define GMAC_BYTE_4_IN_ADDR_SHIFT (0U)
161 #define GMAC_BYTE_3_IN_ADDR_SHIFT (24U)
162 #define GMAC_BYTE_2_IN_ADDR_SHIFT (16U)
163 #define GMAC_BYTE_1_IN_ADDR_SHIFT (8U)
164 #define GMAC_BYTE_0_IN_ADDR_SHIFT (0U)
165
166 #define GMAC_GCRA_LOWER_BTR ((uint16)0U)
167 #define GMAC_GCRA_UPPER_BTR ((uint16)1U)
168 #define GMAC_GCRA_LOWER_CTR ((uint16)2U)
169 #define GMAC_GCRA_UPPER_CTR ((uint16)3U)
170 #define GMAC_GCRA_TER ((uint16)4U)
171 #define GMAC_GCRA_LLR ((uint16)5U)
172
173 #define GMAC_MAC_HW_ADDRESS1_HIGH_RESET_MASK (0x0000FFFFU)
174 #define GMAC_MAC_HW_ADDRESS1_LOW_RESET_MASK (0xFFFFFFFFU)
175
176 #define GMAC_SYS_TIME_SEC_MAX_VALUE (0x100000000U)
177 #define GMAC_SYS_TIME_NANOSEC_MAX_VALUE (0x03B9ACA00U)
178
179 #define GMAC_MAX_WEIGHT_VALUE (0x64U)
180
181 #define GMAC_BYTE_MASK (0xFFU)
182
183 #define GMAC_MDIO_CSR_NO (9U)
184
185 #define GMAC_BUFFDESCR_IS_ALIGNED(x) (((uint32)(x) & (FEATURE_GMAC_BUFFDESCR_ALIGNMENT_BYTES - 1UL)) == 0UL)
186 #define GMAC_BUFF_IS_ALIGNED(x) (((uint32)(x) & (FEATURE_GMAC_BUFF_ALIGNMENT_BYTES - 1UL)) == 0UL)
187 #define GMAC_BUFFLEN_IS_ALIGNED(x) (((uint32)(x) & (FEATURE_GMAC_BUFFLEN_ALIGNMENT_BYTES - 1UL)) == 0UL)
188 #define GMAC_TXRINGLEN_IS_BLOCK_ALIGNED(x) (((uint32)(x) & (FEATURE_GMAC_TXRINGLEN_ALIGNMENT_BYTES - 1UL)) == 0UL)
189 #define GMAC_RXRINGLEN_IS_BLOCK_ALIGNED(x) (((uint32)(x) & (FEATURE_GMAC_RXRINGLEN_ALIGNMENT_BYTES - 1UL)) == 0UL)
190
191 #define GMAC_CH_NORMAL_INTERRUPTS ((uint32)GMAC_DMA_CH0_STATUS_TI_MASK | (uint32)GMAC_DMA_CH0_STATUS_TBU_MASK | (uint32)GMAC_DMA_CH0_STATUS_RI_MASK | \
192 (uint32)GMAC_DMA_CH0_STATUS_ERI_MASK)
193 #define GMAC_CH_ABNORMAL_INTERRUPTS ((uint32)GMAC_DMA_CH0_STATUS_TPS_MASK | (uint32)GMAC_DMA_CH0_STATUS_RBU_MASK | (uint32)GMAC_DMA_CH0_STATUS_RPS_MASK | \
194 (uint32)GMAC_DMA_CH0_STATUS_ETI_MASK | (uint32)GMAC_DMA_CH0_STATUS_FBE_MASK | (uint32)GMAC_DMA_CH0_STATUS_CDE_MASK)
195
196 #if (GMAC_IP_DEV_ERROR_DETECT == STD_ON)
197 #define GMAC_DEV_ASSERT(x) DevAssert(x)
198 #else
199 #define GMAC_DEV_ASSERT(x)
200 #endif
201
202 #if (GMAC_IP_DEV_ERROR_DETECT == STD_ON)
203 #define DEFINE_ERROR_VAR(type, var_name) type var_name
204 #else
205 #define DEFINE_ERROR_VAR(type, var_name)
206 #endif
207
208 #define FEATURE_GMAC_NUM_COUNTER_REG (uint32)(GMAC_CTR_NUMBER_OF_COUNTERS)
209 /*******************************************************************************
210 * Variables
211 ******************************************************************************/
212 #define ETH_43_GMAC_START_SEC_VAR_CLEARED_UNSPECIFIED
213 #include "Eth_43_GMAC_MemMap.h"
214
215
216 /*! @brief Pointers to GMAC internal driver state for each Instance. */
217 Gmac_Ip_StateType *Gmac_apxState[FEATURE_GMAC_NUM_INSTANCES] = {NULL_PTR};
218
219
220 #define ETH_43_GMAC_STOP_SEC_VAR_CLEARED_UNSPECIFIED
221 #include "Eth_43_GMAC_MemMap.h"
222
223 #if (STD_ON == GMAC_IP_HAS_EXTERNAL_TX_BUFFERS)
224 #define ETH_43_GMAC_START_SEC_CONST_BOOLEAN
225 #include "Eth_43_GMAC_MemMap.h"
226
227 /** @brief Table storing information related to the method of Tx Data Buffers Management.*/
228 static const boolean Gmac_Ip_InstHasExternalTxBufferManagement[FEATURE_GMAC_NUM_INSTANCES] = GMAC_IP_INST_HAS_EXTERNAL_TX_BUFFERS;
229
230 #define ETH_43_GMAC_STOP_SEC_CONST_BOOLEAN
231 #include "Eth_43_GMAC_MemMap.h"
232 #endif
233
234 #if (GMAC_HAS_CACHE_MANAGEMENT == STD_ON)
235 /* FEATURE_GMAC_CACHABLE_BUFFERS_LMEM and FEATURE_GMAC_CACHABLE_BUFFERS_CORE are generated based on the
236 platform and the core type in case both cache IPs are supported.
237 These macros must be both defined for the driver when the cache management feature is enabled.
238 They must not be simultaneosly enabled at runtime.*/
239 #ifdef FEATURE_GMAC_CACHABLE_BUFFERS_LMEM
240 #ifdef FEATURE_GMAC_CACHABLE_BUFFERS_CORE
241 #define ETH_43_GMAC_START_SEC_CONST_UNSPECIFIED
242 #include "Eth_43_GMAC_MemMap.h"
243 #if (FEATURE_GMAC_CACHABLE_BUFFERS_LMEM > 0U)
244 /** @brief Global variable which contains the type of CACHE Type used on the current platform.
245 * CACHE_IP_LMEM is using LMEM peripheral.
246 * CACHE_IP_CORE is using SCB peripheral.
247 */
248 static const Cache_Ip_Type CacheType = CACHE_IP_LMEM;
249 #elif (FEATURE_GMAC_CACHABLE_BUFFERS_CORE > 0U)
250 /** @brief Global variable which contains the type of CACHE Type used on the current platform.
251 * CACHE_IP_LMEM is using LMEM peripheral.
252 * CACHE_IP_CORE is using SCB peripheral.
253 */
254 static const Cache_Ip_Type CacheType = CACHE_IP_CORE;
255 #endif
256 #define ETH_43_GMAC_STOP_SEC_CONST_UNSPECIFIED
257 #include "Eth_43_GMAC_MemMap.h"
258 #endif /* defined (FEATURE_GMAC_CACHABLE_BUFFERS_CORE) */
259 #endif /* defined (FEATURE_GMAC_CACHABLE_BUFFERS_LMEM) */
260 #endif /*GMAC_HAS_CACHE_MANAGEMENT == STD_ON */
261
262 /*******************************************************************************
263 * Prototypes
264 ******************************************************************************/
265 #define ETH_43_GMAC_START_SEC_CODE
266 #include "Eth_43_GMAC_MemMap.h"
267
268 static uint32 Gmac_Ip_ComputeCRC32(const uint8 *Mac, uint8 Size);
269
270 static Gmac_Ip_StatusType Gmac_Ip_InitDMA(uint8 Instance,
271 const Gmac_CtrlConfigType *Config);
272 static void Gmac_Ip_InitStateStructure(uint8 Instance,
273 const Gmac_CtrlConfigType *Config);
274 static void Gmac_Ip_InitTxBD(uint8 Instance,
275 const Gmac_Ip_ConfigType *Config,
276 const Gmac_Ip_TxRingConfigType TxRingConfig[]
277 );
278 static void Gmac_Ip_InitRxBD(uint8 Instance,
279 const Gmac_Ip_ConfigType *Config,
280 const Gmac_Ip_RxRingConfigType RxRingConfig[]
281 );
282
283 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC)
284 static void Gmac_Ip_InitSafetyEvents(GMAC_Type *Base,
285 const Gmac_Ip_ConfigType *Config);
286 #endif
287
288 static uint8 Gmac_Ip_WriteGateControlList(
289 uint8 Instance,
290 uint16 AddrGateList,
291 uint32 Data,
292 boolean IsGCLA
293 );
294
295 static void Gmac_Ip_InitMTL(uint8 Instance, const Gmac_CtrlConfigType *Config);
296
297 static void Gmac_Ip_InitMAC(GMAC_Type *Base,
298 const Gmac_CtrlConfigType *Config);
299
300 static void Gmac_Ip_GetTimestamp(const GMAC_Type *Base,
301 const Gmac_Ip_BufferDescriptorType * Bd,
302 Gmac_Ip_TimestampType * Timestamp);
303
304 static boolean Gmac_Ip_RestoreRxCtxtDescr(Gmac_Ip_BufferDescriptorType *Bd);
305
306 static void Gmac_Ip_RestoreTxDescr(uint8 Instance);
307
308 static void Gmac_Ip_RestoreRxDescr(uint8 Instance);
309
310 static Gmac_Ip_StatusType Gmac_Ip_CheckMTLEmpty(
311 uint8 Instance,
312 uint16 NumQueues,
313 boolean IsTransmit
314 );
315
316 static Gmac_Ip_PayloadType Gmac_Ip_GetPayloadType(uint32 PayloadTypeVal);
317
318 static void Gmac_Ip_ReadTimeStampInfo(uint8 Instance,
319 uint8 Ring,
320 Gmac_Ip_RxInfoType * Info
321 );
322
323 /*******************************************************************************
324 * Private functions
325 ******************************************************************************/
326
327 /*FUNCTION**********************************************************************
328 *
329 * Function Name : Gmac_Ip_ComputeCRC32
330 * Description : Computes the CRC32 of a given MAC address.
331 *
332 *END**************************************************************************/
Gmac_Ip_ComputeCRC32(const uint8 * Mac,uint8 Size)333 static uint32 Gmac_Ip_ComputeCRC32(const uint8 *Mac, uint8 Size)
334 {
335 uint32 Crc = 0xFFFFFFFFUL;
336 uint32 i, j;
337
338 for (i = 0; i < Size; i++)
339 {
340 Crc = Crc ^ Mac[i];
341 for (j = 0; j < 8U; j++)
342 {
343 if ((Crc & 0x1U) != 0U)
344 {
345 Crc = (Crc >> 1U) ^ 0xEDB88320U;
346 }
347 else
348 {
349 Crc = (Crc >> 1U);
350 }
351 }
352 }
353
354 return ~Crc;
355 }
356
357 /*FUNCTION**********************************************************************
358 *
359 * Function Name : Gmac_Ip_ReadTimeStampInfo
360 * Description : Read timestamp value
361 *
362 *END**************************************************************************/
Gmac_Ip_ReadTimeStampInfo(uint8 Instance,uint8 Ring,Gmac_Ip_RxInfoType * Info)363 static void Gmac_Ip_ReadTimeStampInfo(uint8 Instance,
364 uint8 Ring,
365 Gmac_Ip_RxInfoType * Info
366 )
367 {
368 const GMAC_Type *Base;
369 const Gmac_Ip_BufferDescriptorType *Bd;
370 uint16 CurrTimeSecHi;
371 uint32 CurrTimeSec;
372 uint32 BdSec;
373
374 Base = Gmac_apxBases[Instance];
375 Bd = Gmac_apxState[Instance]->RxCurrentDesc[Ring];
376
377 if ((Bd->Des1 & GMAC_RDES1_TSA_MASK) != 0U)
378 {
379 Bd++;
380 Gmac_apxState[Instance]->RxCurrentDesc[Ring]++;
381
382 CurrTimeSec = (uint32)(Base->MAC_SYSTEM_TIME_SECONDS);
383 CurrTimeSecHi = (uint16)(Base->MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS);
384 BdSec = (uint32)(Bd->Des1);
385
386 if (BdSec <= CurrTimeSec)
387 {
388 Info->Timestamp.secondsHi = CurrTimeSecHi;
389 }
390 else
391 {
392 Info->Timestamp.secondsHi = (uint16)(CurrTimeSecHi - 1U);
393 }
394 Info->Timestamp.seconds = BdSec;
395 Info->Timestamp.nanoseconds = (uint32)(Bd->Des0);
396 }
397 else
398 {
399 Info->Timestamp.secondsHi = 0U;
400 Info->Timestamp.seconds = 0U;
401 Info->Timestamp.nanoseconds = 0U;
402 }
403 }
404
405 /*FUNCTION**********************************************************************
406 *
407 * Function Name : Gmac_Ip_InitDMA
408 * Description : Initializes the DMA subsystem
409 *
410 * Warning : DMA_CHx_CONTROL_DSL will fail miserably on platforms with
411 * 128-bit Data bus width. If such a platform is encountered,
412 * Gmac_Ip_BufferDescriptorType will have to use four Info
413 * fields instead of just two.
414 *
415 *END**************************************************************************/
Gmac_Ip_InitDMA(uint8 Instance,const Gmac_CtrlConfigType * Config)416 static Gmac_Ip_StatusType Gmac_Ip_InitDMA(uint8 Instance,
417 const Gmac_CtrlConfigType *Config)
418 {
419 GMAC_Type *Base;
420 Gmac_Ip_StatusType Status = GMAC_STATUS_TIMEOUT;
421 uint32 StartTime;
422 uint32 ElapsedTime;
423 uint32 TimeoutTicks;
424
425 Base = Gmac_apxBases[Instance];
426
427 /* Provide a software reset. */
428 Base->DMA_MODE |= GMAC_DMA_MODE_SWR_MASK;
429
430 GMAC_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, GMAC_TIMEOUT_VALUE_US);
431
432 #ifdef MCAL_ENABLE_FAULT_INJECTION
433 MCAL_FAULT_INJECTION_POINT(ETH_DMA_BUSY);
434 #endif
435
436 do
437 {
438 if ((Base->DMA_MODE & GMAC_DMA_MODE_SWR_MASK) == 0U)
439 {
440 Status = GMAC_STATUS_SUCCESS;
441 break;
442 }
443 }
444 while (!GMAC_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
445
446 if (Status == GMAC_STATUS_SUCCESS)
447 {
448 /* Initialize the global DMA registers. */
449 #if FEATURE_GMAC_DATA_BUS_AXI
450 Base->DMA_MODE = GMAC_DMA_MODE_INTM(1) | GMAC_DMA_MODE_DSPW(1);
451
452 /* Workaround for Errata ERR050614 */
453 #if defined(ERR_IPV_GMAC_E050614)
454 #if (STD_ON == ERR_IPV_GMAC_E050614)
455 Base->DMA_MODE &= ~GMAC_DMA_MODE_DSPW(1);
456 #endif
457 #endif
458
459 #else
460 Base->DMA_MODE = GMAC_DMA_MODE_INTM(1);
461 #endif
462
463 #if FEATURE_GMAC_DATA_BUS_AXI
464 /* Each Tx DMA channel can have 2 outstanding read requests per channel */
465 /* All Rx DMA channels can have 1 oustanding write request to avoid loss of bandwidth in early burst termination scenarios */
466 Base->DMA_SYSBUS_MODE = GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT(((uint32)Config->Gmac_pCtrlConfig->TxRingCount * 2U) - 1U) |
467 GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT(0U) |
468 GMAC_DMA_SYSBUS_MODE_AAL(1U) |
469 GMAC_DMA_SYSBUS_MODE_BLEN32(1U);
470 #else
471 Base->DMA_SYSBUS_MODE = GMAC_DMA_SYSBUS_MODE_AAL(1U);
472 #endif
473
474 Gmac_Ip_InitTxBD(Instance, Config->Gmac_pCtrlConfig, Config->Gmac_paCtrlTxRingConfig);
475 Gmac_Ip_InitRxBD(Instance, Config->Gmac_pCtrlConfig, Config->Gmac_paCtrlRxRingConfig);
476 }
477
478 return Status;
479 }
480
481 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC)
482 /*FUNCTION**********************************************************************
483 *
484 * Function Name : Gmac_Ip_InitSafetyEvents
485 * Description : Initializes the safety events
486 *
487 *END**************************************************************************/
Gmac_Ip_InitSafetyEvents(GMAC_Type * Base,const Gmac_Ip_ConfigType * Config)488 static void Gmac_Ip_InitSafetyEvents(GMAC_Type *Base,
489 const Gmac_Ip_ConfigType *Config)
490 {
491 /* Mask correctable error IRQs */
492 Base->MTL_ECC_INTERRUPT_ENABLE = 0U;
493
494 /* Configure ECC Protection */
495 if ((Config->SafetyInterrupts & (uint32)GMAC_SAF_ERR_ECC) != 0U)
496 {
497 Base->MTL_ECC_CONTROL |= GMAC_MTL_ECC_CONTROL_MESTEE_MASK | GMAC_MTL_ECC_CONTROL_MRXEE_MASK | GMAC_MTL_ECC_CONTROL_MTXEE_MASK;
498 }
499 else
500 {
501 Base->MTL_ECC_CONTROL &= ~(GMAC_MTL_ECC_CONTROL_MESTEE_MASK | GMAC_MTL_ECC_CONTROL_MRXEE_MASK | GMAC_MTL_ECC_CONTROL_MTXEE_MASK);
502 }
503
504 #if FEATURE_GMAC_ASP_ALL
505 /* Configure Datapath Parity Protection */
506 if ((Config->SafetyInterrupts & (uint32)GMAC_SAF_ERR_DATA_PATH_PARITY) != 0U)
507 {
508 Base->MTL_DPP_CONTROL |= GMAC_MTL_DPP_CONTROL_OPE_MASK | GMAC_MTL_DPP_CONTROL_EDPP_MASK;
509 }
510 else
511 {
512 Base->MTL_DPP_CONTROL &= ~(GMAC_MTL_DPP_CONTROL_OPE_MASK | GMAC_MTL_DPP_CONTROL_EDPP_MASK);
513 }
514
515 /* Configure FSM State Parity Protection */
516 if ((Config->SafetyInterrupts & (uint32)GMAC_SAF_ERR_FSM_STATE_PARITY) != 0U)
517 {
518 Base->MAC_FSM_CONTROL |= GMAC_MAC_FSM_CONTROL_PRTYEN_MASK;
519 }
520 else
521 {
522 Base->MAC_FSM_CONTROL &= ~GMAC_MAC_FSM_CONTROL_PRTYEN_MASK;
523 }
524
525 /* Configure FSM Timeout Protection */
526 if ((Config->SafetyInterrupts & (uint32)GMAC_SAF_ERR_FSM_TIMEOUT) != 0U)
527 {
528 Base->MAC_FSM_ACT_TIMER &= ~GMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK;
529 /* TBD: Get the actual module clock frequency for the TMR field */
530 Base->MAC_FSM_ACT_TIMER |= GMAC_MAC_FSM_ACT_TIMER_NTMRMD(2U) | GMAC_MAC_FSM_ACT_TIMER_TMR(80U);
531 Base->MAC_FSM_CONTROL |= GMAC_MAC_FSM_CONTROL_TMOUTEN_MASK;
532 }
533 else
534 {
535 Base->MAC_FSM_CONTROL &= ~GMAC_MAC_FSM_CONTROL_TMOUTEN_MASK;
536 }
537 #endif
538 }
539 #endif /* #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC) */
540 /*FUNCTION**********************************************************************
541 *
542 * Function Name : Gmac_Ip_WriteGateControlList
543 * Description : Initializes value to Gate Control List.
544 *
545 *END**************************************************************************/
Gmac_Ip_WriteGateControlList(uint8 Instance,uint16 AddrGateList,uint32 Data,boolean IsGCLA)546 static uint8 Gmac_Ip_WriteGateControlList(
547 uint8 Instance,
548 uint16 AddrGateList,
549 uint32 Data,
550 boolean IsGCLA
551 )
552 {
553 Gmac_Ip_StatusType Status = GMAC_STATUS_TIMEOUT;
554 uint32 StartTime;
555 uint32 ElapsedTime;
556 uint32 TimeoutTicks;
557 uint8 u8ErrorNum = 0U;
558
559 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
560
561 Gmac_apxBases[Instance]->MTL_EST_GCL_DATA = GMAC_MTL_EST_GCL_DATA_GCD(Data);
562
563 Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL = GMAC_MTL_EST_GCL_CONTROL_ADDR(AddrGateList);
564
565 if ((boolean)FALSE == IsGCLA)
566 {
567 Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL |= GMAC_MTL_EST_GCL_CONTROL_GCRR_MASK;
568 }
569 else
570 {
571 Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL &= ~GMAC_MTL_EST_GCL_CONTROL_GCRR_MASK;
572 }
573
574 Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL |= GMAC_MTL_EST_GCL_CONTROL_R1W0(0U);
575
576 Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL |= GMAC_MTL_EST_GCL_CONTROL_SRWO_MASK;
577
578 GMAC_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, GMAC_TIMEOUT_VALUE_US);
579
580 /* Add fault label for testing */
581 #ifdef MCAL_ENABLE_FAULT_INJECTION
582 MCAL_FAULT_INJECTION_POINT(ETH_WRITE_GATE_CONTROLIST_TIMEOUT);
583 #endif
584
585 do
586 {
587 if ((Gmac_apxBases[Instance]->MTL_EST_GCL_CONTROL & GMAC_MTL_EST_GCL_CONTROL_SRWO_MASK) == 0U)
588 {
589 Status = GMAC_STATUS_SUCCESS;
590 break;
591 }
592 }
593 while (!GMAC_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
594
595 u8ErrorNum = ((GMAC_STATUS_TIMEOUT == Status) ? ((uint8)1U) : ((uint8)0U));
596
597 return u8ErrorNum;
598 }
599 /*FUNCTION**********************************************************************
600 *
601 * Function Name : Gmac_Ip_InitMTL
602 * Description : Initializes the MTL subsystem
603 *
604 *END**************************************************************************/
Gmac_Ip_InitMTL(uint8 Instance,const Gmac_CtrlConfigType * Config)605 static void Gmac_Ip_InitMTL(uint8 Instance,
606 const Gmac_CtrlConfigType *Config)
607 {
608 uint32 FifoSize;
609 uint8 i;
610
611 /* Set the global Tx Scheduling Algorithm affecting all Tx Queues */
612 Gmac_apxBases[Instance]->MTL_OPERATION_MODE = GMAC_MTL_OPERATION_MODE_SCHALG((uint32)(Config->Gmac_pCtrlConfig->TxSchedAlgo));
613
614 /* Configure MTL Tx Queues */
615 for (i = 0U; i < Config->Gmac_pCtrlConfig->TxRingCount; ++i)
616 {
617 FifoSize = (uint32)Config->Gmac_paCtrlTxRingConfig[i].RingSize * Config->Gmac_paCtrlTxRingConfig[i].BufferLen;
618
619 if ((GMAC_OP_MODE_DCB_GEN == Config->Gmac_paCtrlTxRingConfig[i].QueueOpMode) && (Config->Gmac_pCtrlConfig->TxRingCount > 0U))
620 {
621 GMAC_SetTxQueueQuantumWeight(Gmac_apxQueueBases[Instance][i], Config->Gmac_paCtrlTxRingConfig[i].Weight);
622 }
623 else if ((GMAC_OP_MODE_AVB == Config->Gmac_paCtrlTxRingConfig[i].QueueOpMode) && (i > 0U))
624 {
625 GMAC_SetTxQueueQuantumWeight(Gmac_apxQueueBases[Instance][i], Config->Gmac_paCtrlTxRingConfig[i].IdleSlopeCredit);
626 GMAC_SetTxQueueCreditBasedShaper(Gmac_apxQueueBases[Instance][i],
627 Config->Gmac_paCtrlTxRingConfig[i].SendSlopeCredit,
628 Config->Gmac_paCtrlTxRingConfig[i].HiCredit,
629 Config->Gmac_paCtrlTxRingConfig[i].LoCredit);
630 }
631 else
632 {
633 /* do nothing */
634 }
635
636 /* Enable the Tx Queue in the given mode and set its size */
637 GMAC_SetTxQueueOperationMode(Gmac_apxQueueBases[Instance][i], Config->Gmac_paCtrlTxRingConfig[i].QueueOpMode, FifoSize);
638 }
639
640
641 /* Set default scheduling algorithm for Rx as Strict priority. */
642 Gmac_apxBases[Instance]->MTL_OPERATION_MODE &= ~GMAC_MTL_OPERATION_MODE_RAA_MASK;
643
644 /* Set 1:1 mapping between Rx Queues and Rx DMA Channels */
645 GMAC_SetRxQueuesDmaChMap(Gmac_apxBases[Instance], Config->Gmac_pCtrlConfig->RxRingCount);
646
647 /* Configure MTL Rx Queues */
648 for (i = 0U; i < Config->Gmac_pCtrlConfig->RxRingCount; ++i)
649 {
650 FifoSize = (uint32)Config->Gmac_paCtrlRxRingConfig[i].RingSize * Config->Gmac_paCtrlRxRingConfig[i].BufferLen;
651
652 /* Set the size of the Rx Queue */
653 GMAC_SetRxQueueOperationMode(Gmac_apxQueueBases[Instance][i], FifoSize);
654
655 /* Enable the Rx Queue for generic traffic with the given VLAN priorities */
656 GMAC_EnableRxQueue(Gmac_apxBases[Instance], Config->Gmac_paCtrlRxRingConfig[i].PriorityMask, i);
657 }
658
659 }
660
661 /*FUNCTION**********************************************************************
662 *
663 * Function Name : Gmac_Ip_InitMAC
664 * Description : Initializes the MAC subsystem
665 *
666 *END**************************************************************************/
Gmac_Ip_InitMAC(GMAC_Type * Base,const Gmac_CtrlConfigType * Config)667 static void Gmac_Ip_InitMAC(GMAC_Type *Base,
668 const Gmac_CtrlConfigType *Config)
669 {
670 Base->MAC_Q0_TX_FLOW_CTRL = 0U;
671
672 Base->MAC_INTERRUPT_ENABLE = Config->Gmac_pCtrlConfig->Interrupts;
673
674 Base->MAC_CONFIGURATION = Config->Gmac_pCtrlConfig->MacConfig;
675 Base->MAC_CONFIGURATION |= (uint32)(((uint32)Config->Gmac_pCtrlConfig->Speed) << GMAC_MAC_CONFIGURATION_FES_SHIFT);
676 Base->MAC_CONFIGURATION |= GMAC_MAC_CONFIGURATION_DM(Config->Gmac_pCtrlConfig->Duplex);
677 if (Config->Gmac_pCtrlConfig->EnableCtrl)
678 {
679 Base->MAC_CONFIGURATION |= GMAC_MAC_CONFIGURATION_TE_MASK | GMAC_MAC_CONFIGURATION_RE_MASK;
680 }
681
682 /* Set MAC packet filter. */
683 Base->MAC_PACKET_FILTER = Config->Gmac_pCtrlConfig->MacPktFilterConfig;
684
685 /* Disable common interrupt from MMC */
686 Base->MMC_TX_INTERRUPT_MASK = 0x03FFFFFFU;
687 Base->MMC_RX_INTERRUPT_MASK = 0x03FFFFFFU;
688 }
689
690 /*FUNCTION**********************************************************************
691 *
692 * Function Name : Gmac_Ip_InitStateStructure
693 * Description : Initializes State Structure
694 *
695 *END**************************************************************************/
Gmac_Ip_InitStateStructure(uint8 Instance,const Gmac_CtrlConfigType * Config)696 static void Gmac_Ip_InitStateStructure(uint8 Instance,
697 const Gmac_CtrlConfigType *Config)
698 {
699 uint8 i;
700
701 /* Initialize state structure. */
702 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC)
703 Config->Gmac_pCtrlState->SafetyCallback = Config->Gmac_pCtrlConfig->SafetyCallback;
704 #endif
705 Config->Gmac_pCtrlState->Callback = Config->Gmac_pCtrlConfig->Callback;
706 Config->Gmac_pCtrlState->RxRingCount = Config->Gmac_pCtrlConfig->RxRingCount;
707 Config->Gmac_pCtrlState->TxRingCount = Config->Gmac_pCtrlConfig->TxRingCount;
708 for (i = 0; i < Config->Gmac_pCtrlConfig->RxRingCount; i++)
709 {
710 Config->Gmac_pCtrlState->RxChCallback[i] = Config->Gmac_paCtrlRxRingConfig[i].Callback;
711 Config->Gmac_pCtrlState->RxCurrentDesc[i] = Config->Gmac_paCtrlRxRingConfig[i].RingDesc;
712 Config->Gmac_pCtrlState->RxAllocDesc[i] = Config->Gmac_paCtrlRxRingConfig[i].RingDesc;
713 }
714 for (i = 0; i < Config->Gmac_pCtrlConfig->TxRingCount; i++)
715 {
716 Config->Gmac_pCtrlState->TxChCallback[i] = Config->Gmac_paCtrlTxRingConfig[i].Callback;
717 Config->Gmac_pCtrlState->TxCurrentDesc[i] = Config->Gmac_paCtrlTxRingConfig[i].RingDesc;
718 }
719
720 Gmac_apxState[Instance] = Config->Gmac_pCtrlState;
721 }
722
723 /*FUNCTION**********************************************************************
724 *
725 * Function Name : Gmac_Ip_InitTxBD
726 * Description : Initializes Tx Buffer Descriptor
727 *
728 *END**************************************************************************/
Gmac_Ip_InitTxBD(uint8 Instance,const Gmac_Ip_ConfigType * Config,const Gmac_Ip_TxRingConfigType TxRingConfig[])729 static void Gmac_Ip_InitTxBD(uint8 Instance,
730 const Gmac_Ip_ConfigType *Config,
731 const Gmac_Ip_TxRingConfigType TxRingConfig[]
732 )
733 {
734 uint8 i;
735 uint16 j;
736
737 /* Configure Transmit Ring */
738 for (i = 0U; i < Config->TxRingCount; i++)
739 {
740 for (j = 0U; j < TxRingConfig[i].RingSize; j++)
741 {
742 TxRingConfig[i].RingDesc[j].Des0 = (TxRingConfig[i].Buffer != NULL_PTR)? (uint32)(&TxRingConfig[i].Buffer[TxRingConfig[i].BufferLen * j]) : 0U;
743 TxRingConfig[i].RingDesc[j].Des1 = 0U;
744 TxRingConfig[i].RingDesc[j].Des2 = 0U;
745 TxRingConfig[i].RingDesc[j].Des3 = 0U;
746 TxRingConfig[i].RingDesc[j].Info0 = 0U;
747 TxRingConfig[i].RingDesc[j].Info1 = (uint32)((uint32)TxRingConfig[i].BufferLen & GMAC_INFO1_LENGTH_MASK);
748 }
749
750 /* Initialize transmit descriptor list address and tail pointer */
751 Gmac_apxChBases[Instance][i]->DMA_TXDESC_TAIL_POINTER = (uint32)TxRingConfig[i].RingDesc;
752 Gmac_apxChBases[Instance][i]->DMA_TXDESC_LIST_ADDRESS = (uint32)TxRingConfig[i].RingDesc;
753
754 /* Program the Transmit Ring length register */
755 Gmac_apxChBases[Instance][i]->DMA_TXDESC_RING_LENGTH = ((uint32)TxRingConfig[i].RingSize) - 1UL;
756
757 /* Program the settings of the following registers for the parameters like maximum burst-length (PBL)
758 initiated by DMA, descriptor skip lengths, OSP, and so on */
759 if (32U < TxRingConfig[i].DmaBurstLength)
760 {
761 Gmac_apxChBases[Instance][i]->DMA_CONTROL = GMAC_DMA_CH0_CONTROL_DSL((FEATURE_GMAC_SW_BUFFDESCR_SIZE_BYTES - FEATURE_GMAC_HW_BUFFDESCR_SIZE_BYTES) / FEATURE_GMAC_DATA_BUS_WIDTH_BYTES) | GMAC_DMA_CH0_CONTROL_PBLx8(1);
762 Gmac_apxChBases[Instance][i]->DMA_TX_CONTROL = GMAC_DMA_CH0_TX_CONTROL_TxPBL((uint32)TxRingConfig[i].DmaBurstLength / 8U) | GMAC_DMA_CH0_TX_CONTROL_OSF(1);
763 }
764 else
765 {
766 Gmac_apxChBases[Instance][i]->DMA_CONTROL = GMAC_DMA_CH0_CONTROL_DSL((FEATURE_GMAC_SW_BUFFDESCR_SIZE_BYTES - FEATURE_GMAC_HW_BUFFDESCR_SIZE_BYTES) / FEATURE_GMAC_DATA_BUS_WIDTH_BYTES);
767 Gmac_apxChBases[Instance][i]->DMA_TX_CONTROL = GMAC_DMA_CH0_TX_CONTROL_TxPBL(TxRingConfig[i].DmaBurstLength) | GMAC_DMA_CH0_TX_CONTROL_OSF(1);
768 }
769
770 /* Enable the interrupts */
771 Gmac_apxChBases[Instance][i]->DMA_INTERRUPT_ENABLE = TxRingConfig[i].Interrupts |
772 (((TxRingConfig[i].Interrupts & GMAC_CH_NORMAL_INTERRUPTS) != 0U) ? (uint32)GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK : 0U) |
773 (((TxRingConfig[i].Interrupts & GMAC_CH_ABNORMAL_INTERRUPTS) != 0U) ? (uint32)GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK : 0U);
774
775 if (Config->EnableCtrl)
776 {
777 /* Start the Transmit DMA */
778 Gmac_apxChBases[Instance][i]->DMA_TX_CONTROL |= GMAC_DMA_CH0_TX_CONTROL_ST_MASK;
779 }
780 }
781 }
782
783 /*FUNCTION**********************************************************************
784 *
785 * Function Name : Gmac_Ip_InitRxBD
786 * Description : Initializes Rx Buffer Descriptor
787 *
788 *END**************************************************************************/
Gmac_Ip_InitRxBD(uint8 Instance,const Gmac_Ip_ConfigType * Config,const Gmac_Ip_RxRingConfigType RxRingConfig[])789 static void Gmac_Ip_InitRxBD(uint8 Instance,
790 const Gmac_Ip_ConfigType *Config,
791 const Gmac_Ip_RxRingConfigType RxRingConfig[]
792 )
793 {
794 uint8 i;
795 uint16 j;
796
797 /* Configure Receive Ring */
798 for (i = 0U; i < Config->RxRingCount; i++)
799 {
800 for (j = 0U; j < RxRingConfig[i].RingSize; j++)
801 {
802 if (RxRingConfig[i].Buffer != NULL_PTR)
803 {
804 RxRingConfig[i].RingDesc[j].Des0 = (uint32)(&RxRingConfig[i].Buffer[RxRingConfig[i].BufferLen * j]);
805 RxRingConfig[i].RingDesc[j].Des1 = 0U;
806 RxRingConfig[i].RingDesc[j].Des2 = 0U;
807 RxRingConfig[i].RingDesc[j].Info0 = RxRingConfig[i].RingDesc[j].Des0;
808 RxRingConfig[i].RingDesc[j].Info1 = (uint32)((uint32)RxRingConfig[i].BufferLen & GMAC_INFO1_LENGTH_MASK);
809 RxRingConfig[i].RingDesc[j].Des3 = GMAC_RDES3_OWN_MASK | GMAC_RDES3_INTE_MASK | GMAC_RDES3_BUF1V_MASK;
810 }
811 else
812 {
813 RxRingConfig[i].RingDesc[j].Des0 = 0U;
814 RxRingConfig[i].RingDesc[j].Des1 = 0U;
815 RxRingConfig[i].RingDesc[j].Des2 = 0U;
816 RxRingConfig[i].RingDesc[j].Info0 = 0U;
817 RxRingConfig[i].RingDesc[j].Info1 = (uint32)((uint32)RxRingConfig[i].BufferLen & GMAC_INFO1_LENGTH_MASK);
818 RxRingConfig[i].RingDesc[j].Des3 = GMAC_RDES3_INTE_MASK | GMAC_RDES3_BUF1V_MASK;
819 }
820 }
821
822 /* Initialize transmit descriptor list address and tail pointer */
823 Gmac_apxChBases[Instance][i]->DMA_RXDESC_TAIL_POINTER = (uint32)(&RxRingConfig[i].RingDesc[RxRingConfig[i].RingSize]);
824 Gmac_apxChBases[Instance][i]->DMA_RXDESC_LIST_ADDRESS = (uint32)RxRingConfig[i].RingDesc;
825
826 /* Program the Transmit Ring length register */
827 Gmac_apxChBases[Instance][i]->DMA_RXDESC_RING_LENGTH = ((uint32)RxRingConfig[i].RingSize) - 1UL;
828
829 /* Program the settings of the following registers for the parameters like maximum burst-length (PBL)
830 initiated by DMA, descriptor skip lengths, RBSZ, and so on */
831 if (32U < RxRingConfig[i].DmaBurstLength)
832 {
833 Gmac_apxChBases[Instance][i]->DMA_CONTROL = GMAC_DMA_CH0_CONTROL_DSL((FEATURE_GMAC_SW_BUFFDESCR_SIZE_BYTES - FEATURE_GMAC_HW_BUFFDESCR_SIZE_BYTES) / FEATURE_GMAC_DATA_BUS_WIDTH_BYTES) | GMAC_DMA_CH0_CONTROL_PBLx8(1);
834 Gmac_apxChBases[Instance][i]->DMA_RX_CONTROL = GMAC_DMA_CH0_RX_CONTROL_RxPBL((uint32)RxRingConfig[i].DmaBurstLength / 8U) | GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y(((uint32)RxRingConfig[i].BufferLen) >> FEATURE_GMAC_LOG2_DATA_BUS_WIDTH_BYTES);
835 }
836 else
837 {
838 Gmac_apxChBases[Instance][i]->DMA_CONTROL = GMAC_DMA_CH0_CONTROL_DSL((FEATURE_GMAC_SW_BUFFDESCR_SIZE_BYTES - FEATURE_GMAC_HW_BUFFDESCR_SIZE_BYTES) / FEATURE_GMAC_DATA_BUS_WIDTH_BYTES);
839 Gmac_apxChBases[Instance][i]->DMA_RX_CONTROL = GMAC_DMA_CH0_RX_CONTROL_RxPBL(RxRingConfig[i].DmaBurstLength) | GMAC_DMA_CH0_RX_CONTROL_RBSZ_13_y(((uint32)RxRingConfig[i].BufferLen) >> FEATURE_GMAC_LOG2_DATA_BUS_WIDTH_BYTES);
840 }
841
842 /* Enable the interrupts */
843 Gmac_apxChBases[Instance][i]->DMA_INTERRUPT_ENABLE |= RxRingConfig[i].Interrupts |
844 (((RxRingConfig[i].Interrupts & GMAC_CH_NORMAL_INTERRUPTS) != 0U) ? (uint32)GMAC_DMA_CH0_INTERRUPT_ENABLE_NIE_MASK : 0U) |
845 (((RxRingConfig[i].Interrupts & GMAC_CH_ABNORMAL_INTERRUPTS) != 0U) ? (uint32)GMAC_DMA_CH0_INTERRUPT_ENABLE_AIE_MASK : 0U);
846
847 if (Config->EnableCtrl)
848 {
849 /* Start the Receive DMA */
850 Gmac_apxChBases[Instance][i]->DMA_RX_CONTROL |= GMAC_DMA_CH0_RX_CONTROL_SR_MASK;
851 }
852 }
853 }
854 /*FUNCTION**********************************************************************
855 *
856 * Function Name : Gmac_Ip_GetTimestamp
857 * Description : Gets the Timestamp from a buffer descriptor
858 *
859 *END**************************************************************************/
Gmac_Ip_GetTimestamp(const GMAC_Type * Base,const Gmac_Ip_BufferDescriptorType * Bd,Gmac_Ip_TimestampType * Timestamp)860 static void Gmac_Ip_GetTimestamp(const GMAC_Type *Base,
861 const Gmac_Ip_BufferDescriptorType * Bd,
862 Gmac_Ip_TimestampType * Timestamp)
863 {
864 uint16 CurrTimeSecHi;
865 uint32 CurrTimeSec;
866 uint32 BdSec;
867
868 if ((Bd->Des3 & GMAC_TX_STAT_TTSS_MASK) != 0U)
869 {
870 CurrTimeSec = (uint32)(Base->MAC_SYSTEM_TIME_SECONDS);
871 CurrTimeSecHi = (uint16)(Base->MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS);
872 BdSec = (uint32)(Bd->Des1);
873
874 if (BdSec <= CurrTimeSec)
875 {
876 Timestamp->secondsHi = CurrTimeSecHi;
877 }
878 else
879 {
880 Timestamp->secondsHi = (uint16)(CurrTimeSecHi - 1U);
881 }
882 Timestamp->seconds = BdSec;
883 Timestamp->nanoseconds = (uint32)(Bd->Des0);
884 }
885 else
886 {
887 Timestamp->secondsHi = 0U;
888 Timestamp->seconds = 0U;
889 Timestamp->nanoseconds = 0U;
890 }
891 }
892
893 /*FUNCTION**********************************************************************
894 *
895 * Function Name : Gmac_Ip_RestoreRxCtxtDescr
896 * Description : Restores an Rx descriptor to be used for reception.
897 *
898 *END**************************************************************************/
Gmac_Ip_RestoreRxCtxtDescr(Gmac_Ip_BufferDescriptorType * Bd)899 static boolean Gmac_Ip_RestoreRxCtxtDescr(Gmac_Ip_BufferDescriptorType *Bd)
900 {
901 boolean restored = FALSE;
902
903 GMAC_DEV_ASSERT((Bd->Des3 & GMAC_RDES3_OWN_MASK) == 0U);
904 GMAC_DEV_ASSERT((Bd->Des3 & GMAC_RDES3_CTXT_MASK) != 0U);
905
906 if (Bd->Info0 != 0U)
907 {
908 Bd->Des0 = Bd->Info0;
909 Bd->Des1 = 0U;
910 Bd->Des2 = 0U;
911 Bd->Info1 &= ~GMAC_INFO1_CONSUMED_MASK;
912 Bd->Des3 = GMAC_RDES3_OWN_MASK | GMAC_RDES3_INTE_MASK | GMAC_RDES3_BUF1V_MASK;
913
914 restored = TRUE;
915 }
916
917 return restored;
918 }
919
920 /*FUNCTION**********************************************************************
921 *
922 * Function Name : Gmac_Ip_RestoreTxDescr
923 * Description : Restores a Tx descriptor to be used for transmit.
924 *
925 *END**************************************************************************/
Gmac_Ip_RestoreTxDescr(uint8 Instance)926 static void Gmac_Ip_RestoreTxDescr(uint8 Instance)
927 {
928 Gmac_Ip_BufferDescriptorType *ListBd;
929 uint32 i;
930 uint32 j;
931
932 for (i = 0U; i < Gmac_apxState[Instance]->TxRingCount; i++)
933 {
934 ListBd = (Gmac_Ip_BufferDescriptorType *)Gmac_apxChBases[Instance][i]->DMA_TXDESC_LIST_ADDRESS;
935 for (j = 0U; j <= Gmac_apxChBases[Instance][i]->DMA_TXDESC_RING_LENGTH; ++j)
936 {
937 if (0U != ListBd[j].Info0)
938 {
939 ListBd[j].Des0 = ListBd[j].Info0;
940 ListBd[j].Info0 = 0U;
941 }
942
943 ListBd[j].Des3 &= ~GMAC_TDES3_OWN_MASK;
944 ListBd[j].Info1 &= ~GMAC_INFO1_LOCKED_MASK;
945 }
946 }
947 }
948
949 /*FUNCTION**********************************************************************
950 *
951 * Function Name : Gmac_Ip_RestoreRxDescr
952 * Description : Restores an Rx descriptor to be used for reception.
953 *
954 *END**************************************************************************/
Gmac_Ip_RestoreRxDescr(uint8 Instance)955 static void Gmac_Ip_RestoreRxDescr(uint8 Instance)
956 {
957 Gmac_Ip_BufferDescriptorType *ListBd;
958 uint32 i;
959 uint32 j;
960
961 for (i = 0U; i < Gmac_apxState[Instance]->RxRingCount; i++)
962 {
963 ListBd = (Gmac_Ip_BufferDescriptorType *)Gmac_apxChBases[Instance][i]->DMA_RXDESC_LIST_ADDRESS;
964 for (j = 0U; j <= Gmac_apxChBases[Instance][i]->DMA_RXDESC_RING_LENGTH; ++j)
965 {
966 ListBd[j].Des0 = ListBd[j].Info0;
967 ListBd[j].Info1 &= ~GMAC_INFO1_CONSUMED_MASK;
968 ListBd[j].Des3 = (ListBd[j].Info0 != 0U)?
969 (GMAC_RDES3_OWN_MASK | GMAC_RDES3_INTE_MASK | GMAC_RDES3_BUF1V_MASK):
970 ( GMAC_RDES3_INTE_MASK | GMAC_RDES3_BUF1V_MASK);
971 }
972 }
973 }
974
975 /*FUNCTION**********************************************************************
976 *
977 * Function Name : Gmac_Ip_CheckMTLEmpty
978 * Description : Check MTL Tx/Rx empty or not.
979 *
980 *END**************************************************************************/
Gmac_Ip_CheckMTLEmpty(uint8 Instance,uint16 NumQueues,boolean IsTransmit)981 static Gmac_Ip_StatusType Gmac_Ip_CheckMTLEmpty(
982 uint8 Instance,
983 uint16 NumQueues,
984 boolean IsTransmit
985 )
986 {
987 uint32 StartTime;
988 uint32 ElapsedTime;
989 uint32 TimeoutTicks;
990 boolean TimeoutOccurred;
991 boolean QueueEmpty;
992 uint16 i;
993
994 TimeoutOccurred = FALSE;
995
996 for (i = 0U; (i < NumQueues) && !TimeoutOccurred; i++)
997 {
998 GMAC_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, GMAC_TIMEOUT_VALUE_US);
999 do
1000 {
1001 /* Check MTL queue is empty */
1002 if (IsTransmit)
1003 {
1004 QueueEmpty = ((Gmac_apxQueueBases[Instance][i]->MTL_TXQ_DEBUG & GMAC_MTL_TXQ0_DEBUG_TXQSTS_MASK) == 0U);
1005 }
1006 else
1007 {
1008 QueueEmpty = ((Gmac_apxQueueBases[Instance][i]->MTL_RXQ_DEBUG & GMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK) == 0U);
1009 }
1010 TimeoutOccurred = GMAC_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
1011 }
1012 while (!QueueEmpty && !TimeoutOccurred);
1013 }
1014
1015 return ((TimeoutOccurred == TRUE)? (GMAC_STATUS_TIMEOUT) : (GMAC_STATUS_SUCCESS));
1016 }
1017
1018 /*FUNCTION**********************************************************************
1019 *
1020 * Function Name : Gmac_Ip_GetPayloadType
1021 * Description : Get payload type of Rx frame.
1022 *
1023 *END**************************************************************************/
Gmac_Ip_GetPayloadType(uint32 PayloadTypeVal)1024 static Gmac_Ip_PayloadType Gmac_Ip_GetPayloadType(uint32 PayloadTypeVal)
1025 {
1026 Gmac_Ip_PayloadType PayloadType;
1027
1028 if (1U == PayloadTypeVal)
1029 {
1030 PayloadType = GMAC_IP_PAYLOAD_TYPE_UDP;
1031 }
1032 else if (2U == PayloadTypeVal)
1033 {
1034 PayloadType = GMAC_IP_PAYLOAD_TYPE_TCP;
1035 }
1036 else if (3U == PayloadTypeVal)
1037 {
1038 PayloadType = GMAC_IP_PAYLOAD_TYPE_ICMP;
1039 }
1040 else
1041 {
1042 PayloadType = GMAC_IP_PAYLOAD_TYPE_UNKNOWN;
1043 }
1044
1045 return PayloadType;
1046 }
1047 #if (STD_ON == GMAC_SET_USER_ACCESS_ALLOWED_AVAILABLE)
1048 /*FUNCTION**********************************************************************
1049 *
1050 * Function Name : Gmac_Ip_SetUserAccessAllowed
1051 * Description : Sets the UAA bit in REG_PROT to make the Instance accessible in user mode.
1052 *
1053 *END**************************************************************************/
Gmac_Ip_SetUserAccessAllowed(const GMAC_Type * Base)1054 void Gmac_Ip_SetUserAccessAllowed(const GMAC_Type *Base)
1055 {
1056 SET_USER_ACCESS_ALLOWED((uint32)Base, GMAC_PROT_MEM_U32);
1057 }
1058
1059 /*FUNCTION**********************************************************************
1060 *
1061 * Function Name : Gmac_Ip_ClrUserAccessAllowed
1062 * Description : Clears the UAA bit in REG_PROT to make the Instance accessible in user mode.
1063 *
1064 *END**************************************************************************/
Gmac_Ip_ClrUserAccessAllowed(const GMAC_Type * Base)1065 void Gmac_Ip_ClrUserAccessAllowed(const GMAC_Type *Base)
1066 {
1067 CLR_USER_ACCESS_ALLOWED((uint32)Base, GMAC_PROT_MEM_U32);
1068 }
1069 #endif
1070
1071
1072 /*******************************************************************************
1073 * Code
1074 ******************************************************************************/
1075
1076 /*FUNCTION**********************************************************************
1077 *
1078 * Function Name : Gmac_Ip_Init
1079 * Description : Initializes the GMAC module
1080 * implements Gmac_Ip_Init_Activity
1081 *END**************************************************************************/
Gmac_Ip_Init(uint8 Instance,const Gmac_CtrlConfigType * Config)1082 Gmac_Ip_StatusType Gmac_Ip_Init(uint8 Instance,
1083 const Gmac_CtrlConfigType *Config)
1084 {
1085 GMAC_Type *Base;
1086 Gmac_Ip_StatusType Status;
1087 #if (GMAC_IP_DEV_ERROR_DETECT == STD_ON)
1088 uint32 i;
1089 #endif
1090 DEFINE_ERROR_VAR(uint32, PoolSize);
1091
1092 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1093 GMAC_DEV_ASSERT(Config != NULL_PTR);
1094 GMAC_DEV_ASSERT(Config->Gmac_pCtrlState != NULL_PTR);
1095 GMAC_DEV_ASSERT(Config->Gmac_pCtrlConfig != NULL_PTR);
1096 GMAC_DEV_ASSERT(Config->Gmac_paCtrlRxRingConfig != NULL_PTR);
1097 GMAC_DEV_ASSERT(Config->Gmac_paCtrlTxRingConfig != NULL_PTR);
1098 GMAC_DEV_ASSERT(Config->Gmac_pau8CtrlPhysAddr != NULL_PTR);
1099 GMAC_DEV_ASSERT((Config->Gmac_pCtrlConfig->RxRingCount > 0U) && (Config->Gmac_pCtrlConfig->RxRingCount <= FEATURE_GMAC_NUM_CHANNELS));
1100 GMAC_DEV_ASSERT((Config->Gmac_pCtrlConfig->TxRingCount > 0U) && (Config->Gmac_pCtrlConfig->TxRingCount <= FEATURE_GMAC_NUM_CHANNELS));
1101
1102 #if (GMAC_IP_DEV_ERROR_DETECT == STD_ON)
1103 PoolSize = 0U;
1104
1105 for (i = 0U; i < Config->Gmac_pCtrlConfig->RxRingCount; ++i)
1106 {
1107 GMAC_DEV_ASSERT(Config->Gmac_paCtrlRxRingConfig[i].RingDesc != NULL_PTR);
1108 GMAC_DEV_ASSERT(Config->Gmac_paCtrlRxRingConfig[i].RingSize > 1U);
1109 GMAC_DEV_ASSERT(GMAC_BUFFDESCR_IS_ALIGNED(Config->Gmac_paCtrlRxRingConfig[i].RingDesc));
1110 GMAC_DEV_ASSERT((Config->Gmac_paCtrlRxRingConfig[i].Buffer == NULL_PTR) || GMAC_BUFF_IS_ALIGNED(Config->Gmac_paCtrlRxRingConfig[i].Buffer));
1111 GMAC_DEV_ASSERT(GMAC_BUFFLEN_IS_ALIGNED(Config->Gmac_paCtrlRxRingConfig[i].BufferLen));
1112 GMAC_DEV_ASSERT(GMAC_RXRINGLEN_IS_BLOCK_ALIGNED((uint32)Config->Gmac_paCtrlRxRingConfig[i].RingSize * Config->Gmac_paCtrlRxRingConfig[i].BufferLen));
1113
1114 PoolSize += ((uint32)Config->Gmac_paCtrlRxRingConfig[i].RingSize * Config->Gmac_paCtrlRxRingConfig[i].BufferLen);
1115 }
1116
1117 GMAC_DEV_ASSERT(PoolSize <= FEATURE_GMAC_MTL_RX_POOL_SIZE);
1118
1119 PoolSize = 0U;
1120
1121 for (i = 0U; i < Config->Gmac_pCtrlConfig->TxRingCount; ++i)
1122 {
1123 GMAC_DEV_ASSERT(Config->Gmac_paCtrlTxRingConfig[i].RingDesc != NULL_PTR);
1124 GMAC_DEV_ASSERT(Config->Gmac_paCtrlTxRingConfig[i].RingSize > 1U);
1125 GMAC_DEV_ASSERT(GMAC_BUFFDESCR_IS_ALIGNED(Config->Gmac_paCtrlTxRingConfig[i].RingDesc));
1126 GMAC_DEV_ASSERT((Config->Gmac_paCtrlTxRingConfig[i].Buffer == NULL_PTR) || GMAC_BUFF_IS_ALIGNED(Config->Gmac_paCtrlTxRingConfig[i].Buffer));
1127 GMAC_DEV_ASSERT(GMAC_BUFFLEN_IS_ALIGNED(Config->Gmac_paCtrlTxRingConfig[i].BufferLen));
1128 GMAC_DEV_ASSERT(GMAC_TXRINGLEN_IS_BLOCK_ALIGNED((uint32)Config->Gmac_paCtrlTxRingConfig[i].RingSize * Config->Gmac_paCtrlTxRingConfig[i].BufferLen));
1129
1130 PoolSize += ((uint32)Config->Gmac_paCtrlTxRingConfig[i].RingSize * Config->Gmac_paCtrlTxRingConfig[i].BufferLen);
1131 }
1132
1133 GMAC_DEV_ASSERT(PoolSize <= FEATURE_GMAC_MTL_TX_POOL_SIZE);
1134 #endif
1135
1136 Base = Gmac_apxBases[Instance];
1137
1138 if (Instance < 1U)
1139 {
1140 #if (STD_ON == GMAC_SET_USER_ACCESS_ALLOWED_AVAILABLE)
1141 /* Set the UAA bit in REG_PROT to make the Instance accessible in user mode */
1142 OsIf_Trusted_Call1param(Gmac_Ip_SetUserAccessAllowed, Base);
1143 #endif
1144 }
1145
1146 /* Initialize hardware module. */
1147 Status = Gmac_Ip_InitDMA(Instance, Config);
1148
1149 if (Status == GMAC_STATUS_SUCCESS)
1150 {
1151 #if (FEATURE_GMAC_ASP_ALL || FEATURE_GMAC_ASP_ECC)
1152 Gmac_Ip_InitSafetyEvents(Base, Config->Gmac_pCtrlConfig);
1153 #endif
1154 Gmac_Ip_InitMTL(Instance, Config);
1155 Gmac_Ip_SetMacAddr(Instance, Config->Gmac_pau8CtrlPhysAddr);
1156 Gmac_Ip_InitMAC(Base, Config);
1157 Gmac_Ip_InitStateStructure(Instance, Config);
1158 }
1159
1160 return Status;
1161 }
1162 /*FUNCTION**********************************************************************
1163 *
1164 * Function Name : Gmac_Ip_TxTimeAwareShaperInit
1165 * Description : Install duration time for transmit frame
1166 *
1167 *END**************************************************************************/
Gmac_Ip_TxTimeAwareShaperInit(uint8 Instance,const Gmac_CtrlConfigType * Config)1168 Gmac_Ip_StatusType Gmac_Ip_TxTimeAwareShaperInit(uint8 Instance,
1169 const Gmac_CtrlConfigType *Config
1170 )
1171 {
1172 uint8 ErrorCnt = 0U;
1173 uint16 GateListNum;
1174 uint32 WriteData;
1175 Gmac_Ip_StatusType Status;
1176
1177 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1178 GMAC_DEV_ASSERT(Config != NULL_PTR);
1179 GMAC_DEV_ASSERT(Config->Gmac_pCtrlTxTimeAwareShaper != NULL_PTR);
1180
1181 /*Check Preemption supported or not*/
1182 if ((uint16)0U != Config->Gmac_pCtrlTxTimeAwareShaper->ReleaseAdvanceTime)
1183 {
1184 Gmac_apxBases[Instance]->MAC_FPE_CTRL_STS = GMAC_MAC_FPE_CTRL_STS_EFPE_MASK;
1185
1186 Gmac_apxBases[Instance]->MTL_FPE_CTRL_STS = GMAC_MTL_FPE_CTRL_STS_PEC(Config->Gmac_pCtrlTxTimeAwareShaper->PreemptionClassic);
1187
1188 Gmac_apxBases[Instance]->MTL_FPE_ADVANCE = GMAC_MTL_FPE_ADVANCE_HADV(Config->Gmac_pCtrlTxTimeAwareShaper->HoldAdvanceTime) | GMAC_MTL_FPE_ADVANCE_RADV(Config->Gmac_pCtrlTxTimeAwareShaper->ReleaseAdvanceTime);
1189 }
1190
1191 for (GateListNum = 0U; GateListNum < Config->Gmac_pCtrlTxTimeAwareShaper->GateControlDepth; GateListNum++)
1192 {
1193 WriteData = ((uint32)Config->Gmac_pCtrlTxTimeAwareShaper->GateControlList[GateListNum].GateControl << 24U) | Config->Gmac_pCtrlTxTimeAwareShaper->GateControlList[GateListNum].TimeInterval;
1194 /* Write value to Gate Control List*/
1195 ErrorCnt += Gmac_Ip_WriteGateControlList(Instance, GateListNum, WriteData, (boolean)TRUE);
1196 }
1197
1198 /* Write value to BTR (upper Base Time register)*/
1199 ErrorCnt += Gmac_Ip_WriteGateControlList(Instance, GMAC_GCRA_UPPER_BTR, Config->Gmac_pCtrlTxTimeAwareShaper->BaseTimeSecond, (boolean)FALSE);
1200
1201 /* Write value to BTR (lower Base Time register)*/
1202 ErrorCnt += Gmac_Ip_WriteGateControlList(Instance, GMAC_GCRA_LOWER_BTR, Config->Gmac_pCtrlTxTimeAwareShaper->BaseTimeNanoSecond, (boolean)FALSE);
1203
1204 /* Write value to CTR (upper Cycle Time register)*/
1205 ErrorCnt += Gmac_Ip_WriteGateControlList(Instance, GMAC_GCRA_UPPER_CTR, Config->Gmac_pCtrlTxTimeAwareShaper->CycleTimeSecond, (boolean)FALSE);
1206
1207 /* Write value to CTR (lower Cycle Time register)*/
1208 ErrorCnt += Gmac_Ip_WriteGateControlList(Instance, GMAC_GCRA_LOWER_CTR, Config->Gmac_pCtrlTxTimeAwareShaper->CycleTimeNanoSecond, (boolean)FALSE);
1209
1210 /* Write value to TER (Time extension register)*/
1211 ErrorCnt += Gmac_Ip_WriteGateControlList(Instance, GMAC_GCRA_TER, Config->Gmac_pCtrlTxTimeAwareShaper->ExtendedTime, (boolean)FALSE);
1212
1213 /* Write value to LLR (List Length register)*/
1214 ErrorCnt += Gmac_Ip_WriteGateControlList(Instance, GMAC_GCRA_LLR, (uint32)Config->Gmac_pCtrlTxTimeAwareShaper->GateControlDepth, (boolean)FALSE);
1215
1216 Gmac_apxBases[Instance]->MTL_EST_CONTROL = GMAC_MTL_EST_CONTROL_SSWL_MASK | GMAC_MTL_EST_CONTROL_EEST_MASK;
1217
1218 /* Workaround for Errata ERR050705*/
1219 #if defined(ERR_IPV_GMAC_E050705)
1220 #if (STD_ON == ERR_IPV_GMAC_E050705)
1221 Gmac_apxBases[Instance]->MTL_EST_CONTROL |= GMAC_MTL_EST_CONTROL_DDBF(1U);
1222 #endif
1223 #endif
1224
1225 Status = ((ErrorCnt > 0U) ? ((Gmac_Ip_StatusType)GMAC_STATUS_TIMEOUT) : ((Gmac_Ip_StatusType)GMAC_STATUS_SUCCESS));
1226
1227 return Status;
1228 }
1229 /*FUNCTION**********************************************************************
1230 *
1231 * Function Name : Gmac_Ip_Deinit
1232 * Description : Deinitializes the GMAC module
1233 * implements Gmac_Ip_Deinit_Activity
1234 *END**************************************************************************/
Gmac_Ip_Deinit(uint8 Instance)1235 void Gmac_Ip_Deinit(uint8 Instance)
1236 {
1237 GMAC_Type *Base;
1238
1239 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1240
1241 Base = Gmac_apxBases[Instance];
1242
1243 /* Reset controller */
1244 Base->DMA_MODE |= GMAC_DMA_MODE_SWR_MASK;
1245
1246 if (Instance < 1U)
1247 {
1248 #if (STD_ON == GMAC_SET_USER_ACCESS_ALLOWED_AVAILABLE)
1249 /* Clear the UAA bit in REG_PROT to reset the elevation requirement */
1250 OsIf_Trusted_Call1param(Gmac_Ip_ClrUserAccessAllowed, Base);
1251 #endif
1252 }
1253
1254 /* Reset state variables */
1255 Gmac_apxState[Instance] = NULL_PTR;
1256 }
1257
1258 /*FUNCTION**********************************************************************
1259 *
1260 * Function Name : Gmac_Ip_GetPowerState
1261 * Description : Gets the current power state of the GMAC module
1262 *END**************************************************************************/
Gmac_Ip_GetPowerState(uint8 Instance)1263 Gmac_Ip_PowerStateType Gmac_Ip_GetPowerState(uint8 Instance)
1264 {
1265 const GMAC_Type *Base;
1266
1267 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1268
1269 Base = Gmac_apxBases[Instance];
1270 return GMAC_GetPowerState(Base);
1271 }
1272
1273 /*FUNCTION**********************************************************************
1274 *
1275 * Function Name : Gmac_Ip_SetPowerState
1276 * Description : Sets the power state of the GMAC module
1277 *END**************************************************************************/
Gmac_Ip_SetPowerState(uint8 Instance,Gmac_Ip_PowerStateType PowerState)1278 void Gmac_Ip_SetPowerState(uint8 Instance, Gmac_Ip_PowerStateType PowerState)
1279 {
1280 GMAC_Type *Base;
1281
1282 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1283
1284 Base = Gmac_apxBases[Instance];
1285 GMAC_SetPowerState(Base, PowerState);
1286 }
1287
1288 /*FUNCTION**********************************************************************
1289 *
1290 * Function Name : Gmac_Ip_EnableController
1291 * Description : Enables all Configured transmit and receive buffers and then enables the controller
1292 *END**************************************************************************/
Gmac_Ip_EnableController(uint8 Instance)1293 void Gmac_Ip_EnableController(uint8 Instance)
1294 {
1295 uint32 i;
1296
1297 /* Start all configured TxDMA channels */
1298 for (i = 0U; i < Gmac_apxState[Instance]->TxRingCount; i++)
1299 {
1300 Gmac_apxChBases[Instance][i]->DMA_TX_CONTROL |= GMAC_DMA_CH0_TX_CONTROL_ST_MASK;
1301 }
1302
1303 /* Start all configured RxDMA channels */
1304 for (i = 0U; i < Gmac_apxState[Instance]->RxRingCount; i++)
1305 {
1306 Gmac_apxChBases[Instance][i]->DMA_RX_CONTROL |= GMAC_DMA_CH0_RX_CONTROL_SR_MASK;
1307 }
1308
1309 /* Enable the MAC transmitter and receiver */
1310 Gmac_apxBases[Instance]->MAC_CONFIGURATION |= (GMAC_MAC_CONFIGURATION_TE_MASK | GMAC_MAC_CONFIGURATION_RE_MASK);
1311 }
1312
1313 /*FUNCTION**********************************************************************
1314 *
1315 * Function Name : Gmac_Ip_DisableController
1316 * Description : Disables the controller and resets all the configured transmit and receive buffers
1317 *END**************************************************************************/
Gmac_Ip_DisableController(uint8 Instance)1318 Gmac_Ip_StatusType Gmac_Ip_DisableController(uint8 Instance)
1319 {
1320 Gmac_Ip_StatusType Status;
1321 uint32 i;
1322
1323 /* Stop all configured TxDMA channels and flush the corresponding MTL queues */
1324 for (i = 0U; i < Gmac_apxState[Instance]->TxRingCount; i++)
1325 {
1326 /* Stop the TxDMA channel (This will set flag DMA_CHi_Status[TPS]) */
1327 Gmac_apxChBases[Instance][i]->DMA_TX_CONTROL &= ~GMAC_DMA_CH0_TX_CONTROL_ST_MASK;
1328
1329 /* Flush the corresponding MTL Tx Queue (Channels and queues are mapped 1:1) */
1330 Gmac_apxQueueBases[Instance][i]->MTL_TXQ_OPERATION_MODE |= GMAC_MTL_TXQ0_OPERATION_MODE_FTQ_MASK;
1331 }
1332
1333 /* Make sure all configured MTL queues are now empty */
1334 Status = Gmac_Ip_CheckMTLEmpty(Instance, Gmac_apxState[Instance]->TxRingCount, (boolean)TRUE);
1335
1336 if (GMAC_STATUS_SUCCESS == Status)
1337 {
1338 /* Disable the MAC transmitter and receiver */
1339 Gmac_apxBases[Instance]->MAC_CONFIGURATION &= ~(GMAC_MAC_CONFIGURATION_TE_MASK | GMAC_MAC_CONFIGURATION_RE_MASK);
1340
1341 /* Stop all configured RxDMA channels and flush the corresponding MTL queues */
1342 for (i = 0U; i < Gmac_apxState[Instance]->RxRingCount; i++)
1343 {
1344 /* Stop the RxDMA channel (This will set flag DMA_CHi_Status[RPS]) */
1345 Gmac_apxChBases[Instance][i]->DMA_RX_CONTROL &= ~GMAC_DMA_CH0_RX_CONTROL_SR_MASK;
1346
1347 /* Flush the corresponding MTL Rx Queue (Channels and queues are not necessarily mapped 1:1) */
1348 Gmac_apxChBases[Instance][i]->DMA_RX_CONTROL |= GMAC_DMA_CH0_RX_CONTROL_RPF_MASK;
1349 }
1350
1351 Status = Gmac_Ip_CheckMTLEmpty(Instance, Gmac_apxState[Instance]->RxRingCount, (boolean)FALSE);
1352
1353 if (GMAC_STATUS_SUCCESS == Status)
1354 {
1355 /* Restore all Tx buffer addresses, clear all pending Tx requests and unlock all Tx buffers */
1356 Gmac_Ip_RestoreTxDescr(Instance);
1357
1358 /* Restore all Rx buffer addreses and clear all pending Rx requests */
1359 Gmac_Ip_RestoreRxDescr(Instance);
1360 }
1361 }
1362
1363 return Status;
1364 }
1365
1366 /*FUNCTION**********************************************************************
1367 *
1368 * Function Name : Gmac_Ip_SetSpeed
1369 * Description : Sets the speed of the MII interface
1370 * implements Gmac_Ip_SetSpeed_Activity
1371 *END**************************************************************************/
Gmac_Ip_SetSpeed(uint8 Instance,Gmac_Ip_SpeedType Speed)1372 void Gmac_Ip_SetSpeed(uint8 Instance, Gmac_Ip_SpeedType Speed)
1373 {
1374 GMAC_Type *Base;
1375
1376 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1377
1378 Base = Gmac_apxBases[Instance];
1379 GMAC_SetSpeed(Base, Speed);
1380 }
1381
1382 /*FUNCTION**********************************************************************
1383 *
1384 * Function Name : Gmac_Ip_GetTxBuff
1385 * Description : Provides a transmit buffer to be used by the application for transmission.
1386 *END**************************************************************************/
Gmac_Ip_GetTxBuff(uint8 Instance,uint8 Ring,Gmac_Ip_BufferType * Buff,uint16 * BuffId)1387 Gmac_Ip_StatusType Gmac_Ip_GetTxBuff(uint8 Instance,
1388 uint8 Ring,
1389 Gmac_Ip_BufferType * Buff,
1390 uint16 * BuffId)
1391 {
1392 Gmac_Ip_BufferDescriptorType *Bd;
1393 const Gmac_Ip_ChannelType *ChBase;
1394 Gmac_Ip_BufferDescriptorType * ListBd;
1395 Gmac_Ip_StatusType Status = GMAC_STATUS_SUCCESS;
1396
1397 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1398 GMAC_DEV_ASSERT(Gmac_apxState[Instance] != NULL_PTR);
1399 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->TxRingCount);
1400 GMAC_DEV_ASSERT(Buff != NULL_PTR);
1401
1402 ChBase = Gmac_apxChBases[Instance][Ring];
1403
1404 Bd = Gmac_apxState[Instance]->TxCurrentDesc[Ring];
1405 ListBd = (Gmac_Ip_BufferDescriptorType *)ChBase->DMA_TXDESC_LIST_ADDRESS;
1406
1407 if (((Bd->Des3 & GMAC_TDES3_OWN_MASK) != 0U) ||
1408 ((Bd->Info1 & GMAC_INFO1_LOCKED_MASK) != 0U))
1409 {
1410 Status = GMAC_STATUS_TX_BUFF_BUSY;
1411 }
1412 else
1413 {
1414 if (Buff->Length > (Bd->Info1 & GMAC_INFO1_LENGTH_MASK))
1415 {
1416 Status = GMAC_STATUS_TX_BUFF_OVERFLOW;
1417 Buff->Length = (uint16)(Bd->Info1 & GMAC_INFO1_LENGTH_MASK);
1418 }
1419 else
1420 {
1421 #if (GMAC_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON)
1422 if (!Gmac_Ip_InstHasExternalTxBufferManagement[Instance])
1423 {
1424 #endif
1425 /* Relies on function "Gmac_Ip_GetTransmitStatus" to restore the Buffer address pointer */
1426 Buff->Data = (uint8 *)Bd->Des0;
1427 Buff->Length = (uint16)(Bd->Info1 & GMAC_INFO1_LENGTH_MASK);
1428 #if (GMAC_IP_HAS_EXTERNAL_TX_BUFFERS == STD_ON)
1429 }
1430 #endif
1431 Bd->Info1 |= GMAC_INFO1_LOCKED_MASK;
1432
1433 if (BuffId != NULL_PTR)
1434 {
1435 *BuffId = (uint16)((sint32)(Bd - ListBd));
1436 }
1437
1438 Gmac_apxState[Instance]->TxCurrentDesc[Ring]++;
1439 if ((uint32)Gmac_apxState[Instance]->TxCurrentDesc[Ring] >=
1440 (uint32)&ListBd[ChBase->DMA_TXDESC_RING_LENGTH + 1UL])
1441 {
1442 Gmac_apxState[Instance]->TxCurrentDesc[Ring] = ListBd;
1443 }
1444 }
1445 }
1446
1447 return Status;
1448 }
1449
1450 /*FUNCTION**********************************************************************
1451 *
1452 * Function Name : Gmac_Ip_GetTxMultiBuff
1453 * implements
1454 *END**************************************************************************/
Gmac_Ip_GetTxMultiBuff(uint8 Instance,uint8 ring,uint16 NumBuffers,const uint16 BufferLength[],uint16 * buffId)1455 Gmac_Ip_StatusType Gmac_Ip_GetTxMultiBuff(uint8 Instance,
1456 uint8 ring,
1457 uint16 NumBuffers,
1458 const uint16 BufferLength[],
1459 uint16 *buffId)
1460 {
1461 Gmac_Ip_BufferDescriptorType *Bd;
1462 const Gmac_Ip_ChannelType *ChBase;
1463 Gmac_Ip_BufferDescriptorType * ListBd;
1464 Gmac_Ip_StatusType Status = GMAC_STATUS_SUCCESS;
1465 uint16 FreeBuffers = 0U;
1466
1467 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1468 GMAC_DEV_ASSERT(Gmac_apxState[Instance] != NULL_PTR);
1469 GMAC_DEV_ASSERT(buffId != NULL_PTR);
1470 GMAC_DEV_ASSERT(ring < Gmac_apxState[Instance]->TxRingCount);
1471
1472 ChBase = Gmac_apxChBases[Instance][ring];
1473 Bd = Gmac_apxState[Instance]->TxCurrentDesc[ring];
1474 ListBd = (Gmac_Ip_BufferDescriptorType *)ChBase->DMA_TXDESC_LIST_ADDRESS;
1475
1476 while ((FreeBuffers < NumBuffers) && (GMAC_STATUS_SUCCESS == Status))
1477 {
1478 if (((Bd->Des3 & GMAC_TDES3_OWN_MASK) != 0U) ||
1479 ((Bd->Info1 & GMAC_INFO1_LOCKED_MASK) != 0U))
1480 {
1481 Status = GMAC_STATUS_TX_BUFF_BUSY;
1482 }
1483 else
1484 {
1485 if (BufferLength[FreeBuffers] > (Bd->Info1 & GMAC_INFO1_LENGTH_MASK))
1486 {
1487 Status = GMAC_STATUS_TX_BUFF_OVERFLOW;
1488 }
1489 else
1490 {
1491 FreeBuffers++;
1492 Bd++;
1493 if ((uint32)Bd >= (uint32)&ListBd[ChBase->DMA_TXDESC_RING_LENGTH + 1UL])
1494 {
1495 Bd = ListBd;
1496 }
1497 }
1498 }
1499 }
1500
1501 if (FreeBuffers == NumBuffers)
1502 {
1503 *buffId = (uint16)((sint32)(Gmac_apxState[Instance]->TxCurrentDesc[ring] - ListBd));
1504 }
1505
1506 return Status;
1507 }
1508
1509 /*FUNCTION**********************************************************************
1510 *
1511 * Function Name : Gmac_Ip_SendFrame
1512 * Description : Sends an Ethernet frame
1513 * implements Gmac_Ip_SendFrame_Activity
1514 *END**************************************************************************/
Gmac_Ip_SendFrame(uint8 Instance,uint8 Ring,const Gmac_Ip_BufferType * Buff,const Gmac_Ip_TxOptionsType * Options)1515 Gmac_Ip_StatusType Gmac_Ip_SendFrame(uint8 Instance,
1516 uint8 Ring,
1517 const Gmac_Ip_BufferType * Buff,
1518 const Gmac_Ip_TxOptionsType * Options)
1519 {
1520 Gmac_Ip_ChannelType *Base;
1521 Gmac_Ip_BufferDescriptorType *Bd;
1522 Gmac_Ip_BufferDescriptorType *ListBd;
1523 Gmac_Ip_StatusType Status = GMAC_STATUS_SUCCESS;
1524 #if (STD_ON == GMAC_HAS_CACHE_MANAGEMENT)
1525 Std_ReturnType CacheStatus = E_NOT_OK;
1526 #endif
1527 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1528 GMAC_DEV_ASSERT(Gmac_apxState[Instance] != NULL_PTR);
1529 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->TxRingCount);
1530 GMAC_DEV_ASSERT(Buff != NULL_PTR);
1531 GMAC_DEV_ASSERT(Buff->Data != NULL_PTR);
1532 GMAC_DEV_ASSERT(Buff->Length > 0U);
1533
1534 Base = Gmac_apxChBases[Instance][Ring];
1535
1536 Bd = (Gmac_Ip_BufferDescriptorType *)Base->DMA_TXDESC_TAIL_POINTER;
1537 ListBd = (Gmac_Ip_BufferDescriptorType *)Base->DMA_TXDESC_LIST_ADDRESS;
1538
1539 if ((Bd->Des3 & GMAC_TDES3_OWN_MASK) != 0U)
1540 {
1541 Status = GMAC_STATUS_TX_QUEUE_FULL;
1542 }
1543 else
1544 {
1545 Bd->Des0 = (uint32)Buff->Data;
1546 Bd->Des2 = (uint32)Buff->Length | GMAC_TDES2_IOC_MASK | GMAC_TDES2_TTSE_MASK;
1547 Bd->Info0 = (uint32)Buff->Data;
1548
1549
1550 Bd->Des3 = GMAC_TDES3_FD_MASK | GMAC_TDES3_LD_MASK |
1551 (uint32)Buff->Length | GMAC_TDES3_OWN_MASK;
1552
1553 if (Options != NULL_PTR)
1554 {
1555 if (Options->NoInt)
1556 {
1557 Bd->Des2 &= ~GMAC_TDES2_IOC_MASK;
1558 }
1559 Bd->Des3 |= GMAC_TDES3_CPC(Options->CrcPadIns) |
1560 GMAC_TDES3_CIC(Options->ChecksumIns);
1561 }
1562
1563 Bd++;
1564
1565 /* Issued DMB Before */
1566 MCAL_DATA_SYNC_BARRIER();
1567
1568 #if (STD_ON == GMAC_HAS_CACHE_MANAGEMENT)
1569 /* Before sending, Flush + Invalidate cache in order write back the contents to main memory and mark the cache lines as invalid so that
1570 the future reads will be done from the memory. */
1571 CacheStatus = Cache_Ip_CleanByAddr(CacheType, CACHE_IP_DATA, TRUE,(uint32) Buff->Data, Buff->Length);
1572
1573 if (E_NOT_OK == CacheStatus)
1574 {
1575 Status = GMAC_STATUS_CACHE_ERROR;
1576 }
1577 else
1578 {
1579 #endif
1580 Base->DMA_TXDESC_TAIL_POINTER = (uint32)(((uint32)Bd >= (uint32)&ListBd[Base->DMA_TXDESC_RING_LENGTH + 1UL])? ListBd : Bd);
1581 #if (STD_ON == GMAC_HAS_CACHE_MANAGEMENT)
1582 }/* E_NOT_OK == CacheStatus */
1583 #endif
1584 }
1585 return Status;
1586 }
1587
1588 /*FUNCTION**********************************************************************
1589 *
1590 * Function Name : Gmac_Ip_SendMultiBufferFrame
1591 * Description : Sends an Ethernet frame composed out of multiple buffers (not necessarily contiguous)
1592 * implements
1593 *END**************************************************************************/
Gmac_Ip_SendMultiBufferFrame(uint8 Instance,uint8 Ring,const Gmac_Ip_BufferType Buffers[],const Gmac_Ip_TxOptionsType * Options,uint32 NumBuffers)1594 Gmac_Ip_StatusType Gmac_Ip_SendMultiBufferFrame(uint8 Instance,
1595 uint8 Ring,
1596 const Gmac_Ip_BufferType Buffers[],
1597 const Gmac_Ip_TxOptionsType *Options,
1598 uint32 NumBuffers)
1599 {
1600 Gmac_Ip_ChannelType *Base;
1601 Gmac_Ip_BufferDescriptorType *Bd;
1602 Gmac_Ip_BufferDescriptorType *ListBd;
1603 Gmac_Ip_BufferDescriptorType *FirstBd, *LastBd;
1604 Gmac_Ip_StatusType Status = GMAC_STATUS_SUCCESS;
1605 uint32 i = 0U;
1606 uint32 RingLength = 0U;
1607 #if (STD_ON == GMAC_HAS_CACHE_MANAGEMENT)
1608 Std_ReturnType CacheStatus = E_NOT_OK;
1609 #endif
1610 boolean DeAllocate = FALSE;
1611
1612 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1613 GMAC_DEV_ASSERT(Gmac_apxState[Instance] != NULL_PTR);
1614 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->TxRingCount);
1615 GMAC_DEV_ASSERT(Buffers != NULL_PTR);
1616 GMAC_DEV_ASSERT(Options != NULL_PTR);
1617 GMAC_DEV_ASSERT(NumBuffers > 0U);
1618
1619 Base = Gmac_apxChBases[Instance][Ring];
1620 Bd = (Gmac_Ip_BufferDescriptorType *)Base->DMA_TXDESC_TAIL_POINTER;
1621 ListBd = (Gmac_Ip_BufferDescriptorType *)Base->DMA_TXDESC_LIST_ADDRESS;
1622 RingLength = Base->DMA_TXDESC_RING_LENGTH;
1623
1624 GMAC_DEV_ASSERT(NumBuffers <= RingLength);
1625
1626
1627 FirstBd = Bd;
1628 LastBd = Bd;
1629 while (i < NumBuffers)
1630 {
1631 GMAC_DEV_ASSERT(Buffers[i].Data != NULL_PTR);
1632 GMAC_DEV_ASSERT(Buffers[i].Length > 0U);
1633
1634 if ((Bd->Des3 & GMAC_TDES3_OWN_MASK) != 0U)
1635 {
1636 Status = GMAC_STATUS_TX_QUEUE_FULL;
1637 break;
1638 }
1639 else
1640 {
1641 Bd->Des0 = (uint32)Buffers[i].Data;
1642 Bd->Des2 = (uint32)Buffers[i].Length;
1643 Bd->Info0 = (uint32)Buffers[i].Data;
1644 Bd->Des3 = (uint32)Buffers[i].Length | ((Bd == FirstBd)? 0U : GMAC_TDES3_OWN_MASK);
1645
1646 LastBd = Bd;
1647 ++Bd;
1648 }
1649
1650 Bd = ((uint32)Bd >= (uint32)&ListBd[RingLength + 1UL])? ListBd : Bd;
1651
1652 ++i;
1653 }
1654
1655 if (i == NumBuffers)
1656 {
1657 LastBd->Des2 |= GMAC_TDES2_TTSE_MASK | ((Options->NoInt == TRUE)? 0U : GMAC_TDES2_IOC_MASK);
1658 LastBd->Des3 |= GMAC_TDES3_LD_MASK;
1659 FirstBd->Des3 |= GMAC_TDES3_FD_MASK |
1660 GMAC_TDES3_OWN_MASK |
1661 GMAC_TDES3_CPC(Options->CrcPadIns) |
1662 GMAC_TDES3_CIC(Options->ChecksumIns);
1663
1664 /* Issued DMB Before */
1665 MCAL_DATA_SYNC_BARRIER();
1666 #if (STD_ON == GMAC_HAS_CACHE_MANAGEMENT)
1667 /* Before sending, Flush + Invalidate cache in order write back the contents to main memory and mark the cache lines as invalid so that
1668 the future reads will be done from the memory. */
1669 for (i = 0U; i < NumBuffers; i++)
1670 {
1671 CacheStatus = Cache_Ip_CleanByAddr(CacheType, CACHE_IP_DATA, TRUE,(uint32)Buffers[i].Data, (uint32)Buffers[i].Length);
1672 if (E_NOT_OK == CacheStatus)
1673 {
1674 DeAllocate = TRUE;
1675 break;
1676 }
1677
1678 }
1679
1680 if (E_NOT_OK == CacheStatus)
1681 {
1682 Status = GMAC_STATUS_CACHE_ERROR;
1683 }
1684 else
1685 {
1686 #endif
1687 Base->DMA_TXDESC_TAIL_POINTER = (uint32)Bd;
1688 #if (STD_ON == GMAC_HAS_CACHE_MANAGEMENT)
1689 }
1690 #endif
1691 }
1692 else
1693 {
1694 DeAllocate = TRUE;
1695 }
1696
1697 /* This operation can happen when there are no enough descriptors for all the buffers or when cache operation failed */
1698 if (DeAllocate)
1699 {
1700 /* Clear the previously set OWN bits when the ring is full. Otherwise, future calls
1701 * on this ring will always (erroneously) believe that it is full. */
1702 while (Bd != FirstBd)
1703 {
1704 --Bd;
1705
1706 Bd = ((uint32)Bd < (uint32)ListBd)? &ListBd[RingLength] : Bd;
1707
1708 Bd->Des3 &= ~GMAC_TDES3_OWN_MASK;
1709 }
1710 }
1711
1712 return Status;
1713 }
1714
1715 /*FUNCTION**********************************************************************
1716 *
1717 * Function Name : Gmac_Ip_ReadFrame
1718 * Description : Reads a received Ethernet frame
1719 * implements Gmac_Ip_ReadFrame_Activity
1720 *END**************************************************************************/
Gmac_Ip_ReadFrame(uint8 Instance,uint8 Ring,Gmac_Ip_BufferType * Buff,Gmac_Ip_RxInfoType * Info)1721 Gmac_Ip_StatusType Gmac_Ip_ReadFrame(uint8 Instance,
1722 uint8 Ring,
1723 Gmac_Ip_BufferType * Buff,
1724 Gmac_Ip_RxInfoType * Info)
1725 {
1726 const Gmac_Ip_ChannelType *ChBase;
1727 Gmac_Ip_BufferDescriptorType *Bd;
1728 Gmac_Ip_BufferDescriptorType *ListBd;
1729 Gmac_Ip_StatusType Status = GMAC_STATUS_SUCCESS;
1730 #if (STD_ON == GMAC_HAS_CACHE_MANAGEMENT)
1731 Std_ReturnType CacheStatus = E_NOT_OK;
1732 #endif
1733
1734 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1735 GMAC_DEV_ASSERT(Gmac_apxState[Instance] != NULL_PTR);
1736 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->RxRingCount);
1737 GMAC_DEV_ASSERT(Buff != NULL_PTR);
1738
1739 ChBase = Gmac_apxChBases[Instance][Ring];
1740
1741 Bd = Gmac_apxState[Instance]->RxCurrentDesc[Ring];
1742 ListBd = (Gmac_Ip_BufferDescriptorType *)ChBase->DMA_RXDESC_LIST_ADDRESS;
1743
1744 if (((Bd->Des3 & GMAC_RDES3_OWN_MASK) != 0U) ||
1745 ((Bd->Info1 & GMAC_INFO1_CONSUMED_MASK) != 0U) ||
1746 (Bd->Info0 == 0U))
1747 {
1748 Status = GMAC_STATUS_RX_QUEUE_EMPTY;
1749 }
1750 else
1751 {
1752
1753 #if (STD_ON == GMAC_HAS_CACHE_MANAGEMENT)
1754 /* Mark the cache lines where external data buffers are placed as invalid in order to get the new data from data buffers from memory. */
1755 CacheStatus = Cache_Ip_InvalidateByAddr(CacheType, CACHE_IP_DATA, (uint32)Bd->Info0, Bd->Info1 & GMAC_INFO1_LENGTH_MASK);
1756 if (E_NOT_OK == CacheStatus)
1757 {
1758 Status = GMAC_STATUS_CACHE_ERROR;
1759 }
1760 else
1761 {
1762 #endif
1763 Buff->Data = (uint8 *)Bd->Info0;
1764 Buff->Length = (uint16)(Bd->Des3 & GMAC_RDES3_PL_MASK);
1765 #ifdef MCAL_ENABLE_FAULT_INJECTION
1766 MCAL_FAULT_INJECTION_POINT(ETH_CHANGE_BUffER_LENGTH_FIP_1);
1767 #endif
1768
1769 /* According to requirement CPR_RTD_00284.eth */
1770 if (Buff->Length > (uint16)(Bd->Info1 & GMAC_INFO1_LENGTH_MASK))
1771 {
1772 Buff->Length = (uint16)(Bd->Info1 & GMAC_INFO1_LENGTH_MASK);
1773 }
1774
1775 Bd->Info0 = 0U;
1776 Bd->Info1 |= GMAC_INFO1_CONSUMED_MASK;
1777
1778 if (Info != NULL_PTR)
1779 {
1780 Info->ErrMask = Bd->Des3 & GMAC_RX_STAT_ERR_MASK;
1781 Info->PktLen = Buff->Length;
1782
1783 if ((Bd->Des3 & GMAC_RDES3_RS1V_MASK) != 0U)
1784 {
1785 Info->IpHeaderErr = ((Bd->Des1 & GMAC_RDES1_IPHE_MASK) != 0U);
1786 Info->IpPayloadErr = ((Bd->Des1 & GMAC_RDES1_IPCE_MASK) != 0U);
1787 Info->Ipv4 = ((Bd->Des1 & GMAC_RDES1_IPV4_MASK) != 0U);
1788 Info->Ipv6 = ((Bd->Des1 & GMAC_RDES1_IPV6_MASK) != 0U);
1789 Info->PayloadType = Gmac_Ip_GetPayloadType(Bd->Des1 & GMAC_RDES1_PT_MASK);
1790 }
1791
1792 if ((Bd->Des3 & GMAC_RDES3_RS0V_MASK) != 0U)
1793 {
1794 Info->OuterVlanTag = (uint16)(Bd->Des0 & GMAC_RDES0_OVT_MASK);
1795 Info->InnerVlanTag = (uint16)((Bd->Des0 & GMAC_RDES0_IVT_MASK) >>
1796 GMAC_RDES0_IVT_SHIFT);
1797 }
1798 else
1799 {
1800 Info->OuterVlanTag = 0U;
1801 Info->InnerVlanTag = 0U;
1802 }
1803
1804 Gmac_Ip_ReadTimeStampInfo(Instance, Ring, Info);
1805 }
1806
1807 Gmac_apxState[Instance]->RxCurrentDesc[Ring]++;
1808 if ((uint32)Gmac_apxState[Instance]->RxCurrentDesc[Ring] >=
1809 (uint32)&ListBd[ChBase->DMA_RXDESC_RING_LENGTH + 1UL])
1810 {
1811 Gmac_apxState[Instance]->RxCurrentDesc[Ring] = ListBd;
1812 }
1813 #if (STD_ON == GMAC_HAS_CACHE_MANAGEMENT)
1814 }
1815 #endif
1816 }
1817 return Status;
1818 }
1819
1820 /*FUNCTION**********************************************************************
1821 *
1822 * Function Name : Gmac_Ip_SetRxExternalBuffer
1823 * Description : Provides a receive Buffer to be used by the driver for external buffer.
1824 * implements Gmac_Ip_SetRxExternalBuffer
1825 *END**************************************************************************/
Gmac_Ip_SetRxExternalBuffer(uint8 Instance,uint8 Ring,const Gmac_Ip_BufferType * Buff)1826 void Gmac_Ip_SetRxExternalBuffer(uint8 Instance,
1827 uint8 Ring,
1828 const Gmac_Ip_BufferType * Buff)
1829 {
1830 Gmac_Ip_ChannelType *Base;
1831 Gmac_Ip_BufferDescriptorType *Bd;
1832 Gmac_Ip_BufferDescriptorType *CtxtBd;
1833 Gmac_Ip_BufferDescriptorType *ListBd;
1834 uint32 RingLength;
1835
1836 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1837 GMAC_DEV_ASSERT(Gmac_apxState[Instance] != NULL_PTR);
1838 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->RxRingCount);
1839 GMAC_DEV_ASSERT(Buff != NULL_PTR);
1840 GMAC_DEV_ASSERT(Buff->Data != NULL_PTR);
1841
1842 Base = Gmac_apxChBases[Instance][Ring];
1843
1844 Bd = Gmac_apxState[Instance]->RxAllocDesc[Ring];
1845 ListBd = (Gmac_Ip_BufferDescriptorType *)Base->DMA_RXDESC_LIST_ADDRESS;
1846 RingLength = Base->DMA_RXDESC_RING_LENGTH + 1UL;
1847 if ((Bd->Des1 & GMAC_RDES1_TSA_MASK) != 0U)
1848 {
1849 CtxtBd = ((uint32)&Bd[1U] >= (uint32)&ListBd[RingLength])? ListBd : &Bd[1U];
1850
1851 if (Gmac_Ip_RestoreRxCtxtDescr(CtxtBd) == TRUE)
1852 {
1853 Gmac_apxState[Instance]->RxAllocDesc[Ring] = CtxtBd;
1854 }
1855 }
1856 Bd->Des0 = (uint32)Buff->Data;
1857 Bd->Des1 = 0U;
1858 Bd->Des2 = 0U;
1859 Bd->Info0 = (uint32)Buff->Data;
1860 Bd->Info1 = (uint32)((uint32)Buff->Length & GMAC_INFO1_LENGTH_MASK);
1861 Bd->Des3 = GMAC_RDES3_OWN_MASK | GMAC_RDES3_INTE_MASK | GMAC_RDES3_BUF1V_MASK;
1862
1863 Gmac_apxState[Instance]->RxAllocDesc[Ring]++;
1864
1865 if ((uint32)Gmac_apxState[Instance]->RxAllocDesc[Ring] >= (uint32)&ListBd[RingLength])
1866 {
1867 Gmac_apxState[Instance]->RxAllocDesc[Ring] = ListBd;
1868 }
1869
1870
1871 }
1872 /*FUNCTION**********************************************************************
1873 *
1874 * Function Name : Gmac_Ip_ProvideRxBuff
1875 * Description : Provides a receive Buffer to be used by the driver for reception.
1876 * implements Gmac_Ip_ProvideRxBuff_Activity
1877 *END**************************************************************************/
Gmac_Ip_ProvideRxBuff(uint8 Instance,uint8 Ring,const Gmac_Ip_BufferType * Buff)1878 void Gmac_Ip_ProvideRxBuff(uint8 Instance,
1879 uint8 Ring,
1880 const Gmac_Ip_BufferType * Buff)
1881 {
1882 Gmac_Ip_ChannelType *Base;
1883 Gmac_Ip_BufferDescriptorType *Bd;
1884 Gmac_Ip_BufferDescriptorType *CtxtBd;
1885 Gmac_Ip_BufferDescriptorType *ListBd;
1886 uint32 TailPtr;
1887 uint32 RingLength;
1888
1889 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1890 GMAC_DEV_ASSERT(Gmac_apxState[Instance] != NULL_PTR);
1891 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->RxRingCount);
1892 GMAC_DEV_ASSERT(Buff != NULL_PTR);
1893 GMAC_DEV_ASSERT(Buff->Data != NULL_PTR);
1894
1895 Base = Gmac_apxChBases[Instance][Ring];
1896
1897 Bd = Gmac_apxState[Instance]->RxAllocDesc[Ring];
1898 ListBd = (Gmac_Ip_BufferDescriptorType *)Base->DMA_RXDESC_LIST_ADDRESS;
1899 TailPtr = Base->DMA_RXDESC_TAIL_POINTER;
1900 RingLength = Base->DMA_RXDESC_RING_LENGTH + 1UL;
1901
1902 GMAC_DEV_ASSERT((Bd->Des3 & GMAC_RDES3_OWN_MASK) == 0U);
1903
1904 if ((Bd->Des1 & GMAC_RDES1_TSA_MASK) != 0U)
1905 {
1906 CtxtBd = ((uint32)&Bd[1U] >= (uint32)&ListBd[RingLength])? ListBd : &Bd[1U];
1907
1908 if (Gmac_Ip_RestoreRxCtxtDescr(CtxtBd) == TRUE)
1909 {
1910 Gmac_apxState[Instance]->RxAllocDesc[Ring] = CtxtBd;
1911 }
1912 }
1913
1914 Bd->Des0 = (uint32)Buff->Data;
1915 Bd->Des1 = 0U;
1916 Bd->Des2 = 0U;
1917 Bd->Info0 = (uint32)Buff->Data;
1918 Bd->Info1 &= ~GMAC_INFO1_CONSUMED_MASK;
1919 Bd->Des3 = GMAC_RDES3_OWN_MASK | GMAC_RDES3_INTE_MASK | GMAC_RDES3_BUF1V_MASK;
1920
1921 Gmac_apxState[Instance]->RxAllocDesc[Ring]++;
1922 if ((uint32)Gmac_apxState[Instance]->RxAllocDesc[Ring] >= (uint32)&ListBd[RingLength])
1923 {
1924 Gmac_apxState[Instance]->RxAllocDesc[Ring] = ListBd;
1925 }
1926
1927 MCAL_DATA_SYNC_BARRIER();
1928
1929 Base->DMA_RXDESC_TAIL_POINTER = TailPtr;
1930 }
1931
1932 /*FUNCTION**********************************************************************
1933 *
1934 * Function Name : Gmac_Ip_IsFrameAvailable
1935 * Description : Checks if there are more frames available in the given queue
1936 *END**************************************************************************/
Gmac_Ip_IsFrameAvailable(uint8 Instance,uint8 Ring)1937 boolean Gmac_Ip_IsFrameAvailable(uint8 Instance,
1938 uint8 Ring)
1939 {
1940 const Gmac_Ip_BufferDescriptorType *Bd;
1941 boolean IsFrameAvailable = FALSE;
1942
1943 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1944 GMAC_DEV_ASSERT(Gmac_apxState[Instance] != NULL_PTR);
1945 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->RxRingCount);
1946
1947 Bd = Gmac_apxState[Instance]->RxCurrentDesc[Ring];
1948
1949 if (((Bd->Des3 & GMAC_RDES3_OWN_MASK) == 0U) &&
1950 ((Bd->Info1 & GMAC_INFO1_CONSUMED_MASK) == 0U) &&
1951 (Bd->Info0 != 0U))
1952 {
1953 IsFrameAvailable = TRUE;
1954 }
1955
1956 return IsFrameAvailable;
1957 }
1958
1959 /*FUNCTION**********************************************************************
1960 *
1961 * Function Name : Gmac_Ip_GetTransmitStatus
1962 * Description : Checks if the transmission of a Buffer is complete.
1963 * implements Gmac_Ip_GetTransmitStatus_Activity
1964 *END**************************************************************************/
Gmac_Ip_GetTransmitStatus(uint8 Instance,uint8 Ring,const Gmac_Ip_BufferType * Buff,Gmac_Ip_TxInfoType * Info)1965 Gmac_Ip_StatusType Gmac_Ip_GetTransmitStatus(uint8 Instance,
1966 uint8 Ring,
1967 const Gmac_Ip_BufferType * Buff,
1968 Gmac_Ip_TxInfoType * Info)
1969 {
1970 const GMAC_Type *Base;
1971 const Gmac_Ip_ChannelType *ChBase;
1972 Gmac_Ip_BufferDescriptorType *ListBd;
1973 Gmac_Ip_BufferDescriptorType *Bd;
1974 const Gmac_Ip_BufferDescriptorType *StartBd;
1975 Gmac_Ip_StatusType Status = GMAC_STATUS_BUFF_NOT_FOUND;
1976 uint32 i;
1977 uint32 RingLength;
1978
1979 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
1980 GMAC_DEV_ASSERT(Gmac_apxState[Instance] != NULL_PTR);
1981 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->TxRingCount);
1982 GMAC_DEV_ASSERT(Buff != NULL_PTR);
1983
1984 Base = Gmac_apxBases[Instance];
1985 ChBase = Gmac_apxChBases[Instance][Ring];
1986
1987 ListBd = (Gmac_Ip_BufferDescriptorType *)ChBase->DMA_TXDESC_LIST_ADDRESS;
1988 Bd = ListBd;
1989 RingLength = ChBase->DMA_TXDESC_RING_LENGTH;
1990 /* Add fault label for testing */
1991 #ifdef MCAL_ENABLE_FAULT_INJECTION
1992 MCAL_FAULT_INJECTION_POINT(ETH_READ_BUffER_ADDRESS_FIP);
1993 #endif
1994 /* Search for the Buffer descriptor associated with the given Buffer. */
1995 for (i = 0; i <= RingLength; i++)
1996 {
1997 if (Bd->Info0 == ((uint32)Buff->Data))
1998 {
1999 StartBd = Bd; /* Prevent endless loop */
2000 while (((Bd->Des3 & GMAC_TDES3_LD_MASK) == 0U) && ((Bd->Des3 & GMAC_TDES3_OWN_MASK) == 0U))
2001 {
2002 /* Restore Buffer address pointer and clear intermediary descriptor */
2003 /* The writes to Des0 and Info1 are relevant only for internal buffers */
2004 Bd->Des0 = Bd->Info0;
2005 Bd->Info0 = 0U;
2006 Bd->Info1 &= ~GMAC_INFO1_LOCKED_MASK;
2007
2008 ++Bd;
2009 if ((uint32)Bd >= (uint32)&ListBd[RingLength + 1UL])
2010 {
2011 Bd = ListBd;
2012 }
2013
2014 /* This guarantees that the loop will be terminated even if the HW malfunctions.
2015 * In normal working conditions, this check will never be true. */
2016 if (Bd == StartBd) { break; }
2017 }
2018
2019 /* Check if the last Buffer descriptor is still in use. */
2020 if (((Bd->Des3 & GMAC_TDES3_LD_MASK) != 0U) && ((Bd->Des3 & GMAC_TDES3_OWN_MASK) == 0U))
2021 {
2022 Status = GMAC_STATUS_SUCCESS;
2023 if (Info != NULL_PTR)
2024 {
2025 Info->ErrMask = Bd->Des3 & GMAC_TX_STAT_ERR_MASK;
2026 Gmac_Ip_GetTimestamp(Base, Bd, &Info->Timestamp);
2027 }
2028
2029 /* Restore Buffer address pointer and clear the last descriptor after the Status was read. */
2030 /* The writes to Des0 and Info1 are relevant only for internal buffers */
2031 Bd->Des0 = Bd->Info0;
2032 Bd->Info0 = 0U;
2033 Bd->Info1 &= ~GMAC_INFO1_LOCKED_MASK;
2034 }
2035 else
2036 {
2037 Status = GMAC_STATUS_BUSY;
2038 }
2039
2040 break;
2041 }
2042 Bd++;
2043 }
2044
2045 return Status;
2046 }
2047
2048 /*FUNCTION**********************************************************************
2049 *
2050 * Function Name : Gmac_Ip_GetCounter
2051 * Description : Gets statistics from the specified counter.
2052 * implements Gmac_Ip_GetCounter_Activity
2053 *END**************************************************************************/
Gmac_Ip_GetCounter(uint8 Instance,Gmac_Ip_CounterType Counter)2054 uint32 Gmac_Ip_GetCounter(uint8 Instance,
2055 Gmac_Ip_CounterType Counter)
2056 {
2057 const GMAC_Type *Base;
2058 volatile uint32 CounterAddr;
2059 volatile uint32 (*Count_Reg)[FEATURE_GMAC_NUM_COUNTER_REG];
2060
2061 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2062
2063 Base = Gmac_apxBases[Instance];
2064 CounterAddr = (uint32)(&Base->TX_OCTET_COUNT_GOOD_BAD);
2065 Count_Reg = (volatile uint32 (*)[FEATURE_GMAC_NUM_COUNTER_REG])CounterAddr;
2066
2067 return (*Count_Reg)[Counter];
2068 }
2069
2070 /*FUNCTION**********************************************************************
2071 *
2072 * Function Name : Gmac_Ip_EnableMDIO
2073 * Description : Enables the MDIO interface
2074 * implements Gmac_Ip_EnableMDIO_Activity
2075 *END**************************************************************************/
Gmac_Ip_EnableMDIO(uint8 Instance,boolean MiiPreambleDisabled,uint32 ModuleClk)2076 void Gmac_Ip_EnableMDIO(uint8 Instance,
2077 boolean MiiPreambleDisabled,
2078 uint32 ModuleClk)
2079 {
2080 static const uint32 Freq[GMAC_MDIO_CSR_NO] = { 20000000UL, 35000000UL,
2081 60000000UL, 100000000UL,
2082 150000000UL, 250000000UL,
2083 300000000UL, 500000000UL,
2084 800000000UL};
2085 static const uint8 CsrValues[GMAC_MDIO_CSR_NO] = { 2U, 2U, 3U, 0U, 1U, 4U, 5U, 6U, 7U };
2086
2087 GMAC_Type *Base;
2088 uint8 Csr, i;
2089
2090 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2091
2092 Base = Gmac_apxBases[Instance];
2093
2094 GMAC_DEV_ASSERT(ModuleClk != 0U);
2095
2096 Csr = 0U;
2097
2098 for (i = 0U; i < GMAC_MDIO_CSR_NO; i++)
2099 {
2100 if (ModuleClk <= Freq[i])
2101 {
2102 Csr = CsrValues[i];
2103 break;
2104 }
2105
2106 }
2107
2108 Base->MAC_MDIO_ADDRESS = GMAC_MAC_MDIO_ADDRESS_PSE(MiiPreambleDisabled ? 1UL : 0UL) | GMAC_MAC_MDIO_ADDRESS_CR(Csr);
2109 }
2110
2111 /*FUNCTION**********************************************************************
2112 *
2113 * Function Name : Gmac_Ip_MDIORead
2114 * Description : Reads the selected register of the PHY
2115 * implements Gmac_Ip_MDIORead_Activity
2116 *END**************************************************************************/
Gmac_Ip_MDIORead(uint8 Instance,uint8 PhyAddr,uint8 PhyReg,uint16 * Data,uint32 TimeoutMs)2117 Gmac_Ip_StatusType Gmac_Ip_MDIORead(uint8 Instance,
2118 uint8 PhyAddr,
2119 uint8 PhyReg,
2120 uint16 *Data,
2121 uint32 TimeoutMs)
2122 {
2123 GMAC_Type *Base;
2124 Gmac_Ip_StatusType Status;
2125 Gmac_Ip_ManagementInfo ManageInfo;
2126
2127 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2128 GMAC_DEV_ASSERT(Data != NULL_PTR);
2129
2130 Base = Gmac_apxBases[Instance];
2131 ManageInfo.PhysAddr = PhyAddr;
2132 ManageInfo.PhysReg = PhyReg;
2133 ManageInfo.MmdAddr = 0U;
2134 ManageInfo.OpFrameType = GMAC_MMFR_OP_READ;
2135 ManageInfo.FrameData = 0U;
2136 ManageInfo.SupportedClause45 = FALSE;
2137
2138 /* Write management frame */
2139 Status = GMAC_WriteManagementFrame(Base, &ManageInfo, TimeoutMs * 1000U);
2140
2141 if (Status == GMAC_STATUS_SUCCESS)
2142 {
2143 *Data = GMAC_ReadManagementFrameData(Base);
2144 }
2145
2146 return Status;
2147 }
2148
2149 /*FUNCTION**********************************************************************
2150 *
2151 * Function Name : Gmac_Ip_MDIOWrite
2152 * Description : Writes the selected register of the PHY
2153 * implements Gmac_Ip_MDIOWrite_Activity
2154 *END**************************************************************************/
Gmac_Ip_MDIOWrite(uint8 Instance,uint8 PhyAddr,uint8 PhyReg,uint16 Data,uint32 TimeoutMs)2155 Gmac_Ip_StatusType Gmac_Ip_MDIOWrite(uint8 Instance,
2156 uint8 PhyAddr,
2157 uint8 PhyReg,
2158 uint16 Data,
2159 uint32 TimeoutMs)
2160 {
2161 GMAC_Type *Base;
2162 Gmac_Ip_StatusType Status;
2163 Gmac_Ip_ManagementInfo ManageInfo;
2164
2165 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2166
2167 Base = Gmac_apxBases[Instance];
2168 ManageInfo.PhysAddr = PhyAddr;
2169 ManageInfo.PhysReg = PhyReg;
2170 ManageInfo.MmdAddr = 0U;
2171 ManageInfo.OpFrameType = GMAC_MMFR_OP_WRITE;
2172 ManageInfo.FrameData = Data;
2173 ManageInfo.SupportedClause45 = FALSE;
2174
2175 /* Write management frame */
2176 Status = GMAC_WriteManagementFrame(Base, &ManageInfo, TimeoutMs * 1000U);
2177
2178 return Status;
2179 }
2180
2181 /*FUNCTION**********************************************************************
2182 *
2183 * Function Name : Gmac_Ip_MDIOReadMMD
2184 * Description : Reads a register of the specified MMD in a PHY device
2185 * implements Gmac_Ip_MDIOReadMMD_Activity
2186 *END**************************************************************************/
Gmac_Ip_MDIOReadMMD(uint8 Instance,uint8 PhyAddr,uint8 Mmd,uint16 PhyReg,uint16 * Data,uint32 TimeoutMs)2187 Gmac_Ip_StatusType Gmac_Ip_MDIOReadMMD(uint8 Instance,
2188 uint8 PhyAddr,
2189 uint8 Mmd,
2190 uint16 PhyReg,
2191 uint16 *Data,
2192 uint32 TimeoutMs)
2193 {
2194 GMAC_Type *Base;
2195 Gmac_Ip_StatusType Status;
2196 Gmac_Ip_ManagementInfo ManageInfo;
2197
2198 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2199 GMAC_DEV_ASSERT(Data != NULL_PTR);
2200
2201 Base = Gmac_apxBases[Instance];
2202 ManageInfo.PhysAddr = PhyAddr;
2203 ManageInfo.PhysReg = PhyReg;
2204 ManageInfo.MmdAddr = Mmd;
2205 ManageInfo.OpFrameType = GMAC_MMFR_OP_READ;
2206 ManageInfo.FrameData = 0U;
2207 ManageInfo.SupportedClause45 = TRUE;
2208
2209 /* Write management frame */
2210 Status = GMAC_WriteManagementFrame(Base, &ManageInfo, TimeoutMs * 1000U);
2211
2212 if (Status == GMAC_STATUS_SUCCESS)
2213 {
2214 *Data = GMAC_ReadManagementFrameData(Base);
2215 }
2216
2217 return Status;
2218 }
2219
2220 /*FUNCTION**********************************************************************
2221 *
2222 * Function Name : Gmac_Ip_MDIOWriteMMD
2223 * Description : Writes a register of the specified MMD in a PHY device
2224 * implements Gmac_Ip_MDIOWriteMMD_Activity
2225 *END**************************************************************************/
Gmac_Ip_MDIOWriteMMD(uint8 Instance,uint8 PhyAddr,uint8 Mmd,uint16 PhyReg,uint16 Data,uint32 TimeoutMs)2226 Gmac_Ip_StatusType Gmac_Ip_MDIOWriteMMD(uint8 Instance,
2227 uint8 PhyAddr,
2228 uint8 Mmd,
2229 uint16 PhyReg,
2230 uint16 Data,
2231 uint32 TimeoutMs)
2232 {
2233 GMAC_Type *Base;
2234 Gmac_Ip_StatusType Status;
2235 Gmac_Ip_ManagementInfo ManageInfo;
2236
2237 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2238
2239 Base = Gmac_apxBases[Instance];
2240 ManageInfo.PhysAddr = PhyAddr;
2241 ManageInfo.PhysReg = PhyReg;
2242 ManageInfo.MmdAddr = Mmd;
2243 ManageInfo.OpFrameType = GMAC_MMFR_OP_WRITE;
2244 ManageInfo.FrameData = Data;
2245 ManageInfo.SupportedClause45 = TRUE;
2246
2247 /* Write management frame */
2248 Status = GMAC_WriteManagementFrame(Base, &ManageInfo, TimeoutMs * 1000U);
2249
2250 return Status;
2251 }
2252
2253 /*FUNCTION**********************************************************************
2254 *
2255 * Function Name : Gmac_Ip_SetMacAddr
2256 * Description : Configures the physical address of the MAC
2257 * implements Gmac_Ip_SetMacAddr_Activity
2258 *END**************************************************************************/
Gmac_Ip_SetMacAddr(uint8 Instance,const uint8 * MacAddr)2259 void Gmac_Ip_SetMacAddr(uint8 Instance,
2260 const uint8 *MacAddr)
2261 {
2262 uint32 Address;
2263 GMAC_Type *Base;
2264
2265 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2266 GMAC_DEV_ASSERT(MacAddr != NULL_PTR);
2267
2268 Base = Gmac_apxBases[Instance];
2269
2270 /* Set physical address high register. */
2271 Base->MAC_ADDRESS0_HIGH = ((uint32)MacAddr[5] << GMAC_BYTE_5_IN_ADDR_SHIFT) |
2272 ((uint32)MacAddr[4] << GMAC_BYTE_4_IN_ADDR_SHIFT) |
2273 GMAC_MAC_ADDRESS0_HIGH_AE_MASK;
2274
2275 /* Set physical address lower register. */
2276 Address = ((uint32)MacAddr[3] << GMAC_BYTE_3_IN_ADDR_SHIFT) |
2277 ((uint32)MacAddr[2] << GMAC_BYTE_2_IN_ADDR_SHIFT) |
2278 ((uint32)MacAddr[1] << GMAC_BYTE_1_IN_ADDR_SHIFT) |
2279 ((uint32)MacAddr[0] << GMAC_BYTE_0_IN_ADDR_SHIFT);
2280 Base->MAC_ADDRESS0_LOW = Address;
2281 }
2282
2283 /*FUNCTION**********************************************************************
2284 *
2285 * Function Name : Gmac_Ip_GetMacAddr
2286 * Description : Gets the physical Address of the MAC
2287 * implements Gmac_Ip_GetMacAddr_Activity
2288 *END**************************************************************************/
Gmac_Ip_GetMacAddr(uint8 Instance,uint8 * MacAddr)2289 void Gmac_Ip_GetMacAddr(uint8 Instance,
2290 uint8 *MacAddr)
2291 {
2292 const GMAC_Type *Base;
2293 uint32 Address;
2294
2295 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2296 GMAC_DEV_ASSERT(MacAddr != NULL_PTR);
2297
2298 Base = Gmac_apxBases[Instance];
2299
2300 /* Get from physical Address lower register. */
2301 Address = Base->MAC_ADDRESS0_LOW;
2302 MacAddr[0] = (uint8)(GMAC_BYTE_MASK & (Address >> GMAC_BYTE_0_IN_ADDR_SHIFT));
2303 MacAddr[1] = (uint8)(GMAC_BYTE_MASK & (Address >> GMAC_BYTE_1_IN_ADDR_SHIFT));
2304 MacAddr[2] = (uint8)(GMAC_BYTE_MASK & (Address >> GMAC_BYTE_2_IN_ADDR_SHIFT));
2305 MacAddr[3] = (uint8)(GMAC_BYTE_MASK & (Address >> GMAC_BYTE_3_IN_ADDR_SHIFT));
2306
2307 /* Get from physical Address high register. */
2308 Address = Base->MAC_ADDRESS0_HIGH & GMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK;
2309 MacAddr[4] = (uint8)(GMAC_BYTE_MASK & (Address >> GMAC_BYTE_4_IN_ADDR_SHIFT));
2310 MacAddr[5] = (uint8)(GMAC_BYTE_MASK & (Address >> GMAC_BYTE_5_IN_ADDR_SHIFT));
2311 }
2312
2313 /*FUNCTION**********************************************************************
2314 *
2315 * Function Name : Gmac_Ip_GetInterruptFlags
2316 * Description : Gets a mask of the common interrupt events which occurred.
2317 *END**************************************************************************/
Gmac_Ip_GetInterruptFlags(uint8 Instance)2318 uint32 Gmac_Ip_GetInterruptFlags(uint8 Instance)
2319 {
2320 const GMAC_Type *Base;
2321
2322 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2323
2324 Base = Gmac_apxBases[Instance];
2325
2326 return Base->MAC_INTERRUPT_STATUS;
2327 }
2328
2329 /*FUNCTION**********************************************************************
2330 *
2331 * Function Name : Gmac_Ip_GetChInterruptFlags
2332 * Description : Gets a mask of the interrupt events associated to a channel
2333 * which occurred.
2334 *END**************************************************************************/
Gmac_Ip_GetChInterruptFlags(uint8 Instance,uint8 Channel)2335 uint32 Gmac_Ip_GetChInterruptFlags(uint8 Instance,
2336 uint8 Channel)
2337 {
2338 const Gmac_Ip_ChannelType *Base;
2339
2340 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2341
2342 Base = Gmac_apxChBases[Instance][Channel];
2343
2344 return Base->DMA_STATUS;
2345 }
2346
2347 /*FUNCTION**********************************************************************
2348 *
2349 * Function Name : Gmac_Ip_SetBroadcastForwardAll
2350 * Description : Enables/Disables forwarding of the broadcast traffic.
2351 * implements Gmac_Ip_SetBroadcastForwardAll_Activity
2352 *END**************************************************************************/
Gmac_Ip_SetBroadcastForwardAll(uint8 Instance,boolean Enable)2353 void Gmac_Ip_SetBroadcastForwardAll(uint8 Instance,
2354 boolean Enable)
2355 {
2356 GMAC_Type *Base;
2357
2358 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2359
2360 Base = Gmac_apxBases[Instance];
2361
2362 if (Enable)
2363 {
2364 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_DBF_MASK;
2365 }
2366 else
2367 {
2368 /* Disable receive all and promiscuous modes. */
2369 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_RA_MASK;
2370 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_PR_MASK;
2371
2372 Base->MAC_PACKET_FILTER |= GMAC_MAC_PACKET_FILTER_DBF_MASK;
2373 }
2374 }
2375
2376 /*FUNCTION**********************************************************************
2377 *
2378 * Function Name : Gmac_Ip_SetMulticastForwardAll
2379 * Description : Enables/Disables forwarding of the multicast traffic,
2380 * irrespective of the destination MAC Address.
2381 * implements Gmac_Ip_SetMulticastForwardAll_Activity
2382 *END**************************************************************************/
Gmac_Ip_SetMulticastForwardAll(uint8 Instance,boolean Enable)2383 void Gmac_Ip_SetMulticastForwardAll(uint8 Instance,
2384 boolean Enable)
2385 {
2386 GMAC_Type *Base;
2387
2388 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2389
2390 Base = Gmac_apxBases[Instance];
2391
2392 if (Enable)
2393 {
2394 /* Set Pass Multicast bit. */
2395 Base->MAC_PACKET_FILTER |= GMAC_MAC_PACKET_FILTER_PM_MASK;
2396 }
2397 else
2398 {
2399 /* Disable receive all and promiscuous modes. */
2400 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_RA_MASK;
2401 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_PR_MASK;
2402
2403 /* Reset Pass Multicast and Hash Multicast bits. */
2404 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_PM_MASK;
2405 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_HMC_MASK;
2406 }
2407 }
2408
2409 /*FUNCTION**********************************************************************
2410 *
2411 * Function Name : Gmac_Ip_SetUnicastHashFilter
2412 * Description : Enables/Disables hash filteRing for unicast traffic.
2413 * implements Gmac_Ip_SetUnicastHashFilter_Activity
2414 *END**************************************************************************/
Gmac_Ip_SetUnicastHashFilter(uint8 Instance,boolean Enable)2415 void Gmac_Ip_SetUnicastHashFilter(uint8 Instance,
2416 boolean Enable)
2417 {
2418 GMAC_Type *Base;
2419
2420 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2421
2422 Base = Gmac_apxBases[Instance];
2423
2424 if (Enable)
2425 {
2426 /* Disable receive all and promiscuous modes. */
2427 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_RA_MASK;
2428 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_PR_MASK;
2429
2430 Base->MAC_PACKET_FILTER |= GMAC_MAC_PACKET_FILTER_HUC_MASK;
2431 }
2432 else
2433 {
2434 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_HUC_MASK;
2435 }
2436 }
2437
2438 /*FUNCTION**********************************************************************
2439 *
2440 * Function Name : Gmac_Ip_SetMulticastHashFilter
2441 * Description : Enables/Disables hash filtering for multicast traffic.
2442 * implements Gmac_Ip_SetMulticastHashFilter_Activity
2443 *END**************************************************************************/
Gmac_Ip_SetMulticastHashFilter(uint8 Instance,boolean Enable)2444 void Gmac_Ip_SetMulticastHashFilter(uint8 Instance,
2445 boolean Enable)
2446 {
2447 GMAC_Type *Base;
2448
2449 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2450
2451 Base = Gmac_apxBases[Instance];
2452
2453 if (Enable)
2454 {
2455 /* Disable receive all and promiscuous modes. */
2456 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_RA_MASK;
2457 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_PR_MASK;
2458
2459 Base->MAC_PACKET_FILTER |= GMAC_MAC_PACKET_FILTER_HMC_MASK;
2460 }
2461 else
2462 {
2463 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_HMC_MASK;
2464 }
2465 }
2466
2467 /*FUNCTION**********************************************************************
2468 *
2469 * Function Name : Gmac_Ip_SetHashOrPerfectFilter
2470 * Description : Enables/Disables either hash or perfect filters.
2471 * implements Gmac_Ip_SetHashOrPerfectFilter_Activity
2472 *END**************************************************************************/
Gmac_Ip_SetHashOrPerfectFilter(uint8 Instance,boolean Enable)2473 void Gmac_Ip_SetHashOrPerfectFilter(uint8 Instance,
2474 boolean Enable)
2475 {
2476 GMAC_Type *Base;
2477
2478 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2479
2480 Base = Gmac_apxBases[Instance];
2481
2482 if (Enable)
2483 {
2484 /* Disable receive all and promiscuous modes. */
2485 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_RA_MASK;
2486 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_PR_MASK;
2487
2488 Base->MAC_PACKET_FILTER |= GMAC_MAC_PACKET_FILTER_HPF_MASK;
2489 }
2490 else
2491 {
2492 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_HPF_MASK;
2493 }
2494 }
2495
2496 /*FUNCTION**********************************************************************
2497 *
2498 * Function Name : Gmac_Ip_AddDstAddrToHashFilter
2499 * Description : Adds a hardware Address to the hash filter.
2500 * implements Gmac_Ip_AddDstAddrToHashFilter_Activity
2501 *END**************************************************************************/
Gmac_Ip_AddDstAddrToHashFilter(uint8 Instance,const uint8 * MacAddr)2502 void Gmac_Ip_AddDstAddrToHashFilter(uint8 Instance,
2503 const uint8 *MacAddr)
2504 {
2505 const GMAC_Type *Base;
2506 uint32 Crc;
2507
2508 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2509 GMAC_DEV_ASSERT(MacAddr != NULL_PTR);
2510
2511 Base = Gmac_apxBases[Instance];
2512 Crc = Gmac_Ip_ComputeCRC32(MacAddr, 6U);
2513
2514 GMAC_AddToHashTable(Base, Crc);
2515 }
2516
2517 /*FUNCTION**********************************************************************
2518 *
2519 * Function Name : Gmac_Ip_RemoveDstAddrFromHashFilter
2520 * Description : Removes a hardware Address from the hash filter.
2521 * implements Gmac_Ip_RemoveDstAddrFromHashFilter_Activity
2522 *END**************************************************************************/
Gmac_Ip_RemoveDstAddrFromHashFilter(uint8 Instance,const uint8 * MacAddr)2523 void Gmac_Ip_RemoveDstAddrFromHashFilter(uint8 Instance,
2524 const uint8 *MacAddr)
2525 {
2526 const GMAC_Type *Base;
2527 uint32 Crc;
2528
2529 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2530 GMAC_DEV_ASSERT(MacAddr != NULL_PTR);
2531
2532 Base = Gmac_apxBases[Instance];
2533 Crc = Gmac_Ip_ComputeCRC32(MacAddr, 6U);
2534
2535 GMAC_RemoveFromHashTable(Base, Crc);
2536 }
2537
2538 /*FUNCTION**********************************************************************
2539 *
2540 * Function Name : Gmac_Ip_SetAddrPerfectFilter
2541 * Description : Sets the second destination/source Address perfect filter.
2542 * implements Gmac_Ip_SetAddrPerfectFilter_Activity
2543 *END**************************************************************************/
Gmac_Ip_SetAddrPerfectFilter(uint8 Instance,const uint8 * MacAddr,const uint8 Mask,const Gmac_Ip_MacAddrFilterType AddrType,boolean Enable)2544 void Gmac_Ip_SetAddrPerfectFilter(uint8 Instance,
2545 const uint8 *MacAddr,
2546 const uint8 Mask,
2547 const Gmac_Ip_MacAddrFilterType AddrType,
2548 boolean Enable)
2549 {
2550 uint32 Address;
2551 GMAC_Type *Base;
2552
2553 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2554
2555 Base = Gmac_apxBases[Instance];
2556
2557 if (Enable) {
2558 GMAC_DEV_ASSERT(MacAddr != NULL_PTR);
2559
2560 /* Set destination/source Address filtering. */
2561 if (AddrType != GMAC_DST_ADRR_FILTER)
2562 {
2563 Base->MAC_PACKET_FILTER |= GMAC_MAC_PACKET_FILTER_SAF_MASK;
2564
2565 /* Enable source Address inverse filter. */
2566 if (AddrType == GMAC_SRC_ADDR_INV_FILTER)
2567 {
2568 Base->MAC_PACKET_FILTER |= GMAC_MAC_PACKET_FILTER_SAIF_MASK;
2569 }
2570
2571 /* Enable MAC Address to be used to compare source Address of received packet. */
2572 Base->MAC_ADDRESS1_HIGH = GMAC_MAC_ADDRESS1_HIGH_SA(1);
2573 }
2574 else
2575 {
2576 Base->MAC_ADDRESS1_HIGH = GMAC_MAC_ADDRESS1_HIGH_SA(0);
2577 }
2578
2579 /* Set the mask for group Address filtering. */
2580 Base->MAC_ADDRESS1_HIGH |= GMAC_MAC_ADDRESS1_HIGH_MBC(Mask);
2581
2582 /* Set physical Address high register. */
2583 Base->MAC_ADDRESS1_HIGH |= ((uint32)MacAddr[5] << GMAC_BYTE_5_IN_ADDR_SHIFT) |
2584 ((uint32)MacAddr[4] << GMAC_BYTE_4_IN_ADDR_SHIFT) |
2585 GMAC_MAC_ADDRESS1_HIGH_AE_MASK;
2586
2587 /* Set physical Address lower register. */
2588 Address = ((uint32)MacAddr[3] << GMAC_BYTE_3_IN_ADDR_SHIFT) |
2589 ((uint32)MacAddr[2] << GMAC_BYTE_2_IN_ADDR_SHIFT) |
2590 ((uint32)MacAddr[1] << GMAC_BYTE_1_IN_ADDR_SHIFT) |
2591 ((uint32)MacAddr[0] << GMAC_BYTE_0_IN_ADDR_SHIFT);
2592 Base->MAC_ADDRESS1_LOW = Address;
2593 }
2594 else
2595 {
2596 Base->MAC_ADDRESS1_HIGH = GMAC_MAC_HW_ADDRESS1_HIGH_RESET_MASK;
2597 Base->MAC_ADDRESS1_LOW = GMAC_MAC_HW_ADDRESS1_LOW_RESET_MASK;
2598 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_SAF_MASK;
2599 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_SAIF_MASK;
2600 }
2601 }
2602
2603
2604 #if FEATURE_GMAC_ARP_EN
2605 /*FUNCTION**********************************************************************
2606 *
2607 * Function Name : Gmac_Ip_SetArpOffloading
2608 * Description : Enables/Disables recognition of ARP requests and automatic
2609 * transmission of ARP responses.
2610 * implements Gmac_Ip_SetArpOffloading_Activity
2611 *END**************************************************************************/
Gmac_Ip_SetArpOffloading(uint8 Instance,const uint8 * DstAddr,boolean Enable)2612 void Gmac_Ip_SetArpOffloading(uint8 Instance,
2613 const uint8 *DstAddr,
2614 boolean Enable)
2615 {
2616 GMAC_Type *Base;
2617 uint32 Address;
2618
2619 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2620
2621 Base = Gmac_apxBases[Instance];
2622
2623 if (Enable)
2624 {
2625 GMAC_DEV_ASSERT(DstAddr != NULL_PTR);
2626
2627 Base->MAC_CONFIGURATION |= GMAC_MAC_CONFIGURATION_ARPEN_MASK;
2628
2629 Address = ((uint32)DstAddr[0] << GMAC_BYTE_3_IN_ADDR_SHIFT) |
2630 ((uint32)DstAddr[1] << GMAC_BYTE_2_IN_ADDR_SHIFT) |
2631 ((uint32)DstAddr[2] << GMAC_BYTE_1_IN_ADDR_SHIFT) |
2632 ((uint32)DstAddr[3] << GMAC_BYTE_0_IN_ADDR_SHIFT);
2633 Base->MAC_ARP_ADDRESS = Address;
2634 }
2635 else
2636 {
2637 Base->MAC_CONFIGURATION &= ~GMAC_MAC_CONFIGURATION_ARPEN_MASK;
2638 }
2639 }
2640 #endif /* FEATURE_GMAC_ARP_EN */
2641
2642 /*FUNCTION**********************************************************************
2643 *
2644 * Function Name : Gmac_Ip_EnableVlan
2645 * Description : Enables and configures VLAN for transmitted and received
2646 * packets.
2647 * implements Gmac_Ip_EnableVlan_Activity
2648 *END**************************************************************************/
Gmac_Ip_EnableVlan(uint8 Instance,const Gmac_Ip_VlanConfigType * VlanConfig)2649 void Gmac_Ip_EnableVlan(uint8 Instance,
2650 const Gmac_Ip_VlanConfigType * VlanConfig)
2651 {
2652 GMAC_Type *Base;
2653
2654 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2655 GMAC_DEV_ASSERT(VlanConfig != NULL_PTR);
2656
2657 Base = Gmac_apxBases[Instance];
2658
2659 Base->MAC_VLAN_TAG_CTRL_REG = GMAC_MAC_VLAN_TAG_CTRL_EDVLP((VlanConfig->EnDoubleVlan) ? 1UL : 0UL) |
2660 GMAC_MAC_VLAN_TAG_CTRL_ESVL((VlanConfig->EnSvlan) ? 1UL : 0UL) |
2661 GMAC_MAC_VLAN_TAG_CTRL_EIVLRXS(1U) |
2662 GMAC_MAC_VLAN_TAG_CTRL_EIVLS(VlanConfig->InnerVlanStrip) |
2663 GMAC_MAC_VLAN_TAG_CTRL_EVLRXS(1U) |
2664 GMAC_MAC_VLAN_TAG_CTRL_EVLS(VlanConfig->OuterVlanStrip);
2665 Base->MAC_VLAN_INCL_REG = GMAC_MAC_VLAN_INCL_VLTI(0U) |
2666 GMAC_MAC_VLAN_INCL_VLP(1U) |
2667 ((uint32)(((uint32)VlanConfig->OuterVlanIns) <<
2668 GMAC_MAC_VLAN_INCL_VLC_SHIFT));
2669
2670 if (VlanConfig->OuterVlanIns == GMAC_VLAN_TAG_INSERTION)
2671 {
2672 Base->MAC_VLAN_INCL_REG |= GMAC_MAC_VLAN_INCL_CBTI_MASK;
2673 }
2674
2675 Base->MAC_INNER_VLAN_INCL = GMAC_MAC_INNER_VLAN_INCL_VLTI(0U) |
2676 GMAC_MAC_INNER_VLAN_INCL_VLP(1U) |
2677 ((uint32)(((uint32)VlanConfig->InnerVlanIns) <<
2678 GMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT));
2679
2680 }
2681
2682 /*FUNCTION**********************************************************************
2683 *
2684 * Function Name : Gmac_Ip_SetTxOuterVlanTagForInsertion
2685 * Description : Sets outer VLAN type and tag to be inserted for a
2686 * particular transmission ring.
2687 * implements Gmac_Ip_SetTxOuterVlanTagForInsertion_Activity
2688 *END**************************************************************************/
Gmac_Ip_SetTxOuterVlanTagForInsertion(uint8 Instance,uint8 Ring,Gmac_Ip_VlanType VlanType,uint16 VlanTag)2689 Gmac_Ip_StatusType Gmac_Ip_SetTxOuterVlanTagForInsertion(uint8 Instance,
2690 uint8 Ring,
2691 Gmac_Ip_VlanType VlanType,
2692 uint16 VlanTag)
2693 {
2694 GMAC_Type *Base;
2695 Gmac_Ip_StatusType Status = GMAC_STATUS_TIMEOUT;
2696 uint32 StartTime;
2697 uint32 ElapsedTime;
2698 uint32 TimeoutTicks;
2699
2700 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2701 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->TxRingCount);
2702
2703 Base = Gmac_apxBases[Instance];
2704
2705 if (((uint32)((Base->MAC_VLAN_INCL_REG & GMAC_MAC_VLAN_INCL_VLC_MASK) >>
2706 GMAC_MAC_VLAN_INCL_VLC_SHIFT)) ==
2707 ((uint32)GMAC_VLAN_TAG_INSERTION))
2708 {
2709 /* Add fault label for testing */
2710 #ifdef MCAL_ENABLE_FAULT_INJECTION
2711 MCAL_FAULT_INJECTION_POINT(ETH_VLAN_TAG_INSERTION_BUSY);
2712 #endif
2713 /* Check if the Ring is being updated. */
2714 if ((Base->MAC_VLAN_INCL_REG & GMAC_MAC_VLAN_INCL_BUSY_MASK) != 0U)
2715 {
2716 Status = GMAC_STATUS_BUSY;
2717 }
2718 else
2719 {
2720 Base->MAC_VLAN_INCL_REG &= ~GMAC_MAC_VLAN_INCL_ADDR_MASK;
2721
2722 /* Initiate indirect write access for the selected Ring. */
2723 Base->MAC_VLAN_INCL_REG |= (uint32)(((uint32)Ring) <<
2724 GMAC_MAC_VLAN_INCL_ADDR_SHIFT);
2725
2726 /* Enable write access. */
2727 Base->MAC_VLAN_INCL_REG |= GMAC_MAC_VLAN_INCL_RDWR(1U);
2728
2729 Base->MAC_VLAN_INCL_REG &= ~(GMAC_MAC_VLAN_INCL_CSVL_MASK |
2730 GMAC_MAC_VLAN_INCL_VLT_MASK);
2731
2732 /* Set the VLAN type and tag to be inserted/replaced. */
2733 Base->MAC_VLAN_INCL_REG |= ((uint32)(((uint32)VlanType) <<
2734 GMAC_MAC_VLAN_INCL_CSVL_SHIFT)) |
2735 ((uint32)(((uint32)VlanTag) <<
2736 GMAC_MAC_VLAN_INCL_VLT_SHIFT));
2737
2738 /* Disable write access. */
2739 Base->MAC_VLAN_INCL_REG &= ~GMAC_MAC_VLAN_INCL_RDWR_MASK;
2740 /* Add fault label for testing */
2741 #ifdef MCAL_ENABLE_FAULT_INJECTION
2742 MCAL_FAULT_INJECTION_POINT(ETH_VLAN_TAG_INSERTION_TIMEOUT);
2743 #endif
2744 GMAC_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, GMAC_TIMEOUT_VALUE_US);
2745 do
2746 {
2747 if ((Base->MAC_VLAN_INCL_REG & GMAC_MAC_VLAN_INCL_BUSY_MASK) == 0U)
2748 {
2749 Status = GMAC_STATUS_SUCCESS;
2750 break;
2751 }
2752 }
2753 while (!GMAC_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
2754 }
2755 }
2756 else
2757 {
2758 Status = GMAC_STATUS_UNSUPPORTED;
2759 }
2760
2761 return Status;
2762 }
2763
2764 /*FUNCTION**********************************************************************
2765 *
2766 * Function Name : Gmac_Ip_SetTxOuterVlanTagForReplacement
2767 * Description : Sets outer VLAN tag to be replaced for all transmission
2768 * rings.
2769 * implements Gmac_Ip_SetTxOuterVlanTagForReplacement_Activity
2770 *END**************************************************************************/
Gmac_Ip_SetTxOuterVlanTagForReplacement(uint8 Instance,Gmac_Ip_VlanType VlanType,uint16 VlanTag)2771 Gmac_Ip_StatusType Gmac_Ip_SetTxOuterVlanTagForReplacement(uint8 Instance,
2772 Gmac_Ip_VlanType VlanType,
2773 uint16 VlanTag)
2774 {
2775 GMAC_Type *Base;
2776 Gmac_Ip_StatusType Status = GMAC_STATUS_SUCCESS;
2777
2778 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2779
2780 Base = Gmac_apxBases[Instance];
2781
2782 if (((uint32)((Base->MAC_VLAN_INCL_REG & GMAC_MAC_VLAN_INCL_VLC_MASK) >>
2783 GMAC_MAC_VLAN_INCL_VLC_SHIFT)) ==
2784 ((uint32)GMAC_VLAN_TAG_REPLACEMENT))
2785 {
2786 Base->MAC_VLAN_INCL_REG &= ~(GMAC_MAC_VLAN_INCL_CSVL_MASK |
2787 GMAC_MAC_VLAN_INCL_VLT_MASK);
2788
2789 /* Set the VLAN type and tag to be inserted/replaced. */
2790 Base->MAC_VLAN_INCL_REG |= ((uint32)(((uint32)VlanType) <<
2791 GMAC_MAC_VLAN_INCL_CSVL_SHIFT)) |
2792 ((uint32)(((uint32)VlanTag) <<
2793 GMAC_MAC_VLAN_INCL_VLT_SHIFT));
2794 }
2795 else
2796 {
2797 Status = GMAC_STATUS_UNSUPPORTED;
2798 }
2799
2800 return Status;
2801 }
2802
2803 /*FUNCTION**********************************************************************
2804 *
2805 * Function Name : Gmac_Ip_SetTxInnerVlanTag
2806 * Description : Sets inner VLAN type and tag to be inserted/replaced on
2807 * transmission.
2808 * implements Gmac_Ip_SetTxInnerVlanTag_Activity
2809 *END**************************************************************************/
Gmac_Ip_SetTxInnerVlanTag(uint8 Instance,Gmac_Ip_VlanType VlanType,uint16 VlanTag)2810 void Gmac_Ip_SetTxInnerVlanTag(uint8 Instance,
2811 Gmac_Ip_VlanType VlanType,
2812 uint16 VlanTag)
2813 {
2814 GMAC_Type *Base;
2815
2816 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2817
2818 Base = Gmac_apxBases[Instance];
2819
2820 Base->MAC_INNER_VLAN_INCL &= ~(GMAC_MAC_INNER_VLAN_INCL_CSVL_MASK |
2821 GMAC_MAC_INNER_VLAN_INCL_VLT_MASK);
2822
2823 /* Set the VLAN type and tag to be inserted/replaced. */
2824 Base->MAC_INNER_VLAN_INCL |= ((uint32)(((uint32)VlanType) <<
2825 GMAC_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) |
2826 ((uint32)(((uint32)VlanTag) <<
2827 GMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT));
2828 }
2829
2830 #if (FEATURE_GMAC_VLAN_RX_FILTERS_NUM > 0U)
2831 /*FUNCTION**********************************************************************
2832 *
2833 * Function Name : Gmac_Ip_SetVlanTagRxFilter
2834 * Description : Enables/disables and configures the Rx filters for VLAN tag.
2835 * implements Gmac_Ip_SetVlanTagRxFilter_Activity
2836 *END**************************************************************************/
Gmac_Ip_SetVlanTagRxFilter(uint8 Instance,boolean Enable,const Gmac_Ip_VlanRxFilterType * RxFilter)2837 void Gmac_Ip_SetVlanTagRxFilter(uint8 Instance,
2838 boolean Enable,
2839 const Gmac_Ip_VlanRxFilterType * RxFilter)
2840 {
2841 GMAC_Type *Base;
2842
2843 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2844
2845 Base = Gmac_apxBases[Instance];
2846
2847 if (Enable)
2848 {
2849 GMAC_DEV_ASSERT(RxFilter != NULL_PTR);
2850
2851 Base->MAC_PACKET_FILTER |= GMAC_MAC_PACKET_FILTER_VTFE_MASK;
2852 Base->MAC_VLAN_TAG_CTRL_REG |= GMAC_MAC_VLAN_TAG_CTRL_VTHM_MASK;
2853
2854 GMAC_SetVlanTagInvMatch(Base, RxFilter->EnInverseMatch);
2855 Base->MAC_VLAN_TAG_CTRL_REG |= GMAC_MAC_VLAN_TAG_CTRL_VTHM_MASK;
2856 GMAC_SetVlanTagDataRxMatch(Base,
2857 RxFilter->EnInnerVlanMatch,
2858 RxFilter->EnSvlanMatch,
2859 RxFilter->DisVlanTypeMatch,
2860 RxFilter->En12bitMatch);
2861 }
2862 else
2863 {
2864 Base->MAC_PACKET_FILTER &= ~GMAC_MAC_PACKET_FILTER_VTFE_MASK;
2865 Base->MAC_VLAN_TAG_CTRL_REG &= ~GMAC_MAC_VLAN_TAG_CTRL_VTHM_MASK;
2866 }
2867 }
2868
2869 /*FUNCTION**********************************************************************
2870 *
2871 * Function Name : Gmac_Ip_AddVlanTagToRxFilter
2872 * Description : Adds a VLAN Tag to the Rx filter
2873 *
2874 * Note: The acceptance criteria depend on the options configured for the Rx
2875 * filters. To enable and configure the Rx filter, please see the documentation
2876 * for Gmac_Ip_SetVlanTagRxFilter() function.
2877 * implements Gmac_Ip_AddVlanTagToRxFilter_Activity
2878 *END**************************************************************************/
Gmac_Ip_AddVlanTagToRxFilter(uint8 Instance,uint8 FilterIdx,uint16 VlanTag)2879 Gmac_Ip_StatusType Gmac_Ip_AddVlanTagToRxFilter(uint8 Instance,
2880 uint8 FilterIdx,
2881 uint16 VlanTag)
2882 {
2883 GMAC_Type *Base;
2884 Gmac_Ip_StatusType Status = GMAC_STATUS_TIMEOUT;
2885 uint32 StartTime;
2886 uint32 ElapsedTime;
2887 uint32 TimeoutTicks;
2888 uint16 Tag;
2889
2890 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2891 GMAC_DEV_ASSERT(FilterIdx < FEATURE_GMAC_VLAN_RX_FILTERS_NUM);
2892
2893 Base = Gmac_apxBases[Instance];
2894
2895 /* Clear VLAN tag. */
2896 Base->MAC_VLAN_TAG_DATA_REG &= ~GMAC_MAC_VLAN_TAG_DATA_VID_MASK;
2897 /* Clear filter offset. */
2898 Base->MAC_VLAN_TAG_CTRL_REG &= ~GMAC_MAC_VLAN_TAG_CTRL_OFS_MASK;
2899
2900 /* Set the VLAN tag. */
2901 Base->MAC_VLAN_TAG_DATA_REG |= ((uint32)(((uint32)VlanTag) <<
2902 GMAC_MAC_VLAN_TAG_DATA_VID_SHIFT)) |
2903 GMAC_MAC_VLAN_TAG_DATA_VEN_MASK;
2904
2905 /* Set filter offset. */
2906 Base->MAC_VLAN_TAG_CTRL_REG |= (uint32)(((uint32)FilterIdx) <<
2907 GMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT);
2908 /* Enable write operation. */
2909 Base->MAC_VLAN_TAG_CTRL_REG &= ~GMAC_MAC_VLAN_TAG_CTRL_CT_MASK;
2910 /* Set busy bit. */
2911 Base->MAC_VLAN_TAG_CTRL_REG |= GMAC_MAC_VLAN_TAG_CTRL_OB_MASK;
2912 /* Add fault label for testing */
2913 #ifdef MCAL_ENABLE_FAULT_INJECTION
2914 MCAL_FAULT_INJECTION_POINT(ETH_ADD_VLAN_TAG_TIMEOUT);
2915 #endif
2916 GMAC_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, GMAC_TIMEOUT_VALUE_US);
2917 do
2918 {
2919 if ((Base->MAC_VLAN_TAG_CTRL_REG & GMAC_MAC_VLAN_TAG_CTRL_OB_MASK) == 0U)
2920 {
2921 Status = GMAC_STATUS_SUCCESS;
2922 break;
2923 }
2924 }
2925 while (!GMAC_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
2926
2927 /* Read filter contents. */
2928 (void)GMAC_ReadVlanTagRxFilter(Base, FilterIdx, &Tag);
2929 (void)Tag;
2930
2931 return Status;
2932 }
2933
2934 /*FUNCTION**********************************************************************
2935 *
2936 * Function Name : Gmac_Ip_ReadVlanTagRxFilter
2937 * Description : Reads a VLAN Tag Rx filter.
2938 * implements Gmac_Ip_ReadVlanTagRxFilter_Activity
2939 *END**************************************************************************/
Gmac_Ip_ReadVlanTagRxFilter(uint8 Instance,uint8 FilterIdx,uint16 * VlanTag)2940 Gmac_Ip_StatusType Gmac_Ip_ReadVlanTagRxFilter(uint8 Instance,
2941 uint8 FilterIdx,
2942 uint16 * VlanTag)
2943 {
2944 GMAC_Type *Base;
2945
2946 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2947 GMAC_DEV_ASSERT(FilterIdx < FEATURE_GMAC_VLAN_RX_FILTERS_NUM);
2948
2949 Base = Gmac_apxBases[Instance];
2950
2951 return GMAC_ReadVlanTagRxFilter(Base, FilterIdx, VlanTag);
2952 }
2953
2954 /*FUNCTION**********************************************************************
2955 *
2956 * Function Name : Gmac_Ip_ClearVlanTagRxFilter
2957 * Description : Clears a VLAN Tag Rx filter.
2958 * implements Gmac_Ip_ClearVlanTagRxFilter_Activity
2959 *END**************************************************************************/
Gmac_Ip_ClearVlanTagRxFilter(uint8 Instance,uint8 FilterIdx)2960 Gmac_Ip_StatusType Gmac_Ip_ClearVlanTagRxFilter(uint8 Instance,
2961 uint8 FilterIdx)
2962 {
2963 GMAC_Type *Base;
2964 Gmac_Ip_StatusType Status = GMAC_STATUS_TIMEOUT;
2965 uint32 StartTime, ElapsedTime, TimeoutTicks;
2966
2967 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
2968 GMAC_DEV_ASSERT(FilterIdx < FEATURE_GMAC_VLAN_RX_FILTERS_NUM);
2969
2970 Base = Gmac_apxBases[Instance];
2971
2972 /* Clear and disable the VLAN Tag. */
2973 Base->MAC_VLAN_TAG_DATA_REG &= ~(GMAC_MAC_VLAN_TAG_DATA_VID_MASK |
2974 GMAC_MAC_VLAN_TAG_DATA_VEN_MASK);
2975
2976 /* Clear filter offset. */
2977 Base->MAC_VLAN_TAG_CTRL_REG &= ~GMAC_MAC_VLAN_TAG_CTRL_OFS_MASK;
2978 /* Set filter offset. */
2979 Base->MAC_VLAN_TAG_CTRL_REG |= (uint32)(((uint32)FilterIdx) <<
2980 GMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT);
2981 /* Enable write operation. */
2982 Base->MAC_VLAN_TAG_CTRL_REG &= ~GMAC_MAC_VLAN_TAG_CTRL_CT_MASK;
2983 /* Set busy bit. */
2984 Base->MAC_VLAN_TAG_CTRL_REG |= GMAC_MAC_VLAN_TAG_CTRL_OB_MASK;
2985
2986 #ifdef MCAL_ENABLE_FAULT_INJECTION
2987 MCAL_FAULT_INJECTION_POINT(ETH_CLEAR_VLAN_TAG_RX_FILTER_TIMEOUT);
2988 #endif
2989
2990 GMAC_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, GMAC_TIMEOUT_VALUE_US);
2991 do
2992 {
2993 if ((Base->MAC_VLAN_TAG_CTRL_REG & GMAC_MAC_VLAN_TAG_CTRL_OB_MASK) == 0U)
2994 {
2995 Status = GMAC_STATUS_SUCCESS;
2996 break;
2997 }
2998 }
2999 while (!GMAC_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
3000
3001 return Status;
3002 }
3003 #endif
3004
3005 /*FUNCTION**********************************************************************
3006 *
3007 * Function Name : Gmac_Ip_AddVlanTagToHashTable
3008 * Description : Adds a VLAN Tag to the hash table
3009 *
3010 * Note: The hash table filter only applies to 16-bit outer VLAN tag. The
3011 * options configured via Gmac_Ip_SetVlanTagRxFilter() do not apply as
3012 * acceptance criteria for Hash Table filter.
3013 * implements Gmac_Ip_AddVlanTagToHashTable_Activity
3014 *END**************************************************************************/
Gmac_Ip_AddVlanTagToHashTable(uint8 Instance,uint16 VlanTag)3015 void Gmac_Ip_AddVlanTagToHashTable(uint8 Instance,
3016 uint16 VlanTag)
3017 {
3018 GMAC_Type *Base;
3019 uint32 crc;
3020 uint32 tag32;
3021 const uint8 *tag;
3022
3023 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
3024
3025 Base = Gmac_apxBases[Instance];
3026
3027 tag32 = (uint32)VlanTag;
3028 tag = (uint8 *)&tag32;
3029
3030 crc = Gmac_Ip_ComputeCRC32(tag, 2U);
3031 GMAC_AddVlanToHashTable(Base, crc);
3032 }
3033
3034 /*FUNCTION**********************************************************************
3035 *
3036 * Function Name : Gmac_Ip_RemoveVlanTagFromHashTable
3037 * Description : Adds a VLAN Tag to the hash table
3038 * implements Gmac_Ip_RemoveVlanTagFromHashTable_Activity
3039 *END**************************************************************************/
Gmac_Ip_RemoveVlanTagFromHashTable(uint8 Instance,uint16 VlanTag)3040 void Gmac_Ip_RemoveVlanTagFromHashTable(uint8 Instance,
3041 uint16 VlanTag)
3042 {
3043 GMAC_Type *Base;
3044 uint32 Crc;
3045 uint32 Tag32;
3046 const uint8 *Tag;
3047
3048 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
3049
3050 Base = Gmac_apxBases[Instance];
3051
3052 Tag32 = (uint32)VlanTag;
3053 Tag = (uint8 *)&Tag32;
3054
3055 Crc = Gmac_Ip_ComputeCRC32(Tag, 2U);
3056 GMAC_RemoveVlanFromHashTable(Base, Crc);
3057 }
3058
3059 /*FUNCTION**********************************************************************
3060 *
3061 * Function Name : Gmac_Ip_InitSysTime
3062 * Description : Initializes the system time.
3063 * implements Gmac_Ip_InitSysTime_Activity
3064 *END**************************************************************************/
Gmac_Ip_InitSysTime(uint8 Instance,const Gmac_Ip_SysTimeConfigType * SysTimeConfig)3065 void Gmac_Ip_InitSysTime(uint8 Instance,
3066 const Gmac_Ip_SysTimeConfigType * SysTimeConfig)
3067 {
3068 GMAC_Type *Base;
3069
3070 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
3071 GMAC_DEV_ASSERT(SysTimeConfig != NULL_PTR);
3072 GMAC_DEV_ASSERT(SysTimeConfig->InitialTimestamp != NULL_PTR);
3073
3074 Base = Gmac_apxBases[Instance];
3075
3076 /* Set sub-second and sub-nanosecond increments. */
3077 Base->MAC_SUB_SECOND_INCREMENT = GMAC_MAC_SUB_SECOND_INCREMENT_SSINC(SysTimeConfig->SubSecondInc) |
3078 GMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(SysTimeConfig->SubNanoSecondsInc);
3079 /* Enable digital rollover, enable Timestamping for all packets, enable Timestamp. */
3080 Base->MAC_TIMESTAMP_CONTROL = GMAC_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK |
3081 GMAC_MAC_TIMESTAMP_CONTROL_TSENALL_MASK |
3082 GMAC_MAC_TIMESTAMP_CONTROL_TSENA_MASK;
3083 /* Set initial value for system time. */
3084 Base->MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS = SysTimeConfig->InitialTimestamp->secondsHi;
3085 Base->MAC_SYSTEM_TIME_SECONDS_UPDATE = SysTimeConfig->InitialTimestamp->seconds;
3086 Base->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE = (SysTimeConfig->InitialTimestamp->nanoseconds) &
3087 GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK;
3088 /* Initialize the Timestamp. */
3089 Base->MAC_TIMESTAMP_CONTROL |= GMAC_MAC_TIMESTAMP_CONTROL_TSINIT_MASK;
3090 }
3091
3092 /*FUNCTION**********************************************************************
3093 *
3094 * Function Name : Gmac_Ip_SetSysTimeCorr
3095 * Description : Sets the system time correction by either adding or subtracting
3096 * the selected value from the current system time.
3097 * implements Gmac_Ip_SetSysTimeCorr_Activity
3098 *END**************************************************************************/
Gmac_Ip_SetSysTimeCorr(uint8 Instance,Gmac_Ip_SysTimeCorrOffsetType Offset,uint32 SecondsUpdate,uint32 NanoSecondsUpdate)3099 Gmac_Ip_StatusType Gmac_Ip_SetSysTimeCorr(uint8 Instance,
3100 Gmac_Ip_SysTimeCorrOffsetType Offset,
3101 uint32 SecondsUpdate,
3102 uint32 NanoSecondsUpdate)
3103 {
3104 GMAC_Type *Base;
3105 uint32 seconds, Nanoseconds;
3106 Gmac_Ip_StatusType Status = GMAC_STATUS_TIMEOUT;
3107 uint32 StartTime;
3108 uint32 ElapsedTime;
3109 uint32 TimeoutTicks;
3110
3111 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
3112
3113 Base = Gmac_apxBases[Instance];
3114
3115 if (((uint32)Offset) != 0U)
3116 {
3117 seconds = (uint32)(GMAC_SYS_TIME_SEC_MAX_VALUE - SecondsUpdate);
3118 Nanoseconds = (uint32)(GMAC_SYS_TIME_NANOSEC_MAX_VALUE -
3119 NanoSecondsUpdate);
3120 }
3121 else
3122 {
3123 seconds = SecondsUpdate;
3124 Nanoseconds = NanoSecondsUpdate;
3125 }
3126
3127 Base->MAC_SYSTEM_TIME_NANOSECONDS_UPDATE = GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(Offset) |
3128 GMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(Nanoseconds);
3129 Base->MAC_SYSTEM_TIME_SECONDS_UPDATE = GMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(seconds);
3130
3131 Base->MAC_TIMESTAMP_CONTROL |= GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK;
3132
3133 GMAC_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, GMAC_TIMEOUT_VALUE_US);
3134
3135 #ifdef MCAL_ENABLE_FAULT_INJECTION
3136 MCAL_FAULT_INJECTION_POINT(ETH_SETSYSTIMECORR);
3137 #endif
3138
3139 do
3140 {
3141 if ((Base->MAC_TIMESTAMP_CONTROL & GMAC_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK) == 0U)
3142 {
3143 Status = GMAC_STATUS_SUCCESS;
3144 break;
3145 }
3146 }
3147 while (!GMAC_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
3148
3149 return Status;
3150 }
3151
3152 /*FUNCTION**********************************************************************
3153 *
3154 * Function Name : Gmac_Ip_SetRateRatioCorr
3155 * Description : Sets the system time correction by rate ratio
3156 * the selected value from the current system time.
3157 *
3158 * Implements : Gmac_Ip_SetRateRatioCorr_Activity
3159 *END**************************************************************************/
Gmac_Ip_SetRateRatioCorr(uint8 Instance,float64 RateRatio)3160 Gmac_Ip_StatusType Gmac_Ip_SetRateRatioCorr(uint8 Instance,
3161 float64 RateRatio
3162 )
3163 {
3164 GMAC_Type *Base;
3165 Gmac_Ip_StatusType Status = GMAC_STATUS_TIMEOUT;
3166 uint32 StartTime;
3167 uint32 ElapsedTime;
3168 uint32 TimeoutTicks;
3169
3170 Base = Gmac_apxBases[Instance];
3171
3172 Base->MAC_TIMESTAMP_ADDEND = GMAC_MAC_TIMESTAMP_ADDEND_TSAR((uint32)((float64)0x100000000ULL / RateRatio));
3173
3174 Base->MAC_TIMESTAMP_CONTROL |= GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK;
3175 /* Add fault label for testing */
3176 #ifdef MCAL_ENABLE_FAULT_INJECTION
3177 MCAL_FAULT_INJECTION_POINT(ETH_RATE_RATIO_TIMEOUT);
3178 #endif
3179 GMAC_StartTimeOut(&StartTime, &ElapsedTime, &TimeoutTicks, GMAC_TIMEOUT_VALUE_US);
3180
3181 do
3182 {
3183 if ((Base->MAC_TIMESTAMP_CONTROL & GMAC_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK) == 0U)
3184 {
3185 Status = GMAC_STATUS_SUCCESS;
3186 break;
3187 }
3188 }
3189 while (!GMAC_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks));
3190
3191 Base->MAC_TIMESTAMP_CONTROL |= GMAC_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK;
3192
3193 return Status;
3194 }
3195 /*FUNCTION**********************************************************************
3196 *
3197 * Function Name : Gmac_Ip_GetSysTime
3198 * Description : Gets the current system time.
3199 * implements Gmac_Ip_GetSysTime_Activity
3200 *END**************************************************************************/
Gmac_Ip_GetSysTime(uint8 Instance,Gmac_Ip_TimestampType * Timestamp)3201 void Gmac_Ip_GetSysTime(uint8 Instance, Gmac_Ip_TimestampType * Timestamp)
3202 {
3203 const GMAC_Type *Base;
3204
3205 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
3206 GMAC_DEV_ASSERT(Timestamp != NULL_PTR);
3207
3208 Base = Gmac_apxBases[Instance];
3209
3210 Timestamp->secondsHi = (uint16)(Base->MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS);
3211 Timestamp->seconds = (uint32)(Base->MAC_SYSTEM_TIME_SECONDS);
3212 Timestamp->nanoseconds = (uint32)(Base->MAC_SYSTEM_TIME_NANOSECONDS);
3213 }
3214
3215 /*FUNCTION**********************************************************************
3216 *
3217 * Function Name : Gmac_Ip_SetTxSchedAlgo
3218 * Description : Sets the transmitter scheduling algorithm.
3219 * implements Gmac_Ip_SetTxSchedAlgo_Activity
3220 *END**************************************************************************/
Gmac_Ip_SetTxSchedAlgo(uint8 Instance,Gmac_Ip_TxSchedAlgoType SchedAlgo)3221 void Gmac_Ip_SetTxSchedAlgo(uint8 Instance, Gmac_Ip_TxSchedAlgoType SchedAlgo)
3222 {
3223 GMAC_Type *Base;
3224
3225 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
3226
3227 Base = Gmac_apxBases[Instance];
3228
3229 GMAC_SetSchedAlg(Base, SchedAlgo);
3230 }
3231
3232 /*FUNCTION**********************************************************************
3233 *
3234 * Function Name : Gmac_Ip_SetTxRingWeight
3235 * Description : Sets the Weight (in WRR scheduling algorithm) for a
3236 * particular Tx ring.
3237 *
3238 * If multiple rings are configured and the WWR scheduling algorithm is
3239 * selected, the Weight must be programmed with a non-zero value. The maximum
3240 * value for the Weight is 0x64.
3241 * implements Gmac_Ip_SetTxRingWeight_Activity
3242 *END**************************************************************************/
Gmac_Ip_SetTxRingWeight(uint8 Instance,uint8 Ring,uint32 Weight)3243 void Gmac_Ip_SetTxRingWeight(uint8 Instance, uint8 Ring, uint32 Weight)
3244 {
3245 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
3246 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->TxRingCount);
3247 GMAC_DEV_ASSERT((Weight > 0U) && (Weight <= GMAC_MAX_WEIGHT_VALUE));
3248
3249 if (Gmac_apxState[Instance]->TxRingCount > 1U)
3250 {
3251 GMAC_SetTxQueueQuantumWeight(Gmac_apxQueueBases[Instance][Ring], Weight);
3252 }
3253 }
3254
3255 /*FUNCTION**********************************************************************
3256 *
3257 * Function Name : Gmac_Ip_EnableTxStoreAndForward
3258 * Description : Enables the store and forward feature on the transmit path.
3259 * implements Gmac_Ip_EnableTxStoreAndForward_Activity
3260 *END**************************************************************************/
Gmac_Ip_EnableTxStoreAndForward(uint8 Instance,uint8 Ring)3261 void Gmac_Ip_EnableTxStoreAndForward(uint8 Instance, uint8 Ring)
3262 {
3263 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
3264 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->TxRingCount);
3265
3266 GMAC_SetTxStoreAndForward(Gmac_apxQueueBases[Instance][Ring]);
3267 }
3268
3269 /*FUNCTION**********************************************************************
3270 *
3271 * Function Name : Gmac_Ip_SetTxThreshold
3272 * Description : Sets transmit threshold levels.
3273 *
3274 * The transmission starts when the packet size within the Tx Queue is larger
3275 * than the threshold. In addition, full packets with length less than the
3276 * threshold are also transmitted.
3277 * implements Gmac_Ip_SetTxThreshold_Activity
3278 *END**************************************************************************/
Gmac_Ip_SetTxThreshold(uint8 Instance,uint8 Ring,Gmac_Ip_TxThresholdType ThresholdValue)3279 void Gmac_Ip_SetTxThreshold(uint8 Instance,
3280 uint8 Ring,
3281 Gmac_Ip_TxThresholdType ThresholdValue)
3282 {
3283 GMAC_DEV_ASSERT(Instance < FEATURE_GMAC_NUM_INSTANCES);
3284 GMAC_DEV_ASSERT(Ring < Gmac_apxState[Instance]->TxRingCount);
3285
3286 GMAC_SetTxThreshold(Gmac_apxQueueBases[Instance][Ring], ThresholdValue);
3287 }
3288
3289 #define ETH_43_GMAC_STOP_SEC_CODE
3290 #include "Eth_43_GMAC_MemMap.h"
3291
3292
3293 #ifdef __cplusplus
3294 }
3295 #endif
3296 /** @} */
3297
